CA2371760C - Electroluminescent laminate with patterned phosphor structure and thick film dielectric with improved dielectric properties - Google Patents

Abstract

An improved dielectric layer for use in an EL laminate, including a pressed, sintered ceramic material having, compared to an unpressed, sintered dielectric layer of the same composition, improved dielectric strength, reduced porosity and uniform luminosity in an EL
laminate. Also provided is a method of forming a thick film dielectric layer in an EL
laminate by depositing a ceramic material in one or more layers by a thick film technique to form a dielectric layer having a thickness of 10 to 300 µm; pressing the dielectric layer to form a densified layer with reduced porosity and surface roughness; and sintering the dielectric layer to form a pressed, sintered dielectric layer. The formed EL
laminate has an improved uniform luminosity over an unpressed, sintered dielectric layer of the same composition.

Description

FIELD OF THE INVENTION
6 This invention relates to AC electroluminescent (EL) devices fabricated using thin 7 film and/or thick film technologies. The invention also relates to full colour EL devices.

9 U.S. Patent 5,432,015, issued July 11, 1995, to Wu et al., and U.S.
Patent 5,756,147, issued May 26, 1998, to Wu et al. disclose an electroluminescent laminate structure which 11 combines a thick film dielectric layer with thin film layers, and a rear to front method of 12 forming same on a rigid, rear substrate. Solid state displays (SSD) using this hybrid thick 13 film/thin film technology have been demonstrated to have good performance and brightness 14 (luminosity) in monochrome (ZnS:Mn phosphor) and full colour (ZnS:Mn/SrS:Ce bilayer phosphor) applications (Bailey et al., SID 95 Digest, 1995), however, improvements are still 16 needed.
17 The potential for EL as a competitive alternative for fabricating flat panel displays has 18 been hindered by the inability to generate bright, stable full colour.
This has resulted in EL
19 only penetrating markets for niche applications, in which the inherent benefits of the technology, such as ruggedness, wide viewing angle, temperature insensitivity, and fast time 21 response, are needed.
22 Two basic alternatives have been used to produce full colour EL
devices. One 23 approach is to use patterned phosphors, that is alternating red, green and blue (RGB) 24 phosphor elements in a layer (see for example U.S. Patent 4,977,350, issued December 11, 1990, to Tanaka et al.). This approach has the disadvantage of requiring the three phosphors 26 to be patterned into red, green and blue sub-pixels that make up each pixel, in separate steps.
27 Furthermore, the three colours cannot all be produced brightly enough by currently available 28 EL phosphors to gain the brightness advantage desired. A second approach is to use a colour 29 by white technique, first described by Tanaka et al., (SID 88 Digest, p 293, 1988, see also, U.S. Patent 4,727,003, issued February 23, 1988 to Ohseto et al.). In the colour by white 31 method, the phosphor layer comprises layers of phosphors, typically ZnS:Mn and SrS:Ce, 32 which when superimposed produce white light. Red, green and blue sub-pixels are then 1 obtained by placing a patterned filter in front of the white light. The white phosphor emits 2 light at wavelengths over the entire visible portion of the electromagnetic spectrum, and the 3 filters transmit a narrowed range of wavelengths corresponding to the colours for each sub-4 pixel. This approach has the disadvantage of relatively poor energy efficiency, in high measure because a high fraction of the light is absorbed in the filters and the overall energy 6 efficiency of the display is correspondingly reduced.
7 Another requirement for full colour displays is gray scale capability, that is the ability 8 to generate a number of defined and consistent luminosities (light emission intensities) for 9 each sub-pixel. Typically, 256 gray scale luminosities span a range from zero to full luminosity controlled by predetermined input electrical signals for each sub-pixel. This 11 number of gray levels provides a total of about 16 million individual colours.
12 Electroluminescent displays have pixels and sub-pixels that are defined by 13 intersecting sets of conductor stripes at right angles to one another on opposite sides of a 14 phosphor layer. These sets of stripes are respectively referred to as "rows" and "columns".
The sub-pixels are independently illuminated using an addressing scheme called passive 16 matrix addressing. This entails sequentially addressing the rows by applying a short flat-17 topped electrical pulse with a peak voltage called the threshold voltage sequentially on each 18 of the rows such that the duration of the pulse is less than the time allocated for addressing 19 each row. Electrical pulses, each with a defined and independent peak voltage, termed the "modulation voltage", are simultaneously applied to each of the columns intersecting the 21 addressed row. This provides independently controllable voltages across the sub-pixels 22 making up the pixels along that row, in accordance with the instantaneous luminosity 23 required for each sub-pixel to achieve the desired pixel colours. While each row is being 24 addressed, the remaining rows are disconnected, or are connected to a voltage level near zero.
Independent operation of all sub-pixels on the display requires that sub-pixels not on the 26 addressed row do not illuminate. The electro-optical characteristics of the sub-pixels on an 27 electroluminescent display facilitate meeting this requirement, by virtue of the fact that no 28 luminosity is generated if the voltage across the sub-pixels is below the threshold voltage.
29 The time required to address all the rows in a display is called a frame, and for video images, the frame repetition rate must be at least about 50 Hz in order to avoid image flicker.
31 At the same time there is a maximum frame repetition rate, typically about 200 Hz, that is 1 achievable due to a limitation on the voltage rise time associated with the electrical 2 characteristics of the display and its associated electronics. In principle, a measure of gray 3 scale can be achieved by controlling the average pixel luminosity by modulating the average 4 frame rate. This requires omitting a fraction of the electrical pulses over a suitably short period of time. In practice, however, due to the limited range of frame rates, only a few levels 6 of gray scale can be realized this way. Another option, called dithering, is to extinguish one 7 or more pixels in the immediate vicinity of a pixel where reduced luminosity is required, 8 thereby spatially modulating luminosity. This technique, however, causes a loss of display 9 resolution and image quality.
The preferred method of gray scale control is to control the instantaneous sub-pixel 11 luminosity, which must be done by modulating the electrical pulse peak voltage, pulse 12 duration or pulse shape. At the same time, to minimize power consumption in 13 electroluminescent displays addressed using passive matrix addressing, it is desirable to have 14 the row voltage as close as possible to the threshold voltage above which luminosity is generated. This requires the threshold voltage for all sub-pixels to be equal.
16 Filters used to tailor the spectral emission characteristics of sub-pixels typically do not 17 have ideal characteristics. They do not have perfect transmission in the desired wavelength 18 ranges to achieve the desired red, green and blue colours, and they have some optical 19 transparency in the wavelength ranges where they should be opaque. These deviations from ideal behavior impose design limitations on the overall pixel design. For example, the 21 polymer based blue filters commonly used for electroluminescent and other types of flat panel 22 displays have some transmission also in the red portion of the spectrum.
The need to 23 suppress red contamination of the blue pixel requires that thicker polymer films be used, 24 which reduces the transparency in the desired blue wavelength range.
They also have some transparency in the green wavelength range introducing a similar requirement for thicker 26 polymers that are less transparent to blue light. To meet the requirements for full colour 27 displays, the ratios of luminosity for red:green:blue sub-pixels should be 3:6:1, to give a 28 white colour for that pixel. The crE colour coordinates for red sub-pixels should be in the 29 range 0.60<x<0.65 and 0.34<y<0.36. The CIE colour coordinates for green sub-pixels should be in the range 0.35<x<0.38 and 0.55<y<0.62. For blue sub-pixels the CIE
colour 31 coordinates should be in the range 0.13<x<0.15 and 0.14<y<0.18. The combined (white) 1 luminosity for a pixel comprising red, green and blue sub-pixels should be at least about 70 2 candelas per square meter (cd/m2) and the CIE colour coordinates for full white should be in 3 the range 0.35<x<0.40 and 0.35<y<0.40. Higher luminosity is desirable for some 4 applications.
Phosphors useful in electroluminescent displays are well known, and consist of a host 6 material and an activator or dopant. The host material is usually a compound of a Group II
7 element of the periodic table, with a Group VI element, or is a thiogallate compound.
8 Examples of typical phosphors include zinc sulfide or strontium sulfide, with a dopant or 9 activator which functions as the luminescent center when an electric field is applied across the phosphor. Typical activators with phosphors based on zinc sulfide include manganese 11 (Mn) for an amber emission, terbium (Tb) for a green emission and samarium (Sm) for a red 12 emission. A typical activator with phosphors based on strontium sulfide is Ce for a blue-13 green emission. It is conventional to refer to phosphors as, for example, SrS:Ce to designate 14 a phosphor based on SrS doped with Ce, and ZnS:Mn to designate a phosphor based on ZnS
doped with Mn, and this convention is used herein. It is also conventional, when using the 16 formula for the phosphor, for example as in ZnS, to mean phosphors which are formed 17 predominantly from a stoichiometric zinc sulfide. Other elements might be included in the 18 host material for the phosphor, however it is typically still referred to as a phosphor based on 19 the predominant component of the host material. Thus for instance when referring to a phosphor based on zinc sulfide, or a zinc sulfide phosphor, the terminology includes both 21 pure zinc sulfide as a host material and, for example, the phosphor Zn 1,Mg,S:Mn 22 (designating a phosphor based on zinc sulfide but also including magnesium sulfide in the 23 zinc sulfide host material, doped with Mn), although it is also understood that ZnS and ZnI_ 24 õMgõS are different host materials. This phosphor terminology is used herein and the patent claims.

27 The present invention provides improvements in a thick film dielectric layer for use in 28 a hybrid thick film/thin film electroluminescent device. The thick film dielectric layer of this 29 invention is formed by thick film techniques from a dielectric material having a high dielectric constant, generally greater than about 500. The improvements are realized by 31 compressing, for example by isostatic pressing, the thick film dielectric layer prior to 32 sintering, to significantly reduce the porosity and the thickness of the layer, and to 1 significantly increase the dielectric strength of the layer. The result is an unexpected 2 improvement in the dielectric properties of the dielectric layer, significant reductions in the 3 thickness, porosity, void space and interconnectedness of the void space of the layer, and an 4 improvement in the surface smoothness of the layer, leading to more uniform luminance and reduced dielectric breakdown in electroluminescent displays formed therefrom.
6 Electroluminescent laminates made with the thick film dielectric as set forth in U.S.
7 Patent 5,432,015, generally show uniform luminosity as viewed by the naked eye, but when 8 viewed under a X100 microscope show a mottled appearance with some areas brightly 9 illuminated and other areas dimly illuminated or not illuminated at all.
When the driving voltage is near the threshold voltage this mottled appearance is most pronounced. The effect 11 is diminished as the voltage is increased above this value and all regions become illuminated.
12 The effect of this behavior is that the onset of luminosity occurs gradually as the voltage is 13 raised above the nominal threshold value and the rate of increase in the average luminosity 14 with increasing voltage is relatively low. The scale of the observed variability of the luminosity is of the order of 10 um. In contrast, electroluminescent laminates made with a 16 thick film dielectric layer which has been isostatically pressed prior to sintering, in 17 accordance with this invention, do not show this mottled characteristic of the luminosity near 18 the threshold voltage and increases nearly linearly up to about 50 volts above the threshold 19 voltage, so that the average luminosity at a fixed voltage above the threshold voltage is about 50% higher than for an otherwise identical electroluminescent laminate.
"Uniform 21 luminosity", as used herein, means the luminosity resolved to a scale of about 10 um appears 22 uniform.
23 Broadly stated, in one aspect of the invention there is provided a method of forming a 24 thick film dielectric layer in an EL laminate of the type including one or more phosphor layers sandwiched between a front and a rear electrode, the phosphor layer being separated from the 26 rear electrode by the thick film dielectric layer, comprising:
27 depositing a ceramic material in one or more layers on a rigid substrate providing the 28 rear electrode, by a thick film technique, to form a dielectric layer having a thickness of 10 to 29 300 um;
pressing the dielectric layer to form a densified layer with reduced porosity and 31 surface roughness; and 32 sintering the dielectric layer to form a pressed, sintered dielectric layer which, in an 1 EL laminate, has an improved uniform luminosity over an unpressed, sintered dielectric layer 2 or the same composition.
3 In another broad aspect, the invention provides an improved combined substrate and 4 dielectric layer component for use in an EL laminate, comprising:
a rigid substrate providing a rear electrode;

6 a thick film dielectric layer on the substrate providing the rear electrode, the thick film 7 dielectric layer being formed from a pressed, sintered ceramic material having, compared to 8 an unpressed, sintered dielectric layer of the same composition, improved dielectric strength, 9 reduced porosity and uniform luminosity in an EL laminate.
In still a further broad aspect, the invention provides an EL laminate, comprising:
11 a planar phosphor layer;
12 a front and rear planar electrode on either side of the phosphor layer;
13 a rear substrate providing the rear electrode, the rear substrate having sufficient 14 mechanical strength and rigidity to support the laminate; and a thick film dielectric layer on the substrate providing the rear electrode, the thick film 16 dielectric layer being formed from a pressed, sintered ceramic material having, compared to an 17 unpressed, sintered dielectric layer of the same composition, improved dielectric strength, 18 reduced porosity and uniform luminosity in an EL laminate.
19 The present invention further provides a patterned phosphor structure particularly useful in AC thin film/thick film electroluminescent devices, and also useful in AC thin film 21 electroluminescent devices if the thickness of the phosphor over the sub-pixels is not too great.
22 In the phosphor structure of the invention, the emitted light from the phosphor underlying the 23 red, green and blue sub-pixels falls within a narrowed wavelength range of the visible 24 electromagnetic spectrum that more closely matches the range transmitted by the respective filters. In this manner, both the luminosity and the energy efficiency of the display can be 26 substantially increased over the values achievable with a conventional colour by white 27 phosphor design. Another feature of the patterned phosphor structure of the present invention 28 is that the sub-pixel threshold voltages can be made equal and, the relative luminosities of the 29 sub-pixels can be set so that they bear set ratios to one another at each operating modulation voltage used to generate the desired luminosities for red, green and blue.
Preferably, the set 31 ratios remain substantially constant over the full range of the modulation voltage, for proper 32 colour balance. Most preferably, for a full colour display, the set luminosity ratios for the red, 1 green and blue sub-pixels are in the ratio of about 3:6:1, or sufficiently close to this ratio so as 2 to enable adequate colour fidelity (gray scale).
3 To reduce the negative impact of the limitations inherent in filter characteristics, it is 4 desirable to use a phosphor for the blue sub-pixels that does not emit significant intensities of green or red light. Cerium doped strontium sulfide (SrS:Ce), optionally codoped with 6 phosphorus, preferably prepared as set out herein, provides desirable CIE
colour coordinates 7 and luminosity for the blue, and optionally for the green sub-pixels. For green sub-pixels, 8 manganese doped zinc sulfide (ZnS:Mn) does not generally provide an adequate luminosity 9 when filtered to provide acceptable colour coordinates, but in accordance with this invention, it can be combined with cerium doped strontium sulfide to give higher luminosity with good 11 colour coordinates. Alternatively, ZnI,MgõS:Mn, which, with an appropriate ratio of Zn to 12 Mg, has a higher luminosity in the green region of the spectrum than does ZnS:Mn, can be 13 used for the green sub-pixels, optionally with ZnS:Mn. Either or both of the ZniMg,S:Mn or 14 the ZnS:Mn phosphors can be used for the red sub-pixels, x being between 0.1 and 0.3.
In accordance with this invention, one or more means are included with the one or 16 more of the phosphor deposits for setting and equalizing the threshold voltages of the sub-17 pixels, and for setting the relative luminosities of the sub-pixels so that they bear set ratios to 18 one another at each operating modulation voltage used to generate the desired luminosities for 19 red, green and blue. Threshold voltage means the highest amplitude of a voltage pulse that, when applied to a sub-pixel at the desired repetition rate, generates a measurable filtered 21 luminosity less than the lowest specified gray scale luminosity for that sub-pixel. Thus, the 22 means for setting and equalizing the threshold voltages also functions to set the relative sub-23 pixel luminosities so that they bear set ratios to one another over the full range of the 24 modulation voltage used. Generally, the means is one or more of (a) a threshold voltage adjustment layer formed from a dielectric or semiconductor material which is located in one or 26 more of the positions of over, under and embedded within one or more of the phosphor 27 deposits, and/or (b) one or more of the phosphor deposits being formed with different 28 thicknesses.
29 It should be noted that the terms "sub-pixel" and "sub-pixel phosphor elements" are used interchangeably herein to refer to the phosphor deposits for a particular red, green or blue 31 sub-pixel element, along with any threshold voltage adjustment deposit associated with that 32 sub-pixel element.

1 Appropriate colour filters can be chosen for the three sub-pixels to achieve self-2 consistent optimization of luminosity and colour coordinates for each, and overall pixel energy 3 efficiency. The present invention has application to other colour phosphors, the strontium 4 sulfide and zinc sulfide phosphors being representative only. Usually, at least two different phosphors are used, each being formed from different host materials. It is also possible to 6 extend the present invention to three or more different phosphor layers for further 7 optimization.
8 Broadly stated, the invention provides a patterned phosphor structure having red, green 9 and blue sub-pixel phosphor elements for an AC electroluminescent display, comprising:
at least a first and a second phosphor, each emitting light in different ranges of the 11 visible spectrum, but whose combined emission spectra contains red, green and blue light;
12 said at least first and second phosphors being in a layer, arranged in adjacent, repeating 13 relationship to each other to provide a plurality of repeating at least first and second phosphor 14 deposits; and one or more means associated with one or more of the at least first and second 16 phosphor deposits, and which together with the at least first and second phosphor deposits, 17 form the red, green and blue sub-pixel phosphor elements, for setting and equalizing the 18 threshold voltages of the red, green and blue sub-pixel phosphor elements, and for setting the 19 relative luminosities of the red, green and blue sub-pixel phosphor elements so that they bear set ratios to one another at each operating modulation voltage used to generate the desired 21 luminosities for red, green and blue.
22 Suitable materials for the threshold voltage adjustment layers are those which, when 23 deposited as a layer, at an appropriate thickness, will not conduct until the voltage across the 24 patterned phosphor structure exceeds the threshold voltage for an otherwise identical patterned phosphor structure that does not include the threshold voltage adjustment layer. A suitable 26 material can be chosen by examination of its dielectric constant and dielectric breakdown 27 strength to meet the above condition, with materials having relatively high dielectric constants 28 and dielectric breakdown strengths as compared to those of the phosphor materials being 29 preferable. The materials for the threshold voltage adjustment layer are compatible with those materials that are in contact with them in the patterned phosphor structure, and are chosen 31 from dielectric materials and semiconductors. By semiconductors is meant both intrinsic 32 semiconductors, and semiconductors with deep impurity levels that have effective electronic 1 band gaps that are comparable to, or larger than, the effective band gap of the phosphor 2 material. Examples of suitable materials include binary metal oxides such as alumina and 3 tantalum oxide, binary metal sulfides such as zinc sulfide and strontium sulfide, silica, and 4 silicon oxynitride. The suitability of these materials is dependent on the properties of the interface between the materials and any phosphor materials and the dielectric materials in 6 contact with them. In general, when the phosphor deposit is of a phosphor which is based on 7 zinc sulfide, the preferred threshold voltage adjustment material is a binary metal oxide, most 8 preferably alumina.
9 Alternatively, or in addition, the means for setting and equalizing the threshold voltages and for setting the relative luminosities comprises forming the first and second 11 phosphor deposits with different thicknesses so as to balance the threshold voltages and the 12 luminosities of the sub-pixel elements. In this case, the overall colour balance can be achieved 13 for a pixel by setting the luminosities for the sub-pixel by using different sub-pixel element 14 areas, for instance by making the sub-pixel elements of the less efficient phosphors wider than the width of the sub-pixel elements with the more efficient phosphors.
16 The patterned phosphor structure of this invention allows for correct CIE colour 17 coordinates for a full colour display to be achieved for all operating modulation voltage 18 levels, while allowing for the equalizing of the threshold voltages of the sub-pixel elements.
19 The means for setting and equalizing the threshold voltages, and for setting the relative luminosities of the red, green and blue sub-pixels may also comprise, in addition to the 21 threshold voltage adjustment deposits and/or altering the thicknesses of the phosphor deposits, 22 varying one or more of the following in order to set the relative luminosities:
23 i. the areas of the phosphor deposits; and 24 ii. the concentrations of a dopant or co-dopant in the phosphor deposits.
Preferably, the first and second phosphors are of different host materials, such as a 26 strontium sulfide phosphor or a zinc sulfide phosphor. Generally, a different host material 27 implies that a different element has been introduced to the phosphor host material at an atomic 28 percent greater than about 5 atomic percent. Preferred first and second phosphors are SrS:Ce 29 and ZnS:Mn; SrS:Ce and ZnIMgxS:Mn; or SrS:Ce with layers of both ZnS:Mn and ZnI_ xMgxS:Mn, it being possible for the SrS:Ce to be codoped with phosphorus.
These are 31 examples of zinc sulfide and strontium sulfide phosphors which, if they were superimposed, 32 would have a combined emission spectrum which covers the wavelengths of white light 1 (individual visible spectra for ZnS:Mn and SrS:Ce are shown in Figures 7 and 8 respectively).
2 Within the scope of the present invention, each of the first and second phosphor deposits may 3 comprise one or more layers of a same or different phosphor for each sub-pixel element, and 4 each of the phosphor deposits may themselves be composed of one or more phosphor compositions (i.e. mixtures of more than one phosphors). As set out below, the phosphor 6 structure of this invention may be provided on one or more layers. For example, in a single 7 layer phosphor structure, as set forth in Example 3, the phosphors can be arranged such that 8 ZniMgxS:Mn forms the red and green sub-pixel elements, while SrS:Ce forms the blue sub-9 pixel element. A threshold voltage adjustment layer of a binary metal oxide such as alumina can be provided over the red and green sub-pixel elements to achieve the desired luminous 11 intensity ratios between the sub-pixel elements. Alternatively, as set forth in Example 4, 12 SrS:Ce deposits can be used for the blue sub-pixel elements, and a layer of ZniMgxS:Mn 13 between layers of ZnS:Mn can be used for the red and green sub-pixel elements. The stacked 14 zinc sulfide phosphor deposits of this embodiment can be formed thick enough to equalize the threshold voltages between the sub-pixel elements. To achieve the desired relative 16 luminosities between the sub-pixel elements, the SrS:Ce deposits for the blue sub-pixels can 17 be made wider than the sub-pixels for red and green. Alternatively, as set forth in Example 5, 18 SrS:Ce deposits can be used for both the green and blue sub-pixel elements, and ZnS:Mn can 19 be used for the red sub-pixel elements. A threshold voltage adjustment layer of a binary metal oxide such as alumina can be used over the red sub-pixel deposits to equalize the threshold 21 voltages.
22 When two layers of phosphors are used, as in Example 2, the phosphors may be 23 arranged such that SrS:Ce is patterned in a first layer with ZnS:Mn or ZnMgõS:Mn, and a 24 second layer of SrS:Ce can be formed over the first layer. In this embodiment, the stacked phosphor deposits of SrS:Ce form the blue sub-pixel elements, while the red and green sub-26 pixel elements are formed by the stacked zinc sulfide phosphor deposit under the SrS:Ce 27 deposit.
28 Compared to conventional colour by white techniques in which the white light is 29 provided by coplanar, stacked layers of SrS:Ce and ZnS:Mn, the patterned phosphor structure of the present invention has the advantage of being able to provide a thicker layer of SrS:Ce 31 for the blue sub-pixel element, without having an over- or under- layer of ZnS:Mn. This 32 results in increased blue luminance and, since there is no yellow-orange light being emitted in 1 the blue sub-pixels, the filtered light from the SrS:Ce phosphor is a more saturated blue.
2 The patterned phosphor structure of this invention has particular application in hybrid 3 thick film/thin film AC electroluminescent devices such as described in U.S. Patent 5,432,015, 4 in which the EL laminate is fabricated on a rigid rear substrate, with a thick film dielectric layer below the phosphor structure. AC thin film electroluminescent devices (TFELs) have 6 the disadvantage of generally requiring its thin layers to be planarized, that is of even 7 thicknesses. Such devices generally preclude the ability to use colour phosphor sub-pixels of 8 differing thicknesses. However, using a thick film dielectric layer in an EL laminate in 9 combination with the patterned phosphor structure of the present invention allows one to use different thicknesses of the individual phosphor sub-pixel deposits, so as to optimize the 11 colour coordinates and luminosity of a particular sub-pixel element, while still setting and 12 equalizing the threshold voltages for the sub-pixel elements.
13 The present invention also extends to novel methods for fabricating the patterned 14 phosphor structure of the present invention. Broadly stated, the invention provides a method of forming a patterned phosphor structure having red, green and blue sub-pixel elements for an 16 AC electroluminescent display, comprising:
17 selecting at least a first and a second phosphor, each emitting light in different ranges 18 of the visible spectrum, but whose combined emission spectra contains red, green and blue 19 light;
- 20 depositing and patterning said at least first and second phosphors in a layer to form a 21 plurality of repeating at least first and second phosphor deposits arranged in adjacent, 22 repeating relationship to each other; and 23 providing one or more means associated with one or more of the at least first and 24 second phosphor deposits, and which together with the at least first and second phosphor deposits, form the red, green and blue sub-pixel phosphor elements, for setting and equalizing 26 the threshold voltages of the red, green and blue sub-pixel phosphor elements, and for setting 27 the luminosities of the red, green and blue sub-pixel elements so that they bear set relative 28 luminosities to one another at each operating modulation voltage used to generate the desired 29 luminosities for red, green and blue; and optionally annealing the patterned phosphor structure so formed.
31 Preferably the patterning of the at least first and second phosphor is achieved by 32 photolithographic techniques, including the steps of:

1 a) depositing a layer of the first phosphor which is to form at least one of the red, green 2 and blue sub-pixel elements;
3 b) removing the first phosphor material in regions which are to define the other of the 4 red, green and blue sub-pixel elements, leaving spaced first phosphor deposits;
c) depositing the second phosphor over the first phosphor deposits and in the regions 6 which are to define the other of the red, green and blue sub-pixel elements; and 7 d) removing the second phosphor from above the first phosphor deposits, leaving a 8 plurality of repeating first and second phosphor deposits arranged in adjacent, repeating 9 relationship to each other.
Novel photolithographic techniques have been developed which are particularly useful 11 in patterning strontium and zinc sulfide phosphors, but which have application to other 12 phosphor combinations. In its most preferred embodiments, the photolithographic methods of 13 this invention utilizes a negative photoresist, and has the advantage of needing only one photo-14 mask to accomplish the patterning of the red, green and blue sub-pixel elements. In accordance with this method, steps b) through d) include, applying a negative resist to the 16 first phosphor; exposing and developing the resist through a photo-mask in the areas that the 17 first phosphor is to define one or more of the red, green and blue sub-pixel elements; removing 18 the first phosphor as in step b), depositing the second phosphor over the first phosphor 19 deposits and in the regions which are to define the other of the red, green and blue sub-pixel elements; and then removing, by lift-off, the second phosphor from above the first phosphor 21 deposits. Typically in this method, the first phosphor is a strontium sulfide phosphor, most 22 preferably SrS:Ce, which forms the blue sub-pixel elements and optionally the green sub-pixel 23 elements, and the second phosphor is a zinc sulfide phosphor, most preferably ZnS:Mn or Zni_ 24 xMgxS:Mn, or both, which forms the red, and optionally the green, sub-pixel elements. In accordance with the method, the means for setting and equalizing the threshold voltages and 26 for setting the luminosities of the sub-pixel elements can include adding a threshold voltage 27 adjustment deposit beneath, within or above one or more of the phosphor deposits and/or 28 forming the phosphor deposits with different thicknesses, as set out above. In addition, the 29 means for setting and equalizing the threshold voltages, and for setting the luminosities, of the sub-pixel elements may include varying one or more of:
31 i. the areas of the phosphor deposits; and 32 ii. the concentrations of a dopant or co-dopant in the phosphor deposits.

1 The invention also provides a novel photolithographic technique which is particularly 2 useful for patterning a phosphor which is subject to hydrolysis, such as alkaline earth metal 3 sulfide or selenide phosphors. Broadly, the invention provides a method of forming a 4 patterned phosphor structure having red, green and blue sub-pixel elements for an AC
electroluminescent display, comprising:
6 a) selecting at least a first and a second phosphor, each emitting light in different 7 ranges of the visible spectrum, but whose combined emission spectra contains red, green and 8 blue light;
9 b) depositing a layer of the first phosphor which is to form at least one of the red, green or blue sub-pixel elements;
11 c) applying a photo-resist to the first phosphor, exposing the photo-resist through a 12 photo-mask, developing the photo-resist, and removing the first phosphor in regions that the 13 first phosphor is to define as one or more of the red, green and blue sub-pixel elements, 14 leaving spaced first phosphor deposits, wherein the first phosphor is removed with an etchant solution comprising a mineral acid, or a source of anions of a mineral acid, in a non-aqueous, 16 polar, organic solvent which solubilizes the reaction product of the first phosphor with anions 17 of the mineral acid, and wherein optionally, prior to removing the first phosphor with the 18 etchant solution, the first phosphor layer is immersed in the non-aqueous organic solvent;
19 d) depositing the second phosphor material over the first phosphor deposits and in regions which are to define the other of the red, green and blue sub-pixel elements; and 21 e) removing by lift-off, the second phosphor material and the resist from above the first 22 phosphor deposits leaving a plurality of repeating first and second phosphor deposits arranged 23 in adjacent, repeating relationship to each other.
24 The invention also extends to EL laminates combining, as described above, a rigid rear substrate, a thick film dielectric layer and the patterned phosphor structure, together with front 26 and rear column and row electrodes on either side of the phosphor layer, in which the front and 27 rear column and row electrodes are generally aligned with the phosphor sub-pixel elements, 28 and bandpass colour filter means aligned with the red, green and blue phosphor sub-pixel 29 elements for passing therethrough red, green and blue light emitted from the phosphor sub-pixel elements.
31 Another aspect of the present invention provides novel and separate selection criteria 32 for barrier diffusion layers and injection layers useful with electroluminescent phosphors, and 1 particularly useful with the patterned phosphor structure and the thick film dielectric of the 2 present invention. Preferably, a diffusion barrier layer is included above the thick film 3 dielectric layer, or if present, above the second ceramic material. The diffusion barrier layer is 4 composed of a metal-containing electrically insulating binary compound which is compatible with any adjacent layers, and which is precisely stoichiometric, preferably varying from its 6 precise stoichiometric composition by less than 0.1 atomic percent, and having a thickness of 7 100 to 1000 A. Preferred materials will vary with the particular phosphors and the materials in 8 the dielectric layers, but most preferred materials are alumina, silica and zinc sulfide.
9 Preferably, an injection layer is included above the thick film dielectric layer, or if present, above the second ceramic material or the barrier diffusion layer, to provide a phosphor 11 interface. The injection layer is composed of a binary dielectric or semi-conductor material 12 which is non-stoichiometric in its composition and which has electrons in a preferred range of 13 energy for injection into the phosphor layer. The material is compatible with adjacent layers 14 and is preferably non-stoichiometric by greater than 0.5 atomic percent.
Preferred materials vary with the particular phosphor and the materials in the underlying dielectric layers, but 16 preferred materials for providing optimum electron energies are hafnia or yttria. There is a 17 compromise between optimum electron injection and compatibility with adjacent layers. As a 18 result, sometimes a non-stoichiometric compound cannot be used as an injection layer.
19 Another broad aspect of the invention provides a method of synthesizing strontium sulfide, comprising:
21 providing a source of high purity strontium carbonate in a dispersed form;
22 heating the strontium carbonate in a reactor with gradual heating up to a maximum 23 temperature in the range of 800 to 1200 C;
24 contacting the heated strontium carbonate with a flow of sulfur vapours formed heating elemental sulfur in the reactor to at least 300 C in an inert atmosphere; and 26 terminating the reaction by stopping the flow of sulfur at a point when sulfur dioxide or 27 carbon dioxide in the reaction gas reaches an amount which correlates with an amount of 28 oxygen in oxygen-containing strontium compounds in the reaction product which is in the 29 range of 1 to 10 atomic percent.
By "dispersed form", in reference to the source of strontium carbonate, as used herein 31 and in the claims, is meant that the strontium carbonate powder particles are exposed to the 32 process conditions substantially uniformly. This can preferably be achieved by using small 1 batches, using volatile, non-contaminating, clean evaporating compounds or solvents which 2 decompose into gaseous products prior to the onset of the reaction, using fluidized beds or 3 tumbler reactors.
4 The term "phosphor" as used herein and in the claims, means a substance which provides electroluminescence when a sufficient electric field is applied across it, and electrons 6 are injected into it.
7 The term "white light" when used herein and in the claims, when referring to the 8 combined emission spectra of two or more phosphors, means that white light is emitted when 9 the phosphors are superimposed in a manner such that the light can be filtered to provide red, green and blue light.
11 The term "compatible" when used herein and in the claims, means that the material is 12 chemically stable to that it does not chemically react with adjacent layers.

14 Figure 1 is a schematic sectional view of an EL laminate having a thick film dielectric of the present invention with conventional colour by white bilayer phosphors and red, green 16 and blue filters;
17 Figure 2 is a schematic sectional view of an EL laminate having a thick film dielectric 18 of the present invention combined with a two layer patterned phosphor structure of the present 19 invention;
Figure 3 is a graph comparing the unfiltered luminance plotted against voltage for the 21 colour by white structure of Figure 1 (shown in dotted line in the graph) and the patterned 22 phosphor structure of Figure 2 (shown in solid lines in the graph), at a driving frequency of 60 23 Hz;
24 Figure 4 is a graph comparing the filtered luminances plotted against voltage for the colour by white structure of Figure 1 and the patterned phosphor structure of Figure 2, at a 26 driving frequency of 60 Hz:
27 Figure 5 is a plan view of the ITO column electrode over several pixels, showing 28 alignment with the underlying red, green and blue phosphor sub-pixel elements;
29 Figure 6 is a schematic sectional view of a single pixel of an EL
laminate with a two layer patterned phosphor structure of the present invention with additional diffusion barrier 31 and injection layers;
32 Figure 7 is a graph of the emission spectrum for ZnS:Mn, plotting intensity in arbitrary 1 units against wavelength in nanometres;
2 Figure 8 is a graph of the emission spectrum for SrS:Ce, when synthesized by the 3 process of the present invention, plotting intensity in arbitrary units against wavelength in 4 nanometres; and Figure 9 is a schematic plot of energy against distance to illustrate phosphor electron 6 bands in the presence of an electric field.
7 The figures showing the thick film dielectric layers and the patterned phosphor 8 structures of this invention are not shown to scale.

EL Laminate With Isostatic Pressed Thick Film Dielectric 11 The present invention provides a thick film dielectric layer having increased dielectric 12 strength and dielectric constant, significantly reduced void space, void interconnectedness, 13 porosity and thickness, and significantly improved surface smoothness, when compared to the 14 thick films dielectric layers such as described in U.S. Patent 5,432,015. The smoother surface of the dielectric layer results in an unexpected improvement by providing a higher and more 16 uniform luminosity across an EL display formed therefrom. The improvement is achieved by 17 compressing a thick film dielectric layer prior to sintering, such as by isostatic pressing.
18 The thick film dielectric layer will be described with reference to Figures 1, 2, 5 and 6.
19 An EL laminate 10 is built from the rear to the front (viewing) side on a rear substrate 12.
Preferably, the substrate 12 is a rigid substrate such as a preformed sheet, providing sufficient 21 mechanical strength and rigidity to support the laminate 10.
Alternatively, the substrate 12 22 could be a green tape or the like which will sinter to provide the rigidity for the laminate 10.
23 Thus, the term "rigid substrate" as used herein refers to the substrate after sintering. The 24 substrate 12 is preferably formed from a ceramic which can withstand the high sintering temperatures (typically up to 1000 C) used in processing other layers of the laminate 10. An 26 alumina sheet is most preferred, having a thickness and rigidity sufficient to support the EL
27 laminate 10. A rear electrode layer 14 is formed on the substrate 12.
For lamp applications, 28 the rear substrate 12 and rear electrode 14 might be integral, for example by being provided by 29 a rigid, electrically conductive metal sheet. For display applications, the rear electrode 14 consists of rows of conductive metal address lines centered on the substrate 12 and spaced 31 from the substrate edges. Preferably conductive metal address lines are screen printed from 32 noble metal pastes, as is well known. An electrical contact tab 16 protrudes from the electrode 1 14, as seen in Figure 5. The thick film dielectric layer 18 is formed above the electrode 14, 2 and may be formed as a single layer, or as multiple layers. In Figures 1 and 2, the layer is 3 shown schematically as one layer, while in Figure 6, the layer comprises a thicker, first 4 dielectric layer 18, and a thinner, second dielectric layer 20. One or more phosphor layers 22 are provided above the dielectric layer 18, or dielectric layers 18, 20. In Figure 1, the 6 phosphor is shown as two layers as in a conventional colour by white design. In Figure 2 and 7 6, the phosphor layer 22 is shown to comprise a patterned phosphor structure 30 of the present 8 invention, as is described in greater detail below. Above the phosphor layer(s) 22, there may 9 be provided a third dielectric layer. Above the optional third dielectric layer is a front, transparent electrode layer 24. The front electrode layer 24 is shown in Figures 1 and 2 as 11 solid, but in actuality, for display applications, it consists of columns of address lines arranged 12 perpendicularly to the row address lines of the rear electrode 14. The front electrode 24 is 13 preferably formed from indium tin oxide (ITO) by known thin film or photolithographic 14 techniques. Although not shown, the front electrode is also provided with an electrical contact.
Figures 1 and 2 show bandpass colour filter means 25 above the ITO lines, such as polymeric 16 red, green and blue filters 25a, 25b, and 25c respectively, aligned with the ITO address lines.
17 In Figure 2, these filters 25a, 25b, and 25c are also aligned with red, green and blue phosphor 18 sub-pixel elements 30a, 30b and 30c, in the patterned phosphor structure 30. Also not shown, 19 the EL laminate 10 is encapsulated with a transparent sealing layer to prevent moisture penetration. The EL laminate 10 is operated by connecting an AC power source to the 21 electrode contacts. Voltage driving circuitry (not shown) is well known in the art. The EL
22 laminate 10, incorporating the thick film dielectric layer 18, has application in both EL lamps 23 and displays.
24 It will be understood by persons skilled in the art that further intervening layers, including for example one or more barrier diffusion layers 26, injection layers 28 or dielectric 26 layers (such as optional second and third dielectric layers) can be included in the laminate 10, 27 some of which are described more particularly below in association with the patterned 28 phosphor structure 30. Thus, throughout this description and in the patent claims, when an EL
29 laminate is defined as including certain layers, additional, intervening layers are not meant to be excluded.
31 It will be appreciated that, in general, the criteria for establishing the thickness and 32 dielectric constant of the dielectric layer(s) are calculated so as to provide adequate dielectric 1 strength at minimal operating voltages. The criteria are interrelated as set forth below, in 2 respect of a single phosphor layer and a single dielectric layer. In the case of multilayers, such 3 as a two layer phosphor, or the patterned phosphor structure described below, the criteria are 4 adjusted for the multiple layers, for example by using the thickest dimension and average dielectric constant of the entire phosphor layer.
6 Given a typical range of thickness for the phosphor layer (d1) of between about 0.2 and 7 2.5 microns, a dielectric constant range for the phosphor layer (k1) of between about 5 and 10 8 and a dielectric strength range for the dielectric layer(s) of about 106 to 107 V/m, the following 9 relationships and calculations can be used to determine typical thickness (d2) and dielectric constant (k,) values for the dielectric layer of the present invention. These relationships and 11 calculations may be used as guidelines to determine d, and k2 values, without departing from 12 the intended scope of the present invention, should the typical ranges change significantly.
13 The applied voltage V across a bilayer comprising a uniform dielectric layer and a 14 uniform non-conducting phosphor layer sandwiched between two conductive electrodes is given by equation 1:
16 V = E2*d, + E1*(11 (1) 17 wherein:
18 E. is the electric field strength in the dielectric layer;
19 E1 is the electric field strength in the phosphor layer;
d, is the thickness of the dielectric layer; and 21 di is the thickness of the phosphor.
22 In these calculations, the electric field direction is perpendicular to the interface 23 between the phosphor layer and the dielectric layer. Equation 1 holds true for applied voltages 24 below the threshold voltage at which the electric field strength in the phosphor layer is sufficiently high that the phosphor begins to break down electrically and the device begins to 26 emit light.
27 From electromagnetic theory, the component of electric displacement D
perpendicular 28 to an interface between two insulating materials with different dielectric constants is 29 continuous across the interface. This electric displacement component in a material is defined as the product of the dielectric constant and the electric field component in the same direction.
31 From this relationship equation 2 is derived for the interface in the bilayer structure:
32 k2*E2 = k1*El (2) 1 wherein:
2 k, is the dielectric constant of the dielectric material; and 3 lc, is the dielectric constant of the phosphor material.
4 Equations 1 and 2 can be combined to give equation 3:
V = (ki*d,/k2 + di)*E, (3) 6 To minimize the threshold voltage, the first term in equation 3 needs to be as small as 7 is practical. The second term is fixed by the requirement to choose the phosphor thickness to 8 maximize the phosphor light output. For this evaluation the first term is taken to be one tenth 9 the magnitude of the second term. Substituting this condition into equation 3 yields equation 4:
11 d2/k2= 0.1*cli/k, (4) 12 Equation 4 establishes the ratio of the thickness of the dielectric layer to its dielectric 13 constant in terms of the phosphor properties. This thickness is determined independently from 14 the requirement that the dielectric strength of the layer be sufficient to hold the entire applied voltage when the phosphor layer becomes conductive above the threshold voltage. The 16 thickness is calculated using equation 5:
17 d2 = V/S (5) 18 wherein:
19 S is the strength of the dielectric material.
Use of the above equations and reasonable values for di, ki, and S provides the range 21 of dielectric layer thickness and dielectric constant. In general, the lower limit of the thickness 22 of the dielectric layer is that it must be sufficiently thick that the dielectric strength of the 23 dielectric layer is higher than the actual electric field present during operation of the device.
24 Generally, the combined thickness of the dielectric layers 18 and 20 can be as low as about 10 ,um, with a phosphor layer thicknesses as high as about 2.5 ktm.
26 A method of constructing the thick film dielectric layer 18 will now be described with 27 preferred materials and process steps.
28 The dielectric layer 18 is deposited by thick film techniques which are well known in 29 the electronics/semiconductor industries. The layer 18 is preferably formed from a ferroelectric material, most preferably one having a perovskite crystal structure, to provide a 31 high dielectric constant compared to that of the phosphor layer(s) 22.
The material will have a 32 minimum dielectric constant of 500 over a reasonable operating temperature for the laminate 1 10 (generally 20 - 100 C). More preferably, the dielectric constant of the dielectric layer 2 material is 1000 or greater. Exemplary materials for the layer include BaTiO3, PbTiO3. lead 3 magnesium niobate (PMN) and PMN-PT, a material including lead and magnesium niobates 4 and titanates, the latter being most preferred. Such materials may be formulated from their dielectric powders, or may be obtained as commercial pastes.
6 Thick film deposition techniques are known in art, such as green tapes, roll coating, 7 and doctor blade application, but screen printing is most preferred.
Commercially available 8 dielectric pastes can be used, with the recommended sintering steps set out by the paste 9 manufacturers. Pastes should be chosen or formulated to permit sintering at a high temperature, typically about 800 - 1000 C. The dielectric layer 18 is screen printed in single 11 or multiple layers. Multiple layers are preferred, following each deposition with drying or 12 baking or sintering in order to achieve low porosity, high crystallinity and minimal cracking.
13 The deposited thickness of the dielectric layer 18 (i.e. prior to pressing) will vary with its 14 dielectric constant after sintering, and with the dielectric constant and thickness of the phosphor layer(s) 22, and of the second dielectric layer 20. The deposited thickness will also 16 vary according to the degree of increased dielectric strength that is accomplished by the 17 subsequent isostatic pressing and sintering steps. Generally the deposited thickness of the 18 dielectric layer 18 will be in the range of 10 to 300 izm, more preferably 20 - 50 ktm, and most 19 preferably 25 - 40 ,um.
Pressing is preferably accomplished by cold isostatic pressing the combined substrate, 21 electrode, dielectric layer part at a high pressure such as 10,000 -50,000 psi (70,000 - 350,000 22 kPa), prior to sintering the material, while encapsulating the part in a sealed bag with non-stick 23 materials in contact with the dielectric layer 18.. The thickness is preferably reduced by 20 to 24 50%, preferably about 30 - 40%, with a preferred thickness being about 10 - 20 kim (all numbers referred to are after sintering). This is found to reduce the surface roughness by 26 about a factor of 10 and the surface porosity by about 50%, after sintering. The final porosity 27 is less than 20% after sintering. The dielectric strength has been shown to be improved by a 28 factor of 1.5 or more after sintering. Dielectric strengths greater than 5.0 x 106 are achieved 29 after sintering. EL displays formed from isostatically pressed thick film dielectric layers in accordance with the present invention have demonstrated higher luminosity and more uniform 31 luminosity across the display, and the thick film dielectric layers, once pressed, have a much 32 reduced sensitivity to dielectric breakdown due to printing defects.

1 A thinner, second dielectric layer 20 is preferably provided above the pressed and 2 sintered dielectric layer 18 to provide a smoother surface. It is formed from a second ceramic 3 material which may have a dielectric constant less than that of the dielectric layer 18. A
4 thickness of about 1 - 10 /..tm, and preferably about 1 - 3 ktm is usually sufficient. The desired thickness of this second dielectric layer 20 is generally a function of smoothness, that is the 6 layer may be as thin as possible, provided a smooth surface is achieved.
To provide a smooth 7 surface, sol gel deposition techniques are preferably used, also referred to a metal organic 8 deposition (MOD), followed by high temperature heating or firing, in order to convert to a 9 ceramic material. Sol gel deposition techniques are well understood in the art, see for example "Fundamental Principles of Sol Gel Technology", R.W. Jones, The Institute of Metals, 1989.

11 In general, the sol gel process enables materials to be mixed on a molecular level in the sol 12 before being brought out of solution either as a colloidal gel or a polymerizing 13 macromolecular network, while still retaining the solvent. The solvent, when removed, leaves 14 a solid ceramic with a high level of fine porosity, therefore raising the value of the surface free energy, enabling the solid to be fired and densified at lower temperatures than obtainable using 16 most other techniques.
17 The sol gel materials are deposited on the first dielectric layer 18 in a manner to 18 achieve a smooth surface. In addition to providing a smooth surface, the sol gel process 19 facilitates filling of pores in the sintered thick film layer. Spin deposition or dipping are most preferred. For spin deposition, the sol material is dropped onto the first dielectric layer 18 21 which is spinning at a high speed, typically a few thousand RPM. The sol can be deposited in 22 several stages if desired. The thickness of the layer 20 is controlled by varying the viscosity of 23 the sol gel and by altering the spinning speed. After spinning, a thin layer of wet sol is formed 24 on the surface. The sol gel layer 20 is heated, generally at less than 1000 C, to form a ceramic surface. The sol may also be deposited by dipping. The surface to be coated is dipped into the 26 sol and then pulled out at a constant speed, usually very slowly. The thickness of the layer is 27 controlled by altering the viscosity of the sol and the pulling speed.
The sol may also be 28 screen printed or spray coated, although it may be more difficult to control the thickness of the 29 layer with these techniques.
The ceramic material used in the second dielectric layer 20 is preferably a ferroelectric 31 ceramic material, preferably having a perovskite crystal structure to provide a high dielectric 32 constant. The dielectric constant is preferably similar to that of the first dielectric layer 1 material in order to avoid voltage fluctuations across the two dielectric layers 18, 20.
2 However, with a thinner layer being utilized in the second dielectric layer 20, a dielectric 3 constant as low as about 20 may be used, but will preferably be greater than 100. Exemplary 4 materials include lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), and the titanates of Sr, Pb and B a used in the first dielectric layer 18, PZT and PLZT being most 6 preferred.
7 The next layer to be deposited may be one or more phosphor layers 22, as set out 8 above, and hereinbelow. However, it is possible, within the scope of this invention to include 9 additional layers of for diffusion barrier and injectivity purposes, as set out below. Phosphor layers 22 may be deposited by known thin film deposition techniques such as vacuum 11 evaporation with an electron beam evaporator, sputtering etc.
Particularly preferred is the 12 patterned phosphor structure of the present invention, as described hereinbelow.
13 A further transparent dielectric layer above the phosphor layers 22 may be included, if 14 desired, followed by the front electrode 24. The EL laminate 10 may be annealed and then sealed with a sealing layer (not shown) such as glass.
16 Diffusion Barrier Layer 17 The invention preferably provides a diffusion barrier layer 26 above the thick film 18 dielectric layer(s) 18, 20 and below the phosphor layer(s) 22, particularly the patterned 19 phosphor structure 30 described below. The diffusion barrier layer is preferably provided on both sides of the phosphor layer(s) 22, as shown in Figure 6. Alternatively, the diffusion 21 barrier layer can be provided within the patterned phosphor structure of this invention, as set 22 out in the examples below.
23 A good diffusion barrier should be free of cracks and pinholes. These can be 24 eliminated through thermal expansion coefficient matching, stress relief, and conformal coating techniques. There still may be residual diffusion due to grain boundary diffusion 26 which is dependent on the size and nature of the grains comprising the film, or crystal lattice 27 diffusion, which depends on the density of atomic vacancies. Diffusion through pinholes and 28 cracks can be distinguished from grain boundary or lattice diffusion in that it should result in 29 spatial variation of luminosity on the scale of the pinholes or cracks which increases with time rather than spatially uniform time degradation in luminosity. Grain boundary diffusion, which 31 is generally much faster than crystal lattice diffusion, can be minimized by ensuring that the 32 deposited grains in the diffusion barrier layer are as large as possible. This minimizes the areal 1 density of grain boundaries. Chemical inertness of the barrier films in contact with the 2 immediately adjacent layers is also desired to preserve the integrity of the barrier layer.
3 Phosphor luminosity stability is improved when silica, alumina or zinc sulfide 4 diffusion barrier layers are used, rather than hafnia or yttria. The improvement results even if a thin 100 A injection layer 28, comprising a different material, is interposed between the 6 barrier layer 26 and the phosphor structure 30. Thus, in accordance with the present invention, 7 the diffusion barrier layer 26 is formed from compounds which have precise stoichiometric 8 compositions. The phase diagrams for the silicon-oxygen, aluminum-oxygen and zinc-sulphur 9 binary systems show that alumina, silica, and zinc sulfide exist only as precisely stoichiometric compounds. By contrast, the yttria-oxygen and hafnium-oxygen phase diagrams show that 11 yttria can exist up to about 1 atomic percent deficient in oxygen, and hafnia can exist up to 12 about 3 atomic percent deficient in oxygen. Thus, these latter two materials, when deposited 13 as coatings, likely have a significant oxygen deficiency. Comparison of the experimental 14 stability data with the stoichiometry of the diffusion barrier layer provides evidence that precise stoichiometric ceramic materials provide effective diffusion barriers.
16 Based on the above, materials suitable as diffusion barriers can be predicted. Metal-17 containing electrically insulating binary compounds (dielectrics) that are inert in the presence 18 of adjacent layers and can be deposited without cracks or pinholes and are precisely 19 stoichiometric are preferred materials. The latter aspect can be ascertained by examining binary phase diagrams for materials. Compounds providing the lowest lattice diffusion are 21 those for which the compounds exist only over a very small range of the ratio of their 22 constituent elements, preferably less than 0.1 atomic percent deviation from the stoichiometric 23 ratio. A deviation from the stoichiometric ratio will entail the formation of vacancies in place 24 of the deficient element. Among the materials known in the art as dielectric materials for electroluminescent displays, alumina, silica and zinc sulfide are examples of such 26 stoichiometric compounds.
27 Injection Layer 28 The present invention may include an injection layer 28 above the diffusion barrier 29 layer 26, next to the phosphor layer(s) 22, particularly with the patterned phosphor structure 30 described below. The layer is preferably provided on both sides of the phosphor layer(s) 22, in 31 contact with the phosphor layer(s) 22. Alternatively, or as well, the injection layer may be 32 provided within the patterned phosphor structure of this invention, as set out in the examples 1 below.
2 A feature of this invention is the discovery that the selection criteria for injection layer 3 materials are different than for diffusion barrier materials, so a better combined utility can be 4 obtained by providing the diffusion barrier and injection layer characteristics using two distinct layers for these functions. This does not preclude the possibility that with some thick film 6 dielectric compositions and/or some phosphor compositions, acceptable diffusion barrier and 7 injection characteristics might be found in the same material.
8 The purpose of this layer is to provide efficient injection characteristics for electrons 9 injected into the phosphor. The purpose is to maximize the number of electrons per unit area of the phosphor that are injected into the phosphor within a preferred energy range so as to 11 maximize the electro-optical energy efficiency associated with the injection of electrons into 12 the phosphor and the subsequent conversion of that energy into light.
Generally, this can be 13 accomplished by designing the injection layer phosphor interface so that a maximum number 14 of electrons at the interface are in states with a narrow range of energies that result in the most efficient electro-optic efficiency. The literature reveals data on a large number of such 16 interfaces. With ZnS phosphors, it is found that hafnia and yttria provide higher injection 17 efficiencies than do silica and alumina. With SrS:Ce, it is found that pure ZnS provides a 18 somewhat higher efficiency than does alumina, hafnia, or silica, although this may be because 19 ZnS has a better compatibility with SrS:Ce, making the ZnS layer more of a diffusion barrier layer in its function. In general, the injection layer 28 is a dielectric, binary material which is 21 non-stoichiometric in its composition, that is having greater than about 0.5% atomic deviation 22 from its stoichiometric ratio, so as to have more electrons within a preferred range of energy 23 for better injection efficiency.
24 Patterned Phosphor Structure The patterned phosphor structure of this invention is shown generally at 30 in Figures 26 2, 5 and 6. It is described below in the examples, Example 2 being directed to a two layer 27 patterned phosphor structure, and Examples 3, 4 and 5 being directed to a single layer 28 patterned phosphor structure.
29 An EL laminate 10 incorporating the patterned phosphor structure 30 of the present invention will preferably include all of the layers of the EL laminate 10 as set out above. The 31 description of the patterned phosphor structure 30 is provided for one or a few pixels, but of 32 course multiple pixels are repeated cyclically across the EL laminate 10 of an EL display. In 1 that respect, three sub-pixels of row and column electrodes together form a single pixel, 2 aligned with the red, blue and green phosphor sub-pixel elements 30a, 30b and 30c 3 respectively, and the red, blue and green filters 25a, 25b, and 25c respectively.
4 The patterned phosphor structure 30 is formed on the dielectric layer 18 or 20, or more preferably above any barrier diffusion and injection layers 26 and 28, by depositing and 6 patterning two or more phosphors emitting light in different ranges of the visible spectrum in 7 at least one layer to form a plurality of repeating phosphor deposits arranged in adjacent, 8 repeating relationship to each other. The patterning may be accomplished by photolithography 9 or by shadow mask patterning, however photolithography is preferred. In accordance with this invention, a photolithography method with a negative photoresist and lift-off procedure 11 involving as few as one photo-mask is used. This process is particularly advantageous for 12 patterning moisture sensitive strontium sulfide phosphors along with zinc sulfide phosphors, 13 but has application for other colour phosphors, particularly for alkaline earth metal sulfide or 14 selenide phosphors which are subject to hydrolysis.
A first layer of a first phosphor is deposited by known techniques to form one or more 16 of the red, green or blue sub-pixel elements. Preferably, the first layer is a strontium sulfide 17 phosphor, to form the blue, or the blue and the green sub-pixel elements. A negative 18 photoresist is applied to this first phosphor layer, followed by exposure through a photo-mask 19 designed to expose either the blue, or the blue and green, sub-pixel elements.
A negative resist is used due to its superior stability at the elevated temperatures to 21 which the resist is exposed during subsequent processing, and its ability to be used with non-22 aqueous solutions. A negative resist based on polyisoprene is preferred.
Alternative negative 23 resists such as those based on polyimide can also be used, as can positive resists if they are 24 first subject to deep ultraviolet curing before being exposed to high temperature. Positive resists that can be exposed using e-beam writing rather than light exposure may also be used, 26 particularly if very high resolution patterning is desired.
27 The exposure process requires the use of only one mask through all of the phosphor 28 pattering steps, simplifying the process over multi-mask processes commonly used in 29 photolithography. Negative resists have the property that they can be rendered insoluble in developer chemicals when they are exposed to light. Accordingly, the patterning mask is 31 designed to allow exposure of the resist over the regions corresponding to the blue, or the blue 32 and green, sub-pixel elements.

1 Following exposure, the resist is developed, rinsed and de-scummed, prior to acid 2 etching to remove the phosphor in the regions which are to form the red and green, or the red, 3 sub-pixel elements. Etching is preferably preceded by first immersing in a polar, non-aqueous, 4 organic solvent, preferably methanol, in order to permeate the pores of the phosphor. Etching is accomplished with an etchant solution which includes a mineral acid, or a source of anions 6 of a mineral acid, in a non-aqueous, polar, organic solvent which solubilizes the reaction 7 product of the first phosphor with anions of the mineral acid. By non-aqueous is meant a 8 solvent which has less than 1% by volume water, preferably less than 0.5%
water. Mineral 9 acids include hydrofluoric acid, hydrochloric acid, sulfuric acid, nitric acid, phosphoric acid, and hydrobromic acid, or mixtures thereof, with hydrochloric acid and phosphoric acid being 11 most preferred. The non-aqueous, polar, organic solvent is most preferably methanol. The 12 mineral acid is preferably used from its concentrated form in the etchant solution in order to 13 limit the amount of water which is included. Generally, the amount of concentrated mineral 14 acid is in the range of 0.1 to 1% by volume. The part with the first phosphor is immersed in this etchant solution to dissolve the areas of unexposed strontium sulfide.
Etchant solutions of 16 0.5% HC1 in methanol, or 0.1% HC1 and 0.1% H3PO4 in methanol, are exemplary of preferred 17 embodiments.
18 A second phosphor, or optionally a second and a third phosphor, for the red and green, 19 or the red, sub-pixel elements is deposited over both the first phosphor, overlaid with the exposed resist, and the regions where the first phosphor has been removed.
Preferably the 21 second, or second and third, phosphors are zinc sulfide phosphors. At this point, additional 22 layers such as injection layers, or threshold voltage adjustment layers may be deposited above 23 the second, or above the second and third, phosphors. Alternatively, such additional layers 24 may be deposited before the first phosphor deposition, or after removal of the first phosphor, depending on their desired placement. A still further alternative is to deposit such additional 26 layers between the second and third phosphors. This photolithographic method allows for a 27 wide degree of flexibility.
28 The second phosphor layer, and any third phosphor or additional layers, are selectively 29 removed from the regions above the first phosphor by a lift-off step.
Preferably a solvent solution is used which is predominantly a polar, aprotic solvent, and which will allow removal 31 of the resist in a time which is sufficiently fast that it does not cause significant hydrolysis of 32 the phosphors. For lift-off of a zinc sulfide phosphor, a solution of a minor amount (up to 1 50%, preferably about 5 to 20%, most preferably about 10% by volume) of methanol in 2 toluene is particularly preferred. Other non-aqueous, polar, aprotic solvents such as 3 acetonitrile, diethyl carbonate, propylene carbonate, dimethyl ether, dimethyl formamide, 4 tetrahydrofuran and dimethyl sulfoxide might also be used, depending on the particular phosphors involved. The particular solvents used are chosen to minimize hydrolysis of the 6 phosphors while still removing the resist in a reasonable time period.
7 This first layer of the patterned phosphors may then be covered by another layer of a 8 phosphor material which is the same as or different from the first, second, or third phosphors, 9 in order to achieve the desired threshold voltages and luminosities for the sub-pixel element.
Alternatively, the threshold voltages and the luminosities for the sub-pixel elements may be set 11 with appropriate threshold voltage adjustment layers deposited below, between or above the 12 phosphors. In addition, or as a further alternative, the thicknesses of the phosphor deposits 13 may be varied to equalize the threshold voltages and to set the desired relative luminosities of 14 the sub-pixel elements. A still further or additional alternative to the above is to adjust one or more of the areas of the sub-pixel elements, or the compositions of the phosphors and dopants, 16 in order to achieve the desired threshold voltages and relative luminosities of the sub-pixel 17 elements.
18 The photolithographic method of this invention allows great flexibility in the 19 adjustment of the above parameters and/or layers in order to individually set the desired threshold voltages and relative luminosities of the sub-pixels elements.
21 Above the patterned phosphor structure 30 may be formed a second dielectric layer 28 22 and a patterned transparent conductor to define column electrodes 24 perpendicular to the row 23 electrodes 14 positioned beneath the phosphor structure 30.
24 When ZnI,MgxS:Mn is used as a phosphor, the value of x is preferably between about 0.1 and 0.3, more preferably between about 0.2 and 0.3. When SrS:Ce is used as a phosphor, 26 it may be codoped with phosphorus.
27 a) Factors Affecting Pixel Performance 28 This section is included to provide guidance for the criteria relating to the choice of 29 phosphors and the particular thicknesses to be used in the sub-pixel elements. In the following section, the thickness criteria are discussed for particular preferred, and exemplary phosphors.
31 A high pixel energy efficiency is required to obtain a high luminosity and a high 32 overall energy efficiency for an electroluminescent display. The pixel energy efficiency is 1 defined as the ratio of light power within the desired wavelength range radiated from the 2 surface of a pixel divided by the electrical power input to the pixel.
The light power, 3 expressible in watts per square meter, can be directly related to the luminosity of the pixel 4 expressed in candelas per square meter using well known relationships.
These relationships are a function of the angular distribution of light from a sub-pixel as well as a wavelength 6 factor accounting for the sensitivity of the human eye to different colours or wavelengths of 7 light. The following discussion details the factors that affect the pixel energy efficiency. This 8 efficiency can be expressed as the product of several independent factors. These are defined 9 here as the electron injection efficiency, the electron multiplication efficiency, the activator excitation efficiency, the radiative decay efficiency and the light extraction efficiency. Four of 11 these five factors are dependent on the thickness of the phosphor film as discussed below.
12 1. Electron Injection Efficiency 13 The electron injection efficiency is defined herein as the ratio of the energy flux of hot 14 electrons injected into the phosphor layer of a display sub-pixel to the electrical power input to that sub-pixel. Generally, injection occurs by electrons tunnelling into the phosphor from 16 surface states at or near the interface between the phosphor and the immediately adjacent 17 dielectric layer. With reference to the numbers in Figure 9, typically, the energy of the 18 electrons in the surface states, shown at 32, lies below the bottom of the electron conduction 19 band in the phosphor material. When an electric potential is applied across the phosphor, the conduction band bottom, shown at 34, decreases linearly with distance away from the 21 interface, shown at 36. The slope of this linear decrease is proportional to the applied 22 potential, and inversely proportional to the phosphor thickness.
Tunnelling will occur if the 23 distance (shown as the tunneling distance 38), between the interface 36 and the first point at 24 which the bottom of the conduction band 34, is approximately equal to the energy of an electron in a surface state 32, and is sufficiently small, generally of the order of a few 26 nanometers. This distance can be reduced to the point where tunnelling occurs by increasing 27 the potential across the phosphor layer or decreasing the phosphor thickness for a fixed 28 potential.
29 Not all of the injected electrons that are injected will be "hot"
electrons. In general, there will be a distribution of energies for the surface electrons that can be injected into the 31 phosphor layer. If the energy difference between a surface electron and the bottom of the 32 conduction band is too small, the electron will be injected into the phosphor with a low energy.

1 Low energy or "cold" electrons tend to interact strongly with the phosphor host material and 2 lose their energy without light being generated. Thus, the fraction of hot or light-generating 3 electrons is related to the energy distribution of surface electrons. The surface electron energy 4 distribution is a function of the phosphor and immediately adjacent dielectric materials used.
The electron injection model described above can be distorted by the presence of trapped 6 positive or negative charges within the phosphor layer that can produce deviations from the 7 assumed constant electric field across the phosphor. Nevertheless, the general principles for 8 optimizing the hot electron injection efficiency by selecting an appropriate phosphor thickness 9 remain the same.
For a defined potential across the phosphor layer the electron injection efficiency in 11 general should decrease as a function of phosphor thickness because the injection tunnelling 12 probability will decrease due to decreased electric field strength. The potential across a sub-13 pixel is normally selected in terms of the voltage and current delivery capability of the 14 electronic circuitry used to operate the sub-pixel and the threshold voltage desired for sub-pixel operation. The fraction of this voltage across the phosphor layer is a function of the 16 thickness and dielectric constant of the phosphor and of the dielectric layers used in 17 conjunction with the phosphor layer, as previously discussed. The injection efficiency 18 decreases when the tunnelling probability drops because a larger fraction of the power input to 19 the pixel is dissipated due to resistive and dielectric hysteresis losses in the dielectric layers of the pixel as well as resistive loss in the conductors supplying electrical current to the sub-21 pixel. These sources of loss can be minimized through the use of dielectric layers having a 22 high dielectric constant as discussed above.
23 2. Electron Multiplication Efficiency 24 The electron multiplication efficiency is defined here as the energy conversion efficiency associated with the generation of a large number of hot electrons through the 26 electron multiplication process described below from a lesser flux of injected hot electrons 27 Electron multiplication depends on a phenomenon whereby an electron accelerated in 28 the phosphor host material in response to the applied electric field can cause a second electron 29 to be extracted from the valance band where it is immobile into the conduction band. The second electron can then also be accelerated in response to the applied field.
For this to occur, 31 the initial electron must have energy at least equal to twice the band gap energy above the top 32 of the valence band, shown at 40 in Figure 9. Electron multiplication is a cascading process 1 that can produce a large number of accelerating electrons from a few injected electrons. The 2 multiplication factor increases as the applied potential across the phosphor layer is increased.
3 For a fixed potential across the phosphor the electron multiplication efficiency should be 4 highest for relatively thin phosphor layers where the electric field strength is relatively high and the distance electrons travel between multiplication events is relatively low. The reduced 6 distance of travel lowers the probability that the electrons will scatter from the phosphor host 7 crystal lattice so that they lose energy and fall out from the cascading process. Electron 8 multiplication is useful particularly if the density of injection electrons is relatively low.
9 The electron multiplication and charge injection processes will be affected by positive charges (holes) created when electrons are promoted from the valence band to the conduction 11 band of the phosphor host material. These charges should be able to migrate in response to the 12 applied potential in the opposite direction, to the interface from which the initial electrons 13 were injected. Facilitation of this migration minimizes the buildup of charge within the 14 phosphor film that will tend to distort the electric field within the phosphor that is induced by the applied potential. The hole-migration rate may be increased if the phosphor layer is 16 relatively thin and the driving electric field is relatively large.
17 3 Activator Excitation Efficiency 18 The activator excitation energy is defined here as the fraction of hot electrons that 19 cause an electron on activator atoms to be promoted to a more energetic or excited state.
The light emitting centers or activators in a phosphor are dopant atoms dispersed 21 throughout the host material, the electrons of which are promoted to an excited state when a 22 hot electron collides with them. The electrons in the excited atoms then can return to their 23 normal ground state, causing a photon to be emitted. The excitation process is called 24 activation. The luminosity of a phosphor is proportional to the rate at which photons are generated. This rate is in turn proportional to the flux of hot electrons incident on the dopant 26 atoms, which is controlled by the factors discussed in the previous paragraphs. The efficiency 27 of the activation process is related to the cross section presented by the dopant atoms to the 28 incident hot electrons. This efficiency is mostly determined by the local environment of the 29 dopant atoms in the host material of the phosphor, and is not likely strongly affected by the phosphor thickness.
31 4. Radiative Decay Efficiency 32 The radiative decay efficiency is defined herein as the fraction of excited dopant atoms 1 that decay to their ground state, emitting a photon with an appropriate energy to contribute to 2 sub-pixel luminosity.
3 When a dopant atom is activated, it can return to its initial or ground state by a variety 4 of processes, of which only some result in the generation of a photon contributing to the phosphor luminosity. The photon must have an energy corresponding to the wavelength range 6 for the colour of light desired (red, green or blue) to be counted as effectively contributing to 7 the luminosity. One of the factors affecting the radiative decay efficiency is the local electric 8 field present at the dopant atom site. This in turn relates back to the phosphor thickness, as 9 well as to the total potential across the phosphor layer. In general, if the electric field strength is too high, a process called field quenching occurs, whereby the excited electrons in the 11 dopant atom have an increased probability of being removed from that atom and injected into 12 the conduction band of the host material. The removed electrons eventually lose their energy 13 in a collision process that does not result in photon emission, resulting in a reduction in 14 radiative decay efficiency. The presence of a high, externally applied electric field at the dopant atom site might also alter the wavelength of any emitted photons, moving it in or out of 16 the range where the photon contributes to the desired colour.
17 Generally, the radiative decay efficiency should be highest when the local electric field 18 strength is below the value at which field quenching can occur. For a fixed potential across 19 the phosphor layer, the field strength is reduced if the phosphor thickness is increased.
5. Light Extraction Efficiency 21 The light extraction efficiency is defined herein as the fraction of photons within the 22 required energy range to contribute to sub-pixel luminosity generated within the phosphor that 23 are transmitted through the front surface of a sub-pixel, thus directly contributing to useful 24 luminosity.
Not all of the light generated by activators within the phosphor material is extracted 26 from the phosphor layer to provide useful luminosity. Typically, some of the light generated 27 within the phosphor may reflect internally from the phosphor surfaces, or from any other 28 interface within the sub-pixel structure. There may be multiple reflections of this nature 29 before the light is transmitted through the upper surface of the sub-pixel structure thus contributing to useful luminosity. The longer the optical path that the photons travel before 31 escaping the pixel structure, the greater is the probability that the light will be absorbed within 32 the sub-pixel structure, causing a reduced light extraction efficiency.
Even if there are no 1 internal reflections, light may still be absorbed along the direct path between the activator 2 atoms from which the light originates and the outer surface of the phosphor. The probability 3 of absorption increases as the thickness of the phosphor layer is increased, so the light 4 extraction efficiency, from this standpoint, is decreased when the phosphor thickness is increased. The probability of reflections (reflection coefficient) at the phosphor surfaces is 6 related to the difference in the index of refraction of the phosphor material and the adjacent 7 layers in the sub-pixel structure. This is an intrinsic property of the materials, and is not 8 dependent on thickness. However, if the phosphor thickness should become sufficiently thin as 9 compared to the wavelength of light in that material, then the reflection coefficient may have a dependence on individual layer thickness within the phosphor and other layers that are part of 11 the sub-pixel structure. Any such dependence is not readily predicable from theory, but can be 12 experimentally determined.
13 6. Total Pixel Energy Efficiency 14 The total pixel energy efficiency is the product of the five efficiency factors defined and described in the preceding paragraphs. For some of these factors, efficiency is an 16 increasing function of phosphor layer thickness, and for others it is a decreasing function of 17 phosphor thickness. Achieving an overall efficiency optimization is a complex process 18 involving many parameters, and in the end the optimum thickness of individual phosphors in a 19 sub-pixel structure may be determined experimentally, using the considerations discussed above as a guide. Typically, the pixel energy efficiency will have a maximum as a function of 21 phosphor thickness due to the trade off between the five contributing factors. The shape of 22 this efficiency curve is dependent on many parameters, and the overall optimum phosphor 23 thickness and operating voltage to achieve maximum luminosity and electro-optic efficiency 24 can be determined experimentally, using the scientific principles discussed above as a guide.
b) Criteria for Selecting Phosphor Deposit or Threshold Voltage Adjustment Layer 26 Thicknesses and Areas of Sub-pixels 27 The performance of a pixel employing a patterned phosphor structure can be optimized 28 through a judicious choice of design parameters. These parameters include the compositions 29 of the phosphors and the dopant concentrations, the relative areas of the sub-pixels and the thickness of the phosphor deposits and any additional threshold voltage adjustment deposits of 31 dielectric or semiconductor materials incorporated into one or more of the sub-pixel elements 32 for the purpose of ensuring that the relative luminosities of the sub-pixel elements bear set 1 ratios to one another at each modulation voltage used, to enable colour balance control for a 2 pixel by setting the colour coordinates for the sub-pixels, most preferably enabling gray scale 3 capability, for full colour. Optimum parameters can be selected by following the steps 4 outlined below:
1. Select the sub-pixel areas, choosing between:
6 i. Equal areas for each sub-pixel 7 ii. Equal areas for each sub-pixel, but including more than one sub-pixel for one 8 or two of the three colours 9 iii. Variable areas selected to maximize total luminosity with the required colour balance, but constrained to a value between a minimum and a maximum width.
11 iv. Variable areas for each sub-pixel and more than one sub-pixel for one or two of 12 the three colours.
13 The selection of the preferred options is on the basis of a trade-off between achieving 14 the maximum possible luminosity, achieving the desired colour coordinates for the sub-pixels using appropriate red, green and blue filters, achieving gray scale operation, avoiding 16 difficulties with uneven electrical loading of the row and column drivers and ease of 17 fabrication considerations. The selection of more than one sub-pixel for a single colour rather 18 than a single sub-pixel with increased area is governed by a desire to keep the load impedance 19 seen by row or column drivers above a critical value below which the luminosity of some sub-pixels may be lower than intended due to a voltage drop caused by excessive current flow from 21 the driver. In this situation, gray scale fidelity may be impaired and undesirable image 22 artifacts may be created. If the load impedance of a set of sub-pixels driven by one driver is 23 too low, the load can be shared by more than one driver by selecting more than one sub-pixel 24 per colour. Independently addressable sub-pixels within a single pixel can be created by incorporating one or more rows and one or more columns within the pixel. One possible sub-26 pixel arrangement is a "quad-pixel" containing four pixels defined by the intersection of each 27 of two columns and two rows. In this arrangement, two of the pixels can be assigned to one 28 colour.
29 2. Determine the phosphor deposit thicknesses for the performance limiting sub-pixel using the steps given below. These steps are independent of the choice of sub-pixel options i.
31 to iv. above.
32 A. Determine the optimum threshold and total driving voltages for the pixel. This 1 choice is governed by considerations of the available driver electronics, the 2 desired sub-pixel luminosities and the desired energy efficiency. Generally, the 3 highest feasible threshold and total voltage will give the highest luminosity.
4 Typically, threshold voltages of up to 200 V and modulation voltages up to 60 V can be provided, giving a maximum operating voltage of about 260 V. It is 6 desirable that the threshold voltage for all sub-pixels be equal so that the 7 maximum threshold voltage can be applied to the rows, consistent with having 8 no emission from any pixel when zero modulation voltage is applied. This 9 facilitates full gray scale control and minimizes overall power consumption as discussed above.
11 B. Determine a thickness of each phosphor deposit to be used for each sub-pixel 12 that will give the desired threshold voltage, consistent with providing the 13 desired colour coordinates and luminosity. It one embodiment of this invention 14 a two layer phosphor structure is used (see Example 2). There, it is found experimentally that a deposit of SrS:Ce ,with 0.1% Ce dopant, with a thickness 16 between about 1.4 and 1.8 gm is appropriate for the blue sub-pixel for the 17 voltages given above. Co-doping of this phosphor with phosphorous to provide 18 charge compensation for the cerium may have the effect of increasing the 19 threshold voltage by about 25%. Two layers of phosphor deposits comprising about 0.7 to 0.9 ',cm of SrS:Ce and about 0.35 to 0.45 ktm of ZnS:Mn are 21 appropriate for the red and green sub-pixels at similar voltages. The correct 22 colour coordinates can be achieved through the use of appropriate filters for red 23 and green. In other embodiments, a single layer of patterned phosphor deposits 24 is used. In Example 3, it is found experimentally that an SrS:Ce deposit of 1.2 to 1.4 ,um is appropriate for the blue sub-pixels, while a deposit of Zni_ 26 xMgõS:Mn of 0.3 to 0.5 kim is appropriate for the green and red sub-pixels. In 27 Example 4, the red and green sub-pixels can be formed from three stacked 28 phosphor deposits of 0.4 to 0.6 ,um of ZniMgõS:Mn sandwiched between two 29 0.08 to 0.1 gm layers of ZnS:Mn. In Example 5, a deposit of 1.2 to 1.4 ,um of SrS:Ce can provide both the green and blue sub-pixels, while a 0.4 to 0.5 ,um 31 deposit of ZnS:Mn can provide the red sub-pixels. In the foregoing, the 32 suggested compositions and thickness ranges are dependent on the physical and 1 electroluminescent properties of the phosphor layers, as well as on the electrical 2 characteristics of the threshold voltage adjustment layers and any additional 3 dielectric layers, and so variations may be expected, depending on the specific 4 properties of the materials employed.
C. Identify which of the sub-pixels defined above will have the lowest luminosity 6 relative to the required luminosity to give the desired pixel colour balance. The 7 thickness of each phosphor deposit for this sub-pixel is then selected to be that 8 determined for this sub-pixel in step B.
9 3. Determine the area of the remaining sub-pixels and the thickness of their phosphor and other threshold voltage adjustment layers. If the option of equal sub-pixel areas has been 11 selected, steps D and E should be followed. If equal areas and more than one sub-pixel for at 12 least one colour is selected, steps J and K should be followed, provided that the sub-pixel 13 dimensions determined fall between the specified minimum and maximum values. If variable 14 areas have been selected using steps J and K, and the dimensions do not fall between the specified minimum and maximum values, steps L and P should be followed instead.
16 D. find the thickness of each of the phosphor deposits for each remaining sub-17 pixel that gives the desired colour coordinates and the desired luminosity 18 relative to the performance limiting sub-pixel. The threshold voltages for these 19 sub-pixels should in general be lower than that for the performance limiting sub-pixel.
21 E. Determine the thickness of a dielectric or semi-conductor deposit required for 22 increasing the threshold voltage for these sub-pixels to the threshold voltage of 23 the performance limiting sub-pixel. This deposit can be disposed under, over, 24 or in the case where more than one phosphor deposit is employed, between phosphor deposits, with the order of the deposits selected on the basis of ease of 26 fabrication considerations, or on the basis of physically isolating incompatible 27 deposits from one another.
28 F. Decide which colours will have more than one sub-pixel. This will typically 29 be the performance-limiting colour.
G. With the increased number of sub-pixels for the original performance limiting 31 colour, re-assess which colour is the performance limiting one, and select the 32 thickness of its phosphor deposits as outlined in step B.

1 H. Determine the thickness of the phosphor deposits for the remaining sub-pixels 2 to give the desired luminosities relative to the performance limiting sub-pixel.
3 I. Determine the thickness of a threshold voltage adjustment layer required to 4 increase the threshold voltage of the remaining sub-pixels relative to that of the performance limiting sub-pixel.
6 J. Select the thickness of all phosphors to make their threshold voltage equal with 7 reference to steps B and C.
8 K. Adjust the sub-pixel areas to achieve the desired relative luminosities.
9 L. Calculate the sub-pixel areas to achieve the desired relative luminosities.
M. Determine which areas require dimensions outside of the specified range, and 11 adjust them up or down accordingly.
12 N. Taking into account the adjusted sub-pixel areas, reevaluate which colour is the 13 performance limiting colour, and select the thickness for each of its phosphor 14 deposits as determined in step B.
0. Select the thickness of the remaining sub-pixels to achieve the desired relative 16 luminosities.
17 P. Select a dielectric or semiconductor deposit to adjust the threshold voltages of 18 the remaining sub-pixels to that of the performance limiting sub-pixels as in 19 step E.
c) Exemplary Application of Selection Criteria 21 Application of the above selection criteria is shown below for a two layer phosphor 22 structure in which the threshold voltage and luminosities are set by a layer of SrS:Ce above a 23 patterned layer of SrS:Ce and ZnS:Mn.
24 1. Total SrS:Ce Thickness The combined thickness of the SrS:Ce layers on the blue sub-pixel is determined on 26 the basis of the desired threshold voltage for the display. This is in turn dictated by the row 27 and maximum column voltages and concomitant currents for full luminosity that can be 28 provided by the display driver electronics. Typically, row drivers can provide a maximum 200 29 V output for the threshold voltage and column drivers can provide a maximum 60 V
modulation voltage. It is found experimentally that a 0.1% cerium doped strontium sulfide 31 layer with a thickness between about 1.4 and 1.8 microns is appropriate for these voltages. In 32 some cases the strontium sulfide is co-doped with phosphorus in the same molar proportion as 1 cerium to provide charge compensation. Charge compensation may be provided because, 2 relative to the host atomic species, cerium is deficient one electron per cerium atom.
3 Phosphorus has one excess electron per phosphorus atom and can compensate for the missing 4 electron from the cerium. Phosphorus induced charge compensation is thought to inhibit spontaneous charge compensation through the creation of atomic vacancies that can change 6 the properties of the phosphor, and possibly reduce the electroluminescent efficiency of the 7 phosphor. Phosphorus co-doping may have the effect of increasing the threshold voltage by 8 about 25% and so this difference must be taken into account in establishing the strontium 9 sulfide layer thickness.
2. The ZnS:Mn Thickness 11 The ZnS:Mn layer thickness on the red and green pixels is determined on the basis of 12 providing the correct red to green to blue luminosity ratio of 3:6:1 at full luminosity.
13 Generally, the limiting luminosity from ZnS:Mn is the green luminosity.
The patterned 14 phosphor structure of this invention makes use of the combined green emission from the ZnS:Mn and the SrS:Ce covering the green sub-pixel. Accordingly, the ZnS:Mn thickness is 16 determined from the required blue to green ratio of 1:6 at the total applied voltage (sum of the 17 threshold and modulation voltage) for full luminosity. The green emission is also dependent 18 on the thickness of the second SrS:Ce layer overlying the green sub-pixel, so the thickness of 19 this layer is dependent on the choice of the thickness of the first SrS:Ce layer as discussed below. The net green luminosity is also dependent on the optical absorption in the filter used 21 to obtain satisfactory colour coordinates for the green pixel.
Accordingly, some experimental 22 optimization is required to select the ZnS:Mn thickness. For the total applied voltage in this 23 example, a ZnS:Mn layer thickness in the range of 0.35 to 0.45 ,um is satisfactory. The correct 24 red luminosity can be obtained by selecting an appropriately attenuating red filter.
3. The First SrS:Ce Layer Thickness 26 The thickness of the first SrS:Ce layer is chosen to match the threshold voltage for the 27 three sub-pixels and thus depends on the ZnS:Mn thickness chosen above.
It is desirable that 28 the threshold voltages be equal so that the maximum threshold voltage can be applied to the 29 rows, consistent with having no emission from any pixel when zero modulation voltage is applied. This facilitates full gray scale control and minimizes overall power consumption as 31 discussed above. The optimum thickness for the first SrS:Ce layer is in the range of about 0.7 32 to 0.9 for this example. In all of the foregoing, the specified ranges are dependent on the 1 physical and electroluminescent properties of the phosphor layers, as well as on the electrical 2 characteristics of the encapsulating dielectric layers, and so variations may be expected, 3 depending on the specific properties of the materials employed.
4 d) Patterned Phosphor Fabrication Process The patterned phosphor structure 30 is described below in Examples 2 - 5, with 6 reference to preferred materials and conditions, to fabricate a pixel having red, green and blue 7 sub-pixels phosphor elements 30a, 30b, and 30c with component red, green and blue colours.
8 The process and structure are not limited by these examples, but are amenable to the 9 fabrication of EL displays with different construction and having a wide variety of pixel sizes, ranges of pixel counts, and types of phosphors. The patterned phosphor structure is described 11 in combination with preferred thick film dielectric layers, phosphors, threshold voltage 12 adjustment layers, barrier diffusion layers, and injection layers, as described above.
13 The present invention is further illustrated by the following non-limiting examples.
14 Examples Example 1 - Isostatically Pressed Thick Film Dielectric Layer 16 A first layer of Heraeus CL90-7239 (TM - Heraeus Cermalloy, Conshohocken, PA) 17 high dielectric constant paste was screen printed using a 98 wires/cm (250 mesh) screen 18 having 1.6 mil wire diameter. The high dielectric constant material in the paste was PMN-PT.
19 The printed paste was dried for between 30 and 60 minutes at 150 C, with the longer times for a more heavily loaded oven. A second layer of the same material was printed over the baked 21 first layer and then baked in at 300 C for 30 min. The thickness of the combined layers at this 22 point was about 26 gm. The entire structure was next cold isostatically pressed (CIPped) 23 using a cold isostatic press at 350,000 kPa (50,000 psi). To ensure adequate pressing and to 24 develop a relatively smooth surface on the dielectric layer, a sheet of aluminized polyester, with the aluminized surface in contact with the dielectric, was laid over the dielectric surface.
26 A further two sheets of plastic bagging material were then folded around the part, so as to 27 isolate the part from an outer, compliant sealing bag to prevent the sealing bag from tearing.
28 The sealing bag was evacuated of air and hot sealed. The bag was isostatically pressed at the 29 indicated pressure and held at that pressure for no more than 60 seconds. After pressing the part was removed from the bag and fired in a belt furnace using a typical thick film 31 temperature profile with a peak temperature of 850 C. After pressing and firing the dielectric 32 material was essentially non-porous. The thickness of the dielectric layer at this point was in 1 the range of 15 - 20 pm, typically 16 pm.
2 To test the compressed thick film dielectric layer, it was fashioned into a capacitor 3 between 1 cm2 metal electrodes evaporated onto its surface. An AC, 60 Hz signal was applied 4 until dielectric breakdown was observed. Testing six samples, gave the following results in Table!.
6 Table 1: Improved Dielectric Properties of Isostatically Pressed Thick Film Dielectric Layer 7 Dielectric Thickness Capacitance/cm2@ 1 kHz Breakdown Voltage 8 UnaPped 24pm 0.120 pF/cm2 80 - 90 V
9 CIPped 16pm 0.156 pF/cm2 140 - 160 V
11 Based on the above data, using a dielectric constant of 3300 for the unCIPped material, 12 the dielectric strength is roughly calculated as 3 x 106 V/m. Using a dielectric constant of 13 2800 for the ClPped material, the dielectric strength is roughly calculated as 107 V/m.
14 To further smooth the surface of the dielectric layer, a second dielectric layer comprising lead zirconium titanate was applied using sol gel precursor materials, as described 16 in Example 3 of U.S. Patent 5,432,015. The thickness of this sol gel layer was about 2 pm.
17 Example 2 - Two Layer Patterned Phosphor Structure 18 Reference may be had to Figure 6 for the EL laminate of this example.
19 2.1. Thick Film Substrate Layers The purpose of the thick film substrate is to provide a mechanical support, a first pixel 21 electrode, and a thick film dielectric layer to electrically isolate the electrode from the 22 phosphor structure. The electrical isolation is required to provide a means to control the 23 density of current over a large area of pixels. The current control results from the injection of 24 localized charge into the phosphor structure from the vicinity of the interface between the phosphor and a dielectric material in contact with it, rather than from the electrode itself. The 26 dielectric layer has a high dielectric constant to minimize the voltage drop across it when a 27 voltage is applied between the pixel electrodes, and a dielectric strength sufficient to prevent 28 an electric breakdown of the dielectric when an appropriate voltage is applied between the 29 pixel electrodes. The teachings of U.S. Patent 5,432,015 to Wu et al., describe the thick film substrate in greater detail.
31 a) Rear Ceramic Substrate and Rear Electrode 1 The rear substrate was a 0.63 mm thick 96% purity alumina sheet (Coors Ceramics, 2 Grand Junction, Colorado, USA). This material typically is used for the fabrication of thick 3 film hybrid electronic circuits. A 0.3 kim thick gold electrode with provision for making an 4 electrical contact as shown in Figure 5 was first deposited on the alumina substrate. The alumina was unpolished to provide sufficient surface roughness to facilitate an adequate 6 bonding strength for the gold layer. The gold electrode was screen printed using Heraeus RP
7 20003/237 - 22% organometallic paste (Heraeus Cermalloy) to form row electrodes and then 8 fired at 850 C using standard manufacturers thick film methods to form the finished gold film.
9 b) Thick Film Dielectric Layers The next step was to apply a thick film dielectric layer. This layer was fabricated in 11 two individual layers, a screen printed and isostatically pressed dielectric layer, and a 12 smoothing sol gel layer, as set out in Example 1. The thick film dielectric layer had a fired 13 thickness of 15 - 20 m, while the sol gel layer had a thickness of about 2 kt.
14 2.2. Diffusion Barrier Layer A 300 A alumina layer was e-beam evaporated onto the surface of the lead zirconium 16 titanate layer. The alumina film was deposited with the substrate at 150 C and the deposition 17 rate was 2 A/sec. The purpose of this layer was to prevent diffusion of atomic species in the 18 thick film dielectric into the phosphor layer.
19 2.3. Injection Layer A 100 A hafnia layer was e-beam deposited onto the alumina diffusion barrier layer.
21 The hafnia layer was deposited with the substrate at 150 C and was deposited at a rate of 1 22 A/sec.
23 2.4. Patterned Phosphor Structure 24 a) First SrS:Ce Layer A first SrS:Ce layer was deposited with a thickness in the range of 0.70 -0.95 ktm.
26 The SrS powder used for the evaporation source was made by the process of this invention 27 described below. The SrS was doped with 0.1% Ce by mixing the appropriate amount of CeF3 28 into the evaporation source material. The deposition was done by reactive evaporation, with 29 the substrate temperature at 450 C and the deposition rate at 30 A/sec.
An H2S atmosphere at a pressure of 0.01 Pa (0.1 mT) was maintained in the vacuum chamber during the deposition, 31 sufficient to prevent a deficiency of sulphur as compared to the stoichiometric ratio in the 32 deposited film. Following deposition, some of the parts were annealed at 600 C in a vacuum 1 for 45 min. to anneal the SrS:Ce layer. The annealed parts developed a web of micro-cracks in 2 the thin film layers following the annealing, but showed somewhat higher initial luminosity in 3 final testing, as described below.
4 b) Patterning of SrS:Ce Layer Following deposition, the initial SrS:Ce layer was patterned using photo-lithographic 6 processes. A negative polyisoprene-based photoresist material, OMR 83 available from the 7 AZ Photoresist Products division of Hoechst Celanese Corp., Somerville N.J., was employed 8 to protect the SrS:Ce on the blue sub-pixels during the etching process used for patterning.
9 The viscosity of the resist was 500 centipoise and spun onto the parts at 1700 rpm for 40 sec.
The viscosity was chosen to ensure that the relatively rough surface (as compared to 11 semiconductor surfaces) was adequately covered by the resist and to optimize a subsequent lift 12 off step set out below. The final resist thickness was in the range of 3.5 to 4.0 ktm.
13 The resist was exposed through a patterning mask designed to allow exposure of the resist 14 over the area corresponding to the blue sub-pixel elements.
Following exposure, the resist was developed by spraying on developer solution at 16 while spinning the part at 1000 rpm for 30 sec. The Developer was OMR B
from the AZ
17 Photoresist Products division of Hoechst Celanese Corp., Somerville, N.J. Following 18 application of the developer, a 50:50 mixture of developer and OMR Rinse solution were 19 sprayed on for 10 sec, followed by an application of rinse only, for 30 sec, all while spinning the substrate at 1000 rpm. Following rinsing, the part was de-scummed in an oxygen plasma 21 etcher for 2 min.
22 Following rinsing of the resist, the part was immersed in anhydrous methanol for 1 23 min. to allow any pores in the surface to be filled with fluid. The part was then immersed at 24 ambient temperature in a solution of 0.5% concentrated hydrochloric acid in anhydrous methanol for 45 - 70 sec to dissolve the SrS:Ce from the red and green sub-pixels element 26 areas. The etching reaction entails reaction of the hydrochloric acid with SrS:Ce to form 27 hydrates of strontium chloride, which is soluble in methanol. The time to etch is dependent on 28 the thickness of the SrS:Ce layer to be dissolved. The pre-immersion in pure anhydrous 29 methanol was designed to inhibit hydrochloric acid from penetrating into the pores and causing deleterious etching or contamination of the underlying structure.
Following etching, 31 the substrates were rinsed in methanol for 2 min. and dried under a nitrogen flow. The etching 32 solution did not dissolve the underlying hafnia injection layer material.

1 c) ZnS:Mn Deposition 2 Following etching of the initial SrS:Ce layer, a layer of ZnS:Mn was e-beam 3 evaporated onto the part to provide the red and green phosphor sub-pixel elements. The Mn 4 concentration was 0.8% and the layer thickness was in the range of 0.3 to 0.5 ,um. The substrate temperature during deposition was 150 C and the deposition rate was 20 A/sec.
6 d) Hafnia Injection Layer 7 This layer was provided as an interlayer to inhibit interdiffusion of dopant species 8 between the SrS and ZnS phosphors, and at the same time preserve good electron injection 9 conditions. The layer may not be needed, provided that good quality phosphor films are deposited. The layer was e-beam evaporated to a thickness of 300 A with a substrate 11 temperature of 150 C and a deposition rate of 1 A/sec.
12 e) ZnS:Mn Lift-Off 13 In this step, the hafnia interlayer and the underlying ZnS
phosphor were removed in the 14 positions where they overlay the blue sub-pixels. This lift-off process was performed by dissolving the resist layer that remained over the blue sub-pixels during the ZnS:Mn and 16 hafnia depositions. To initiate the lift-off process, the part was immersed in a mixture of 10%
17 by vol. methanol in toluene at ambient temperature for 20 to 40 min. The part was removed 18 from the solvent and wiped off, then rinsed in isopropyl alcohol for two more minutes, and 19 dried using a nitrogen gas stream.
f) Second SrS:Ce Layer 21 A second SrS:Ce layer with a thickness of 0.8 -0.9 ,um was deposited over the entire 22 pixel area. The deposition was done under the same conditions as for the first SrS:Ce layer.
23 The resulting phosphor structure now consisted of a 1.6 klm thick SrS:Ce film for the blue sub-24 pixels (widths 150 ,um) and, for the red and green sub-pixels (combined width 300 /um), a 0.4 ,um thick layer of ZnS:Mn covered with a thin hafnia injection layer and a 0.8 /.2m thick SrS:Ce 26 layer.
27 2.5. Second Injection Layer A second 100 A thick hafnia injection layer was deposited on top of the completed 29 pixels (now the patterned phosphor structure) using the same deposition conditions used for the first injection layer. As for the first injection layer, the second injection layer was omitted 31 for some of the samples.
32 2.6. Second Diffusion Barrier Layer 1 A second 300 A thick diffusion barrier layer was deposited on top of the second 2 injection layer using the same procedure as for the first diffusion barrier layer.
3 2.7. Annealing 4 For some samples, the entire substrate was then annealed in air for 10 min. at 550 C.
The benefits and difficulties with cracking were similar as for annealing at the earlier stage.
6 2.8. Transparent Electrode Layer 7 A second resist layer was applied to the substrate using the same procedure as outlined 8 above for the SrS:Ce layer, but using a photo-mask so as to place a resist layer in those 9 locations that were not to be covered by the transparent electrode material. This entailed exposing the resist between those areas (shown in Figure 5) to be covered by the transparent 11 electrodes for each sub-pixel element 30a, 30b, and 30c. The transparent electrodes were 12 designed for external connection for testing of the pixel.
13 An indium tin oxide layer with a thickness in the range of 3000 to 6000 A was e-beam 14 evaporated over the resist layer. The part was held at 250 to 350 C
during the deposition process. The deposition rate was 2 A/sec. Alternatively, the indium tin oxide film could be 16 deposited using sputtering. Following the deposition, the superfluous indium tin oxide was 17 lifted off using the same process as used for lift off of the ZnS:Mn layer. Again, lift off was 18 accomplished by dissolution of the resist layer under the indium tin oxide from the step edges.
19 Next, the processed part was heated at 550 C in air and held at that temperature for 10 min., cooled and then heated in nitrogen at 550 C for a further 5 min. to anneal the indium tin oxide 21 layer to lower its electrical resistance. The ITO lines so formed were about 130 Rm wide, with 22 20 kim spacings.
23 2.9. Metal Contact Deposition 24 To make contact to the transparent conductors, a silver-based polymer thick film (Heraeus PC 5915) was deposited to make contact with the indium tin oxide electrodes. The 26 conductor was printed beyond the edge of the pixel to a contact pad. The conductor paste was 27 cured at 150 C for about 30 minutes.
28 2.10. Filter Plate Attachment and Sealing 29 The pixel structure was overlaid with a glass cover sheet sealed to the pixel structure using an epoxy perimeter seal. The glass sheet had polymer filter film (Brewer Science) 31 deposited on the side of the glass facing the pixel structure aligned with the red, green, and 32 blue sub-pixel elements with the thickness of the polymer films adjusted to give appropriate 1 colour coordinates for the respective sub-pixels. A small hole had been laser drilled through 2 the bare alumina substrate prior to processing to provide a gas path between the rear of the 3 substrate and the void between the front of the pixel structure and the cover plate. A ceramic 4 pot filled with molecular sieve desiccant was sealed to the rear of the substrate aligned over the hole. The ceramic pot and the void space were evacuated through a hole in the pot and this 6 hole was then sealed with a polymer bead (ex. curable epoxy bead).
Sufficient desiccant was 7 provided to absorb any moisture that may have accumulated in the pixel structure during 8 processing and that may have leaked through the seals over time. This facilitated the 9 accumulation of luminosity data over time without device degradation caused by exposure of the internal pixel structure to moisture or other atmospheric contaminants.
11 2.11. Test Results 12 Several pixel structure devices were built as described above and tested at ambient 13 temperature with repetitive alternating positive and negative voltage pulses 85 microseconds 14 long and 60 volts above the threshold voltage in amplitude on all three sub-pixels. The repetition rate was 180 pulses per second. Under these operating conditions, the average 16 luminosity, as measured through the filter plates, was in the range 80 -120 candelas per square 17 meter. The average colour coordinates fell within the range 0.39<x<0.42 and 0.38<y<0.42.
18 The threshold voltage for each sub-pixel was in the range of 120 to 150 volts.
19 The patterned phosphor structure of this example was also compared to the performance of an EL laminate prepared as in Example 2, but using conventional colour by 21 white phosphor layers as shown schematically in Figure 1. The SrS:Ce layer was 1 gm thick, 22 while the ZnS:Mn layer was 0.3 gm thick. All other layers in the EL
laminate were as 23 disclosed above in this example, including a hafnia injection layer between the phosphor 24 layers. Figures 3 and 4 show the luminosity vs. voltage curves for these two displays, Figure 3 showing unfiltered luminosity and Figure 4 showing filtered luminosity. As seen in the 26 Figures, when threshold voltages are taken into account, the unfiltered luminosity was 27 generally improved with the patterned phosphor structure of the present invention. The two 28 displays had a very similar MO (luminosity at 40 V above the threshold voltage), but at higher 29 voltages the patterned phosphor structure display was 50% more luminous than the L60 (luminosity at 60V above the threshold voltage) of the colour by white display. However, the 31 patterned phosphor structure display looks much different than conventional colour by white 32 in that it is composed of alternating columns of blue and yellow-white.
Since its light output o9-oe-ami 9-01 16:51 From:McKAY-CAREY & COMPANY 4210934 1-672 PUG CA000056' 1 is somewhat tailored to the filter above it, it is the filtered luminosity which is more important.
2 When differences in threshold voltages are accounted for between the two displays, 3 Figure 4 shows that the filtered luminosity for the patterned phosphor structure of Example 2 is 4 generally about twice that of the colour by white display. The difference at L40 is 100%, and at L60, the difference is 110%.
6 Example 3 - Single Layer Phosphor Structure 7 This variant of the patterned phosphor structure requires only a single SrS:Ce deposition 8 and includes in the same layer, a manganese doped zinc magnesium sulfide for the red and green 9 sub-pixel elements. For Zni_Ng,S:Mn. the value of x was in the range from 0.1 to 0.3. This phosphor has a much stronger green emission than ZnS:Mn, and can provide adequate green 11 emission without the use of a double layer structure employing SrS
and ZnS phosphors. The 12 fabrication was as follows:
13 3.1. Thick Film Substrate 14 The substrate for this example was a 1.02 mm thick alumina sheet of approximate dimensions 30.5 x 38.1 cm (12 x 15 inches) upon which a set of 480 gold conductor strips were 16 printed using Heraeus RP 20003/237 - 22% organometallic paste obtained from Heraeus 17 Cermalloy and fired to form the addressing rows of a VGA format 43.2 cm (17 inch) diagonal 18 display. The center-to-center spacing of the fired gold rows was 540 yrn, the width of the rows 19 was SOO p.m and the length of the rows was about 27 mm (10.5 inches).
A composite thick film dielectric layer of dimensions 26 x 35 cm (10.2 x 13.6 inches) was deposited on top of the =
21 addressing rows so as to leave the ends of the rows exposed for forming electrical contacts using 22 the methods similar to those set out in Example 1. The high dielectric constant paste in this 23 example was prepared from ink concentrate 98-42 supplied by MRA
Laboratories Inc. (North 24 Adams, Massachusetts, U.S.A.) prepared using high dielectric constant powder comprising PMN-PT. The concentrate was mixed in a blender for 15 min. and then mixed with a solution 26 of a-terpineol, ethyl cellulose and oleic acid in the weight ratio of 100:30:1. The proportion of 27 concentrate to solution was 100:12 by weight. The resulting paste was vacuum filtered through 28 a 10 ym nylon filter and degassed in vacuum for a few minutes. The paste was deposited, 29 CIPped and fired using the methods set out in Example 1, except that the paste was sequentially printed and baked three times prior to CIPping. The thickness of the resulting high dielectric 31 constant layer after CIPping was in the range of 15 - 20 kcm. As in Example 1, a 2 M.111 thick 32 layer of lead zirconium titanate was then applied using so1 gel precursor materials, =
EmplangAMENDED SHEET

1 3.2. Diffusion Barrier Layer 2 The barrier layer consisted of 800 A of alumina, deposited as in Example 2.
3 3.3. SrS:Ce Layer 4 A 1.2 to 1.4 4m thick layer of SrS:Ce co-doped with phosphorus was deposited using e-beam evaporation using the method as set out in Example 2. The phosphor material was 6 prepared as set out in the strontium sulfide synthesis section (f) below, except that the 7 strontium carbonate powder was pre-doped with cerium and phosphorus to yield a strontium 8 sulfide phosphor material containing about 0.1 atomic percent cerium and about 0.15 atomic 9 percent phosphorus. The powder was fired without the addition of other powders, using the temporal temperature profile and sulfur doped process gas as described in section (f) below.
11 3.4. SrS:Ce Patterning 12 The SrS:Ce layer was removed from the green and red sub-pixel element areas using 13 the same procedures as for Example 2, with the exception that the etching time was increased 14 to 1 - 4 min. to account for the thicker SrS:Ce layer. The remaining SrS:Ce stripes were about 190 ,um wide with a spacing between the stripes of 350 ,um.
16 3.5. Zinc Magnesium Sulfide Phosphor (Zni_xMgõS:Mn) 17 A 3000 to 5000 A thick zinc magnesium sulfide film doped with manganese was 18 deposited using e-beam evaporation of ZnS doped with Mn and thermal co-evaporation of 19 magnesium metal. The relative evaporation rates for the ZnS and Mg were adjusted so as to give a film with a Mg to Zn ratio of about 30:70. The deposition conditions and amount of 21 dopant were similar to those of Example 2 for deposition of ZnS:Mn. An alternative to the 22 manganese doped ZniMgxS:Mn phosphor layer in this example is a double phosphor layer 23 comprising ZnS:Tb and ZnS:Mn, preferably with a diffusion barrier interlayer between them.
24 3.6. Threshold Voltage Adjustment Layer A 1000 to 3000 A alumina third dielectric layer was evaporated onto the pixel structure 26 with the thickness chosen to equalize the threshold voltages between the red, green and blue 27 sub-pixels. The deposition conditions were similar to those used for alumina deposition in 28 Example 2. In this example, this threshold voltage layer was only needed over the red and 29 green sub-pixel elements, so was subsequently removed from the blue sub-pixel elements in the next lift off step.
31 3.7. Zinc-Magnesium Sulfide Lift-Off 32 A lift off process similar to that used in Example 2 for ZnS:Mn was used to dissolve 1 the resist covering the SrS:Ce on the blue sub-pixel elements. The dissolving time for lift-off 2 was about 45 min. The substrate was wiped off, rinsed in clean methanol for 30 sec. and spin-3 dried for a further 30 sec. following etching. The result was removal of the (ZnMgS):Mn and 4 overlying alumina layer from the blue sub-pixel elements.
3.8. Diffusion Barrier Layer Deposition 6 An 800 A thick layer of alumina was deposited, as in Example 2.
7 3.9. Phosphor Annealing 8 Optionally, the phosphor structure can was annealed at this stage in a belt furnace in air 9 for 10 min. at a peak temperature of 550 C.
3.10. Transparent Electrode Fabrication 11 This step to deposit and pattern column electrodes onto the display was carried out 12 using the methods as set out in Example 2, except that the surface of the processed part was 13 de-scummed using an oxygen plasma following the lift-off step and the part was annealed at 14 450 C for 5 min. in air for 5 min. rather than at 550 C for 10 min.
following the de-scumming process. The center-to-center spacing of the columns was 180 ,um and the width of the 16 columns was 140 kim. The columns were aligned over the patterned sub-pixels. The column 17 length was 26 cm (10.2 inches) so that the columns extended over all of the rows.
18 3.11. Metal Contact Deposition 19 Sputtered silver metal contacts were fabricated to make contact to the display assembly. For testing purposes, 20 adjacent rows were connected in parallel and 60 adjacent 21 columns were connected in parallel so as to allow illumination of a small square on the display 22 assembly suitable for luminosity and colour coordinate measurements.
23 3.12. Filter Plate Attachment and Sealing 24 These steps were as performed for Example 2.
3.13. Test Results.
26 Several 17 inch diagonal displays were fabricated and tested as described above. The 27 threshold voltage for the blue pixels was in the range of 130 - 160 volts. The threshold voltage 28 for the red and green pixels was in the range 130 - 140 volts. When red, green and blue filters 29 were disposed in front of the corresponding sub-pixels, it was found that a threshold voltage of 140 volts could be used to achieve a minium luminosity below 1 cd/m2 for all of the pixels.
31 The luminosity range for the combined sub-pixels with the filters in place was 35 - 60 cd/m2 32 for 40 volts above the threshold voltage and a refresh rate of 120 Hz.
The driving pulses were 1 260 microseconds in duration. The corresponding colour coordinates for the combined sub-2 pixels were in the range of 0.43 - 0.46 for x and 0.39 - 0.57 for y. It was noted that the colour 3 coordinates corresponded to a slightly yellow tint due to a low relative luminosity from the 4 blue sub-pixels. This can be corrected by slightly reducing the thickness of the phosphor used for the red and green sub-pixels and increasing the thickness of the Threshold Adjustment 6 Layer described above, all in accordance with the present invention.
7 Example 4 - Varying Thickness of Phosphor Deposits to Adjust Threshold Voltage 8 In this Example, as in Example 3, there was only one SrS:Ce deposit for the blue sub-9 pixels, and one ZnIMg,S:Mn deposit for the red and green sub-pixels. The phosphors were made and doped as set out in Example 3, with the approximate value of x in the ZniMgõS:Mn 11 phosphor being between about 0.2 and 0.3. However, in this example, no threshold voltage 12 adjustment layer was used. Rather, the ZnIMgxS:Mn layer was deposited thick enough to 13 balance the threshold voltages. If nothing else was changed, this would lead to a colour 14 imbalance, with the red and green sub-pixels being more than 3 and 6 times as luminous respectively, as the blue sub-pixels. As a result, the filtered white would be too yellow. In this 16 example, this colour imbalance was solved by making the blue sub-pixels wider than the red or 17 green sub-pixels.
18 The substrates used for this example were 5.1 x 5.1 cm (2 x 2 inch)substrates, as set 19 forth in Example 2.
4.1. Thick Film Substrate 21 The thick film substrate layers of Example 2 were used to provide the rear substrate, 22 rear row electrode and thick film dielectric layers.
23 4.2. Diffusion Barrier Layer 24 The barrier layer consisted of 500 A of alumina, deposited as in Example 2. No injection layer was used in this example.
26 4.3. SrS:Ce Layer 27 A 1.2- 1.6 um thick layer of SrS:Ce was deposited by e-beam evaporation, the 28 phosphor being prepared and deposited as described in Example 3.
29 4.4. SrS:Ce Patterning The SrS:Ce layer was removed from the red and green sub-pixels using the procedure 31 described in Example 3. The remaining SrS:Ce stripes were about 320 ,um wide, with a 32 spacing between the stripes of 220 ktm.

1 4.5. Barrier Layer 2 A 500 A layer of undoped ZnS was deposited at this stage by e-beam evaporation. The 3 purpose of this layer was to provide a barrier layer. When this step was omitted, the lower 4 thick film dielectric layer tended to darken during the later annealing step. This layer of undoped ZnS prevented this darkening. It also provided a cleaner interface for the ZnS:Mn, 6 removing the phosphor from any residue that resulted from the SrS:Ce patterning step.
7 4.6. Zinc Sulfide/ Zinc Magnesium Sulfide Phosphor Layers 8 A 800 - 1000 A layer of ZnS:Mn was deposited next, followed by a 9 layer of ZnIMgxS:Mn, and then by a 800- 1000 A layer of ZnS:Mn. The ZnS:Mn was deposited as described in Example 2, whereas the ZnIMgxS:Mn was deposited as in Example 11 3.
12 4.7. Barrier Layer 13 Another 500 A barrier layer of ZnS was deposited at this point by e-beam evaporation.
14 4.8. Zinc Magnesium Sulfide Lift-Off The resist covering the SrS:Ce on the blue sub-pixels was dissolved in the same way as 16 in Example 3. The rinsing procedure was different in that the substrates were soaked in clean, 17 anhydrous methanol for 2 min. and then dried under a nitrogen flow.
18 4.9. Barrier Layer 19 An upper barrier layer of 500 A of alumina was deposited.
4.10. Phosphor Annealing 21 The phosphor was annealed at this stage in a belt furnace in air for 10 min. at a peak 22 temperature of 550 C.
23 4.11. Transparent Electrode Fabrication 24 The indium tin oxide layer was deposited by sputtering using a current of 2 Amps, a temperature of 25 C, a pressure of 1.06 Pa (8 mTorr), an oxygen flow of 0.2 sccm, and an 26 argon flow of about 70 sccm (balanced to give above pressure), to a thickness of 5000 A.
27 4.12. Metal Contact Deposition 28 The metal contacts were printed using polymer thick film silver paste as in Example 2.
29 4.13. Filter Plate Attachment and Sealing These steps were performed as described in Example 2. The filter had the following 31 line widths; red - 60 kan, green - 110 ym, blue - 310 ym. The gaps between the lines (where 32 the colours overlapped) were 20 ,um wide. The total pixel width was 540 ,um.

1 4.14. Test Results 2 Several 5.1 x 5.1 cm (2 x 2 inch) panels were made by the above procedure and were 3 tested as in Example 2. The results of the better panels were as follows:
4 Threshold voltage (blue sub-pixels) 130 - 170 V
Threshold voltage (red, green sub-pixels) 160 - 200 V
6 Overall threshold voltage used (<5 cd/m2) 160 - 180 V
7 Luminosity (white, filtered) 165 - 260 cd/m2 8 White colour coordinates (x) 0.38 - 0.44 9 White colour coordinates (y) 0.40 - 0.45 CIE colour coordinates Red x=0.62, y=0.38 11 Green x=0.42, y=0.58 12 Blue x=0.13, y=0.14 13 In this example, the threshold voltages of the red and green sub-pixels were much 14 higher than those of the blue sub-pixels. This can be prevented by reducing the thickness of the Zni_xMgxS:Mn phosphor and increasing the thickness of the SrS:Ce phosphor.
As a result 16 of this discrepancy, the blue sub-pixels were too luminous for the red and green sub-pixels at 17 lower voltages. For this reason, a higher threshold voltage was chosen, such that the filtered 18 luminosity at threshold was as high as 5 cd/m2. If the phosphor thicknesses were changed to 19 bring the two threshold voltages in line, the colour balance would be better, the luminosity at threshold voltage would be <1 cd/m2, and the total luminosity would be higher.
21 Example 5 - Single Layer Phosphor Structure with SrS:Ce for Green and Blue, Varying 22 Sub-pixel Widths 23 This example, like the previous two examples, includes only one SrS:Ce deposition 24 and one ZnS:Mn deposition. As in Example 4, the sub-pixel widths was adjusted in order to balance the colour. In addition, however, a Threshold Voltage Adjustment Layer was used to 26 further increase the threshold voltage of the ZnS:Mn layer without increasing its luminosity.
27 Another difference is in the phosphors that have been used for the different colours. SrS:Ce 28 alone was used for both the blue and green sub-pixels, and ZnS:Mn was used for the red sub-29 pixels, rather than Zni_xMgxS:Mn, since no green was required from this phosphor.
The substrates used were 5.1 x 5.1 cm (2 x 2 inch) substrates, as in Example 2.
31 5.1. Thick Film Substrate 32 The thick film substrate layers of Example 2 were used to provide the rear substrate, 1 rear row electrode and thick film dielectric layers.
2 5.2. Diffusion Barrier Layer 3 A barrier layer of 500 A alumina was deposited.
4 5.3. Injection Layer An injection layer of 100 A hafnia was deposited.
6 5.4. SrS:Ce Phosphor Layer 7 A 1.2 - 1.4 ym layer of SrS:Ce was deposited by e-beam evaporation as described in 8 Example 4.
9 5.5. SrS:Ce Patterning The SrS:Ce layer was removed from the red sub-pixels using the procedure described 11 in Example 3, with removal times of 1 -2 min. The width of the resulting SrS:Ce lines was 12 470 ym and the gaps between the lines were 70 pm.
13 5.6. Barrier Layer 14 A 300 A layer of alumina was deposited at this stage by e-beam evaporation. The purpose of this step was to provide a cleaner interface for the ZnS:Mn, removing the phosphor 16 from any residue that resulted from the SrS:Ce patterning step.
17 5.7. Zinc Sulfide Phosphor Layer 18 A 4500 A layer of ZnS:Mn was deposited as described in Example 2.
19 5.8. Threshold Voltage Adjustment Layer A layer of 1800 A thick alumina was deposited in the same manner as for the barrier 21 layer.
22 5.9. Zinc Sulfide Lift-off 23 The resist covering the SrS:Ce on the blue sub-pixels was dissolved in the same 24 manner as in Example 4.
5.10. Injection Layer 26 An upper injection layer of 100 A of hafnia was deposited.
27 5.11. Barrier Layer 28 An upper barrier layer of 500 A of alumina was deposited.
29 5.12. Phosphor Annealing The phosphor was annealed at this stage in a belt furnace in air for 10 min.
at a peak 31 temperature of 550 C.
32 5.13. Transparent Electrode Fabrication 1 The indium tin oxide electrodes were deposited by sputtering, using a current of 2 2 Amps, a temperature of 25 C, a pressure of 1.06 Pa (8 mTorr), an oxygen flow of 0.2 sccm, 3 and an argon flow of about 70 sccm (balanced to give above pressure), to a thickness of 5000 4 A.
5.14. Metal Contact Deposition 6 The metal contacts were made from chromium, followed by Al, sputtered as follows:
7 Cr: power 15 kW, temp. 150 C, pressure 0.26 Pa (2 mTorr), thickness 600 A;
8 Al: power 10 kW, temp. 25 C, pressure 0.26 Pa (2 mTorr), thickness 6800 A.
9 5.15. Filter Plate Attachment and Sealing These steps were performed as described in Example 2. The filter had the following 11 line widths: red - 60 gm, green - 270 urn, blue - 150 ,um. The gaps between the lines (where 12 the colours overlapped) were 20 4m. The total pixel width was 540 urn.
The green sub-pixel 13 was much wider than in Example 4. This was because the SrS:Ce was not nearly as bright, 14 even with the green filter, as ZniMgõS:Mn, and so the green sub-pixels were made wider to compensate.
16 5.16. Test Results 17 Several 5.1 x 5.1 cm (2 x 2 inch) panels were made by this procedure, and tested as in 18 Example 2. The results were as follows:
19 Threshold voltage (blue, green sub-pixels) 140 - 170 V
Threshold voltage (red sub-pixels) 130 - 150 V
21 Overall threshold voltage used (<1 cd/m2) 130 -150 V
22 Luminosity (white, filtered) 40 - 64 cd/m2 23 White colour coordinates (x) 0.35 - 0.46 24 White colour coordinates (y) 0.39 - 0.42 It will be noted that these panels also had good colour saturations, like Example 4. For 26 blue, x-0.13, y-0.15, for green, x-0.23, y-0.58, and for red, x-0.65, y-0.35.
27 f) Strontium Sulfide Synthesis 28 The performance of the phosphor structure described above was found to be highly 29 dependent upon the quality of the SrS powder used as a source material for the SrS phosphor.
The following preparation was used to maximize luminance efficiency and blue purity.
31 The desired properties of phosphor films comprising 0.12% Ce doped SrS
are a 32 luminosity of 80 candelas per square meter or higher, up to 200 cd/m2, and colour coordinates 1 of 0.19<x<0.20 and 0.34<y<0.40 corresponding to blue when excited with 80 microsecond 2 pulses having an amplitude of 40 volts above the threshold voltage and a repetition rate of 120 3 pulses/sec. If the preparation procedure for the SrS is not carefully controlled, the luminosity 4 decreases and the colour coordinates shift to x up to 0.3 and y up to 0.5, significantly toward green.
6 In accordance with this invention, the SrS synthesis reaction should be controlled in 7 order to occur homogeneously. Generally, this entails providing a strontium carbonate 8 precursor powder in a dispersed form so that it is substantially uniformly exposed to the 9 process conditions. This can be achieved by using small batches, using volatile, non-contaminating, clean evaporating compounds or solvents which decompose into gaseous 11 products prior to the onset of the reaction, or by using a fluidized bed or tumbler reactor. It is 12 also important to achieve a slow and uniform conversion of a strontium carbonate precursor 13 powder to strontium sulfide, in the presence of sulfur vapours, at an elevated temperature in 14 the range of 800 - 1200 C. Without such control, variation is observed in the photoluminescent emission spectrum and luminosity of the SrS powder, using broadband 16 ultraviolet illumination, and in the electroluminescent emission spectrum and luminosity 17 efficiency of the deposited SrS phosphor layers made from the powder.
The basic synthesis 18 reaction can be written as:
19 4 SrCO3 + 3 S, - 4 SrS + 2 SO, + 4 CO, The reaction occurs in two steps, with the first step involving the decomposition of the 21 strontium carbonate to oxygen-containing strontium compounds and carbon dioxide, and the 22 second step involving a reaction with sulfur to produce strontium sulfide and sulfur dioxide (or 23 perhaps other sulfur oxides). The interrelationship between these two steps is found to have a 24 significant bearing on the quality of powder that is produced.
The reactor for the synthesis consists of a quartz or ceramic tube positioned in the hot 26 zone of a tube furnace into which a strontium carbonate powder is placed. The tube material 27 of the reactor should not react chemically with the reactants or reaction products. In this 28 example, a 3.8 cm (1.5 inch) diameter alumina tube having a length in the hot zone of about 30 29 cm (12 inches) was used. The tube was loaded with about 75 grams of a strontium carbonate powder in the hot zone. The strontium carbonate had a purity level of greater than 99.9% on a 31 metal basis. Powders of such purity may be commercially obtained or generated by 32 precipitating strontium nitrate or strontium hydroxide with ammonium carbonate. The tube 1 was heated gradually, at a rate not exceeding 5 to 10 C/min, to a maximum temperature in the 2 range of 800 to 1200 C. The preferred maximum temperature is about 1100 C.
3 At about the time the maximum temperature is reached, a continuous flow of sulfur 4 vapour is introduced into an argon gas stream (i.e., in an inert atmosphere) at atmospheric pressure entering the reaction tube. The sulfur vapour may be generated by either placing a 6 container containing elemental sulfur at the entrance end of heated reaction tube, or by heating 7 a separate stainless steel container filled with sulfur to between 360 and 440 C which is 8 connected to the entrance end of the reaction tube. An appropriate amount of sulfur vapour is 9 introduced by adjusting the pot temperature and the argon flow rate. A
Ferran Scientific mass spectrometer is connected to the exit end of the reaction tube, and the relative concentrations 11 of carbon dioxide and sulfur dioxide are measured. The reaction is terminated when the mass 12 spectrometer reading of a predetermined concentration of sulfur dioxide is reached. This is 13 done by switching off the sulfur flow into the tube and by cooling down the furnace. The 14 sulfur vapour flow is stopped by turning off the sulfur pot heater. The argon flow continues until the furnace is cool enough for unloading the product, typically below 200 C. The firing 16 time at the maximum temperature is typically in the range of 2 to 8 hours, depending on the 17 maximum temperature, the sulfur vapour delivery rate, the strontium carbonate powder 18 packing density and the end point, at which time the reaction is terminated.
19 The end point is considered reached when the mass spectrometer reading of SO, falls into the range between 0.001 -0.01 Pa (1 X 10-5 to 1 X 10 Ton) in a base pressure of 0.2 -0.3 21 Pa (2 X 10-3 to 3 X 10-3 Torr). This results in a small residual quantity of oxygen-containing 22 strontium compounds, or possibly a fraction of that in the form of strontium carbonate, (i.e., 23 oxygen-containing strontium compounds) remaining in the strontium sulfide product, the 24 presence of which correlates with improved phosphor performance. The most luminous phosphor films have been made using strontium sulfide powders containing about 5 atomic 26 percent of oxygen-containing strontium compounds, but good phosphors may be made over a 27 range of oxide concentrations. The preferred range of concentrations of oxygen-containing 28 strontium compounds is 1 to 10 atomic percent. The correlation between oxide content and 29 phosphor performance is fairly weak, due to the influence of other variables during phosphor preparation. However, it is generally observed that strontium sulfide with too little oxide 31 correlates with a shift from blue to green in photoluminescence from the powder and a 32 deleterious shift from blue to green in electroluminescence of phosphor films prepared 1 therefrom.
2 The strontium carbonate starting powder can be doped with cerium carbonate, cerium 3 fluoride, or another form of cerium additive, or the dopant can be added later as cerium 4 fluoride or cerium sulfide to the resulting strontium sulfide powder, or the dopant may be added prior to phosphor film deposition. No significant dependence of phosphor performance 6 on the method of cerium introduction has been found to exist. The amount of the dopant is 7 preferably in the range of 0.01 to 0.35 mole %, more preferably 0.05 to 0.25%.
8 The initial form of the strontium carbonate powder does have a significant impact on 9 phosphor performance. It is desirable that the powder has a high porosity, and does not fuse during reaction with sulfur. A densely packed strontium carbonate powder specimen or one 11 that fuses during reaction tends to result in green shift in the photoluminescence and 12 electroluminescence of the films deposited with the strontium sulfide powder therefrom, and is 13 thus undesired. A loosely packed powder usually gives the best performance for the phosphor.
14 The impact of the porosity or the dispersed form of the bulk strontium carbonate powder on the quality of the strontium sulfide phosphor is also reflected in the reaction 16 mechanism as evidenced by the relative conversion rate to strontium sulfide at the second 17 stage of the reaction. For a densely packed powder with low porosity, the conversion is 18 usually fast with the onset of sulfur dioxide evolution occurring at about 10 minutes after the 19 onset of carbon dioxide evolution. For a loosely packed powder with high porosity, the onset of sulfur dioxide evolution occurs at a much later time, as long as 100 minutes after the onset 21 of carbon dioxide evolution.
22 The porosity of the powder helps ensure that the process environment is essentially 23 uniform throughout the material being processed, allowing unrestricted diffusion of the sulfur 24 vapour and gaseous reaction products. This is believed to help ensure that the product particles are homogeneous on an atomic scale. Types of atomic scale inhomogeneity include 26 lattice substitutions, interstitial atoms, vacancies and clusters thereof. Lattice substitutions do 27 not necessarily imply that an impurity atom is present, and may include positioning of a 28 strontium atom where a sulfur atom should be, and vice versa. Even though the powder is 29 vaporized during phosphor deposition, clusters of atoms rather than individual atoms may vaporize, preserving atomic scale defects initially present in the source powder used for the 31 deposited films.
32 Several methods to achieve high strontium carbonate powder dispersion or porosity 1 have been developed. One is to mix the strontium carbonate powder with a volatile, clean 2 evaporating non-contaminating powdered compound that decomposes into gaseous products 3 prior to the onset of reactions involving strontium carbonate. Examples of such compounds 4 are high purity powder such as ammonium carbonate, ammonium sulphate and elemental sulfur. The additive can be added giving a weight ratio of additive to strontium carbonate in 6 the range of 1:9 to 1:1, but preferably is in the range of 1:4 to 1:2.5.
This method works well 7 with the free flowing strontium carbonate powder made from strontium nitrate and ammonium 8 carbonate.
9 A second method to effect powder porosity or dispersion is to soak the powder in a solvent that penetrates the powder, modifying the surface properties of the strontium carbonate 11 particles to prevent it from fusing during the reaction with sulfur vapour at high temperatures.
12 The strontium carbonate is mixed with a non-contaminating solvent to form a slurry, which is 13 then partially dried in air at ambient temperature or with mild heating depending on the nature 14 of the solvent to form a free flowing powder. The powder should undergo a weight gain of between 5 and 30% as compared to completely dry powder. The partially dried powder can be 16 loaded in the reactor tube according to the usual procedure. The solvent can include, but is not 17 limited to, acetone, methanol, ethanol and water. This method works well with the granular 18 and sticky strontium carbonate powder such as that made from strontium hydroxide and 19 ammonium carbonate.
The use of argon as an inert carrier gas is preferred. When forming gas (5%
hydrogen 21 in argon) is used in place of argon, green shift in the photoluminescence and 22 electroluminescence of the films deposited from the powder is again observed.
23 Sample size is another significant factor that affects the quality of the strontium sulfide.
24 Large samples of 150 grams of strontium carbonate, also lead to a green shift of emission spectrum of the film. This is believed to be a direct result of the inhomogeneous reaction of 26 the powder with the reactant since repeated regrinding and firing tends to improve the quality 27 of the strontium sulfide.
28 All publications mentioned in this specification are indicative of the level of skill of 29 those skilled in the art to which this invention pertains.
The terms and expressions used in this specification are used as terms of description 1 and not of limitation. There is no intention, in using such terms and expressions, of excluding 2 equivalents of the features shown and described.

Claims (81)

We claim:

1. A combined substrate and dielectric layer component for use in an EL
laminate, comprising:
a rigid substrate providing a rear electrode; and a thick film dielectric layer formed above the rigid substrate providing the rear electrode by (a) a thick film technique with a first ceramic material paste in one or more layers to a thickness of 10 to 300 µm, followed by drying, then pressing the thick film dielectric layer and the rigid substrate providing the rear electrode so as to produce a pressed thick film dielectric layer having reduced thickness, surface roughness and porosity, and then sintering the pressed thick film dielectric layer, the rigid substrate providing the rear electrode to form a pressed, sintered thick film dielectric layer;
and (b) depositing a second ceramic material by a sol gel technique on the pressed, sintered thick film dielectric layer and then heating to form a sol gel dielectric layer to further smooth the surface of the pressed, sintered thick film dielectric layer, such that the thick film dielectric layer so formed has a dielectric strength which is greater than 5.0 x 10 6 V/m, and uniform luminosity over a scale of 10 µm in the EL laminate, and said pressed, sintered thick film dielectric layer has reduced porosity and reduced thickness of 20 to 50% compared to a second dielectric layer of the same composition formed by the same technique with drying and sintering, but without an intervening pressing step.

2. The combined substrate and dielectric layer component as set forth in claim 1, wherein the pressed, sintered thick film dielectric layer has a thickness of between 10 and 20 µm.

3. The combined substrate and dielectric layer component as set forth in claim 1, wherein the first ceramic material is a ferroelectric ceramic material having a dielectric constant greater than 500.

4. The combined substrate and dielectric layer component as set forth in claim 3, wherein the first ceramic material has a perovskite crystal structure.

5. The combined substrate and dielectric layer component as set forth in claim 4, wherein the first ceramic material is selected from the group consisting of one or more of BaTiO3, PbTiO3, PMN and PMN-PT.

6. The combined substrate and dielectric layer component as set forth in claim 4, wherein the first ceramic material is selected from the group consisting of BaTiO3, PbTiO3, PMN and PMN-PT.

7. The combined substrate and dielectric layer component as set forth in claim 6, wherein the second ceramic material is a ferroelectric ceramic material.

8. The combined substrate and dielectric layer component as set forth in claim 7, wherein the second ceramic material has a dielectric constant of at least 20 and a thickness of at least 1 µm.

9. The combined substrate and dielectric layer component as set forth in claim 8, wherein the second ceramic material has a dielectric constant of at least 100.

10. The combined substrate and dielectric layer component as set forth in claim 9, wherein the second ceramic material has a thickness in the range of 1 to 3

11. The combined substrate and dielectric layer component as set forth in claim 10, wherein the second ceramic material is a ferroelectric ceramic material having a perovskite crystal structure.

12. The combined substrate and dielectric layer component as set forth in claim 11, wherein the second ceramic material is lead zirconium titanate or lead lanthanum zirconate titanate.

13. The combined substrate and dielectric layer component as set forth in claim 12, wherein the combined substrate and dielectric layer component is formed on a rigid substrate, on which is formed the rear electrode.

14. The combined substrate and dielectric layer component as set forth in claim 13, wherein the pressing is by cold isostatic pressing.

15. The combined substrate and dielectric layer component as set forth in claim 14, wherein the pressed, sintered thick film dielectric layer has a thickness, after sintering, sufficient to prevent dielectric breakdown during operation as determined by the equation d2 = V/S, wherein d2 is the thickness of the dielectric layer and V is the maximum applied voltage.

16. The combined substrate and dielectric layer component as set forth in claim 15, wherein d2 is 10 µm or greater.

17. The combined substrate and dielectric layer component as set forth in claim 14, wherein the pressed, sintered thick film dielectric layer has a thickness of between 10 and 50 µm.

18. The combined substrate and dielectric layer component as set forth in claim 13, wherein the substrate and the rear electrode are formed from materials which can withstand temperatures of 850°C.

19. The combined substrate and dielectric layer component as set forth in claim 18, wherein the substrate is an alumina sheet.

20. The combined substrate and dielectric layer component as set forth in claim 4, wherein the first ceramic material is PMN-PT.

21. The combined substrate and dielectric layer component as set forth in claim 20, wherein the combined substrate and dielectric layer component is formed on a rigid substrate, on which is formed the rear electrode.

22. An EL laminate, comprising:
a planar phosphor layer;
a front and rear planar electrode on either side of the phosphor layer;
a rear substrate providing the rear electrode, the rear substrate having sufficient rigidity to support the laminate; and a thick film dielectric layer above the rigid substrate providing the rear electrode, the thick film dielectric layer being formed by (a) a thick film technique with a first ceramic material paste in one or more layers to a thickness of 10 to 300 µm, followed by drying, then pressing the thick film dielectric layer, the rear electrode and the rear substrate so as to produce a pressed thick film dielectric layer having reduced thickness, surface roughness and porosity, and then sintering the pressed thick film dielectric layer, the rear electrode and the rear substrate to form a pressed, sintered thick film dielectric layer; and (b) depositing a second ceramic material by a sol gel technique on the pressed, sintered thick film dielectric layer and then heating to form a sol gel dielectric layer to further smooth the surface of the pressed, sintered thick film dielectric layer, such that the thick film dielectric layer so formed has a dielectric strength which is greater than 5.0 x 10 6 V/m and uniform luminosity over a scale of 10 µm in the EL laminate, and said pressed, sintered thick film dielectric layer has a reduced porosity compared to a second dielectric layer of the same composition formed by the same technique with drying and sintering, but without an intervening pressing step.

23. The EL laminate as set forth in claim 22, wherein the pressed, sintered thick film dielectric layer has a reduced thickness of 30 to 40%.

24. The EL laminate as set forth in claim 22, wherein the pressed, sintered thick film dielectric layer has a thickness of between 10 and 50 µm.

25. The EL laminate as set forth in claim 22, wherein the pressed, sintered thick film dielectric layer has a thickness of between 10 and 20 µm.

26. The EL laminate as set forth in claim 25, wherein the first ceramic material is a ferroelectric ceramic material having a dielectric constant greater than 500.

27. The EL laminate as set forth in claim 26, wherein the first ceramic material has a perovskite crystal structure.

28. The EL laminate as set forth in claim 27, wherein the first ceramic material is selected from the group consisting of one or more of BaTiO3, PbTiO3, PMN and PMN-PT.

29. The EL laminate as set forth in claim 27, wherein the first ceramic material is selected from the group consisting of BaTiO3, PbTiO3, PMN and PMN-PT.

30. The EL laminate as set forth in claim 29, wherein the second ceramic material is a ferroelectric ceramic material.

31. The EL laminate as set forth in claim 30, wherein the second ceramic material has a dielectric constant of at least 20 and a thickness of at least 1 µm.

32. The EL laminate as set forth in claim 31, wherein the second ceramic material has a dielectric constant of at least 100.

33. The EL laminate as set forth in claim 32, wherein the second ceramic material has a thickness in the range of 1 to 3 µm.

34. The EL laminate as set forth in claim 33, wherein the second ceramic material is a ferroelectric ceramic material having a perovskite crystal structure.

35. The EL laminate as set forth in claim 34, wherein the second ceramic material is lead zirconium titanate or lead lanthanum zirconate titanate.

36. The EL laminate as set forth in claim 35, wherein the EL laminate is formed on a rigid substrate, on which is formed the rear electrode.

37. The EL laminate as set forth in claim 36, wherein the pressing is by cold isostatic pressing.

38. The EL laminate as set forth in claim 37, wherein the pressed, sintered thick film dielectric layer has a thickness, after sintering, sufficient to prevent dielectric breakdown during operation as determined by the equation d2 = V/S, wherein d2 is the thickness of the thick film dielectric layer and V is the maximum applied voltage.

39. The EL laminate as set forth in claim 38, wherein d2 is 10µm or greater.

40. The EL laminate as set forth in claim 36, wherein the substrate and the rear electrode are formed from materials which can withstand temperatures of 850°C.

41. The EL laminate as set forth in claim 40, wherein the substrate is an alumina sheet.

42. The EL laminate as set forth in claim 29, wherein the EL laminate is formed on a rigid substrate, on which is formed the rear electrode.

43. The EL laminate as set forth in claim 27, wherein the first ceramic material is PMN-PT.

44. A method of forming an EL laminate of the type including one or more phosphor layers sandwiched between a front and a rear electrode, the phosphor layer being separated from the rear electrode by a thick film dielectric layer, comprising the steps of:
a) providing a rigid rear substrate;
b) forming the rear electrode on the rear substrate;

c) depositing a first ceramic material paste above the rear electrode in one or more layers by a thick film technique to form the thick film dielectric layer having a thickness of 10 to 300 µm;
d) drying and then pressing the thick film dielectric layer, the rear electrode and the rear substrate, using a sheet of non-stick material in contact with the thick film dielectric layer during the pressing step, to form a densified thick film dielectric layer with reduced porosity and surface roughness prior to sintering;
e) subsequent to pressing, sintering the thick film dielectric layer, the rear electrode and the rear substrate to form a pressed, sintered thick film dielectric layer;
f) depositing a second ceramic material by a sol gel technique on the pressed, sintered thick film dielectric layer and then heating to form a sol gel dielectric layer to further smooth the surface of the thick film dielectric layer;
g) forming one or more phosphor layers above the sol gel dielectric layer; and h) forming the front electrode above the one or more phosphor layers, wherein the EL
laminate so formed has an improved uniform luminosity over a second EL
laminate of the same composition but formed without the pressing step.

45. The method as set forth in claim 44, wherein the pressing is isostatic pressing.

46. The method as set forth in claim 44, wherein the pressed, sintered thick film dielectric layer has a thickness, after sintering, sufficient to prevent dielectric breakdown during operation as determined by the equation d2 = V/S, wherein d2 is the thickness of the thick film dielectric layer, V is the maximum applied voltage and S is the strength of the first ceramic material.

47. The method as set forth in claim 46, wherein d2 is 10 µm or greater.

48. The method as set forth in claim 44, wherein the pressing is cold isostatic pressing at up to 350,000 kPa.

49. The method of claim 48, wherein the non-stick material is an aluminized polyester, with an aluminized surface in contact with the thick film dielectric layer.

50. The method as set forth in claim 48, wherein the first ceramic material is deposited by screen printing, in one or more layers.

51. The method as set forth in claim 50, wherein the second ceramic material is a ferroelectric ceramic material.

52. The method as set forth in claim 51, wherein the first ceramic material is pressed to reduce the thickness, after sintering, by 20 to 50%.

53. The method as set forth in claim 51, wherein the first ceramic material is pressed to a thickness, after sintering, of between 10 and 20 µm.

54. The method as set forth in claim 53, wherein the thick film dielectric layer has a deposited thickness of 20 to 50 µm.

55. The method as set forth in claim 54, wherein the first ceramic material is a ferroelectric ceramic material having a dielectric constant greater than 500.

56. The method as set forth in claim 51, wherein the first ceramic material is a ferroelectric ceramic material having a dielectric constant greater than 500.

57. The method as set forth in claim 56, wherein the first ceramic material has a perovskite crystal structure.

58. The method as set forth in claim 57, wherein the first ceramic material is selected from the group consisting of one or more of BaTiO3, PbTiO3, PMN and PMN-PT.

59. The method as set forth in claim 57, wherein the first ceramic material is selected from the group consisting of BaTiO3, PbTiO3, PMN and PMN-PT.

60. The method as set forth in claim 59, wherein the first ceramic material is PMN-PT.

61. The method as set forth in claim 51, wherein the second ceramic material has a dielectric constant of at least 20 and a thickness of at least 1 µm.

62. The method as set forth in claim 61, wherein the second ceramic material has a dielectric constant of at least 100.

63. The method as set forth in claim 62, wherein the second ceramic material has a thickness in the range of 1 to 3 µm.

64. The method as set forth in claim 63, wherein the second ceramic material is deposited by a sol gel technique selected from spin deposition or dipping, followed by heating to convert to the sol gel dielectric layer.

65. The method as set forth in claim 64, which further comprises, depositing a diffusion barrier layer above the sol gel dielectric layer, which diffusion barrier layer is composed of a metal-containing electrically insulating binary compound that is chemically compatible with any adjacent layers and which differs from its precise stoichiometric composition by less than 0.1 atomic percent.

66. The method as set forth in claim 64, which further comprises, depositing an injection layer above the sol gel dielectric layer to provide a phosphor interface, composed of a binary, dielectric material which is non-stoichiometric in its composition and having electrons in a range of energy for injection into the one or more phosphor layers.

67. The method of claim 64, wherein the EL laminate is for an EL display and wherein the rear electrode is formed as rows of conductive metal address lines and the front electrode is formed as columns of transparent address lines arranged perpendicularly to the row address lines.

68. The method as set forth in claim 67, wherein the pressed, sintered thick film dielectric layer, compared to an unpressed, sintered dielectric layer of the same composition, has improved dielectric strength which is greater than 5.0 x 10 6 V/m and uniform luminosity over a scale of 10 µm in an EL laminate.

69. The method as set forth in claim 64, wherein the second ceramic material is a ferroelectric ceramic material having a perovskite crystal structure.

70. The method as set forth in claim 69, wherein the second ceramic material is lead zirconium titanate or lead lanthanum zirconate titanate.

71. The method as set forth in claim 70, wherein the substrate and the rear electrode are formed from materials which can withstand temperatures of 850°C.

72. The method as set forth in claim 71, wherein the substrate is an alumina sheet.

73. The method as set forth in claim 72, which further comprises, depositing a diffusion barrier layer above the sol gel dielectric layer, which diffusion barrier layer is composed of a metal-containing electrically insulating binary compound that is chemically compatible with any adjacent layers and which differs from its precise stoichiometric composition by less than 0.1 atomic percent.

74. The method as set forth in claim 73, wherein the diffusion barrier layer is formed from alumina, silica, or zinc sulfide.

75. The method as set forth in claim 74, wherein the diffusion barrier is formed from alumina.

76. The method as set forth in claim 75, wherein the diffusion barrier has a thickness of 100 to 1000 .ANG..

77. The method as set forth in claim 73, which further comprises, depositing an injection layer above the diffusion barrier layer, to provide a phosphor interface, composed of a binary, dielectric material which is non-stoichiometric in its composition and having electrons in a range of energy for injection into the one or more phosphor layers.

78. The method as set forth in claim 77, wherein the injection layer is hafnia when the phosphor is a zinc sulfide phosphor, and wherein the diffusion barrier layer is zinc sulfide when the phosphor is a strontium sulfide phosphor.

79. The method as set forth in claim 77, wherein the injection layer is formed from a material which has greater than 0.5% atomic deviation from its stoichiometric composition.

80. The method as set forth in claim 79, wherein the injection layer is formed from hafnia or yttria.

81. The method as set forth in claim 80, wherein the injection layer has a thickness of 100 to 1000 .ANG..