CA2371760A1 - Electroluminescent laminate with patterned phosphor structure and thick film dielectric with improved dielectric properties - Google Patents

Electroluminescent laminate with patterned phosphor structure and thick film dielectric with improved dielectric properties Download PDF

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Publication number
CA2371760A1
CA2371760A1 CA002371760A CA2371760A CA2371760A1 CA 2371760 A1 CA2371760 A1 CA 2371760A1 CA 002371760 A CA002371760 A CA 002371760A CA 2371760 A CA2371760 A CA 2371760A CA 2371760 A1 CA2371760 A1 CA 2371760A1
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phosphor
set forth
laminate
layer
deposits
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CA2371760C (en
Inventor
Xingwei Wu
George A. Kupsky
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iFire IP Corp
Original Assignee
Ifire Technology Inc.
Xingwei Wu
Seale, Daniel Joseph
Liu, Guo
Carkner, Donald Edward
Doxsee, Daniel
George A. Kupsky
Westcott, Michael Roger
Lovell, David Robin
1115901 Alberta Ltd.
Ifire Technology Corp.
Ifire Ip Corporation
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Publication of CA2371760A1 publication Critical patent/CA2371760A1/en
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Publication of CA2371760C publication Critical patent/CA2371760C/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H05B33/14—Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material, or by the simultaneous addition of the electroluminescent material in or onto the light source
    • H05B33/145—Arrangements of the electroluminescent material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/10—Apparatus or processes specially adapted to the manufacture of electroluminescent light sources
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H05B33/22—Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of auxiliary dielectric or reflective layers

Abstract

An improved dielectric layer for use in an EL laminate, including a pressed, sintered ceramic material having, compared to an unpressed, sintered dielectric layer of the same composition, improved dielectric strength, reduced porosity and uniform luminosity in an EL
laminate. Also provided is a method of forming a thick film dielectric layer in an EL
laminate by depositing a ceramic material in one or more layers by a thick film technique to form a dielectric layer having a thickness of 10 to 300 µm; pressing the dielectric layer to form a densified layer with reduced porosity and surface roughness; and sintering the dielectric layer to form a pressed, sintered dielectric layer. The formed EL
laminate has an improved uniform luminosity over an unpressed, sintered dielectric layer of the same composition.

Claims (242)

1. A patterned phosphor structure having red, green and blue sub-pixel phosphor elements for an AC electroluminescent display, comprising:
at least a first and a second phosphor, each emitting light in different ranges of the visible spectrum, but whose combined emission spectra contains red, green and blue light;
said at least first and second phosphors being in a layer, arranged in adjacent, repeating relationship to each other to provide a plurality of repeating at least first and second phosphor deposits; and one or more means associated with one or more of the at least first and second phosphor deposits, and which together with the at least first and second phosphor deposits, form the red, green and blue sub-pixel phosphor elements, for setting and equalizing the threshold voltages of the red, green and blue sub-pixel phosphor elements, and for setting the relative luminosities of the red, green and blue sub-pixel phosphor elements so that they bear set ratios to one another at each operating modulation voltage used to generate the desired luminosities for red, green and blue.
2. The phosphor structure as set forth in claim 1, wherein the at least first and second phosphor deposits are formed from phosphors of different host materials.
3. The phosphor structure as set forth in claim 2, wherein the set luminosity ratios remain substantially constant over the range of operating modulation voltages.
4. The phosphor structure as set forth in claim 3, wherein the set luminosities ratios between the red, green and blue sub-pixel phosphor elements is about 3:6:1.
5. The phosphor structure as set forth in claim 2, 3 or 4, wherein the means for setting and equalizing the threshold voltages, and for setting the relative luminosities, comprises a threshold voltage adjustment layer of a dielectric material or a semiconductor material located in one or more of the positions of over, under and embedded within one or more of the at least first and second phosphor deposits.
6. The phosphor structure as set forth in claim 2, 3, 4 or 5, wherein the means for setting and equalizing the threshold voltages, and for setting the relative luminosities, comprises the at least first and second phosphor deposits being formed with different thicknesses.
7. The phosphor structure as set forth in claim 5 or 6, wherein, the means for setting and equalizing the threshold voltages, and for setting the relative luminosities, further comprises varying one or both of the following:

i. the areas of the phosphor deposits; and ii. the concentrations of a dopant or co-dopant in the phosphor deposits.
8. The phosphor structure as set forth in claim 7, wherein the at least first and second phosphor deposits are formed from a zinc sulfide phosphor and a strontium sulfide phosphor.
9. The phosphor structure as set forth in claim 8, wherein the blue sub-pixel elements, and optionally the green sub-pixel elements are formed with a strontium sulfide phosphor, and wherein the red sub-pixel elements, and optionally the green sub-pixel elements are formed from one or more zinc sulfide phosphors.
10. The phosphor structure as set forth in claim 9, wherein the strontium sulfide phosphor is SrS:Ce and wherein the zinc sulfide phosphor is one or both of ZnS:Mn or Zn1-x Mg x S:Mn, with x being between 0.1 and 0.3.
11. The phosphor structure as set forth in claim 8, wherein the first phosphor is SrS:Ce and the second phosphor is one or more of ZnS:Mn or Zn1-x Mg x S:Mn, with x being between 0.1 and 0.3, and wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities comprises a further layer of SrS:Ce over the first and second phosphor deposits, whereby the blue sub-pixel elements are provided by SrS:Ce and the red and green sub-pixel elements are provided by SrS:Ce and one or both of ZnS:Mn or Zn1-x Mg x S:Mn.
12. The phosphor structure as set forth in claim 10, wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities comprises a threshold voltage adjustment layer over the red and green sub-pixel phosphor deposits.
13. The phosphor structure as set forth in claim 10, 11 or 12, wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities comprises the phosphor deposits being formed with different thicknesses.
14. The phosphor structure as set forth in claim 10, 11, 12 or 13, wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities comprises varying the areas of one or more of the sub-pixel phosphor deposits.
15. The phosphor structure as set forth claim 1, 2, or 14, wherein the means for setting and equalizing the threshold voltages, and for setting the relative luminosities, comprises a threshold voltage adjustment layer selected from the group consisting of one or more of a dielectric material or a semiconductor material, which, at its deposited thickness, does not conduct until the voltage across the patterned phosphor structure exceeds the threshold voltage which the patterned phosphor structure would have without the threshold voltage adjustment layer.
16. The phosphor structure as set forth in claim 15, wherein the threshold voltage adjustment layer is selected from the group consisting of binary metal oxides, binary metal sulfides, silica and silicon oxynitride.
17. The phosphor structure as set forth in claim 15, wherein the threshold voltage adjustment layer is selected from the group consisting of alumina, tantalum oxide, zinc sulfide, strontium sulfide, silica and silicon oxynitride.
18. The phosphor structure as set forth in claim 15, wherein the threshold voltage adjustment layer is selected from the group consisting of alumina and zinc sulfide.
19. The phosphor structure as set forth in claim 15, wherein threshold voltage adjustment layer is matched with the at least first or second phosphor deposits, such that if the phosphor deposit is formed from a zinc sulfide phosphor, the threshold voltage adjustment layer, if needed with that phosphor deposit, is a binary metal oxide.
20. The phosphor structure as set forth in claim 19, wherein the binary metal oxide is alumina when the phosphor deposit is one or more of ZnS:Mn or Zn1-x Mg x S:Mn, with x being between 0.1 and 0.3.
21. The phosphor structure as set forth in claim 5, 6 or 7, wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities comprises an additional phosphor layer deposited in one or more of the positions of over, under and embedded within the at least first and second phosphor deposits, having a same or different composition from the at least first and second phosphor deposits.
22. The phosphor structure as set forth in claim 5, 6 or 7, wherein the first and second phosphor deposits are a strontium sulfide phosphor providing the blue sub-pixel elements and a zinc sulfide phosphor providing the red and green sub-pixel elements, and wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities is a threshold voltage adjustment layer selected from the group consisting of one or more of a dielectric material or a semiconductor material in one or more of the positions of over, under and embedded within the zinc sulfide phosphor deposits.
23. The phosphor structure as set forth in claim 22, wherein the phosphors are SrS:Ce, which may be codoped with phosphorus, and Zn1-x Mg x S:Mn, with x being between 0.1 and 0.3, and wherein the threshold voltage adjustment layer is a layer of alumina located over the Zn1-x Mg x S:Mn phosphor deposits.
24. The phosphor structure as set forth in claim 5, 6 or 7, wherein the first and second phosphor deposits are a strontium sulfide phosphor providing the blue sub-pixel elements and one or more layers of a zinc sulfide phosphor providing the red and green sub-pixel elements, and wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities is the strontium sulfide phosphor deposits being formed thicker and wider than the zinc sulfide phosphor deposits.
25. The phosphor structure as set forth in claim 24, wherein the phosphors are SrS:Ce for the blue sub-pixel elements, which may be codoped with phosphorus, and for the red and green sub-pixels, Zn1-x Mg x S:Mn between layers of ZnS:Mn, with x being between 0.1 and 0.3.
26. The phosphor structure as set forth in claim 5, 6 or 7, wherein the first and second phosphor deposits are a strontium sulfide phosphor providing the blue and green sub-pixel elements and a zinc sulfide phosphor providing the red sub-pixel elements, and wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities is a threshold voltage adjustment layer selected from the group consisting of one or more of a dielectric material or a semiconductor material in one or more of the position of over, under and embedded within the zinc sulfide phosphor deposits.
27. The phosphor structure as set forth in claim 26, wherein the phosphors are SrS:Ce, which may be codoped with phosphorus, and ZnS:Mn, and wherein the threshold voltage adjustment layer is a layer of alumina located over the ZnS:Mn phosphor deposits.
28. An EL laminate for use in an AC electroluminescent display, comprising:
a rigid rear substrate;
a patterned phosphor structure comprising:
at least a first and a second phosphor, each emitting light in different ranges of the visible spectrum, but whose combined emission spectra contains red, green and blue light;
said at least first and second phosphors being in a layer, arranged in adjacent, repeating relationship to each other to provide a plurality of repeating at least first and second phosphor deposits; and one or more means associated with one or more of the at least first and second phosphor deposits, and which together with the at least first and second phosphor deposits, form the red, green and blue sub-pixel phosphor elements, for setting and equalizing the threshold voltages of the red, green and blue sub-pixel phosphor elements, and for setting the relative luminosities of the red, green and blue sub-pixel phosphor elements so that they bear set ratios to one another at each operating modulation voltage used to generate the desired luminosities for red, green and blue;
front and rear column and row electrodes on either side of the phosphor structure, the rows or columns of the front or rear electrode being aligned with the phosphor sub-pixel elements;
a thick film dielectric layer below the patterned phosphor structure formed from a sintered ceramic material having a dielectric constant greater than 500, and having a thickness greater than about 10 µm; and optionally, optical colour filter means aligned with the red, green and blue phosphor sub-pixel elements for transmitting red, green and blue light emitted from the phosphor sub-pixel elements.
29. The EL laminate as set forth in claim 28, wherein the at least first and second phosphor deposits are formed from phosphors of different host materials.
30. The EL laminate as set forth in claim 29, wherein the set luminosity ratios remain substantially constant over the range of operating modulation voltages.
31. The EL laminate as set forth in claim 30, wherein the set luminosities ratios between the red, green and blue sub-pixel phosphor elements is about 3:6:1.
32. The EL laminate as set forth in claim 29, 30 or 31, wherein the means for setting and equalizing the threshold voltages, and for setting the relative luminosities, comprises a threshold voltage adjustment layer of a dielectric material or a semiconductor material located in one or more of the positions of over, under and embedded within one or more of the at least first and second phosphor deposits.
33. The EL laminate as set forth in claim 29, 30, 31, or 32, wherein the means for setting and equalizing the threshold voltages, and for setting the relative luminosities, comprises the at least first and second phosphor deposits being formed with different thicknesses.
34. The EL laminate as set forth in claim 32 or 33, wherein, the means for setting and equalizing the threshold voltages, and for setting the relative luminosities, further comprises varying one or both of the following:
i. the areas of the phosphor deposits; and ii. the concentrations of a dopant or co-dopant in the phosphor deposits.
35. The EL laminate as set forth in claim 34, wherein the at least first and second phosphor deposits are formed from a zinc sulfide phosphor and a strontium sulfide phosphor.
36. The EL laminate as set forth in claim 35, wherein the blue sub-pixel elements, and optionally the green sub-pixel elements are formed with a strontium sulfide phosphor, and wherein the red sub-pixel elements, and optionally the green sub-pixel elements are formed from one or more zinc sulfide phosphors.
37. The EL laminate as set forth in claim 36, wherein the strontium sulfide phosphor is SrS:Ce and wherein the zinc sulfide phosphor is one or more of ZnS:Mn or Zn1-x Mg x S:Mn, with x being between 0.1 and 0.3.
38. The EL laminate as set forth in claim 35, wherein the first phosphor is SrS:Ce and the second phosphor is one or more of ZnS:Mn or Zn1-x Mg x S:Mn, with x being between 0.1 and 0.3, and wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities comprises a further layer of SrS:Ce over the first and second phosphor deposits, whereby the blue sub-pixel elements are provided by SrS:Ce and the red and green sub-pixel elements are provided by SrS:Ce and one or both of ZnS:Mn or Zn1-x Mg x S:Mn.
39. The EL laminate as set forth in claim 37, wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities comprises a threshold voltage adjustment layer over the red and green sub-pixel phosphor deposits.
40. The EL laminate as set forth in claim 37, 38, or 39, wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities comprises the phosphor deposits being formed with different thicknesses.
41. The EL laminate as set forth in claim 37, 38, 39 or 40, wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities comprises varying the areas of one or more of the sub-pixel phosphor deposits.
42. The EL laminate as set forth claim 28, 29, or 41, wherein the means for setting and equalizing the threshold voltages, and for setting the relative luminosities, comprises a threshold voltage adjustment layer selected from the group consisting of one or more of a dielectric material or a semiconductor material, which, at its deposited thickness, does not conduct until the voltage across the patterned phosphor structure exceeds the threshold voltage which the patterned phosphor structure would have without the threshold voltage adjustment layer.
43. The EL laminate as set forth in claim 42, wherein the threshold voltage adjustment layer is selected from the group consisting of binary metal oxides, binary metal sulfides, silica and silicon oxynitride.
44. The EL laminate as set forth in claim 42, wherein the threshold voltage adjustment layer is selected from the group consisting of alumina, tantalum oxide, zinc sulfide, strontium sulfide, silica and silicon oxynitride.
45. The EL laminate as set forth in claim 42, wherein the threshold voltage adjustment layer is selected from the group consisting of alumina and zinc sulfide.
46. The EL laminate as set forth in claim 42, wherein threshold voltage adjustment layer is matched with the at least first or second phosphor deposits, such that if the phosphor deposit is formed from a zinc sulfide phosphor, the threshold voltage adjustment layer, if needed with that phosphor deposit, is a binary metal oxide.
47. The EL laminate as set forth in claim 46, wherein the binary metal oxide is alumina when the phosphor deposit is one or more of ZnS:Mn or Zn1-x Mg x S:Mn, with x being between 0.1 and 0.3.
48. The EL laminate as set forth in claim 32, 33 or 34, wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities comprises an additional phosphor layer deposited in one or more of the positions of over, under and embedded within the at least first and second phosphor deposits, having a same or different composition from the at least first and second phosphor deposits.
49. The EL laminate as set forth in claim 32, 33 or 34, wherein the first and second phosphor deposits are a strontium sulfide phosphor providing the blue sub-pixel elements and a zinc sulfide phosphor providing the red and green sub-pixel elements, and wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities is a threshold voltage adjustment layer selected from the group consisting of one or more of a dielectric material or a semiconductor material in one or more of the positions of over, under and embedded within the zinc sulfide phosphor deposits.
50. The EL laminate as set forth in claim 49, wherein the phosphors are SrS:Ce, which may be codoped with phosphorus, and Zn1-x Mg x S:Mn, with x being between 0.1 and 0.3, and wherein the threshold voltage adjustment layer is a layer of alumina located over the Zn1-x Mg x S:Mn phosphor deposits.
51. The EL laminate as set forth in claim 32, 33 or 34, wherein the first and second phosphor deposits are a strontium sulfide phosphor providing the blue sub-pixel elements and one or more layers of a zinc sulfide phosphor providing the red and green sub-pixel elements, and wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities is the strontium sulfide phosphor deposits being formed thicker and wider than the zinc sulfide phosphor deposits.
52. The EL laminate as set forth in claim 51, wherein the phosphors are SrS:Ce for the blue sub-pixel elements, which may be codoped with phosphorus, and for the red and green sub-pixels, Zn1-x Mg x S:Mn between layers of ZnS:Mn, with x being between 0.1 and 0.3.
53. The EL laminate as set forth in claim 32, 33 or 34, wherein the first and second phosphor deposits are a strontium sulfide phosphor providing the blue and green sub-pixel elements and a zinc sulfide phosphor providing the red sub-pixel elements, and wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities is a threshold voltage adjustment layer selected from the group consisting of one or more of a dielectric material or a semiconductor material in one or more of the position of over, under and embedded within the zinc sulfide phosphor deposits.
54. The EL laminate as set forth in claim 53, wherein the phosphors are SrS:Ce, which may be codoped with phosphorus, and ZnS:Mn, and wherein the threshold voltage adjustment layer is a layer of alumina located over the ZnS:Mn phosphor deposits.
55. The EL laminate as set forth in claims 28, 29, 32, 33 or 34, wherein the thick film dielectric layer is formed from a pressed, sintered ceramic material having, compared to an unpressed, sintered dielectric layer of the same composition, improved dielectric strength, reduced porosity and uniform luminosity in an EL laminate.
56. The EL laminate as set forth in claim 35, 50, 52, or 54, wherein the thick film dielectric layer is formed from a pressed, sintered ceramic material having, compared to an unpressed, sintered dielectric layer of the same composition, improved dielectric strength, reduced porosity and uniform luminosity in an EL laminate.
57. The EL laminate as set forth in claim 55 or 56, wherein the dielectric layer has been pressed by cold isostatic pressing to reduce the thickness, after sintering, by about 20 to 50%.
58. The EL laminate as set forth in claim 57, wherein the pressed ceramic material has a reduced thickness, after sintering, of 30 to 40%.
59. The EL laminate as set forth in claim 58, wherein the pressed ceramic material has a thickness, after sintering, of between 10 and 50 µm.
60. The EL laminate as set forth in claim 58, wherein the pressed ceramic material has a thickness, after sintering, of between 10 and 20 µm.
61. The EL laminate as set forth in claim 60, wherein the ceramic material is a ferroelectric ceramic material having a dielectric constant greater than 500.
62. The EL laminate as set forth in claim 61, wherein the ceramic material has a perovskite crystal structure.
63. The EL laminate as set forth in claim 62, wherein the ceramic material is selected from the group consisting of one or more of BaTiO3, PbTiO3, PMN and PMN-PT.
64. The EL laminate as set forth in claim 62, wherein the ceramic material is selected from the group consisting of BaTiO3, PbTiO3, PMN and PMN-PT.
65. The EL laminate as set forth in claim 62, wherein the ceramic material is PMN-PT.
66. The EL laminate as set forth in claim 62, 64, or 65, wherein a second ceramic material is formed on the pressed, sintered dielectric layer to further smooth the surface.
67. The EL laminate as set forth in claim 59, wherein the second ceramic material is a ferroelectric ceramic material deposited by sol gel techniques followed by heating to convert to a ceramic material.
68. The EL laminate as set forth in claim 67, wherein the second ceramic material has a dielectric constant of at least 20 and a thickness of at least about 1 µm.
69. The EL laminate as set forth in claim 68, wherein the second ceramic material has a dielectric constant of at least 100.
70. The EL laminate as set forth in claim 69, wherein the second ceramic material has a thickness in the range of 1 to 3 µm.
71. The EL laminate as set forth in claim 70, wherein the second ceramic material is a ferroelectric ceramic material having a perovskite crystal structure.
72. The EL laminate as set forth in claim 71, wherein the second ceramic material is lead zirconium titanate or lead lanthanum zirconate titanate.
73. The EL laminate as set forth in claim 72, wherein the substrate and the rear electrode are formed from materials which can withstand temperatures of about 850°C.
74. The EL laminate as set forth in claim 73, wherein the substrate is an alumina sheet.
75. The EL laminate as set forth in claim 55, 66 or 72, which further comprises, a diffusion barrier layer above the dielectric layer or above the second ceramic material, which diffusion barrier layer is composed of a metal-containing electrically insulating binary compound that is chemically compatible with any adjacent layers and which is precisely stoichiometric.
76. The EL laminate as set forth in claim 75, wherein the diffusion barrier layer is formed from a compound which differs from its precise stoichiometric composition by less than 0.1 atomic percent.
77. The EL laminate as set forth in claim 76, wherein the diffusion barrier layer is formed from alumina, silica, or zinc sulfide.
78. The EL laminate as set forth in claim 76, wherein the diffusion barrier is formed from alumina.
79. The EL laminate as set forth in claim 77 or 78, wherein the diffusion barrier has a thickness of 100 to 1000 .ANG..
80. The EL laminate as set forth in claim 55, 66, 72 or 75, which further comprises, an injection layer above the dielectric layer, the second ceramic material or the barrier diffusion barrier, to provide a phosphor interface, composed of a binary, dielectric material which is non-stoichiometric in its composition and having electrons in a range of energy for injection into the phosphor layer.
81. The EL laminate as set forth in claim 80, wherein the injection layer is formed from a material which has greater than 0.5% atomic deviation from its stoichiometric composition.
82. The EL laminate as set forth in claim 81, wherein the injection layer is formed from hafnia or yttria.
83. The EL laminate as set forth in claim 82, wherein the injection layer has a thickness of 100 to 1000 .ANG..
84. The EL laminate as set forth in claim 75 or 80, wherein an injection layer of hafnia is included with a phosphor formed from a zinc sulfide phosphor, and wherein a diffusion barrier layer of zinc sulfide is used with a phosphor formed from a strontium sulfide phosphor.
85. A method of forming a patterned phosphor structure having red, green and blue sub-pixel elements for an AC electroluminescent display, comprising:
selecting at least a first and a second phosphor, each emitting light in different ranges of the visible spectrum, but whose combined emission spectra contains red, green and blue light;
depositing and patterning said at least first and second phosphors in a layer to form a plurality of repeating at least first and second phosphor deposits arranged in adjacent, repeating relationship to each other; and providing one or more means associated with one or more of the at least first and second phosphor deposits, and which together with the at least first and second phosphor deposits, form the red, green and blue sub-pixel phosphor elements, for setting and equalizing the threshold voltages of the red, green and blue sub-pixel phosphor elements and for setting the relative luminosities of the red, green and blue sub-pixel elements so that they bear set ratios to one another at each modulation voltage used to generate the desired luminosities for red, green and blue; and optionally annealing the patterned phosphor structure so formed.
86. The method as set forth in claim 85, wherein the at least first and second phosphor deposits are formed from phosphors of different host materials.
87. The method as set forth in claim 86, wherein the set luminosity ratios remain substantially constant over the range of operating modulation voltages.
88. The method as set forth in claim 87, wherein the set luminosities ratios between the red, green and blue sub-pixel phosphor elements are about 3:6:1.
89. The method as set forth in claim 86, 87 or 88, wherein the patterning of the at least first and second phosphor is achieved by photolithographic techniques, including the steps of:
a) depositing a layer of a first phosphor which is to form at least one of the red, green or blue sub-pixel elements;
b) removing the first phosphor in regions which are to define the other of the red, green or blue sub-pixel elements, leaving spaced first phosphor deposits;
c) depositing the second phosphor material over the first phosphor deposits and in regions which are to define the other of the red, green and blue sub-pixel elements; and d) removing the second phosphor material from above the first phosphor deposits leaving a plurality of repeating first and second phosphor deposits arranged in adjacent, repeating relationship to each other.
90. The method as set forth in claim 89, wherein step b) includes:
applying a photo-resist to the first phosphor, exposing the photo-resist through a photo-mask, developing the photo-resist, removing the first phosphor in regions that first phosphor is to define as one or more of the red, green and blue sub-pixel elements;
and wherein step d) includes:
removing by lift-off, the second phosphor and the resist from above the first phosphor deposits.
91. The method as set forth in claim 90, wherein the photo-resist in step b) is a negative resist that is exposed in the regions that the first phosphor is to define as one or more of the red, green and blue sub-pixel elements.
92. The method as set forth in claim 91, wherein the patterning is achieved with only one photo-mask.
93. The method as set forth in claim 86, 87, 88 or 91, wherein the means for setting and equalizing the threshold voltages, and for setting the relative luminosities, comprises a threshold voltage adjustment layer selected from the group consisting of one or more of a dielectric material or a semiconductor material deposited in one or more of the positions of over, under and embedded within one or more of the at least first and second phosphor deposits.
94. The method as set forth in claim 86, 87, 88, 91 or 93, wherein the means for setting and equalizing the threshold voltages, and for setting the relative luminosities, comprises the at least first and second phosphor deposits being deposited with different thicknesses.
95. The method as set forth in claim 93 or 94, wherein, the means for setting and equalizing the threshold voltages, and for setting the relative luminosities, further comprises varying one or both of the following:
i. the areas of the phosphor deposits; and ii. the concentrations of a dopant or co-dopant in the phosphor deposits.
96. The method as set forth in claim 95, wherein the at least first and second phosphor deposits include a zinc sulfide phosphor and a strontium sulfide phosphor.
97. The method as set forth in claim 96, wherein the blue sub-pixel elements, and optionally the green sub-pixel elements are formed with a strontium sulfide phosphor, and wherein the red sub-pixel elements, and optionally the green sub-pixel elements are formed from one or more zinc sulfide phosphors.
98. The method as set forth in claim 97, wherein the strontium sulfide phosphor is SrS:Ce and wherein the zinc sulfide phosphor is one or more of ZnS:Mn or Zn1-x Mg x S:Mn, with x being between 0.1 and 0.3.
99. The method as set forth in claim 96, wherein the first phosphor is SrS:Ce and the second phosphor is one or more of ZnS:Mn or Zn1-x Mg x S:Mn, with x being between 0.1 and 0.3, and wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities is provided by depositing a further layer of SrS:Ce over the first and second phosphor deposits, whereby the blue sub-pixel elements are provided by SrS:Ce and the red and green sub-pixel elements are provided by SrS:Ce and one or more of ZnS:Mn or Zn1-x Mg x S:Mn.
100. The method as set forth in claim 98, wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities are provided by depositing a threshold voltage adjustment layer over one or more of the red and green sub-pixel phosphor deposits.
101. The method as set forth in claim 98, 99 or 100, wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities is provided by depositing the phosphor, and thus forming the phosphor deposits, with different thicknesses.
102. The method as set forth in claim 98, 99, 100 or 101, wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities is provided by varying the areas of one or more of the sub-pixel phosphor deposits.
103. The method as set forth claim 85, 86 or 102, wherein the means for setting and equalizing the threshold voltages, and for setting the relative luminosities, is provided by depositing over one or more of the red, green and blue sub-pixel deposits, a threshold voltage adjustment layer selected from the group consisting of one or more of a dielectric material or a semiconductor material, which, at its deposited thickness, does not conduct until the voltage across the patterned phosphor structure exceeds the threshold voltage which the patterned phosphor structure would have without the threshold voltage adjustment layer.
104. The method as set forth in claim 103, wherein the threshold voltage adjustment layer is selected from the group consisting of binary metal oxides, binary metal sulfides, silica and silicon oxynitride.
105. The method as set forth in claim 103, wherein the threshold voltage adjustment layer is selected from the group consisting of alumina, tantalum oxide, zinc sulfide, strontium sulfide, silica and silicon oxynitride.
106. The method as set forth in claim 103, wherein the threshold voltage adjustment layer is selected from the group consisting of alumina and zinc sulfide.
107. The method as set forth in claim 103, wherein threshold voltage adjustment layer is matched with the at least first or second phosphor deposits, such that if the phosphor deposit is formed from a zinc sulfide phosphor, the threshold voltage adjustment layer, if needed with that phosphor deposit, is a binary metal oxide, and if the phosphor deposit is formed from a strontium sulfide phosphor, the threshold voltage adjustment layer, if needed with that phosphor deposit, is a binary metal sulfide.
108. The method as set forth in claim 107, wherein the binary metal oxide is alumina when the phosphor deposit is one or more of ZnS:Mn or Zn1-x Mg x S:Mn, with x being between 0.1 and 0.3.
109. The method as set forth in claim 93, 94, or 98, wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities comprises an additional phosphor layer deposited in one or more of the positions of over, under and embedded within the at least first and second phosphor deposits, having a same or different composition from the at least first and second phosphor deposits.
110. The method as set forth in claim 93, 94 or 95, wherein the first and second phosphor deposits are a strontium sulfide phosphor providing the blue sub-pixel elements and a zinc sulfide phosphor providing the red and green sub-pixel elements, and wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities is provided by depositing a threshold voltage adjustment layer selected from the group consisting of one or more of a dielectric material or a semiconductor material in one or more of the positions of over, under and embedded within the zinc sulfide phosphor deposits.
111. The method as set forth in claim 110, wherein the phosphors are SrS:Ce, which may be codoped with phosphorus, and Zn1-x Mg x S:Mn, with x being between 0.1 and 0.3, and wherein the threshold voltage adjustment layer is a layer of alumina deposited over the Zn1-x Mg x S:Mn phosphor deposits.
112. The method as set forth in claim 93, 94 or 95, wherein the first and second phosphor deposits are a strontium sulfide phosphor providing the blue sub-pixel elements and one or more layers of a zinc sulfide phosphor providing the red and green sub-pixel elements, and wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities is provided by forming the strontium sulfide phosphor deposits thicker and wider than and the zinc sulfide phosphor deposits.
113. The method as set forth in claim 112, wherein the phosphors are SrS:Ce for the blue sub-pixel elements, which may be codoped with phosphorus, and for the red and green sub-pixels, Zn1-x Mg x S:Mn between layers of ZnS:Mn, with x being between 0.1 and 0.3.
114. The method as set forth in claim 93, 94 or 95, wherein the first and second phosphor deposits are a strontium sulfide phosphor providing the blue and green sub-pixel elements and a zinc sulfide phosphor providing the red sub-pixel elements, and wherein the means for setting and equalizing the threshold voltages and for setting the relative luminosities is provided by depositing a threshold voltage adjustment layer selected from the group consisting of one or more of a dielectric material or a semiconductor material in one or more of the positions of over, under and embedded within the zinc sulfide phosphor deposits.
115. The method as set forth in claim 114, wherein the phosphors are SrS:Ce, which may be codoped with phosphorus, and ZnS:Mn, and wherein the threshold voltage adjustment layer is a layer of alumina deposited over the ZnS:Mn phosphor deposits.
116. The method as set forth in claims 91, wherein one or both of the first and second phosphors is susceptible to hydrolysis, wherein the negative resist is a polyisoprene-based resist, wherein the first phosphor is removed with an acid etchant solution, and wherein the second phosphor is removed with a non-aqueous, predominately polar, aprotic solvent solution.
117. The method as set forth in claim 116, wherein the first and second phosphor deposits are a strontium sulfide phosphor and a zinc sulfide phosphor, and wherein the predominately polar, aprotic solvent solution is toluene, with a minor amount of methanol.
118. The method as set forth in claim 117, wherein the first and second phosphor deposits are patterned in a layer from SrS:Ce and ZnS:Mn, and an additional phosphor layer of SrS:Ce is deposited over the patterned layer such that, the SrS:Ce deposits form the blue sub-pixel elements, and the ZnS:Mn deposits overlaid with the SrS:Ce deposits form the red and green sub-pixel elements, the patterning being achieved by:
a) depositing a layer of the SrS:Ce which is to form the blue sub-pixel elements;
b) applying the negative photoresist on the SrS:Ce, exposing the photoresist in those regions which are to form the blue sub-pixel elements, and removing the SrS:Ce and the unexposed photoresist in those regions which are to define the red and green sub-pixel elements, leaving spaced SrS:Ce deposit;
c) depositing the ZnS:Mn to cover both the SrS:Ce deposits and the regions where the SrS:Ce has been removed;
d) optionally depositing an injection layer;
e) removing by lift-off, the ZnS:Mn, the photoresist and the optional injection layer in the regions above SrS:Ce, to form a plurality of repeating first and second phosphor deposits arranged in adjacent, repeating relationship to each other; and f) providing the means for setting and equalizing the threshold voltages and setting the relative luminosities by depositing an additional layer of SrS:Ce over the first and second phosphor deposits.
119. The method as set forth in claim 117, wherein the first and second phosphor deposits are a strontium sulfide phosphor providing the blue sub-pixel elements and a zinc sulfide phosphor providing the red and green sub-pixel elements, and wherein the means for setting and equalizing the threshold voltages is a threshold voltage adjustment layer selected from the group consisting of one or more of a dielectric material or a semiconductor material deposited in one or more of the positions of over, under and embedded within the zinc sulfide phosphor deposits.
120. The method as set forth in claim 119, wherein the phosphors are SrS:Ce, which may be codoped with phosphorus, and Zn1-x Mg x S:Mn, with x being between 0.1 and 0.3, wherein the threshold voltage adjustment layer is a layer of alumina deposited over the Zn1-x Mg x S:Mn phosphor, and wherein the patterning is achieved by:
a) depositing a layer of the SrS:Ce which is to form the blue sub-pixel elements;
b) applying the negative photoresist on the SrS:Ce, exposing the photoresist in those regions which are to form the blue sub-pixel elements, and removing the SrS:Ce and the unexposed photoresist in those regions which are to define the red and green sub-pixel elements, leaving spaced SrS:Ce deposits;
c) depositing the Zn1-x Mg x S:Mn to cover both the SrS:Ce deposits and the regions where the SrS:Ce has been removed;
d) optionally depositing an injection layer;
e) depositing the threshold voltage adjustment layer above the Zn1-x Mg x S:Mn; and e) removing by lift-off, the Zn1-x Mg x S:Mn, the photoresist, the threshold voltage adjustment layer, and the optional injection layer in the regions above SrS:Ce, to form a plurality of repeating first and second phosphor deposits arranged in adjacent, repeating relationship to each other.
121. The method as set forth in claim 117, wherein the first and second phosphor deposits are a strontium sulfide phosphor providing the blue sub-pixel elements and a zinc sulfide phosphor providing the red and green sub-pixel elements, and wherein the means for setting and equalizing the threshold voltages and setting the relative luminosities is provided by forming the strontium sulfide phosphor deposits thicker and with greater area than the zinc sulfide phosphor deposits.
122. The method as set forth in claim 121, wherein the phosphors are SrS:Ce, which may be codoped with phosphorus, and Zn1-x Mg x S:Mn between layers of ZnS:Mn, with x being between 0.1 and 0.3, and wherein the patterning is achieved by:
a) depositing a layer of the SrS:Ce which is to form the blue sub-pixel elements;
b) applying the negative photoresist on the SrS:Ce, exposing the photoresist in those regions which are to form the blue sub-pixel elements, and removing the SrS:Ce and the unexposed photoresist in those regions which are to define the red and green sub-pixel elements, leaving spaced SrS:Ce deposits;
c) depositing the a layer of ZnS:Mn, then a layer of Zn1-x Mg x S:Mn, and then a layer of ZnS:Mn to cover both the SrS:Ce deposits and the regions where the SrS:Ce has been removed;
d) optionally depositing an injection layer;
e) removing by lift-off, the ZnS:Mn and the Zn1-x Mg x S:Mn, the photoresist, and the optional injection layer in the regions above SrS:Ce, to form a plurality of repeating first and second phosphor deposits arranged in adjacent, repeating relationship to each other.
123. The method as set forth in claim 117, wherein the first and second phosphor deposits are a strontium sulfide phosphor providing the blue and green sub-pixel elements and a zinc sulfide phosphor providing the red sub-pixel elements, and wherein the means for setting and equalizing the threshold voltages is provided by depositing a threshold voltage adjustment layer selected from the group consisting of one or more of a dielectric material or a semiconductor material in one or more of the positions of over, under and embedded within the zinc sulfide phosphor deposits.
124. The method as set forth in claim 123, wherein the phosphors are SrS:Ce, which may be codoped with phosphorus, and ZnS:Mn, wherein the threshold voltage adjustment layer is a layer of alumina located over the ZnS:Mn phosphor, and wherein the patterning is achieved by:
a) depositing a layer of the SrS:Ce which is to form the blue and green sub-pixel elements;
b) applying the negative photoresist on the SrS:Ce, exposing the photoresist in those regions which are to form the blue and green sub-pixel elements, and removing the SrS:Ce and the unexposed photoresist in those regions which are to define the red sub-pixel elements, leaving spaced SrS:Ce deposits for the blue and green sub-pixel elements which are wider than the regions left for the red sub-pixel elements;
c) depositing an optional layer of alumina as a barrier diffusion layer;
d) depositing the ZnS:Mn to cover both the SrS:Ce deposits and the regions where the SrS:Ce has been removed;
e) depositing the threshold voltage adjustment layer above the Zn:S:Mn; and f) removing by lift-off, the optional barrier diffusion layer, the ZnS:Mn, the photoresist, and the threshold voltage adjustment layer in the regions above SrS:Ce, to form a plurality of repeating first and second phosphor deposits arranged in adjacent, repeating relationship to each other.
125. A method of forming a thick film dielectric layer in an EL laminate of the type including one or more phosphor layers sandwiched between a front and a rear electrode, the phosphor layer being separated from the rear electrode by the thick film dielectric layer, comprising:
depositing a ceramic material in one or more layers by a thick film technique to form a dielectric layer having a thickness of 10 to 300 µm;
pressing the dielectric layer to form a densified layer with reduced porosity and surface roughness; and sintering the dielectric layer to form a pressed, sintered dielectric layer which, in an EL
laminate, has an improved uniform luminosity over an unpressed, sintered dielectric layer of the same composition.
126. The method as set forth in claim 125, wherein the dielectric layer is deposited on a rigid substrate providing the rear electrode.
127. The method as set forth in claim 125, wherein the pressing is isostatic pressing.
128. The method as set forth in claim 126, wherein the pressing is cold isostatic pressing at up to 350,000 kPa to reduce the thickness of the dielectric layer, after sintering, by about 20 to 50%.
129. The method as set forth in claim 128, wherein the ceramic material is deposited by screen printing, in one or more layers, and is dried prior to pressing.
130. The method as set forth in claim 129, wherein the ceramic material is pressed to reduce the thickness, after sintering, by 30 to 40%.
131. The method as set forth in claim 130, wherein the ceramic material is pressed to a thickness, after sintering, of between 10 and 50 µm.
132. The method as set forth in claim 130, wherein the ceramic material is pressed to a thickness, after sintering, of between 10 and 20 µm.
133. The method as set forth in claim 132, wherein the dielectric layer has a deposited thickness of 20 to 50 µm.
134. The method as set forth in claim 132 or 133, wherein the ceramic material is a ferroelectric ceramic material having a dielectric constant greater than 500.
135. The method as set forth in claim 134, wherein the ceramic material has a perovskite crystal structure.
136. The method as set forth in claim 135, wherein the ceramic material is selected from the group consisting of one or more of BaTiO3, PbTiO3, PMN and PMN-PT.
137. The method as set forth in claim 135, wherein the ceramic material is selected from the group consisting of BaTiO3, PbTiO3, PMN and PMN-PT.
138. The method as set forth in claim 137, wherein the ceramic material is PMN-PT.
139. The method as set forth in claim 136, 137, or 138, wherein a second ceramic material is formed on the pressed, sintered dielectric layer to further smooth the surface.
140. The method as set forth in claim139, wherein the second ceramic material is a ferroelectric ceramic material which is deposited by a sol gel technique to form a sol gel layer.
141. The method as set forth in claim 140, wherein the second ceramic material has a dielectric constant of at least 20 and a thickness of at least about 1 µm.
142. The method as set forth in claim 141, wherein the second ceramic material has a dielectric constant of at least 100.
143. The method as set forth in claim 142, wherein the second ceramic material has a thickness in the range of 1 to 3 µm.
144. The method as set forth in claim 143, wherein the second ceramic material is deposited by a sol gel techniques selected from spin deposition or dipping, followed by heating to convert to a ceramic material.
145. The method as set forth in claim 144, wherein the second ceramic material is a ferroelectric ceramic material having a perovskite crystal structure.
146. The method as set forth in claim 145, wherein the second ceramic material is lead zirconium titanate or lead lanthanum zirconate titanate.
147. The method as set forth in claim 125, 139 or 146, which further comprises, prior to forming the dielectric layer, providing a substrate having sufficient rigidity to support the laminate, and forming the rear electrode on the substrate.
148. The method as set forth in claim 147, wherein the substrate and the rear electrode are formed from materials which can withstand temperatures of about 850°C.
149. The method as set forth in claim 148, wherein the substrate is an alumina sheet.
150. The method as set forth in claim 125, 139 or 149, which further comprises, depositing a diffusion barrier layer above the dielectric layer or above the second ceramic material, which diffusion barrier layer is composed of a metal-containing electrically insulating binary compound that is chemically compatible with any adjacent layers and which is precisely stoichiometric.
151. The method as set forth in claim 150, wherein the diffusion barrier layer is formed from a compound which differs from its precise stoichiometric composition by less than 0.1 atomic percent.
152. The method as set forth in claim 151, wherein the diffusion barrier layer is formed from alumina, silica, or zinc sulfide.
153. The method as set forth in claim 152, wherein the diffusion barrier is formed from alumina.
154. The method as set forth in claim 153, wherein the diffusion barrier has a thickness of 100 to 1000 .ANG..
155. The method as set forth in claim 125, 139 or 150, which further comprises, depositing an injection layer above the dielectric layer, the second ceramic material or the barrier diffusion barrier, to provide a phosphor interface, composed of a binary, dielectric material which is non-stoichiometric in its composition and having electrons in a range of energy for injection into the phosphor layer.
156. The method as set forth in claim 155, wherein the injection layer is formed from a material which has greater than 0.5% atomic deviation from its stoichiometric composition.
157. The method as set forth in claim 156, wherein the injection layer is formed from hafnia or yttria.
158. The method as set forth in claim 157, wherein the injection layer has a thickness of 100 to 1000 .ANG..
159. The method as set forth in claim 156 or 158, wherein the injection layer is hafnia when the phosphor is a zinc sulfide phosphor, and wherein a diffusion barrier layer of zinc sulfide is used with a strontium sulfide phosphor.
160. A combined substrate and dielectric layer component for use in an EL
laminate, comprising:
a substrate providing a rear electrode; and a thick film dielectric layer formed on the substrate from a pressed, sintered ceramic material having, compared to an unpressed, sintered dielectric layer of the same composition, improved dielectric strength, reduced porosity and uniform luminosity in an EL
laminate.
161. The combined substrate and dielectric layer component as set forth in claim 160, formed on a rigid substrate providing a rear electrode.
162. The combined substrate and dielectric layer component as set forth in claim 161, wherein the dielectric layer has been pressed by cold isostatic pressing to reduce the thickness, after sintering, by about 20 to 50%.
163. The combined substrate and dielectric layer component as set forth in claim 162, wherein the pressed ceramic material has a reduced thickness, after sintering, of 30 to 40%.
164. The combined substrate and dielectric layer component as set forth in claim 163, wherein the pressed ceramic material has a thickness, after sintering, of between 10 and 50 µm.
165. The combined substrate and dielectric layer component as set forth in claim 163, wherein the pressed ceramic material has a thickness, after sintering, of between 10 and 20 µm.
166. The combined substrate and dielectric layer component as set forth in claim 165, wherein the ceramic material is a ferroelectric ceramic material having a dielectric constant greater than 500.
167. The combined substrate and dielectric layer component as set forth in claim 166, wherein the ceramic material has a perovskite crystal structure.
168. The combined substrate and dielectric layer component as set forth in claim 167, wherein the ceramic material is selected from the group consisting of one or more of BaTiO3, PbTiO3, PMN and PMN-PT.
169. The combined substrate and dielectric layer component as set forth in claim 167, wherein the ceramic material is selected from the group consisting of BaTiO3, PbTiO3, PMN
and PMN-PT.
170. The combined substrate and dielectric layer component as set forth in claim 167, wherein the ceramic material is PMN-PT.
171. The combined substrate and dielectric layer component as set forth in claim 168, 169, or 170, wherein a second ceramic material is formed on the pressed, sintered dielectric layer to further smooth the surface.
172. The combined substrate and dielectric layer component as set forth in claim 171, wherein the second ceramic material is a ferroelectric ceramic material deposited by sol gel techniques followed by heating to convert to a ceramic material.
173. The combined substrate and dielectric layer component as set forth in claim 172, wherein the second ceramic material has a dielectric constant of at least 20 and a thickness of at least about 1 µm.
174. The combined substrate and dielectric layer component as set forth in claim 173, wherein the second ceramic material has a dielectric constant of at least 100.
175. The combined substrate and dielectric layer component as set forth in claim 174, wherein the second ceramic material has a thickness in the range of 1 to 3 µm.
176. The combined substrate and dielectric layer component as set forth in claim 175, wherein the second ceramic material is a ferroelectric ceramic material having a perovskite crystal structure.
177. The combined substrate and dielectric layer component as set forth in claim 176, wherein the second ceramic material is lead zirconium titanate or lead lanthanum zirconate titanate.
178. The combined substrate and dielectric layer component as set forth in claim 160, 171, or 177, wherein the combined substrate and dielectric layer component is formed on a rigid substrate, on which is formed the rear electrode.
179. The combined substrate and dielectric layer component as set forth in claim 178, wherein the substrate and the rear electrode are formed from materials which can withstand temperatures of about 850°C.
180. The combined substrate and dielectric layer component as set forth in claim 179, wherein the substrate is an alumina sheet.
181. The combined substrate and dielectric layer component as set forth in claim 160, 171, or 178, which further comprises, a diffusion barrier layer above the dielectric layer or above the second ceramic material, which diffusion barrier layer is composed of a metal-containing electrically insulating binary compound that is chemically compatible with any adjacent layers and which is precisely stoichiometric.
182. The combined substrate and dielectric layer component as set forth in claim 181, wherein the diffusion barrier layer is formed from a compound which differs from its precise stoichiometric composition by less than 0.1 atomic percent.
183. The combined substrate and dielectric layer component as set forth in claim 182, wherein the diffusion barrier layer is formed from alumina, silica, or zinc sulfide.
184. The combined substrate and dielectric layer component as set forth in claim 182, wherein the diffusion barrier is formed from alumina.
185. The combined substrate and dielectric layer component as set forth in claim 183 or 184, wherein the diffusion barrier has a thickness of 100 to 1000 .ANG..
186. The combined substrate and dielectric layer component as set forth in claim 160, 171, 178 or 181, which further comprises, an injection layer above the dielectric layer, the second ceramic material or the barrier diffusion barrier, to provide a phosphor interface, composed of a binary, dielectric material which is non-stoichiometric in its composition and having electrons in a range of energy for injection into the phosphor layer.
187. The combined substrate and dielectric layer component as set forth in claim 186, wherein the injection layer is formed from a material which has greater than 0.5% atomic deviation from its stoichiometric composition.
188. The combined substrate and dielectric layer component as set forth in claim 187, wherein the injection layer is formed from hafnia or yttria.
189. The combined substrate and dielectric layer component as set forth in claim 188, wherein the injection layer has a thickness of 100 to 1000 .ANG..
190. The combined substrate and dielectric layer component as set forth in claim 187 or 189, wherein the injection layer is hafnia with a zinc sulfide phosphor, and wherein a diffusion barrier layer of zinc sulfide is used with a strontium sulfide phosphor.
191. An EL laminate, comprising:
a planar phosphor layer;
a front and rear planar electrode on either side of the phosphor layer;
a rear substrate providing the rear electrode, the rear substrate having sufficient rigidity to support the laminate; and a thick film dielectric layer on the rigid substrate providing the rear electrode, the thick film dielectric layer being formed from a pressed, sintered ceramic material having, compared to an unpressed, sintered dielectric layer of the same composition, improved dielectric strength, reduced porosity and uniform luminosity in an EL laminate.
192. The EL laminate as set forth in claim 191, formed on a rigid substrate providing a rear electrode.
193. The EL laminate as set forth in claim 191 or 192, wherein the dielectric layer has been pressed by cold isostatic pressing to reduce the thickness, after sintering, by about 20 to 50%.
194. The EL laminate as set forth in claim 193, wherein the pressed ceramic material has a reduced thickness, after sintering, of 30 to 40%.
195. The EL laminate as set forth in claim 194, wherein the pressed ceramic material has a thickness, after sintering, of between 10 and 50 µm.
196. The EL laminate as set forth in claim 194, wherein the pressed ceramic material has a thickness, after sintering, of between 10 and 20 µm.
197. The EL laminate as set forth in claim 196, wherein the ceramic material is a ferroelectric ceramic material having a dielectric constant greater than 500.
198. The EL laminate as set forth in claim 197, wherein the ceramic material has a perovskite crystal structure.
199. The EL laminate as set forth in claim 198, wherein the ceramic material is selected from the group consisting of one or more of BaTiO3, PbTiO3, PMN and PMN-PT.
200. The EL laminate as set forth in claim 198, wherein the ceramic material is selected from the group consisting of BaTiO3, PbTiO3, PMN and PMN-PT.
201. The EL laminate as set forth in claim 198, wherein the ceramic material is PMN-PT.
202. The EL laminate as set forth in claim 199, 200 or 201, wherein a second ceramic material is formed on the pressed, sintered dielectric layer to further smooth the surface.
203. The EL laminate as set forth in claim 202, wherein the second ceramic material is a ferroelectric ceramic material deposited by sol gel techniques followed by heating to convert to a ceramic material.
204. The EL laminate as set forth in claim 203, wherein the second ceramic material has a dielectric constant of at least 20 and a thickness of at least about 1 µm.
205. The EL laminate as set forth in claim 204, wherein the second ceramic material has a dielectric constant of at least 100.
206. The EL laminate as set forth in claim 205, wherein the second ceramic material has a thickness in the range of 1 to 3 µm.
207. The EL laminate as set forth in claim 206, wherein the second ceramic material is a ferroelectric ceramic material having a perovskite crystal structure.
208. The EL laminate as set forth in claim 207, wherein the second ceramic material is lead zirconium titanate or lead lanthanum zirconate titanate.
209. The EL laminate as set forth in claim 191, 202, or 208, wherein the EL
laminate is formed on a rigid substrate, on which is formed the rear electrode.
210. The EL laminate as set forth in claim 209, wherein the substrate and the rear electrode are formed from materials which can withstand temperatures of about 850°C.
211. The EL laminate as set forth in claim 210, wherein the substrate is an alumina sheet.
212. The EL laminate as set forth in claim 191, 202, or 209, which further comprises, a diffusion barrier layer above the dielectric layer or above the second ceramic material, which diffusion barrier layer is composed of a metal-containing electrically insulating binary compound that is chemically compatible with any adjacent layers and which is precisely stoichiometric.
213. The EL laminate as set forth in claim 212, wherein the diffusion barrier layer is formed from a compound which differs from its precise stoichiometric composition by less than 0.1 atomic percent.
214. The EL laminate as set forth in claim 213, wherein the diffusion barrier layer is formed from alumina, silica, or zinc sulfide.
215. The EL laminate as set forth in claim 213, wherein the diffusion barrier is formed from alumina.
216. The EL laminate as set forth in claim 214 or 215, wherein the diffusion barrier has a thickness of 100 to 1000 .ANG..
217. The EL laminate as set forth in claim 191, 202, 209 or 212, which further comprises, an injection layer above the dielectric layer, the second ceramic material or the barrier diffusion barrier, to provide a phosphor interface, composed of a binary, dielectric material which is non-stoichiometric in its composition and having electrons in a range of energy for injection into the phosphor layer.
218. The EL laminate as set forth in claim 217, wherein the injection layer is formed from a material which has greater than 0.5% atomic deviation from its stoichiometric composition.
219. The EL laminate as set forth in claim 218, wherein the injection layer is formed from hafnia or yttria.
220. The EL laminate as set forth in claim 219, wherein the injection layer has a thickness of 100 to 1000 .ANG..
221. The EL laminate as set forth in claim 218 or 220, wherein the injection layer is hafnia with a zinc sulfide phosphor, and wherein a diffusion barrier layer of zinc sulfide is used with a strontium sulfide phosphor.
222. A method of synthesizing strontium sulfide, comprising:
providing a source of high purity strontium carbonate in a dispersed form;
heating the strontium carbonate in a reactor with gradual heating up to a maximum temperature in the range of 800 to 1200°C;
contacting the heated strontium carbonate with a flow of sulfur vapours formed by heating elemental sulfur in the reactor to at least 300°C in an inert atmosphere; and terminating the reaction by stopping the flow of sulfur at a point when sulfur dioxide or carbon dioxide in the reaction gas reaches an amount which correlates with an amount of oxygen in oxygen-containing strontium compounds in the reaction product which is in the range of 1 to 10 atomic percent.
223. The method as set forth in claim 222, wherein the sulfur is heated in the temperature range of 360 to 440°C.
224. The method as set forth in claim 222 or 223, wherein the strontium carbonate is provided in a dispersed form by mixing with one or more volatile, non-contaminating, clean evaporating compounds which decompose into gaseous products prior to the onset of the reaction of strontium carbonate.
225. The method as set forth in claim 224, wherein the volatile compound is selected from the group consisting of elemental sulfur and ammonium carbonate included in a weight ratio with strontium carbonate in the range of 1:9 to 1:1.
226. The method as set forth in claim 222 or 225, wherein the source of high purity strontium carbonate is doped with a source of cerium in the range of 0.01 to 0.35 mole%.
227. The method as set forth in claim 96, wherein the strontium sulfide phosphor is synthesized by a method comprising:
providing a source of high purity strontium carbonate in a dispersed form;
heating the strontium carbonate in a reactor with gradual heating up to a maximum temperature in the range of 800 to 1200°C;
contacting the heated strontium carbonate with a flow of sulfur vapours formed by heating elemental sulfur in the reactor to at least 300°C in an inert atmosphere; and terminating the reaction by stopping the flow of sulfur at a point when sulfur dioxide or carbon dioxide in the reaction gas reaches an amount which correlates with an amount of oxygen in oxygen-containing strontium compounds in the reaction product which is in the range of 1 to 10 atomic percent.
228. The method as set forth in claim 227, wherein the sulfur is heated in the temperature range of 360 to 440°C.
229. The method as set forth in claim 227 or 228, wherein the strontium carbonate is provided in a dispersed form by mixing with one or more volatile, non-contaminating, clean evaporating compounds which decompose into gaseous products prior to the onset of the reaction of strontium carbonate.
230. The method as set forth in claim 229, wherein the volatile compound is selected from the group consisting of elemental sulfur and ammonium carbonate included in a weight ratio with strontium carbonate in the range of 1:9 to 1:1.
231. The method as set forth in claim 227 or 230, wherein the source of high purity strontium carbonate is doped with a source of cerium in the range of 0.01 to 0.35 mole%.
232. A method of forming a patterned phosphor structure having red, green and blue sub-pixel elements for an AC electroluminescent display, comprising:
a) selecting at least a first and a second phosphor, each emitting light in different ranges of the visible spectrum, but whose combined emission spectra contains red, green and blue light;
b) depositing a layer of the first phosphor which is to form at least one of the red, green or blue sub-pixel elements;
c) applying a photo-resist to the first phosphor, exposing the photo-resist through a photo-mask, developing the photo-resist, and removing the first phosphor in regions that the first phosphor is to define as one or more of the red, green and blue sub-pixel elements, leaving spaced first phosphor deposits, wherein the first phosphor is removed with an etchant solution comprising a mineral acid, or a source of anions of a mineral acid, in a non-aqueous, polar, organic solvent which solubilizes the reaction product of the first phosphor with anions of the mineral acid, and wherein optionally, prior to removing the first phosphor with the etchant solution, the first phosphor layer is immersed in the non-aqueous organic solvent;
d) depositing the second phosphor material over the first phosphor deposits and in regions which are to define the other of the red, green and blue sub-pixel elements; and e) removing by lift-off, the second phosphor material and the resist from above the first phosphor deposits leaving a plurality of repeating first and second phosphor deposits arranged in adjacent, repeating relationship to each other.
233. The method as set forth in claim 232, wherein the lift-off step is accomplished using a non-aqueous, predominately polar, aprotic solvent solution.
234. The method as set forth in claim 233, wherein at least one of the phosphors is an alkaline earth sulfide or selenide phosphor, and wherein the etchant solution is a mineral acid in methanol.
235. The method as set forth in claim 234, wherein the etchant solution includes an amount between 0.1 and 10% by volume of the mineral acid.
236. The method as set forth in claim 235, wherein the mineral acid is mineral acid is HC1 or H3PO4 or mixtures of these acids.
237. The method as set forth in claim 235 or 236, wherein the photoresist is a negative resist.
238. The method as set forth in claim 237, wherein the photoresist is a polyisoprene-based photoresist.
239. The method as set forth in claim 235, 237, or 238, wherein the lift-off is accomplished with a solution of methanol in toluene.
240. The method as set forth in claim 240, wherein the methanol is included in an amount between 5 and 20% by volume.
241. The method as set forth in claim 235, 237, 238 or 240, wherein one of the phosphors is a strontium sulfide phosphor.
242. The method as set forth in claim 241, wherein the first phosphor is a strontium sulfide phosphor, and the second phosphor is a zinc sulfide phosphor.
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DE60027426T2 (en) 2006-11-02
KR100797005B1 (en) 2008-01-22
US7586256B2 (en) 2009-09-08
US7427422B2 (en) 2008-09-23
HK1046616A1 (en) 2003-01-17
AU4738100A (en) 2000-12-05
CA2371760C (en) 2013-06-25
EP1188352A1 (en) 2002-03-20
US6939189B2 (en) 2005-09-06
KR20020003392A (en) 2002-01-12
DE60027426D1 (en) 2006-05-24
JP2003500805A (en) 2003-01-07
CN1360812A (en) 2002-07-24
US20040033307A1 (en) 2004-02-19
US20040033752A1 (en) 2004-02-19
US20040032208A1 (en) 2004-02-19
WO2000070917A1 (en) 2000-11-23
US6771019B1 (en) 2004-08-03
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US20050202157A1 (en) 2005-09-15
EP1188352B1 (en) 2006-04-19

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