CA2367890A1 - A host adapter for combining i/o completion reports and method of using the same - Google Patents

A host adapter for combining i/o completion reports and method of using the same Download PDF

Info

Publication number
CA2367890A1
CA2367890A1 CA002367890A CA2367890A CA2367890A1 CA 2367890 A1 CA2367890 A1 CA 2367890A1 CA 002367890 A CA002367890 A CA 002367890A CA 2367890 A CA2367890 A CA 2367890A CA 2367890 A1 CA2367890 A1 CA 2367890A1
Authority
CA
Canada
Prior art keywords
requests
combining
same
devices
host computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002367890A
Other languages
French (fr)
Other versions
CA2367890C (en
Inventor
Charles Micalizzi Jr.
Thanh X. Nghiem
Richard L. Romaniec
Toan B. Nguyen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
QLogic LLC
Original Assignee
Qlogic Corporation
Charles Micalizzi Jr.
Thanh X. Nghiem
Richard L. Romaniec
Toan B. Nguyen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qlogic Corporation, Charles Micalizzi Jr., Thanh X. Nghiem, Richard L. Romaniec, Toan B. Nguyen filed Critical Qlogic Corporation
Publication of CA2367890A1 publication Critical patent/CA2367890A1/en
Application granted granted Critical
Publication of CA2367890C publication Critical patent/CA2367890C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Abstract

An input/output (I/O) controller (40) in an I/O system processes I/O requests from a host computer (15) to a plurality of I/O devices (80-86). The I/O controller (40) generates an interrupt to the host computer (15) and reports a plurality of completed I/O requests from the I/O devices (80-86) when at least one condition of the I/O system is met. A
first condition of the I/O system comprises a predetermined ratio between the total number of unreported I/O completions by the I/O
devices (80-86) and the total number of remaining I/O requests from the host computer (15). A second condition comprises the expiration of a timer, which starts when the number of remaining I/O
requests left to process for any individual I/O device (80-86) reaches a predetermined minimum limit.
CA002367890A 1999-03-31 2000-03-29 A host adapter for combining i/o completion reports and method of using the same Expired - Fee Related CA2367890C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/282,341 1999-03-31
US09/282,341 US6434630B1 (en) 1999-03-31 1999-03-31 Host adapter for combining I/O completion reports and method of using the same
PCT/US2000/008443 WO2000058843A1 (en) 1999-03-31 2000-03-29 A host adapter for combining i/o completion reports and method of using the same

Publications (2)

Publication Number Publication Date
CA2367890A1 true CA2367890A1 (en) 2000-10-05
CA2367890C CA2367890C (en) 2007-05-29

Family

ID=23081068

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002367890A Expired - Fee Related CA2367890C (en) 1999-03-31 2000-03-29 A host adapter for combining i/o completion reports and method of using the same

Country Status (9)

Country Link
US (1) US6434630B1 (en)
EP (1) EP1163595B1 (en)
JP (1) JP2002540526A (en)
KR (1) KR100677538B1 (en)
AT (1) ATE373844T1 (en)
AU (1) AU4327800A (en)
CA (1) CA2367890C (en)
DE (1) DE60036465T2 (en)
WO (1) WO2000058843A1 (en)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6564271B2 (en) * 1999-06-09 2003-05-13 Qlogic Corporation Method and apparatus for automatically transferring I/O blocks between a host system and a host adapter
US6792477B1 (en) * 2000-05-18 2004-09-14 Microsoft Corporation Discovering printers and shares
US6779054B2 (en) * 2001-10-05 2004-08-17 Intel Corporation Method and apparatus for operating a network controller
US20030086485A1 (en) * 2001-11-08 2003-05-08 John Lin Master to multi-slave asynchronous transmit fifo
US6829660B2 (en) * 2001-12-12 2004-12-07 Emulex Design & Manufacturing Corporation Supercharge message exchanger
JP4212811B2 (en) * 2002-01-10 2009-01-21 富士通株式会社 Information processing system, interface device, information processing device, information storage device
US20030189945A1 (en) * 2002-04-05 2003-10-09 Connor Patrick L. Selective completion indication of controller events
US7397768B1 (en) 2002-09-11 2008-07-08 Qlogic, Corporation Zone management in a multi-module fibre channel switch
FI20021867A (en) * 2002-10-18 2004-04-19 Nokia Corp Method for changing card mode, system, card, and device
WO2004046926A1 (en) * 2002-11-21 2004-06-03 Fujitsu Limited Method, device and processor system for notifying event
US7646767B2 (en) 2003-07-21 2010-01-12 Qlogic, Corporation Method and system for programmable data dependant network routing
US7234101B1 (en) 2003-08-27 2007-06-19 Qlogic, Corporation Method and system for providing data integrity in storage systems
US20050071688A1 (en) * 2003-09-25 2005-03-31 International Business Machines Corporation Hardware CPU utilization meter for a microprocessor
US7219263B1 (en) 2003-10-29 2007-05-15 Qlogic, Corporation Method and system for minimizing memory corruption
US7930377B2 (en) 2004-04-23 2011-04-19 Qlogic, Corporation Method and system for using boot servers in networks
US7669190B2 (en) 2004-05-18 2010-02-23 Qlogic, Corporation Method and system for efficiently recording processor events in host bus adapters
US7577772B2 (en) * 2004-09-08 2009-08-18 Qlogic, Corporation Method and system for optimizing DMA channel selection
US20060064531A1 (en) * 2004-09-23 2006-03-23 Alston Jerald K Method and system for optimizing data transfer in networks
US7676611B2 (en) 2004-10-01 2010-03-09 Qlogic, Corporation Method and system for processing out of orders frames
US7398335B2 (en) * 2004-11-22 2008-07-08 Qlogic, Corporation Method and system for DMA optimization in host bus adapters
US7164425B2 (en) * 2004-12-21 2007-01-16 Qlogic Corporation Method and system for high speed network application
US7392437B2 (en) 2005-01-20 2008-06-24 Qlogic, Corporation Method and system for testing host bus adapters
US7853960B1 (en) * 2005-02-25 2010-12-14 Vmware, Inc. Efficient virtualization of input/output completions for a virtual device
US7231480B2 (en) * 2005-04-06 2007-06-12 Qlogic, Corporation Method and system for receiver detection in PCI-Express devices
US7281077B2 (en) * 2005-04-06 2007-10-09 Qlogic, Corporation Elastic buffer module for PCI express devices
JP2007012021A (en) * 2005-06-01 2007-01-18 Sony Corp Method and apparatus for processing information, and program
US7461195B1 (en) 2006-03-17 2008-12-02 Qlogic, Corporation Method and system for dynamically adjusting data transfer rates in PCI-express devices
US7743195B2 (en) * 2006-12-27 2010-06-22 Intel Corporation Interrupt mailbox in host memory
US7716397B2 (en) * 2007-07-03 2010-05-11 Lsi Corporation Methods and systems for interprocessor message exchange between devices using only write bus transactions
JP5101195B2 (en) * 2007-07-09 2012-12-19 株式会社東芝 Interface controller
US8458730B2 (en) * 2008-02-05 2013-06-04 International Business Machines Corporation Multi-level driver configuration
CN102077181B (en) * 2008-04-28 2014-07-02 惠普开发有限公司 Method and system for generating and delivering inter-processor interrupts in a multi-core processor and in certain shared-memory multi-processor systems
US20100005199A1 (en) * 2008-07-07 2010-01-07 Texas Instruments Incorporated Direct memory access (dma) data transfers with reduced overhead
WO2010021120A1 (en) * 2008-08-20 2010-02-25 パナソニック株式会社 Communication device and communication control method
US7853726B2 (en) * 2008-10-06 2010-12-14 International Business Machines Corporation FCP command-data matching for write operations
FR2952937B1 (en) 2009-11-20 2013-02-08 Chaire Europeenne De Chimie Now Pour Un Developpement Durable NOVEL PHENOPLAST RESINS OBTAINED FROM PHENOLIC COMPOUNDS AND MACROMOLECULAR HARDENERS WITH ALDEHYDE FUNCTIONS
US8719843B2 (en) * 2011-07-27 2014-05-06 Intel Corporation Virtualizable and forward-compatible hardware-software interface
US8856479B2 (en) * 2012-04-20 2014-10-07 International Business Machines Corporation Implementing storage adapter performance optimization with hardware operations completion coalescence
US9727494B1 (en) * 2012-10-11 2017-08-08 Qlogic, Corporation Method and system for communication between a computing device and a peripheral device
US9298652B2 (en) * 2013-03-15 2016-03-29 Microsoft Technology Licensing, Llc Moderated completion signaling
KR102649324B1 (en) * 2016-05-19 2024-03-20 삼성전자주식회사 Computer system for performing adaptive interrupt control and method for controlling interrupt thereof
US10776289B2 (en) 2018-09-21 2020-09-15 Microsoft Technology Licensing, Llc I/O completion polling for low latency storage device
US10740258B2 (en) * 2018-10-23 2020-08-11 Microsoft Technology Licensing, Llc Timer-based I/O completion polling for low latency storage device
US11194503B2 (en) 2020-03-11 2021-12-07 Samsung Electronics Co., Ltd. Storage device having a configurable command response trigger
US20230120600A1 (en) * 2021-10-20 2023-04-20 Western Digital Technologies, Inc. Data Storage Devices, Systems, and Related Methods for Grouping Commands of Doorbell Transactions from Host Devices

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4268906A (en) 1978-12-22 1981-05-19 International Business Machines Corporation Data processor input/output controller
US5129064A (en) 1988-02-01 1992-07-07 International Business Machines Corporation System and method for simulating the I/O of a processing system
JPH0315941A (en) * 1989-06-14 1991-01-24 Hitachi Ltd Semiconductor integrated circuit
EP0551191B1 (en) 1992-01-09 2000-04-12 Cabletron Systems, Inc. Apparatus and method for transferring data to and from host system
JP2901882B2 (en) * 1994-07-26 1999-06-07 株式会社日立製作所 Computer system and method of issuing input / output instructions
US5761427A (en) 1994-12-28 1998-06-02 Digital Equipment Corporation Method and apparatus for updating host memory in an adapter to minimize host CPU overhead in servicing an interrupt
US5689713A (en) 1995-03-31 1997-11-18 Sun Microsystems, Inc. Method and apparatus for interrupt communication in a packet-switched computer system
US5671365A (en) 1995-10-20 1997-09-23 Symbios Logic Inc. I/O system for reducing main processor overhead in initiating I/O requests and servicing I/O completion events
US5892969A (en) 1996-03-15 1999-04-06 Adaptec, Inc. Method for concurrently executing a configured string of concurrent I/O command blocks within a chain to perform a raid 5 I/O operation
JP3586522B2 (en) * 1996-09-26 2004-11-10 日本電気株式会社 Peripheral device controller
US5881296A (en) 1996-10-02 1999-03-09 Intel Corporation Method for improved interrupt processing in a computer system
US6055603A (en) * 1997-09-18 2000-04-25 Emc Corporation Method and apparatus for performing pre-request operations in a cached disk array storage system
US6085277A (en) * 1997-10-15 2000-07-04 International Business Machines Corporation Interrupt and message batching apparatus and method
US6138176A (en) * 1997-11-14 2000-10-24 3Ware Disk array controller with automated processor which routes I/O data according to addresses and commands received from disk drive controllers
US6006340A (en) * 1998-03-27 1999-12-21 Phoenix Technologies Ltd. Communication interface between two finite state machines operating at different clock domains

Also Published As

Publication number Publication date
JP2002540526A (en) 2002-11-26
WO2000058843A1 (en) 2000-10-05
EP1163595A1 (en) 2001-12-19
AU4327800A (en) 2000-10-16
DE60036465T2 (en) 2008-06-12
ATE373844T1 (en) 2007-10-15
EP1163595B1 (en) 2007-09-19
CA2367890C (en) 2007-05-29
DE60036465D1 (en) 2007-10-31
KR100677538B1 (en) 2007-02-01
US6434630B1 (en) 2002-08-13
KR20010104732A (en) 2001-11-26

Similar Documents

Publication Publication Date Title
CA2367890A1 (en) A host adapter for combining i/o completion reports and method of using the same
AU4861000A (en) A method and apparatus for automatically transferring i/o blocks between a host system and a host adapter
US6182165B1 (en) Staggered polling of buffer descriptors in a buffer descriptor ring direct memory access system
EP1357476A3 (en) Method for controlling storage system, and storage control apparatus
TW338809B (en) A method for indentifying and correcting errors in a central processing unit
WO2005010670A3 (en) Apparatus and method for direct memory access in a hub-based memory system
AU6126094A (en) Method and apparatus for data transfer and storage in a highly parallel computer network environment
WO2000039679A3 (en) Method and apparatus for balancing workloads among paths in a multi-path computer system
CA2050129A1 (en) Dynamic bus arbitration with grant sharing each cycle
HUP0302843A2 (en) Method and apparatus for transferring interrupts from a peripheral device to a host computer system
WO2003003619A3 (en) Redundant optical device array
EP0083002A3 (en) Interrupt system for peripheral controller
ATE331989T1 (en) ASYNCHRONOUS CENTRALIZED MULTI-CHANNEL DMA CONTROL
CA2058933A1 (en) Reset Method When Adaptor Module is Faulty and Computer System Executing Same
EP1418494A3 (en) Disc controller and controlling method
WO2004003757A3 (en) Direct transaction mode for peripheral devices
WO2002048891A3 (en) Arbitration and crossbar device and method
EP0344999A3 (en) Data transmission system
DE50305302D1 (en) MEMORY SYSTEM WITH MULTIPLE MEMORY CONTROLLERS AND METHOD FOR SYNCHRONIZING THEM
JPS629418A (en) Timer control system
JPS5491156A (en) Data processing system
JPH02287853A (en) Peripheral controller
JP2003316735A5 (en)
TW275677B (en) Peripheral access architecture in computer system
JPH04344551A (en) Receiving propriety identifying method in information processor

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed

Effective date: 20170329