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Publication numberCA2337677 A1
Publication typeApplication
Application numberCA 2337677
Publication date23 Aug 2001
Filing date22 Feb 2001
Priority date23 Feb 2000
Also published asEP1128274A2, EP1128274A3, US6970911, US20010021944
Publication numberCA 2337677, CA 2337677 A1, CA 2337677A1, CA-A1-2337677, CA2337677 A1, CA2337677A1
InventorsMasanobu Inaba
ApplicantNec Corporation, Masanobu Inaba
Export CitationBiBTeX, EndNote, RefMan
External Links: CIPO, Espacenet
Distributed memory type parallel computer and write data transfer end confirming method thereof
CA 2337677 A1
Abstract
A distributed memory type parallel computer and a write data transfer end confirming method of the distributed memory type parallel computer, in which a series of processes to confirm a write data transfer end between plural computing nodes can be made in high speed, are provided. A computing node in the distributed memory type parallel computer provides a request accepting section, a data accepting section, an arbitration section, an address transforming section, a request/data outputting section, an EOT (end of transfer) judging section, and a selector. By using the EOT judging section and the selector in a remote node, a transfer end mark can be added to transfer data themselves.
Therefore, without executing processes before and after write data transfer by a CPU in a local node, an end confirmation of a write data transfer from the remote node to the local node can be realized by adding a transfer end mark to the transfer data themselves. With this, a series of the processes to confirm the write data transfer end can be executed in high speed.
Claims(9)
1. A distributed memory type parallel computer, in which plural computing nodes providing a CPU (central processing unit), an MMU (main memory unit), and an RCU (remote control unit) are connected through a network, and data are transferred from an arbitrary computing node to the other computing nodes, wherein:
a command expressing an end of transfer of said data is added to said data that are transferred from said arbitrary computing node to said other computing nodes.
2. A distributed memory type parallel computer in accordance with claim 1, wherein:
in said arbitrary computing node, said CPU, comprising:
an issuing means for issuing an EOT (end of transfer) command expressing an end of transfer of said data to said RCU, said RCU, comprising:
a data obtaining means for obtaining transfer data stored in said MMU, when said RCU accepted said EOT command from said issuing means in said CPU
an adding means for adding said EOT command to said transfer data obtained at said data obtaining means and a transferring means for transferring said transfer data added said EOT command to one of said other computing nodes.
3. A distributed memory type parallel computer in accordance with claim 1, wherein:
in each of said other computing nodes, said RCU, comprising:
a first accepting means for accepting a command and an address of said transfer data, which is transferred from a transferring means of said RCU in said arbitrary computing node, and for latching said command and said address;
a second accepting means for accepting said transfer data transferred from said transferring means of said RCU in said arbitrary computing node, and for latching said transferred data;
an arbitrating means for arbitrating said command and said address of said transfer data accepted at said first accepting means an address transforming means for transforming said address arbitrated at said arbitrating means;
a judging means for judging whether said command arbitrated at said arbitrating means is an EOT command issued at said CPU in said arbitrary computing node or not;
a replacing means for replacing a part of said transfer data accepted at said second accepting means with a designated value expressing that said transfer data was transferred with said EOT
command, at the case that said judging means judged that said command was said EOT command; and a memorizing means for memorizing said transfer data whose part was replaced with said designated value at said replacing means and said address transformed at said address transforming means in said MMU.
4. A distributed memory type parallel computer in accordance with claim 3, wherein:
in each of said other computing nodes, said CPU, comprising:
a monitoring means for monitoring a state that a part of said transfer data is replaced with said designated value and said transfer data whose part was replaced are memorized in said MMU by said memorizing means and a data transfer end notifying means for notifying the end of transfer of said transfer data to said arbitrary computing node, when said transfer data whose part was replaced with said designated value had been memorized in said MMU, based on a monitored result at said monitoring means.
5. A distributed memory type parallel computer in accordance with claim 3, wherein:
said replacing means replaces a first element of said transfer data accepted at said second accepting means with said designated value.
6. A distributed memory type parallel computer in accordance with claim 3, wherein:
said replacing means replaces a final element of said transfer data accepted at said second accepting means with said designated value.
7. A write data transfer end confirming method at a distributed memory type parallel computer, in which plural computing nodes providing a CPU, an MMU, and an RCU are connected through a network, and data are transferred from an arbitrary computing node to the other computing nodes, wherein:
in said arbitrary computing node, comprising the steps of:
issuing an EOT (end of transfer) command expressing an end of transfer of said data from said CPU to said RCU, obtaining transfer data stared in said MMU, when said RCU
accepted said EOT command from said issuing step;
adding said EOT command to said transfer data obtained at said obtaining step; and transferring said transfer data added said EOT command to one of said other computing nodes, in each of said other computing nodes, comprising the steps of:
first accepting a command and an address of said transfer data, which is transferred from said transferring step at said arbitrary computing node, and for latching said command and said address;
second accepting said transfer data transferred from said transferring step at said arbitrary computing node, and for latching said transferred data;
arbitrating said command and said address of said transfer data accepted at said first accepting step;
transforming said address arbitrated at said arbitrating step;
judging whether said command arbitrated at said arbitrating step is an EOT command issued at said CPU in said arbitrary computing node or not;
replacing a part of said transfer data accepted at said second accepting step with a designated value expressing that said transfer data was transferred with said EOT command, at the case that said judging step judged that said command was said EOT command;
memorizing said transfer data whose part was replaced with said designated value at said replacing step and said address transformed at said transforming step in said MMU;
monitoring a state that a part of said transfer data is replaced with said designated value and said transfer data whose part was replaced are memorized in said MMU by said memorizing step at said CPU; and notifying the end of transfer of said transfer data to said arbitrary computing node, when said transfer data whose part was replaced with said designated value had been memorized in said MMU, based on a monitored result at said monitoring means.
8. A write data transfer end confirming method at a distributed memory type parallel computer in accordance with claim 7, wherein:
said replacing step replaces a first element of said transfer data accepted at said second accepting step with said designated value.
9. A write data transfer end confirming method at a distributed memory type parallel computer in accordance with claim 7, wherein:
said replacing step replaces a final element of said transfer data accepted at said second accepting step with said designated value.
Description  (OCR text may contain errors)

DISTRIBUTED MEMORY TYPE PARALLEL COMPUTER AND
WRITE DATA TRANSFER END CONFIRMI:L~TG METHOD THEREOF
BACKGROUND OF THE IN~~ENTION
The present invention relates to a distributed memory type parallel computer and a write data transfer end confirming method thereof, in particular, in which a CPU (central processing unit) in a local computing node works as a main role and a write data transfer is executed from the local computing node to a remote computing node and a CPU in the remote computing node confirms its write data transfer end.
Description of the Related Art At a system composed of computers, a distributed memory type parallel computer, in which plural processin3; units (computing nodes) are operated at the same time and high throu;;hput is realized, has been developed.
When computation is executed by this distributed memory type parallel computer, it is desirable that the number of times of write data transfer between computing nodes is made to be small. That is, it is desirable that a closed program is executed in each of the computing nodes. Because, the computing nodes are connected through a network and the distance between the computing node s is longer than that in one computing node.
However, when a large scale technical subject is computed, it is almost impossible that this computation is executed only by the closed program in one computing node, and actually this computation is executed in cooperation with programs of plural computing nodes. For example, at the case that a large scale technic<~1 subject array is allocated to plural computing nodes by mapping, that is, the mapping is applied to plural computing nodes as a global memory :pace, this case is that the computation is executed in cooperation with the plural computing nodes.
Fig. 1 is a block diagram showing a structure of a conventional distributed memory type parallel computer. As shown in Fig. l, at the conventional distributed memory type parallel computer, a first computing node 1 and a second computing node 2 are connected through a network 3. In this, the first computing nade 1 that generates a command is named as a local node 1, and they second computing node 2 that receives the generated command is named as a remote node 2.
The local node 1 consists of a CPU 11, an MMU (main memory unit) 12, and an RCU (remote control unit) 13. And the remote node 2 consists of a CPU 21, an MMU 22, and an RCU 2:3 as the same as the local node 1. The network 3 connects the local node 1 and the remote node 2, and provides a communication register 31 for synchronizing operation between the local node 1 and the remote node 2. In this, the RCU 13 receives commands from the CPU 11 through the MMU 21, and the RCU 23 receives commands from the CPIJ 21 through the MMU 22.
At the local node 1, the CPU 11 loads the MMU 12 with data and makes the MMU 12 store the data, and computes by using the loaded data and makes the MMU 12 store the computed result. The RCU 13 receives a write data transfer command between computing nodes from the CPU 11, and executes a write data transfer between computing nodes in cooperation with the RC1:T 23 in the remote node 2.
For example, when the CPU 11 commands the RCU 13~ to transfer the data in the MMU 12 to the MMIJ 22 in the remote node 2, the RCU 13 loads the data in the MMU 12 an,d transfers the data to the RCU 23 through the network 3. The RCU 23 makes the MMU 22 store the transferred data. This is named to be a vvrite data transfer between computing nodes.
And when the CPU 11 commands the RCU 13 to transfer the data in the MMU 22 in the remote node 2 to the MMU 12, the RCU 13 sends a write data transfer request to the RCU 23. The RCU 23 loads the data in the MMU 22 and transfers the data to the RCU 13 through the network 3. The RCU 13 makes the MM~U 12 store the transferred data. This is named to be a read data transfer between computing nodes.
Fig. 2 is a block diagram showing a detailed structure of the RCU 13 (23) in the computing node 1 (2) of the conventional distributed memory type parallel computer. As shown in Fig. 2, the RCU 13 (23) of the conventional distributed memory type par<~llel computer consists of a request accepting section 131 (231), a data accepting section 132 (232), an arbitration section 133 (233), an address transforming section 134 (234), and a request/data outputting section :L35 (235).
The request accepting section 231 in the RCU 23 accepts a command from the CPU 21, or a command and an address from the RCU
13 through the network 3 and latches the command and the address.
The data accepting section 232 in the RCU 23 accepts write data transferred from the RCU 13 through the network 3 and latches the data.
The arbitration section 233 selects one of the requests (commands and addresses) in the request accepting section 231 one by one by arbitrating.
The address transforming section 234 transforms a logical node number into a physical node number, and a local job number into a remote job number, and a logical address in node into a physical address in node. Especially, the physical node number transformation and the remote job number transformation are needed for a command when the remote node 2 accesses to the other node (in this case, the local node 1).
And the physical address in node transformation is needed for a command accessing to a memory in node (in this case, the MMU22).
The request/data outputting section 235 outputs the command and address transformed at the address transforming section 234 and the loaded data from the MMU 22 to the other node (the RCU 13 through the network 3). And the data latched at the data accepting section 232 are needed at the case that the data are made to store in the MMU 22 from the other node (the RCU 13 through the network 3).
Generally, a program, which a loc<~.l node generates a write data transfer command and its write data transfer end confirmation is executed at a remote node, is shown in the following program.
Local node program:
FLAG = 1 DOI=l,M
NODE 2 ( I + J ) = NODE 1 ( I ) ENB DO
FLAG = 0 Remote node program:
IF FLAG .eq. 0 THEN
CALL NEXT-PROGRAM-SUB
END IF
The program at the distributed me~r~ory type parallel computer is generally described by one program using an MPI (message passing interface) and a HPF (high performance Fortran). However, in order to make its understanding easy, the progra~~ is divided into each of computing nodes in this explanation.
At the conventional distributed memory type parallel computer, an array NODE 1 ( I ) is made to be mapping to the local node l, an array NODE 2 ( I + J ) is made to be mapping to the remote node 2, and a parent process is made to be the CPU 11 in the local node 1.
And a synchronizing flag FLAG showing a write data transferring state is made to be mapping in the communication register 31 in the network 3. In this, FLAG = " 1 " is defined to be that write data are transferring, and FLAG = " 0 " is defined to be that the write data transfer ends.

In this, a case, in which an array copy is allocated to plural computing nodes and the process at one of the computing nodes allocated the array copy can jump to a next subroutine after the copy is ended, is explained.

5 At the program mentioned above, the array NODE 1 ( I ) is copied to the array NODE 2 ( I + J ), and when the copy is ended, that is, after confirming that the value of FLAG was changed from " 1 " to " 0 ", the program can jump to the next subroutine.
In this, the array NODE 1 ( I ) is nnade to be mapping to the local node l, the array NODE 2 ( I + J ) is made to be mapping to the remote node 2, and the flag FLAG is made to be mapping in the communication register 31 in the network 3 located at the same distance from the local node 1 and the remote node 2. And the parent process is made to be the CPU 11 in the local node 1.
In this case, the CPU 11 in the local node 1 issues a flag set command being FLAG = " 1 ", a write data transfer command between computing nodes, and a flag clear command being FLAG = " 0 ".
Fig. 3 is a timing chart showing operation of the conventional distributed memory type parallel computer. Referring to Fig. 3, the operation of the local node 1 and the remote :node 2 at the conventional distributed memory type parallel computer i;> explained.
First, at the local node 1, in order to inform the CPU 21 of that data is transferring to the remote node 2 from the local node l, the CPU
11 issues a write data transfer command to the RCU 13 for the communication register 31 in the network 3.
At the RCU 13, the request accepting section 131 accepts the write data transfer command for the commun~.cation register 31 from the CPU 1l, and the arbitration section 133 arbitrates the request (write data transfer command), after this, the requestldata outputting section 135 outputs the request to the network 3.

At the network 3, the FLAG of the communication register 31 is set to " 1 ", and an end reply signifying that the write process to the FLAG normally ended is returned to the RCU 13. The RCU 13 informs the CPU 11 of this end reply, and the write process to the communication register 31 ends.
Next, the CPU 11 issues a write data transfer command to the RCU 13 for the MMU 22 in the remote node 2.
At the RCU 13, the request accepting section 131 accepts the write data transfer command from the CPtJ 11, and the arbitration section 133 arbitrates the request (write data i;ransfer command). After this, the address transforming section 134 executes the physical node number transformation, the remote job number transformation, and the physical address in node transformation, and the RCU 13 accesses to the MMU 12. After this, the RCU 13 outputs the loaded data from the MMU 12 together with the physical node number and the remote job number to the RCU 23 through the networlL~ 3 from the requestldata outputting section 135.
Next, at the remote node 2, the RCIJ 23 accepts the write data transfer command sent from the RCU 13 through the network 3 at the request accepting section 231, and the arbitration section 233 arbitrates the request (write data transfer command). After this, the address transforming section 234 transforms the logical address into the physical address. And the transferred data are accepted at the data accepting section 232 and are written in the MMU 22 together with the physical address.
The RCU 23 sends an end reply, which signifies that the write data transfer command from the RCU 13 andL the writing process of the transferred data to the MMU 22 end normally, to the RCU 13 through the network 3 from the requestldata outputting section 235. The RCU
13 returns this end reply to the CPU 11, and the write data transfer command ends.
Next, in order to notify that the write data transfer ended to the CPU 21 in the remote node 2, the CPU lI issues a flag write command to the RCU I3 for the communication register 31 in the network 3.
The RCU 13 accepts the flag write command to the communication register 31 at the request accepting section 131, and the arbitration section 133 arbitrates the request (flag write command).
After this, the request/data outputting section 135 outputs the flag write command to the network 3.
At the network 3, the FLAG of the communication register 3I
is cleared to " 0 ", and an end reply signifying that the flag write process normally ended is returned to the RCU 13. The RCU 13 informs the CPU 11 of this end reply, and the write process to the communication register 3I ends.
Next, the operation of the remote node 2 is explained. At the remote node 2, the CPU 21 issues a flag read command to the RCU 23 for the communication register 31. At the RCU~ 23, the request accepting section 231 accepts the flag read command to i;he communication register 31. And the arbitration section 233 arbitrates the request (flag read command), after this, the request/data outputting section 235 outputs the flag read command to the network 3.
At the network 3, the FLAG value in the communication register 31 is read, and an end reply, which signifies that reading the FLAG value and the FLAG reading process are executed normally, is returned to the RCU 23. The RCU 23 informs the CPU 21 of this result.
And the flag reading process in the communication register 31 in the network 3 ends.
This FLAG reading process is repeated until that the FLAG
value becomes " 0 ", that is, until that the end of the write data transfer is confirmed. And when it was confirmed i;hat the FLAG value had become " 0 ", the CPU 21 goes to the next sequence, (NEXT PROGRAM
-SUM). With this, a series of the operation of the conventional distributed memory type parallel computer ends.
At this time, at the conventional distributed memory type parallel computer, the latency in each of units and between the units is expediently defined as follows. In this, T corresponds to one machine clock at the distributed memory type parallel. computer.
1. The latency between the CPU (I1,21) and the MMU (12,22): 1T
2. The latency between the MMU (12,22) and the RCU (13,23): 1T
3. The latency between the network 3 and. the RCU (13,23): 3T
4. The latency passing through each of thc~ units: OT
Therefore, as shown in Fig. 3, at the conventional distributed memory type parallel computer, the total latency in the write data transfer from issuing the write data transfer command at the CPU 11 to confirming the end of the write data transfer at the CPU 22 requires 62T.
That is, the latency until that the CPU 21 confirms that the FLAG = " 0 However, at the conventional distributed memory type parallel computer mentioned above, in the set process .and the clear process of the FLAG executing before and after the write data transfer command between computing nodes, the computing nodes must access to a network in long distance. Therefore, there is a problem that overhead before and after the write data transfer becomes large.
Moreover, the CPU in the remote node continues to issue a flag read command to the RCU, and the remote node accesses to the network in long distance. Consequently, there is a problem that overhead from the end of the write data transfer to that the CPU in the remote node confirms the end of the write data transfer becomes large.
In order to solve these problems, there are two methods to be studied. As a first method, at the CPU in the local node, if the set and clear processes of the FLAG can be eliminated, the local node can execute the write data transfer at earlier timing and .ends in short time.
As a second method, at the remote node, if the write data transfer confirming FLAG does not exists in the network, but exists in a position near to the remote node, its turn around time can be reduced.
Consequently, the process confirming the FLAG is made to be high speed, and after the end of the write data transfer, iii becomes possible to jump to the next subroutine in earlier timing.
As mentioned above, if these two methods are realized, at the distributed memory type parallel computer, confirming the end of the write data transfer at the remote node is made to be high speed.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a distributed memory type parallel computer and a write data transfer end confirming method thereof, in which a CPU iin a local node works as a main role and a write data transfer from the local node to a remote node is executed and a series of processes until that a CPU in the remote node confirms the end of the write data transfer is made to be high speed.
According to a first aspect of the present invention, there is provided a distributed memory type parallel computer, in which plural computing nodes providing a CPU (central processing unit), an MMU
(main memory unit), and an RCU (remote control unit) are connected through a network, and data are transferred from an arbitrary computing node to the other computing nodes. And a command expressing an end of transfer of the data is added to the data that are transferred from the arbitrary computing node to the other computing nodes.
According to a second aspect of the present invention, in the first aspect, in the arbitrary computing node, the CPU provides an issuing means for issuing an EOT (end of transfer) command expressing an end of transfer of the data to the RCU, anc~ the RCU provides a data obtaining means for obtaining transfer data ;>tored in the MMU, when 5 the RCU accepted the EOT command from the issuing means in the CPU, an adding means for adding the EOT command to the transfer data obtained at the data obtaining means, and a transferring means for transferring the transfer data added the EOT command to one of the other computing nodes.
10 According to a third aspect of the present invention, in the first aspect, in each of the other computing nodes., the RCU provides a first accepting means for accepting a command and. an address of the transfer data, which is transferred from a transferring means of the RCU in the arbitrary computing node, and for latching the command and the address, a second accepting means for accepting the transfer data transferred from the transferring means of the RCU in the arbitrary computing node, and for latching the transferred data, a:n arbitrating means for arbitrating the command and the address of the transfer data accepted at the first accepting means, an address transforming means for transforming the address arbitrated at the arbitrating means, a judging means for judging whether the command arbitrated at the arbitrating means is an EOT command issued at the CPU in the arbitrary computing node or not, a replacing means fir replacing a part of the transfer data accepted at the second accepting means with a designated value expressing that the transfer data was transferred with the EOT
command, at the case that the judging means. judged that the command was the EOT command, and a memorizing means for memorizing the transfer data whose part was replaced with the designated value at the replacing means and the address tram>formed at the address transforming means in the MMU.

According to a fourth aspect of the present invention, in the third aspect, in each of the other computing nodes, the CPU provides a monitoring means for monitoring a state that a part of the transfer data is replaced with the designated value and the transfer data whose part was replaced are memorized in the MMU by the memorizing means, and a data transfer end notifying means for notif~~ing the end of transfer of the transfer data to the arbitrary computing; node, when the transfer data whose part was replaced with the designated value had been memorized in the MMU, based on a monitored result at the monitoring means.
According to a fifth aspect of the present invention, in the third aspect, the replacing means replaces a first element of the transfer data accepted at the second accepting means with the designated value.
According to a sixth aspect of the present invention, in the IS third aspect, the replacing means replaces a final element of the transfer data accepted at the second accepting means 'with the designated value.
According to a seventh aspect of the present invention, there is provided a write data transfer end confirming method at a distributed memory type parallel computer, in which plural computing nodes providing a CPU, an MMU, and an RCU are connected through a network, and data are transferred from an arbitrary computing node to the other computing nodes. And in the arbitrary computing node, providing the steps of issuing an EOT (end of transfer) command expressing an end of transfer of the data from the CPU to the RCU, obtaining transfer data stored in the MMU, when the RCU accepted the EOT command from the issuing step, adding the EOT command to the transfer data obtained at the obtaining si~ep, and transferring the transfer data added the EOT command to o:ne of the other computing nodes. And in each of the other computing nodes, providing the steps of first accepting a command and an address of the transfer data, which is transferred from the transferring step at the arbitrary computing node, and for latching the command and the address, second accepting the transfer data transferred from the transferring step at the arbitrary computing node, and for latching the transferred data, arbitrating the command and the address of the transfer data accepted at the first accepting step, transforming the address arbitrated at the arbitrating step, judging whether the command arbitrated at the arbitrating step is an EOT command issued at the CPU in the arbitrary computing node or not, replacing a part of the transfer data accepted at the second accepting step with a designated value expressing that the transfer data was transferred with the EOT command, at the <:ase that the judging step judged that the command was the EOT command, memorizing the transfer data whose part was replaced with t)he designated value at the replacing step and the address transformed at the transforming step in the MMU, monitoring a state that a part of the transfer data is replaced with the designated value and the transfer data whose part was replaced are memorized in the MMU by the memorizing step at the CPU, and notifying the end of transfer of the transfer data to the arbitrary computing node, when the transfer data whose part was replaced with the designated value had been memorized :in the MMU, based on a monitored result at the monitoring means.
According to an eighth aspect of the present invention, in the seventh aspect, the replacing step replaces a first element of the transfer data accepted at the second accepting step with the designated value.
According to ninth aspect of the present invention, in the seventh aspect, the replacing step replaces a final element of the transfer data accepted BRIEF DESCRIPTION OF THE DRAWINGS
The objects and features of the present invention will become more apparent from the consideration of the following detailed description taken in conjunction with the accompanying drawings in which:
Fig. 1 is a block diagram showing a structure of a conventional distributed memory type parallel computer Fig. 2 is a block diagram showing a detailed structure of an RCU in a computing node of the conventional distributed memory type parallel computer Fig. 3 is a timing chart showing opE~ration of the conventional distributed memory type parallel computer Fig. 4 is a block diagram showing a structure of an embodiment of a distributed memory type parallel computer of the present invention Fig. 5 is a block diagram showing a detailed structure of an RCU in a computing node of the embodiment of the distributed memory type parallel computer of the present invention Fig. 6 is a timing chart showing operation of the embodiment of the distributed memory type parallel computer of the present inventions and Fig. 7 is a timing chart showing operation of another embodiment of the distributed memory type parallel computer of the present invention.
DESCRIPTION OF THE PREFERREIJ EMBODIMENTS
Referring now to the drawings, embodiments of the present invention are explained in detail. At the embodiments of the present invention, a function being almost equivalent to the conventional example has the same reference number that. the conventional example has.
Fig. 4 is a block diagram showing a structure of an embodiment of a distributed memory type parallel computer of the present invention. As shown in Fig. 1, the distributed memory type parallel computer of the present invention consists of a first computing node 1 (hereinafter referred to as a local node 1), a second computing node 2 (hereinafter referred to as a remote nodLe 2), and a network 3 that connects the first and second computing nodes 1 and 2. In this, the first computing node 1 is explained as the local node l, however, the first computing node 1 is not limited to the local node 1 and can work as a remote node. Further, in order to make the explanation concise, the number of computing nodes is two in this .explanation, however this number is not limited two, and actually two or more computing nodes are connected to the networks 3.
The local node 1 consists of a CPU 11, an MMU 12, and an RCU 13. And the remote node 2 consists of a CPU 21, an MMU 22, and an RCU 23 as the same as the local node 1. ~Che network 3 connects the local node 1 and the remote node 2. In this, the RCU 13 receives commands from the CPU 11 through the M:MU 21, and the RCU 23 receives commands from the CPU 21 through the MMU 22.
Fig. 5 is a block diagram showing .a detailed structure of the RCU 13 (23) in the computing node 1 (2) of the embodiment of the distributed memory type parallel computer of the present invention. As shown in Fig. 5, the RCU 13 (23) of the embodiment of the distributed memory type parallel computer of the present invention consists of a request accepting section 131 (231), a data accepting section 132 (232), an arbitration section 133 (233), an address transforming section 134 (234), a requestldata outputting section 135 (235), an EOT (end of transfer) judging section 136 (236), and a selector 137 (237). In this, the EOT judging section 136 (236) and the selector 137 (237) work at the remote node 2, however, actually the local node 1 can also work as a remote node, therefore the RCU 13 (23) has t;he same functions.

At the embodiment of the present invention, in order to make write data transfer end confirmation at the remote node 2 high speed, a function issuing a write data transfer command with an EOT mark is newly provided, and the write data transfer command with the EOT
5 mark is issued at the CPU 11 in the local node 1.
In this, the write data transfer command with the EOT mark is that a value of a first element of data to be transferred is replaced with a fixed value at the RCU 23 in the remote node 2 and this fixed value is written in the MMU 22. This fixed value is, for example, " A11 1 " and 10 at 4 byte data, this fixed value is " FFFFFFFF " in hexadecimal, and at 8 byte data, this fixed value is " FFFFFFFFFFFFFFFF" in hexadecimal.
At the case that this first element i;s replaced with a different value, it is necessary that the mapping is executed so that the EOT mark can be written. In order to realize this, at i~he RCU 23 in the remote 15 node 2, the EOT judging section 236 that recognizes the transfer command to be a write data transfer command with an EOT mark, and the selector 237 that replaces the first element of the transfer data with the EOT mark, are newly provided. These two functions being the EOT
judging section 136 (236) and the selector 13'T (237) are newly added to the present invention compared with the conventional example.
The request accepting section 231 in the RCU 23 accepts a command from the CPU 21, or a command and an address from the RCU
13 through the network 3 and latches the command and the address.
The data accepting section 232 in the RCU 23 accepts write data transferred from the RCU 13 through the network 3 and latches the data.
The arbitration section 233 selects one of thE~ requests (commands and addresses) in the request accepting section 231 one by one, by arbitrating.
The address transforming section 234 transforms a logical node number into a physical node number, and a local job number into a remote job number, and a logical address in node into a physical address in node. Especially, the physical node number transformation and the remote job number transformation are neededl for a command when the remote node 2 accesses to the other node (in this case, the local node 1).
And the physical address in node transformation is needed for a command accessing to a memory in node (in this case, the MMU22).
The requestldata outputting section 235 outputs the command and address transformed at the address transforming section 234 and the loaded data from the MMU 22 to the other node (the RCU 13 through the network 3). And the data latched at the data accepting section 232 are needed at the case that the data are mad:e to store in the MMU 22 from the other node (the RCU 13 through the network 3).
Next, the EOT judging section 236 and the selector 237 in the remote node 2 of the present invention are explained in detail.
The EOT judging section 236 is a circuit that recognizes a received command to be a write data transfer command with an EOT
mark. When the received command is the write data transfer command with the EOT mark, the EOT judging section 236 instructs the selector 237 so that the h.rst element of the transferred data is replaced with the EOT mark.
The selector 237 is usually connected to the data accepting section 232. And when the selector 237 receives an instruction from the EOT judging section 236 so that the first element data of the transferred data is replaced with the EOT mark, the selector 237 replaces the first element of the transferred data with the EOT mark. In this, the EOT
mark is a fixed value, at 4 byte data, " FFFFFFFF " in hexadecimal, and at 8 byte data, " FFFFFFFFFFFFFFFF " in hexadecimal.
Fig. 6 is a timing chart showing operation of the embodiment of the distributed memory type parallel computer of the present invention. Referring to Fig. 6, the operation of the local node 1 and the remote node 2 at the embodiment of the distributed memory type parallel computer of the present invention is explained.
At the local node 1, the CPU 11 is;>ues a write data transfer command with an EOT mark to the RCU 13. The RCU 13 loads data to be transferred (array NODE 1 ( I ) ) from the MMU12 and transfers the data to the RCU 23 through the network 3.
At the RCU 23, the EOT judging ;>ection 236 recognizes the write data transfer command transferred through the network 3 to be the write data transfer command with the EO'T mark. And the selector 237 replaces the first element of the transferrf~d data with an EOT mark (at 4 byte data, " FFFFFFFF " in hexadecimal, and at 8 byte data, " FFFFFFFFFFFFFFFF " in hexadecimal). And the transferred data are stored in the MMU 22.
The RCU 23 sends an end reply notifying that the write data transfer command with the EOT mark ended normally to the RCU 13.
The RCU 13 sends this end reply to the CPU ll. With this, the operation of the local nade 1 ends.
At this time, at the CPU 21, a confirming process of the EOT
mark is repeated by reading the first element. of the transferred data in the MMU 22. And when the read data is confirmed to be the transferred data with the EOT mark, the CIPU 21 recognizes that the write data transfer command ends. And the CPU 21 goes to the next sequence and a series of this operation ends.
As mentioned above, FLAG writing processes between the CPU 11 in the local node 1 and the network 3, that is, setting and clearing processes of the FLAG are not required at the present invention.
Further, instead of a FLAG reading process (confirming the value of the FLAG) between the CPU 21 in the remote node 2 and the network 3, a reading process of a fixed address of the EOT mark in the MMU 22 in the remote node 2 is executed, therefore, a series of the operation can be made to be high speed.
Referring to Figs. 4 to 6, operation of write data transfer end confirmation at the remote node 2 at the time when write data transfer is executed at the distributed memory type parallel computer of the present 5 invention is explained in detail.
First, at the local node l, the CP U 11 issues a write data transfer command with an EOT mark to the RCU 13 for the MMU 22 in the remote node 2.
At the RCU 13, the request accepting section 131 accepts the 10 write data transfer command with the EOT mark, and the arbitration section 133 arbitrates the request (write data transfer command with EOT mark), and the address transforming section 134 executes the physical node number transformation, the remote JOB number transformation, and the physical address in unit transformation. And the RCU 13 accesses to the MMU 12. And the request/data outputting section 135 outputs the loaded data from the MMU 12 together with the physical node number and the remote JOB. number to the RCU 23 through the network 3.
Next, in the remote node 2, at i;he RCU 23, the request accepting section 231 accepts the write data transfer command with the EOT mark from the RCU 13 through the network 3. After this the arbitration section 233 arbitrates the request (write data transfer command with EOT mark), and the address transforming section 234 executes the physical address transformation. At the same time, the EOT judging section 236 recognizes that the transferred command is the write data transfer command with the EOT mark. And the selector 237 is instructed so that the first element of the transferred data is replaced with the EOT mark.
And the transferred data are accepted at the data accepting section 232, and the first element of the transferred data is replaced with the EOT mark at the selector 237, and the transferred data are written in the MMU 22 together with the physical address.
At the RCU 23, the request/data outputting section 235 outputs an end reply signifying that the wrii~e data transfer command with the EOT mark from the RCU 13 and the write data transfer process to the MMU 22 end normally to the RCU 13 through the network 3.
The RCU 13 returns this end reply to the CPL:f 11. With this, the write data transfer command with the EOT mark ends.
The CPU 21 in the remote node 2 reads an address, in which the EOT mark should be written in the MMU 22, and checks the address.
This process is repeated until the EOT mark iw~ written in the address, in which the EOT mark should be written in the MMU 22. After written the EOT mark in the MMU 22 from the RCU 23, the CPU 21 confirms this and recognizes that the write data transfer command ends. After this, the CPU 21 goes to the next sequence (rJEXT-PROGRAM_SUB) and a series of this operation ends.
The latency between units and in each of the units is expediently defined as follows. In this, T corresponds to one machine clock at the distributed memory type parallel computer of the present invention.
1. The latency between the CPU (11,21) and the MMU (12,22): IT
2. The latency between the MMU (12,22) and the RCU (13,23): 1T
3. The latency between the network 3 and the RCU (13,23): 3T
4. The latency passing through each of the units: OT
At this time, at the distributed memory type parallel computer of the present invention, the latency from that the local node 1 issued the write data transfer command to that the remote node 2 confirmed the write data transfer end, that is, to that the CPU 21 confirmed the EOT
mark in the MMU 22, is 12T as shown in Fig,. 6.
Fig. 7 is a timing chart showing operation of another embodiment of the distributed memory type parallel computer of the present invention. The difference from th.e embodiment mentioned above is that the position replacing the EOT mark in the transfer data is changed at this embodiment. At the embodiment mentioned above, the 5 first element of the transferred data is replaced with the EOT mark, however, at this embodiment, the final element of the transferred data is replaced with the EOT mark.
First, at the local node l, the CPU 11 issues a write data transfer command with an EOT mark for the MMU 22 in the remote 10 node 2 to the RCU 13.
At the RCU 13, the request accepting section 131 accepts the write data transfer command with the EOT mark, and the arbitration section 133 arbitrates the request (write data transfer command), and the address transforming section 134 executes the physical node number 15 transformation, the remote JOB number transformation, and the physical address in unit transformation. An.d the RCU 13 accesses to the MMU 12. And the request/data outputting section 135 outputs the load data from the MMU 12 together with the physical node number and the remote JOB number to the RCU 23 through the network 3.
20 Next, in the remote node 2, at the RCU 23, the request accepting section 231 accepts the write data transfer command with the EOT mark from the RCU 13 through the network 3. After this, the arbitration section 233 arbitrates the request (write data transfer command with EOT mark), and the address transforming section 234 executes the physical address transformation. At the same time, the EOT judging section 236 recognizes that the transferred command is the write data transfer command with the EOT mark. And the selector 237 is instructed so that the final element of the transferred data is replaced with the EOT mark.
And the transferred data are accepted at the data accepting section 232, and the final element of the transferred data is replaced with the EOT mark at the selector 237, ancL the transferred data are written in the MMU 22 together with the physical address.
At the RCU 23, the request/dat;~. outputting section 235 outputs an end reply signifying that the write data transfer command with the EOT mark from the RCU 13 and the write data transfer process to the MMU 22 end normally to the RCU 13 through the network 3.
The RCU 13 returns this end reply to the CPLJ 11. With this, the write data transfer command with the EOT mark ends.
The CPU 21 in the remote node 2 reads an address, in which the EOT mark should be written in the MMU 22, and checks the address.
This process is repeated until the EOT mark i;> written in the address, in which the EOT mark should be written in the MMU 22. After written the EOT mark in the MMU 22 from the RCL! 23, the CPU 21 confirms this and recognizes that the write data transfer command ends. After this, the CPU 21 goes to the next sequence (1'JEXT-PROGRAM-SUB) and a series of this operation ends.
At this time, at this embodiment of the distributed memory type parallel computer of the present invention, the latency from that the local node 1 issued the write data transfer command to that the remote node 2 confirmed the write data transfer command end, that is, to that the CPU 21 confirmed the EOT mark in the MMU 22, is 26T.
The embodiments mentioned above are preferred embodiments at the present invention, and can be modified to various embodiments without departing from the spirit of the present invention.
For example, the latency between units and in each of the units is explained as fixed values, however the values are not limited the values mentioned above.
And at the embodiments mentioned above, one element of the transfer data has 4 byte width or 8 byte width, however, this data width is not limited to the widths mentioned above.
As mentioned above, according to the distributed memory type parallel computer and the write data transfi~r end confirming method thereof at the present invention, processes before and after the write data transfer by a CPU in a local node can be eliminated. In this, the process before the write data transfer is that a FLAG, which signifies that data is transferring to the CPU in the remote node, is set to " 1 ".
And the process after the write data transfer is that a FLAG, which signifies that the write data transfer to the CPU in the remote node ends, is set to " 0 ". Because, an RCU in the remote node provides an EOT
judging section and a selector, and a transfer end mark is added to the transferred data themselves, therefore, it is enough for the CPU in the remote node only to confirm the transferred data themselves.
Moreover, according to the distributed memory type parallel computer and the write data transfer end confirming method thereof at the present invention, a write data transfer .end confirming process by the CPU in the remote node can be executed in high speed. Because, the CPU in the remote node provides the EO~T judging section and the selector, and the transfer end mark can be added to the transferred data themselves. Therefore, when the write data transfer end is confirmed, it is enough for the CPU in the remote node only to access to an EOT
mark written address in an MMU in the same remote node, consequently turn around time at the confirmation can be largely reduced.
Furthermore, according to the distributed memory type parallel computer and the write data transfer end confirming method thereof at the present invention, the write data transfer end confirming process can be executed in high speed. Therefore, the next sequence after the write data transfer to the remote node can be executed at earlier timing, and the total performance can be improved. Because, at a distributed memory type program, the write data transfer process far the MMU in the remote node is executed frequently, therefore, executing time of the total program can be reduced by the reduction of the time of the write data transfer end confirming process.
And, according to the distributed memory type parallel computer and the write data transfer end confirming method thereof at the present invention, this method can be applied to general logic at exclusive access control. That is, generally, at the case that a user desires to read data in a position but the user can not read the data until newest data arrive, however when this transfer with an EOT mark is applied, for example, to a disk, the user can read the newest data in high speed.
While the present invention has been described with reference to the particular illustrative embodiments, it is not to be restricted by those embodiments but only by the appended claims. It is to be appreciated that those skilled in the art c,an change or modify the embodiments without departing from the scope and spirit of the present invention.

Classifications
International ClassificationG06F15/17, G06F13/00
Cooperative ClassificationG06F15/17
European ClassificationG06F15/17
Legal Events
DateCodeEventDescription
22 Feb 2001EEERExamination request
2 Sep 2008FZDEDead