CA2317480A1 - Dual loop delay-locked loop - Google Patents

Dual loop delay-locked loop Download PDF

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Publication number
CA2317480A1
CA2317480A1 CA002317480A CA2317480A CA2317480A1 CA 2317480 A1 CA2317480 A1 CA 2317480A1 CA 002317480 A CA002317480 A CA 002317480A CA 2317480 A CA2317480 A CA 2317480A CA 2317480 A1 CA2317480 A1 CA 2317480A1
Authority
CA
Canada
Prior art keywords
delay
loop
acquisition loop
clock
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002317480A
Other languages
French (fr)
Other versions
CA2317480C (en
Inventor
Kyeongho Lee
Yongsam Moon
Deog-Kyoon Jeong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Silicon Image Inc
Original Assignee
Kyeongho Lee
Yongsam Moon
Deog-Kyoon Jeong
Silicon Image, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyeongho Lee, Yongsam Moon, Deog-Kyoon Jeong, Silicon Image, Inc. filed Critical Kyeongho Lee
Publication of CA2317480A1 publication Critical patent/CA2317480A1/en
Application granted granted Critical
Publication of CA2317480C publication Critical patent/CA2317480C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop

Abstract

A device and method for synchronizing a local clock to a reference clock. The device uses a frequency acquisition loop (418) and a phase acquisition loop (420). The frequency acquisition loop delays the reference clock (REF-CLK) to produce an intermediate clock (FCLK', BCLK') which falls within the operating range of the phase acquisition loop. The phase acquisition loop then delays the intermediate clock (LOC-CLK) to produce a local clock synchronized to the reference clock. The frequency acquisition loop (418) comprises a first delay circuit (400) adapted to delay the reference clock (REF-CLK) by an adjustable delay period which is selected from a plurality of non-adjustable delay periods by a first delay controller (404). The latter preferably comprises a cross-sensing phase detector pair (504) and a control logic (506). The phase acquisition loop (420) comprises a second delay circuit (402) adapted to delay the intermediate clock (FCLK', BCLK') by an adjustable delay period by a second delay controller (406). The latter may comprise a phase detector, a charge pump and a loop filter.
CA002317480A 1998-01-15 1998-12-21 Dual loop delay-locked loop Expired - Fee Related CA2317480C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/007,707 US5969552A (en) 1998-01-15 1998-01-15 Dual loop delay-locked loop
US09/007,707 1998-01-15
PCT/US1998/027448 WO1999037026A1 (en) 1998-01-15 1998-12-21 Dual loop delay-locked loop

Publications (2)

Publication Number Publication Date
CA2317480A1 true CA2317480A1 (en) 1999-07-22
CA2317480C CA2317480C (en) 2004-01-06

Family

ID=21727711

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002317480A Expired - Fee Related CA2317480C (en) 1998-01-15 1998-12-21 Dual loop delay-locked loop

Country Status (6)

Country Link
US (1) US5969552A (en)
JP (1) JP3564392B2 (en)
KR (1) KR100338212B1 (en)
AU (1) AU2011299A (en)
CA (1) CA2317480C (en)
WO (1) WO1999037026A1 (en)

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US6157691A (en) * 1998-04-14 2000-12-05 Lsi Logic Corporation Fully integrated phase-locked loop with resistor-less loop filer
JP3320651B2 (en) * 1998-05-06 2002-09-03 富士通株式会社 Semiconductor device
US6738417B1 (en) 1998-09-10 2004-05-18 Silicon Image, Inc. Method and apparatus for bidirectional data transfer between a digital display and a computer
US6298105B1 (en) * 1998-10-30 2001-10-02 Intel Corporation Method and apparatus for a low skew, low standby power clock network
KR100319890B1 (en) * 1999-01-26 2002-01-10 윤종용 Delay locked loop and method for controlling the same
JP3630291B2 (en) * 1999-03-01 2005-03-16 シャープ株式会社 Timing generator
JP4101973B2 (en) * 1999-05-21 2008-06-18 株式会社ルネサステクノロジ Output buffer circuit
US6326826B1 (en) 1999-05-27 2001-12-04 Silicon Image, Inc. Wide frequency-range delay-locked loop circuit
US6181168B1 (en) * 1999-09-24 2001-01-30 Motorola, Inc. High speed phase detector and a method for detecting phase difference
DE60024404T2 (en) 2000-02-02 2006-08-03 Telefonaktiebolaget Lm Ericsson (Publ) Method and device for predistorting a digital signal
US6765976B1 (en) 2000-03-29 2004-07-20 G-Link Technology Delay-locked loop for differential clock signals
US6968026B1 (en) 2000-06-01 2005-11-22 Micron Technology, Inc. Method and apparatus for output data synchronization with system clock in DDR
JP4443728B2 (en) * 2000-06-09 2010-03-31 株式会社ルネサステクノロジ Clock generation circuit
JP3617456B2 (en) * 2000-10-19 2005-02-02 ソニー株式会社 PLL circuit and optical communication receiver
US20020184577A1 (en) * 2001-05-29 2002-12-05 James Chow Precision closed loop delay line for wide frequency data recovery
KR100415544B1 (en) * 2001-06-25 2004-01-24 주식회사 하이닉스반도체 Delay locked loop circuits using bi-directional delay
JP3542574B2 (en) * 2001-08-28 2004-07-14 Ｎｅｃマイクロシステム株式会社 System clock synchronization circuit
US6930524B2 (en) * 2001-10-09 2005-08-16 Micron Technology, Inc. Dual-phase delay-locked loop circuit and method
US7024568B2 (en) * 2002-09-06 2006-04-04 National Semiconductor Corporation Method and system for providing self-calibration for adaptively adjusting a power supply voltage in a digital processing system
JP4277979B2 (en) * 2003-01-31 2009-06-10 株式会社ルネサステクノロジ Semiconductor integrated circuit device
US6937076B2 (en) * 2003-06-11 2005-08-30 Micron Technology, Inc. Clock synchronizing apparatus and method using frequency dependent variable delay
US7299329B2 (en) * 2004-01-29 2007-11-20 Micron Technology, Inc. Dual edge command in DRAM
JP4549958B2 (en) * 2005-02-09 2010-09-22 パナソニック株式会社 Delay locked loop circuit
US7439816B1 (en) 2005-09-28 2008-10-21 Cypress Semiconductor Corporation Phase-locked loop fast lock circuit and method
KR100672033B1 (en) * 2005-10-14 2007-01-19 삼성전자주식회사 Dll circuit having two input standard clock, clock signal generation circuit having the dll circuit and clock signal generation method
US20070201596A1 (en) * 2006-02-28 2007-08-30 Flowers John P Clock synchronization using early clock
JP2009147829A (en) * 2007-12-17 2009-07-02 Panasonic Corp Dll circuit, imaging device, and memory device
WO2010097846A1 (en) 2009-02-26 2010-09-02 パナソニック株式会社 Phase adjustment circuit
TWI465045B (en) 2011-02-01 2014-12-11 Novatek Microelectronics Corp Delay lock loop and clock signal generating method
KR20180072082A (en) * 2016-12-21 2018-06-29 에스케이하이닉스 주식회사 Duty correction circuit and method for correcting duty
US10560105B1 (en) 2018-10-30 2020-02-11 Qualcomm Incorporated Delay-locked loop with large tuning range
KR20210126821A (en) * 2020-04-10 2021-10-21 삼성전자주식회사 Semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5101117A (en) * 1988-02-17 1992-03-31 Mips Computer Systems Variable delay line phase-locked loop circuit synchronization system
US5109394A (en) * 1990-12-24 1992-04-28 Ncr Corporation All digital phase locked loop
US5552726A (en) * 1993-05-05 1996-09-03 Texas Instruments Incorporated High resolution digital phase locked loop with automatic recovery logic
JP2771464B2 (en) * 1994-09-29 1998-07-02 日本電気アイシーマイコンシステム株式会社 Digital PLL circuit
US5744991A (en) * 1995-10-16 1998-04-28 Altera Corporation System for distributing clocks using a delay lock loop in a programmable logic circuit

Also Published As

Publication number Publication date
JP2002510156A (en) 2002-04-02
US5969552A (en) 1999-10-19
CA2317480C (en) 2004-01-06
AU2011299A (en) 1999-08-02
WO1999037026A1 (en) 1999-07-22
JP3564392B2 (en) 2004-09-08
KR20010034143A (en) 2001-04-25
KR100338212B1 (en) 2002-06-07

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