CA2304635A1 - Integrated single chip dual mode raid controller - Google Patents

Integrated single chip dual mode raid controller Download PDF

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Publication number
CA2304635A1
CA2304635A1 CA002304635A CA2304635A CA2304635A1 CA 2304635 A1 CA2304635 A1 CA 2304635A1 CA 002304635 A CA002304635 A CA 002304635A CA 2304635 A CA2304635 A CA 2304635A CA 2304635 A1 CA2304635 A1 CA 2304635A1
Authority
CA
Canada
Prior art keywords
raid
chip
mode
interface
host cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002304635A
Other languages
French (fr)
Other versions
CA2304635C (en
Inventor
Brian A. Day
Bret S. Weber
Mark J. Jander
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
Lsi Logic Corporation
Brian A. Day
Bret S. Weber
Mark J. Jander
Symbios Logic Inc.
Lsi Logic (Fsi), Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Logic Corporation, Brian A. Day, Bret S. Weber, Mark J. Jander, Symbios Logic Inc., Lsi Logic (Fsi), Inc. filed Critical Lsi Logic Corporation
Publication of CA2304635A1 publication Critical patent/CA2304635A1/en
Application granted granted Critical
Publication of CA2304635C publication Critical patent/CA2304635C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0626—Reducing size or complexity of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0689—Disk arrays, e.g. RAID, JBOD

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Information Transfer Systems (AREA)

Abstract

A RAID controller integrated into a single chip (100). The RAID controller chip (100) includes a general purpose RISC processor (121), memory interface logic (128), a host CPU PCI bus (150), at least one back-end I/O interface channel (130), at least one direct memory access (DMA) channel (122), and a RAID parity assist (RPA) circuit (126). The RAID chip enables higher integration of RAID functions within a printed circuit board and in particular enables RAID function integration directly on a personal computer or workstation motherboard. The back-end I/O interface channel is preferably dual SCSI channels. The RAID chip is operable in either of two modes. In a first mode, the chip provides pass through from the host CPU (102) interface directly to the dual SCSI channels (130). This first mode of operation, a SCSI
pass-through mode, allows use of the chip for non-RAID storage applications and enables low level manipulation of the disk array in RAID applications of the chip. The first mode of operation permits use of the chip without change to host applications and drivers. Rather, the chip is operable in a manner compatible with known available SCSI controller devices. The second mode of operation, a RAID control mode, provides full RAID management features to the attached host CPU. In the preferred embodiment, the RAID chip presents an Intelligent I/O (I2O) interface to the host CPU to enhance portability and performance of the host/RAID interaction.
CA002304635A 1997-09-30 1998-09-29 Integrated single chip dual mode raid controller Expired - Fee Related CA2304635C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/941,435 US6065096A (en) 1997-09-30 1997-09-30 Integrated single chip dual mode raid controller
US08/941,435 1997-09-30
PCT/US1998/020302 WO1999017190A1 (en) 1997-09-30 1998-09-29 Integrated single chip dual mode raid controller

Publications (2)

Publication Number Publication Date
CA2304635A1 true CA2304635A1 (en) 1999-04-08
CA2304635C CA2304635C (en) 2002-05-28

Family

ID=25476458

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002304635A Expired - Fee Related CA2304635C (en) 1997-09-30 1998-09-29 Integrated single chip dual mode raid controller

Country Status (7)

Country Link
US (1) US6065096A (en)
EP (1) EP1023658B1 (en)
JP (1) JP2001518657A (en)
AU (1) AU1063199A (en)
CA (1) CA2304635C (en)
DE (1) DE69803087T2 (en)
WO (1) WO1999017190A1 (en)

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Also Published As

Publication number Publication date
DE69803087D1 (en) 2002-01-31
US6065096A (en) 2000-05-16
JP2001518657A (en) 2001-10-16
EP1023658B1 (en) 2001-12-19
DE69803087T2 (en) 2002-07-18
EP1023658A1 (en) 2000-08-02
CA2304635C (en) 2002-05-28
WO1999017190A1 (en) 1999-04-08
AU1063199A (en) 1999-04-23

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Effective date: 20150929