CA2304340A1 - Full-duplex communication processor - Google Patents

Full-duplex communication processor Download PDF

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Publication number
CA2304340A1
CA2304340A1 CA002304340A CA2304340A CA2304340A1 CA 2304340 A1 CA2304340 A1 CA 2304340A1 CA 002304340 A CA002304340 A CA 002304340A CA 2304340 A CA2304340 A CA 2304340A CA 2304340 A1 CA2304340 A1 CA 2304340A1
Authority
CA
Canada
Prior art keywords
communication processor
duplex communication
full
data
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002304340A
Other languages
French (fr)
Other versions
CA2304340C (en
Inventor
Bradley Roach
Peter Fiacco
Greg Scherer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Emulex Corp
Original Assignee
Emulex Corporation
Bradley Roach
Peter Fiacco
Greg Scherer
Emulex Design & Manufacturing Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Emulex Corporation, Bradley Roach, Peter Fiacco, Greg Scherer, Emulex Design & Manufacturing Corporation filed Critical Emulex Corporation
Publication of CA2304340A1 publication Critical patent/CA2304340A1/en
Application granted granted Critical
Publication of CA2304340C publication Critical patent/CA2304340C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/546—Message passing systems or structures, e.g. queues
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/2801—Broadband local area networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9084—Reactions to storage capacity overflow
    • H04L49/9089—Reactions to storage capacity overflow replacing packets in a storage arrangement, e.g. pushout
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/28—DMA
    • G06F2213/2802—DMA using DMA transfer descriptors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/12—Protocol engines

Abstract

A full duplex communication processor (20) simultaneously sends and receives frames of data and commands. Separate transmit (32) and receive (30) protocol engines are controlled by separate sequencers. This enables frames of data to be received and transmitted simultaneously without involving the CPU (40) on a frame-by-frame basis.
CA002304340A 1997-09-24 1998-09-24 Full-duplex communication processor Expired - Fee Related CA2304340C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/937,066 1997-09-24
US08/937,066 US6005849A (en) 1997-09-24 1997-09-24 Full-duplex communication processor which can be used for fibre channel frames
PCT/US1998/020003 WO1999016195A1 (en) 1997-09-24 1998-09-24 Full-duplex communication processor

Publications (2)

Publication Number Publication Date
CA2304340A1 true CA2304340A1 (en) 1999-04-01
CA2304340C CA2304340C (en) 2001-12-18

Family

ID=25469444

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002304340A Expired - Fee Related CA2304340C (en) 1997-09-24 1998-09-24 Full-duplex communication processor

Country Status (6)

Country Link
US (1) US6005849A (en)
EP (1) EP1021879A4 (en)
JP (1) JP2001517895A (en)
KR (1) KR100315245B1 (en)
CA (1) CA2304340C (en)
WO (1) WO1999016195A1 (en)

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Also Published As

Publication number Publication date
KR100315245B1 (en) 2001-11-26
KR20010024291A (en) 2001-03-26
US6005849A (en) 1999-12-21
CA2304340C (en) 2001-12-18
WO1999016195A1 (en) 1999-04-01
JP2001517895A (en) 2001-10-09
EP1021879A1 (en) 2000-07-26
EP1021879A4 (en) 2006-04-12

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