CA2269285A1 - Mechanism to support a utopia interface over a backplane - Google Patents
Mechanism to support a utopia interface over a backplane Download PDFInfo
- Publication number
- CA2269285A1 CA2269285A1 CA002269285A CA2269285A CA2269285A1 CA 2269285 A1 CA2269285 A1 CA 2269285A1 CA 002269285 A CA002269285 A CA 002269285A CA 2269285 A CA2269285 A CA 2269285A CA 2269285 A1 CA2269285 A1 CA 2269285A1
- Authority
- CA
- Canada
- Prior art keywords
- transfer rate
- backplane
- atm
- atm cells
- over
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane
- H04L49/405—Physical details, e.g. power supply, mechanical construction or backplane of ATM switches
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5672—Multiplexing, e.g. coding, scrambling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5672—Multiplexing, e.g. coding, scrambling
- H04L2012/5674—Synchronisation, timing recovery or alignment
Abstract
A UTOPIA level interface over a backplane for connecting up to 31 Physical layer devices (250, 270, and 290) to one ATM layer device (210) in a logically partitioned manner utilizing full bandwidth. The communications data is received on a first terminal at a first transfer rate. The communications data transfer rate is reduced from the first transfer rate to a second transfer rate. At the second transfer rate, the communications data is transferred over a backplane to a second terminal. On the second terminal, communications data transfer rate is increased from the second transfer rate to the first transfer rate. The first transfer rate is greater than the second transfer rate.
Description
. MECHANISM TO SUPPORT AN
s UTOPIA INTERFACE OVER A BACKPLANE
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims priority from U.S.
Provisional Patent Application Serial No. 60/030,730, filed November 8, 1996, and is herein incorporated by reference.
BACKGROUND OF THE INVENTION
Asynchronous Transfer Mode (ATM? is a technique of transmitting, multiplexing, switching, and receiving information in a network. ATM provides a high-speed, low-delay network that supports any type of user traffic, such as data, image, video, and voice. ATM segments and multiplexes user traffic into small, fixed-length units called cells. The cell is transmitted as 53-bytes, with 5 bytes reserved for the cell header. Each cell is identified with virtual circuit identifiers that are contained in the cell header. An ATM
network uses these identifiers to relay the traffic through high-speed switches.
The lowest layer of the ATM model is the physical layer. The physical layer is concerned with functions that are dependent on the physical medium itself. Basically, the physical layer sends and receives cells on a physical line.
The physical layer provides mapping of ATM cells to a physical line. The physical layer devices can be either single chips or system level board designs.
The ATM layer resides on top of the physical layer of a conventional layered network protocol suite, but it does not require the use of a specific physical layer protocol.
The ATM layer processes the user traffic contained in the cells. Incoming virtual circuit identifiers on a link are sent to the proper output link by the ATM layer. Also, the cell headers are generated and interpreted by the ATM layer.
Only the upper layers of the ATM Model process the user traffic. The ATM layer is typically a single chip or system on a board.
The ATM Forum defines a specification for the protocol of transferring ATM cells between Physical layer and ATM layer devices. The specification is known as UTOPIA
(Universal Test and Operations Physical Interface) for ATM.
UTOPIA was proposed to standardize the interface between the various layers of the ATM architecture itself. In particular, the UTOPIA level 2 specification defines a protocol for a single ATM layer device to communicate with multiple Physical layer devices with respect to a 50 MHz clock. The UTOPIA
level 2 specification defines that a total of 31 Physical layer devices may be connected to a single ATM layer device.
Typically, system printed circuit boards have dimensions that do not easily accommodate 31 Physical devices and support hardware. The typical solution is to partition devices onto several boards connected by a backplane. A
problem then arises when using multiple Physical layer devices with respect to a 50 MHz signal. It is difficult to maintain signal integrity over a 50 MHz multi-access bus.
The UTOPIA level 2 standard defines the data line and protocol signals between chips, it does not define the specific physical connections between chips. Smaller systems may implement an entire system on a single printed circuit board with different components communicating with one another via bus traces on the printed circuit board. In this case, it may be possible to implement the UTOPIA level 2 interface in a straightforward manner, without much modification to account for the physical requirements of the printed circuit board traces.
However, in many larger ATM switches, it may be desirable to construct a switch out of a number of separate printed circuit boards. In such a case, a standard way for multiple printed circuit boards to communicate with one another would be through use of a backplane, as is known in the art. A problem arises in attempting to use an UTOPIA
level 2 interface on a backplane in that, at the 50 MHz frequency specified in an UTOPIA level 2 interface, trace lengths and capacitance are very large factors affecting the integrity of signals on backplane wires. Therefore, a straightforward adaptation of UTOPIA level 2 interface onto a backplane will in many cases not provide adequate performance in a high performance ATM system. Electromagnetic signal theory dictates that a 50 MHz trace length and capacitance become large factors in maintaining the shape and integrity of signals. At 25 MHz, the trace length and capacitance become less of a factor making backplane designs much easier.
However, when using a 25 MHz clock, there is a division of bandwidth.
Ideally, what is needed is a method and apparatus for allowing up to 31 Physical layer devices to be connected to one ATM layer device utilizing full bandwidth. Also, a method and apparatus capable of providing a simplified but standardized backplane interface for UTOPIA level 2 or similar bus interface standards.
SUMMARY OF THE INVENTION
The present invention provides systems and methods for utilizing an UTOPIA level 2 interface over a backplane to connect up to 31 Physical layer devices to one ATM layer device in a logically partitioned manner utilizing full bandwidth.
An UTOPIA interface over a backplane allows the Physical layer devices placed on several boards to connect with other boards via a backplane. An UTOPIA interface over a backplane reproduces standards based behavior on the far end of the backplane with respect to the ATM layer. Hence, the Physical layer devices operate using normal 50 MHz UTOPIA
level 2 defined handshakes. This requires the ATM layer device to acccept the cell available handshakes at a time later than it would otherwise. Additional hardware is placed between the ATM layer devices and Physical layer devices in ' 35 the form of demultiplexers and multiplexers.
The method of the present invention includes the steps of receiving communications data on a first terminal at a first transfer rate, reducing the rate of transfer of the communications data from the first transfer rate to a second transfer rate, transmitting the communications data over a backplane at the second transfer rate, receiving the communications data on a second terminal, and increasing the rate of transfer of the communications data from the second transfer rate to the first transfer rate. The first transfer rate is greater than the second transfer rate. The method also includes the steps of accepting the cell available handshake later than it would otherwise to reproduce the standardized timing at the PHI interface which is on the other side of the backplane and the means to configure such operation.
The device of the present invention includes a first demultiplexer coupled to an ATM layer device, a first multiplexes coupled to the first demultiplexer using a UTOPIA
level 2 interface over the backplane and a plurality of physical layer devices, a second multiplexes coupled to the ATM layer device, and a second demultiplexer coupled to the second multiplexes using the UTOPIA level 2 interface over the backplane and the plurality of physical layer devices.
The use of a backplane has several advantages. The signals across the backplane switch at 25 MHz which is physically manageable. Another advantage is the backplane allows for a convenient line card design that is useful in communication switches. Yet another advantage is the bandwidth associated with 50 MHz UTOPIA is not sacrificed since there are twice as many lines on the 25 MHz backplane.
Furthermore, using backplane UTOPIA, the trace length and capacitance become less of a factor making backplane designs much easier to implement.
A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
WO 98/20b38 PCT/US97/20450 FIG. 1 illustrates the system and method for connecting and transmitting data over the UTOPIA interface over a backplane; and FIG. 2 illustrates the method for connecting and transmitting data from an ATM layer device to multiple physical layer devices over an UTOPIA level 2 interface over a backplane.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In the description that follows, the present invention will be described in reference to a preferred embodiment that operates over a backplane. In particular, examples will be described which illustrate particular applications of the invention over a backplane. The present invention, however, is not limited to any particular information source nor limited by the examples described herein. Therefore, the description of the embodiments that follow are for purposes of illustration and not limitation.
The UTOPIA level 1 standard defines a mechanism for connecting one ATM layer device to one physical layer device.
Even though the description that follows describes the UTOPIA
level 2 standard, the description also applies to an UTOPIA
level 1 interface.
The UTOPIA level 2 standard defines a mechanism for separate components in an ATM system to communicate data in order to effectuate ATM network switching. For example, an ATM switching system may consist of an ATM switch fabric device on a single chip or a group of related chips connected to up to 31 additional chips, each of the 31 chips providing a physical interface to a transmission line. The UTOPIA level 2 interface defines a standard bus and protocol for communicating data between these devices, so that an ATM
system builder can purchase an ATM switch fabric chip from a different vendor than he purchases the physical layer interface chips and connect them on a board with some confidence that they can all communicate with one another via the UTOPIA level 2 standardized bus interface.
Figure 1 illustrates the system and method for connecting and transmitting data over the UTOPIA interface over a backplane. Communications data is typically transferred from an ATM layer device 110 to one or more physical layer devices 140 over a backplane 170. The communications data may be address, data and control information or any combination thereof. Communications data sent via ATM cells are transmitted at a first transfer rate.
Typically, the first transfer rate is approximately equal to 50 MHz. The backplane 170 can be a bus or any other communications line that carries information. Cards are plugged into the backplane 170 and typically each card has its own microprocessor and is adapted to or supports the standard interface. If the backplane 170 is a bus, the communications data travels from the ATM layer device 110 to the physical layer device 140 without delay since the bus is large enough to transfer the communications data along multiple paths across the backplane 170. If the backplane 170 is a set of point to point lines connecting the ATM layer device 110 to the physical layer devices 140, the first conversion device 120 can include demultiplexing logic together with First-In First-Out's (FIFO's). The FIFO's are used to store cells and act as a buffer so that the communications data can be transferred over the backplane 170 at a second transfer rate.
The first transfer rate is greater than the second transfer rate. Each FIFO stores the cells until the data can be sent at a second transfer rate to the proper physical layer device.
The ATM layer device 110 is coupled to one or more physical layer devices 140 over backplane 170 through one or more conversion devices. These conversion devices increase and decrease the transfer rate of the communications data as it travels between the ATM layer device 110 and the physical layer device 140.
In the preferred embodiment, the ATM layer device 110 is coupled to a first conversion device 120 that decreases the transfer rate of the communications data. Generally, the ATM cells are transmitted from the ATM layer device 110 to the first conversion device 120 at a transfer rate in one WO 98!20638 PCT/US97/20450 embodiment approximately equal to 50 MHz. Typically, the first conversion device 120 is a deinult.iplexer. The demultiplexer divides the ATM cell data along two or more transmission lines 180 and sends the data to a second conversion device 130 along the transmission lines 180. Two transmission lines 180 are generally used resulting in data being transmitted across the backplane 170 at a second transfer rate. The second transmission rate in one embodiment is approximately equal to 25 MHz. Sending the communications data at a second transmission rate allows the signal to maintain its shape and integrity across long traces on the backplane 170.
The second conversion device 130 increases the transfer rate of the data to the first transfer rate.
Typically, the second conversion device 130 is a multiplexer.
The multiplexer reforms the signal to allow for the communications data to be received by the physical layer device over a single transmission channel in the manner it was sent. The ATM layer device 110 timing is adjusted to expect the inherent delays that are encountered when multiplexing and demultiplexing the signals onto the backplane 170 while operating on a 50 MHz clock. The second conversion device 130 can be removed from the circuit resulting in the physical layer devices 140 receiving the communications data at a first transfer rate.
Communications data can also be sent from the physical layer device 140 to the ATM layer device 110. This is accomplished in a similar manner as described above. The physical layer device 140 is coupled to a third conversion device 160. The third conversion device 160 reduces the transfer rate of the communications data. Typically, the third conversion device 160 is a demultiplexer. The demultiplexer divides the ATM cell data along two or more transmission lines and sends the data to a fourth device 150 along the two transmission lines 180. Two transmission lines 180 are generally used resulting in data being transmitted across the backplane 170 at a transmission rate approximately equal to 25 MHz. Sending the communications data at a transmission rate approximately equal to 25 MHz allows the signal to maintain its shape and integrity across long traces on the backplane 170. The fourth conversion device 150 increases the transfer rate of the data. Typically, the fourth conversion device 150 is a multiplexer.
FIG. 2 illustrates the method for connecting and transmitting data from an ATM layer device to multiple physical layer devices over an UTOPIA level 2 interface over a backplane. As shown in FIG. 2, three physical layer devices 250, 270, and 290 are coupled to the ATM layer device 210 over a backplane 230. The UTOPIA level 2 chips are designed to run at 50 MHz, the backplane 230 is designed to run multiple busses each running at 25 MHz serving one or multiple Physical cards. Three physical layer devices are shown in FIG. 2, however, up to 31 physical layer devices can be coupled to the ---ATM layer device 210 utilizing full bandwidth.
The ATM cells are sent from the ATM layer device 210 to the ATM logic unit 220. The ATM logic unit 220 includes multiplexing and demultiplexing logic together with FIFO
logic. The ATM logic unit 220 can be any device or combination of devices that reduce or decrease the transmission rate of a signal. Thereafter, the data is transmitted over the backplane 230 at approximately 25 MHz to multiple logic units.
For example, the data may be received by a first logic unit 240. The first logic unit 240 includes multiplexing and demultiplexing logic together with FIFO's.
The data is received by the first logic unit 240 and the first logic unit 240 increases the transfer rate to approximately 50 MHz. The multiple logic units need not perform a rate transfer. In a similar manner, the data can be transferred to up to 31 physical layer devices. Furthermore, the data can be transferred from the 31 physical layer devices to the ATM
layer device 210. Reverse logic is utilized in this situation.
The invention has now been explained with reference to specific embodiments. Other embodiments will be apparent to one of ordinary skill in the art. It is therefore not intended that this invention be limited, except as indicated by the appended claims.
s UTOPIA INTERFACE OVER A BACKPLANE
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims priority from U.S.
Provisional Patent Application Serial No. 60/030,730, filed November 8, 1996, and is herein incorporated by reference.
BACKGROUND OF THE INVENTION
Asynchronous Transfer Mode (ATM? is a technique of transmitting, multiplexing, switching, and receiving information in a network. ATM provides a high-speed, low-delay network that supports any type of user traffic, such as data, image, video, and voice. ATM segments and multiplexes user traffic into small, fixed-length units called cells. The cell is transmitted as 53-bytes, with 5 bytes reserved for the cell header. Each cell is identified with virtual circuit identifiers that are contained in the cell header. An ATM
network uses these identifiers to relay the traffic through high-speed switches.
The lowest layer of the ATM model is the physical layer. The physical layer is concerned with functions that are dependent on the physical medium itself. Basically, the physical layer sends and receives cells on a physical line.
The physical layer provides mapping of ATM cells to a physical line. The physical layer devices can be either single chips or system level board designs.
The ATM layer resides on top of the physical layer of a conventional layered network protocol suite, but it does not require the use of a specific physical layer protocol.
The ATM layer processes the user traffic contained in the cells. Incoming virtual circuit identifiers on a link are sent to the proper output link by the ATM layer. Also, the cell headers are generated and interpreted by the ATM layer.
Only the upper layers of the ATM Model process the user traffic. The ATM layer is typically a single chip or system on a board.
The ATM Forum defines a specification for the protocol of transferring ATM cells between Physical layer and ATM layer devices. The specification is known as UTOPIA
(Universal Test and Operations Physical Interface) for ATM.
UTOPIA was proposed to standardize the interface between the various layers of the ATM architecture itself. In particular, the UTOPIA level 2 specification defines a protocol for a single ATM layer device to communicate with multiple Physical layer devices with respect to a 50 MHz clock. The UTOPIA
level 2 specification defines that a total of 31 Physical layer devices may be connected to a single ATM layer device.
Typically, system printed circuit boards have dimensions that do not easily accommodate 31 Physical devices and support hardware. The typical solution is to partition devices onto several boards connected by a backplane. A
problem then arises when using multiple Physical layer devices with respect to a 50 MHz signal. It is difficult to maintain signal integrity over a 50 MHz multi-access bus.
The UTOPIA level 2 standard defines the data line and protocol signals between chips, it does not define the specific physical connections between chips. Smaller systems may implement an entire system on a single printed circuit board with different components communicating with one another via bus traces on the printed circuit board. In this case, it may be possible to implement the UTOPIA level 2 interface in a straightforward manner, without much modification to account for the physical requirements of the printed circuit board traces.
However, in many larger ATM switches, it may be desirable to construct a switch out of a number of separate printed circuit boards. In such a case, a standard way for multiple printed circuit boards to communicate with one another would be through use of a backplane, as is known in the art. A problem arises in attempting to use an UTOPIA
level 2 interface on a backplane in that, at the 50 MHz frequency specified in an UTOPIA level 2 interface, trace lengths and capacitance are very large factors affecting the integrity of signals on backplane wires. Therefore, a straightforward adaptation of UTOPIA level 2 interface onto a backplane will in many cases not provide adequate performance in a high performance ATM system. Electromagnetic signal theory dictates that a 50 MHz trace length and capacitance become large factors in maintaining the shape and integrity of signals. At 25 MHz, the trace length and capacitance become less of a factor making backplane designs much easier.
However, when using a 25 MHz clock, there is a division of bandwidth.
Ideally, what is needed is a method and apparatus for allowing up to 31 Physical layer devices to be connected to one ATM layer device utilizing full bandwidth. Also, a method and apparatus capable of providing a simplified but standardized backplane interface for UTOPIA level 2 or similar bus interface standards.
SUMMARY OF THE INVENTION
The present invention provides systems and methods for utilizing an UTOPIA level 2 interface over a backplane to connect up to 31 Physical layer devices to one ATM layer device in a logically partitioned manner utilizing full bandwidth.
An UTOPIA interface over a backplane allows the Physical layer devices placed on several boards to connect with other boards via a backplane. An UTOPIA interface over a backplane reproduces standards based behavior on the far end of the backplane with respect to the ATM layer. Hence, the Physical layer devices operate using normal 50 MHz UTOPIA
level 2 defined handshakes. This requires the ATM layer device to acccept the cell available handshakes at a time later than it would otherwise. Additional hardware is placed between the ATM layer devices and Physical layer devices in ' 35 the form of demultiplexers and multiplexers.
The method of the present invention includes the steps of receiving communications data on a first terminal at a first transfer rate, reducing the rate of transfer of the communications data from the first transfer rate to a second transfer rate, transmitting the communications data over a backplane at the second transfer rate, receiving the communications data on a second terminal, and increasing the rate of transfer of the communications data from the second transfer rate to the first transfer rate. The first transfer rate is greater than the second transfer rate. The method also includes the steps of accepting the cell available handshake later than it would otherwise to reproduce the standardized timing at the PHI interface which is on the other side of the backplane and the means to configure such operation.
The device of the present invention includes a first demultiplexer coupled to an ATM layer device, a first multiplexes coupled to the first demultiplexer using a UTOPIA
level 2 interface over the backplane and a plurality of physical layer devices, a second multiplexes coupled to the ATM layer device, and a second demultiplexer coupled to the second multiplexes using the UTOPIA level 2 interface over the backplane and the plurality of physical layer devices.
The use of a backplane has several advantages. The signals across the backplane switch at 25 MHz which is physically manageable. Another advantage is the backplane allows for a convenient line card design that is useful in communication switches. Yet another advantage is the bandwidth associated with 50 MHz UTOPIA is not sacrificed since there are twice as many lines on the 25 MHz backplane.
Furthermore, using backplane UTOPIA, the trace length and capacitance become less of a factor making backplane designs much easier to implement.
A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
WO 98/20b38 PCT/US97/20450 FIG. 1 illustrates the system and method for connecting and transmitting data over the UTOPIA interface over a backplane; and FIG. 2 illustrates the method for connecting and transmitting data from an ATM layer device to multiple physical layer devices over an UTOPIA level 2 interface over a backplane.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In the description that follows, the present invention will be described in reference to a preferred embodiment that operates over a backplane. In particular, examples will be described which illustrate particular applications of the invention over a backplane. The present invention, however, is not limited to any particular information source nor limited by the examples described herein. Therefore, the description of the embodiments that follow are for purposes of illustration and not limitation.
The UTOPIA level 1 standard defines a mechanism for connecting one ATM layer device to one physical layer device.
Even though the description that follows describes the UTOPIA
level 2 standard, the description also applies to an UTOPIA
level 1 interface.
The UTOPIA level 2 standard defines a mechanism for separate components in an ATM system to communicate data in order to effectuate ATM network switching. For example, an ATM switching system may consist of an ATM switch fabric device on a single chip or a group of related chips connected to up to 31 additional chips, each of the 31 chips providing a physical interface to a transmission line. The UTOPIA level 2 interface defines a standard bus and protocol for communicating data between these devices, so that an ATM
system builder can purchase an ATM switch fabric chip from a different vendor than he purchases the physical layer interface chips and connect them on a board with some confidence that they can all communicate with one another via the UTOPIA level 2 standardized bus interface.
Figure 1 illustrates the system and method for connecting and transmitting data over the UTOPIA interface over a backplane. Communications data is typically transferred from an ATM layer device 110 to one or more physical layer devices 140 over a backplane 170. The communications data may be address, data and control information or any combination thereof. Communications data sent via ATM cells are transmitted at a first transfer rate.
Typically, the first transfer rate is approximately equal to 50 MHz. The backplane 170 can be a bus or any other communications line that carries information. Cards are plugged into the backplane 170 and typically each card has its own microprocessor and is adapted to or supports the standard interface. If the backplane 170 is a bus, the communications data travels from the ATM layer device 110 to the physical layer device 140 without delay since the bus is large enough to transfer the communications data along multiple paths across the backplane 170. If the backplane 170 is a set of point to point lines connecting the ATM layer device 110 to the physical layer devices 140, the first conversion device 120 can include demultiplexing logic together with First-In First-Out's (FIFO's). The FIFO's are used to store cells and act as a buffer so that the communications data can be transferred over the backplane 170 at a second transfer rate.
The first transfer rate is greater than the second transfer rate. Each FIFO stores the cells until the data can be sent at a second transfer rate to the proper physical layer device.
The ATM layer device 110 is coupled to one or more physical layer devices 140 over backplane 170 through one or more conversion devices. These conversion devices increase and decrease the transfer rate of the communications data as it travels between the ATM layer device 110 and the physical layer device 140.
In the preferred embodiment, the ATM layer device 110 is coupled to a first conversion device 120 that decreases the transfer rate of the communications data. Generally, the ATM cells are transmitted from the ATM layer device 110 to the first conversion device 120 at a transfer rate in one WO 98!20638 PCT/US97/20450 embodiment approximately equal to 50 MHz. Typically, the first conversion device 120 is a deinult.iplexer. The demultiplexer divides the ATM cell data along two or more transmission lines 180 and sends the data to a second conversion device 130 along the transmission lines 180. Two transmission lines 180 are generally used resulting in data being transmitted across the backplane 170 at a second transfer rate. The second transmission rate in one embodiment is approximately equal to 25 MHz. Sending the communications data at a second transmission rate allows the signal to maintain its shape and integrity across long traces on the backplane 170.
The second conversion device 130 increases the transfer rate of the data to the first transfer rate.
Typically, the second conversion device 130 is a multiplexer.
The multiplexer reforms the signal to allow for the communications data to be received by the physical layer device over a single transmission channel in the manner it was sent. The ATM layer device 110 timing is adjusted to expect the inherent delays that are encountered when multiplexing and demultiplexing the signals onto the backplane 170 while operating on a 50 MHz clock. The second conversion device 130 can be removed from the circuit resulting in the physical layer devices 140 receiving the communications data at a first transfer rate.
Communications data can also be sent from the physical layer device 140 to the ATM layer device 110. This is accomplished in a similar manner as described above. The physical layer device 140 is coupled to a third conversion device 160. The third conversion device 160 reduces the transfer rate of the communications data. Typically, the third conversion device 160 is a demultiplexer. The demultiplexer divides the ATM cell data along two or more transmission lines and sends the data to a fourth device 150 along the two transmission lines 180. Two transmission lines 180 are generally used resulting in data being transmitted across the backplane 170 at a transmission rate approximately equal to 25 MHz. Sending the communications data at a transmission rate approximately equal to 25 MHz allows the signal to maintain its shape and integrity across long traces on the backplane 170. The fourth conversion device 150 increases the transfer rate of the data. Typically, the fourth conversion device 150 is a multiplexer.
FIG. 2 illustrates the method for connecting and transmitting data from an ATM layer device to multiple physical layer devices over an UTOPIA level 2 interface over a backplane. As shown in FIG. 2, three physical layer devices 250, 270, and 290 are coupled to the ATM layer device 210 over a backplane 230. The UTOPIA level 2 chips are designed to run at 50 MHz, the backplane 230 is designed to run multiple busses each running at 25 MHz serving one or multiple Physical cards. Three physical layer devices are shown in FIG. 2, however, up to 31 physical layer devices can be coupled to the ---ATM layer device 210 utilizing full bandwidth.
The ATM cells are sent from the ATM layer device 210 to the ATM logic unit 220. The ATM logic unit 220 includes multiplexing and demultiplexing logic together with FIFO
logic. The ATM logic unit 220 can be any device or combination of devices that reduce or decrease the transmission rate of a signal. Thereafter, the data is transmitted over the backplane 230 at approximately 25 MHz to multiple logic units.
For example, the data may be received by a first logic unit 240. The first logic unit 240 includes multiplexing and demultiplexing logic together with FIFO's.
The data is received by the first logic unit 240 and the first logic unit 240 increases the transfer rate to approximately 50 MHz. The multiple logic units need not perform a rate transfer. In a similar manner, the data can be transferred to up to 31 physical layer devices. Furthermore, the data can be transferred from the 31 physical layer devices to the ATM
layer device 210. Reverse logic is utilized in this situation.
The invention has now been explained with reference to specific embodiments. Other embodiments will be apparent to one of ordinary skill in the art. It is therefore not intended that this invention be limited, except as indicated by the appended claims.
Claims
WHAT IS CLAIMED IS:
1. A method for carrying communications data over a backplane, comprising the steps of:
receiving communications data on a first terminal at a first transfer rate;
decreasing the rate of transfer of said communications data from said first transfer rate to a second transfer rate, said first transfer rate being greater than said second transfer rate;
transmitting said communications data over a backplane at said second transfer rate; and receiving said communications data on a second terminal.
2. The method of claim 1 further comprising the step of increasing the rate of transfer of said communications data from said second transfer rate to said first transfer rate.
3. The method of claim 1 further comprising the step of sending said communications data from a first device to said first terminal.
4. The method of claim 1 further comprising the step of sending the communications data from said second terminal to a second device.
5. The method of claim 1 further comprising the step of delaying said communications data to reproduce a standardized timing.
6. The method of claim 1 wherein said communications data comprises ATM cells.
7. The method of claim 1 wherein said first transfer rate is approximately equal to 50 MHz.
8. The method of claim 1 wherein said second transfer rate is less than 30 MHz.
9. The method of claim 3 wherein said step of sending occurs at a transfer rate in the range of 49 MHz to 51 MHz.
10. The method of claim 4 wherein said step of sending occurs at a transfer rate in the range of 49 MHz to 51 MHz.
11. A method for transferring ATM cells over a backplane, comprising the steps of:
demultiplexing ATM cells on a first terminal at a first transfer rate;
transmitting said ATM cells over said backplane at a second transfer rate, said ATM cells having a greater transfer rate than available over said backplane; and multiplexing said ATM cells on a second terminal.
12. The method of claim 11 wherein said second transfer rate is less than 30 MHz.
13. The method of claim 11 further comprising the step of sending said ATM cells from said ATM layer device to said demultiplexer at a transfer rate approximately equal to 50 MHz.
14. The method of claim 11 further comprising the step of sending said ATM cells from said multiplexer to said plurality of physical layer devices at a transfer rate approximately equal to 50 MHz.
15. A method for transferring ATM cells over a backplane, comprising the steps of:
coupling an ATM layer device to a demultiplexer;
coupling a plurality of physical layer devices to a multiplexer;
coupling said demultiplexer to said multiplexer; and transferring said ATM cells from said demultiplexer to said multiplexer over said backplane.
15. A method for transferring ATM cells over a backplane, comprising the steps of:
coupling an ATM layer device to a multiplexer;
coupling a plurality of physical layer devices to a demultiplexer;
coupling said multiplexer to said demultiplexer; and transferring said ATM cells from said demultiplexer to said multiplexer over said backplane.
17. The method of claim 16 further comprising the step of sending said ATM cells from said multiplexer to said ATM layer device at a transfer rate approximately equal to 50 MHz.
18. The method of claim 16 further comprising the step of sending said ATM cells from said plurality of physical layer devices to said demultiplexer at a transfer rate approximately equal to 50 MHz.
19. A method for implementing a UTOPIA interface over a backplane, comprising the steps of:
demultiplexing ATM cells on a first terminal at a first transfer rate;
transmitting said ATM cells at a second transfer rate using a UTOPIA level 2 interface over said backplane, said ATM cells having a greater transfer rate than available using said UTOPIA level 2 interface over said backplane; and multiplexing said ATM cells on a second terminal.
20. A method for implementing a UTOPIA interface over a backplane, comprising the steps of:
demultiplexing ATM cells on a first terminal at a first transfer rate;
transmitting said ATM cells at a second transfer rate using a UTOPIA level 2 interface over said backplane, said first transfer rate being greater than said second transfer rate; and multiplexing said ATM cells on a second terminal.
21. An apparatus for implementing a UTOPIA
interface over a backplane having a plurality of physical layer devices and an ATM layer device, comprising:
a first demultiplexer coupled to an ATM layer device;
a first multiplexer coupled to said first demultiplexer using a UTOPIA level 2 interface over said backplane and a plurality of physical layer devices;
a second multiplexer coupled to said ATM layer device; and a second demultiplexer coupled to said second multiplexer using said UTOPIA level 2 interface over said backplane and said plurality of physical layer devices.
1. A method for carrying communications data over a backplane, comprising the steps of:
receiving communications data on a first terminal at a first transfer rate;
decreasing the rate of transfer of said communications data from said first transfer rate to a second transfer rate, said first transfer rate being greater than said second transfer rate;
transmitting said communications data over a backplane at said second transfer rate; and receiving said communications data on a second terminal.
2. The method of claim 1 further comprising the step of increasing the rate of transfer of said communications data from said second transfer rate to said first transfer rate.
3. The method of claim 1 further comprising the step of sending said communications data from a first device to said first terminal.
4. The method of claim 1 further comprising the step of sending the communications data from said second terminal to a second device.
5. The method of claim 1 further comprising the step of delaying said communications data to reproduce a standardized timing.
6. The method of claim 1 wherein said communications data comprises ATM cells.
7. The method of claim 1 wherein said first transfer rate is approximately equal to 50 MHz.
8. The method of claim 1 wherein said second transfer rate is less than 30 MHz.
9. The method of claim 3 wherein said step of sending occurs at a transfer rate in the range of 49 MHz to 51 MHz.
10. The method of claim 4 wherein said step of sending occurs at a transfer rate in the range of 49 MHz to 51 MHz.
11. A method for transferring ATM cells over a backplane, comprising the steps of:
demultiplexing ATM cells on a first terminal at a first transfer rate;
transmitting said ATM cells over said backplane at a second transfer rate, said ATM cells having a greater transfer rate than available over said backplane; and multiplexing said ATM cells on a second terminal.
12. The method of claim 11 wherein said second transfer rate is less than 30 MHz.
13. The method of claim 11 further comprising the step of sending said ATM cells from said ATM layer device to said demultiplexer at a transfer rate approximately equal to 50 MHz.
14. The method of claim 11 further comprising the step of sending said ATM cells from said multiplexer to said plurality of physical layer devices at a transfer rate approximately equal to 50 MHz.
15. A method for transferring ATM cells over a backplane, comprising the steps of:
coupling an ATM layer device to a demultiplexer;
coupling a plurality of physical layer devices to a multiplexer;
coupling said demultiplexer to said multiplexer; and transferring said ATM cells from said demultiplexer to said multiplexer over said backplane.
15. A method for transferring ATM cells over a backplane, comprising the steps of:
coupling an ATM layer device to a multiplexer;
coupling a plurality of physical layer devices to a demultiplexer;
coupling said multiplexer to said demultiplexer; and transferring said ATM cells from said demultiplexer to said multiplexer over said backplane.
17. The method of claim 16 further comprising the step of sending said ATM cells from said multiplexer to said ATM layer device at a transfer rate approximately equal to 50 MHz.
18. The method of claim 16 further comprising the step of sending said ATM cells from said plurality of physical layer devices to said demultiplexer at a transfer rate approximately equal to 50 MHz.
19. A method for implementing a UTOPIA interface over a backplane, comprising the steps of:
demultiplexing ATM cells on a first terminal at a first transfer rate;
transmitting said ATM cells at a second transfer rate using a UTOPIA level 2 interface over said backplane, said ATM cells having a greater transfer rate than available using said UTOPIA level 2 interface over said backplane; and multiplexing said ATM cells on a second terminal.
20. A method for implementing a UTOPIA interface over a backplane, comprising the steps of:
demultiplexing ATM cells on a first terminal at a first transfer rate;
transmitting said ATM cells at a second transfer rate using a UTOPIA level 2 interface over said backplane, said first transfer rate being greater than said second transfer rate; and multiplexing said ATM cells on a second terminal.
21. An apparatus for implementing a UTOPIA
interface over a backplane having a plurality of physical layer devices and an ATM layer device, comprising:
a first demultiplexer coupled to an ATM layer device;
a first multiplexer coupled to said first demultiplexer using a UTOPIA level 2 interface over said backplane and a plurality of physical layer devices;
a second multiplexer coupled to said ATM layer device; and a second demultiplexer coupled to said second multiplexer using said UTOPIA level 2 interface over said backplane and said plurality of physical layer devices.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US3073096P | 1996-11-08 | 1996-11-08 | |
| US60/030,730 | 1996-11-08 | ||
| PCT/US1997/020450 WO1998020638A1 (en) | 1996-11-08 | 1997-11-07 | Mechanism to support a utopia interface over a backplane |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2269285A1 true CA2269285A1 (en) | 1998-05-14 |
Family
ID=21855698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002269285A Abandoned CA2269285A1 (en) | 1996-11-08 | 1997-11-07 | Mechanism to support a utopia interface over a backplane |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6147997A (en) |
| CA (1) | CA2269285A1 (en) |
| WO (1) | WO1998020638A1 (en) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6690670B1 (en) * | 1998-03-13 | 2004-02-10 | Paradyne Corporation | System and method for transmission between ATM layer devices and PHY layer devices over a serial bus |
| US6775302B1 (en) * | 1998-12-14 | 2004-08-10 | Agere Systems Inc. | Communications system with symmetrical interfaces and associated methods |
| US6449655B1 (en) * | 1999-01-08 | 2002-09-10 | Cisco Technology, Inc. | Method and apparatus for communication between network devices operating at different frequencies |
| CA2362704C (en) * | 1999-02-23 | 2005-01-11 | Siemens Aktiengesellschaft | Time-critical routing of data to a clocked interface with asynchronous data transmission |
| US6826187B1 (en) * | 1999-05-07 | 2004-11-30 | Cisco Technology, Inc. | Interfacing between a physical layer and a bus |
| CA2271539A1 (en) * | 1999-05-12 | 2000-11-12 | Pmc-Sierra Inc. | Interface between a link layer device and one or more physical layer devices |
| WO2000079828A1 (en) * | 1999-06-17 | 2000-12-28 | Nokia Corporation | Multiplexing and demultiplexing method and apparatus |
| GB2352142B (en) * | 1999-07-12 | 2004-04-14 | Virata Ltd | QOS aware expansion mechanism |
| DE19943115A1 (en) * | 1999-09-09 | 2001-03-22 | Siemens Ag | Data communication method |
| KR100308907B1 (en) * | 1999-11-15 | 2001-11-02 | 윤종용 | Low speed subscriber enlarge system |
| US6718419B1 (en) * | 1999-11-17 | 2004-04-06 | Globespanvirata, Inc. | System and method for extending the number of addressable physical devices on a data bus |
| US7370110B2 (en) * | 2000-04-18 | 2008-05-06 | Hoshiko Llc | Method and system for operating a network server to discourage inappropriate use |
| US20020031141A1 (en) * | 2000-05-25 | 2002-03-14 | Mcwilliams Patrick | Method of detecting back pressure in a communication system using an utopia-LVDS bridge |
| KR100336593B1 (en) * | 2000-06-14 | 2002-05-16 | 박종섭 | Interface between UTOPIA level 2 and UTOPIA level 1 in ATM mutiplexing/demultiplexing assembly |
| US20040202170A1 (en) * | 2001-03-13 | 2004-10-14 | Adc Telecommunications Israel Ltd. | Implementing priority for multiple physical layer devices at a UTOPIA interface |
| US7315900B1 (en) * | 2001-06-20 | 2008-01-01 | Juniper Networks, Inc. | Multi-link routing |
| US7349401B2 (en) * | 2001-09-05 | 2008-03-25 | Symmetricom, Inc. | Bonded G.shdsl links for ATM backhaul applications |
| US8145787B1 (en) * | 2001-10-16 | 2012-03-27 | Cisco Technology, Inc. | Adaptive bandwidth utilization over fabric links |
| US7464180B1 (en) | 2001-10-16 | 2008-12-09 | Cisco Technology, Inc. | Prioritization and preemption of data frames over a switching fabric |
| US7203197B2 (en) * | 2002-06-26 | 2007-04-10 | Adtran, Inc. | Method and apparatus for interfacing utopia bus with serial TDM channel transporting ATM data |
| CN100433621C (en) * | 2005-05-17 | 2008-11-12 | 华为技术有限公司 | Method for improving DSL user board bandwidth and DSL user board using the same |
| US7544105B2 (en) * | 2005-08-23 | 2009-06-09 | Utilx Corporation | Cable and cable connection assembly |
| CN100426899C (en) * | 2005-09-13 | 2008-10-15 | 华为技术有限公司 | Apparatus and method for regulating interface transmission rate of transmission device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2938611B2 (en) * | 1991-05-14 | 1999-08-23 | 富士通株式会社 | TV signal exchange system |
| US5457687A (en) * | 1993-09-02 | 1995-10-10 | Network Equipment Technologies, Inc. | Method and apparatus for backward explicit congestion notification (BECN) in an ATM network |
| US5872645A (en) * | 1994-07-07 | 1999-02-16 | Gpt Limited | Telecommunications network |
| US5450411A (en) * | 1994-09-02 | 1995-09-12 | At&T Global Information Solutions Company | Network interface for multiplexing and demultiplexing isochronous and bursty data streams in ATM networks |
| JP3014080B2 (en) * | 1994-12-28 | 2000-02-28 | 三菱電機株式会社 | Exchange adapter and general-purpose computer |
| US5784370A (en) * | 1995-12-29 | 1998-07-21 | Cypress Semiconductor Corp. | Method and apparatus for regenerating a control signal at an asynchronous transfer mode (ATM) layer or a physical (PHY) layer |
| US5774465A (en) * | 1996-05-17 | 1998-06-30 | Transwitch Corp. | Method and apparatus for providing multiple multicast communication sessions in an ATM destination switch |
| AU5791098A (en) * | 1996-11-27 | 1998-06-22 | Alcatel Usa Sourcing, L.P. | Optical network unit for communicating telephony and video information |
-
1997
- 1997-11-07 CA CA002269285A patent/CA2269285A1/en not_active Abandoned
- 1997-11-07 US US08/965,737 patent/US6147997A/en not_active Expired - Lifetime
- 1997-11-07 WO PCT/US1997/020450 patent/WO1998020638A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| US6147997A (en) | 2000-11-14 |
| WO1998020638A1 (en) | 1998-05-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6147997A (en) | Mechanism to support an UTOPIA interface over a backplane | |
| US5533018A (en) | Multi-protocol packet framing over an isochronous network | |
| JP2001510002A (en) | ATM cell transmission | |
| JP3349914B2 (en) | ATM transmission equipment | |
| US6356557B1 (en) | Hot insertable UTOPIA interface with automatic protection switching for backplane applications | |
| US6091729A (en) | Methods and apparatus for high-speed data transfer that minimizes conductors | |
| JP3516490B2 (en) | Line interface device | |
| WO2003019873A1 (en) | Methods and systems for improving utilization of high-speed time division multiplexed communications links at signal transfer point | |
| US6823137B2 (en) | Optical line protection device and optical line protection method | |
| US6690670B1 (en) | System and method for transmission between ATM layer devices and PHY layer devices over a serial bus | |
| US5732069A (en) | ATM switch | |
| US20040202173A1 (en) | Utopia level interface in ATM multiplexing/demultiplexing assembly | |
| KR100284004B1 (en) | Host Digital Terminal in Demand-Density Optical Subscriber Transmitter | |
| EP1063595B1 (en) | Video/network interface | |
| US20010036202A1 (en) | Multiplexing apparatus | |
| KR100282406B1 (en) | Tone and DFM Switching Apparatus and Method in ATM Cell Conversion System | |
| KR100272568B1 (en) | Apparatus and method of switching cell in the private branch exchange | |
| KR0183346B1 (en) | Dma control apparatus in bisdn interface device | |
| KR100364744B1 (en) | Apparatus for duplexing link port Synchronous Transport Module | |
| KR20030019835A (en) | Apparatus for ATM switching using cellbus | |
| JP3398678B2 (en) | Switching method | |
| JP3679214B2 (en) | Propagation phase difference absorption method and apparatus in redundant configuration system | |
| KR100354269B1 (en) | Apparatus and method for data communication between block in mobile communication BTS | |
| JPH08149137A (en) | Stm-atm exchange | |
| KR19990053251A (en) | Independent communication port link device for easy expansion of communication ports |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued |