CA2263478A1 - Inverse multiplexing of digital data - Google Patents
Inverse multiplexing of digital data Download PDFInfo
- Publication number
- CA2263478A1 CA2263478A1 CA002263478A CA2263478A CA2263478A1 CA 2263478 A1 CA2263478 A1 CA 2263478A1 CA 002263478 A CA002263478 A CA 002263478A CA 2263478 A CA2263478 A CA 2263478A CA 2263478 A1 CA2263478 A1 CA 2263478A1
- Authority
- CA
- Canada
- Prior art keywords
- cells
- transmission links
- inverse multiplexing
- series
- links
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5614—User Network Interface
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5619—Network Node Interface, e.g. tandem connections, transit switching
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5619—Network Node Interface, e.g. tandem connections, transit switching
- H04L2012/5624—Path aspects, e.g. path bundling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5625—Operations, administration and maintenance [OAM]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5625—Operations, administration and maintenance [OAM]
- H04L2012/5627—Fault tolerance and recovery
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5628—Testing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5629—Admission control
- H04L2012/563—Signalling, e.g. protocols, reference model
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5649—Cell delay or jitter
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/565—Sequence integrity
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5672—Multiplexing, e.g. coding, scrambling
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
In ATM networks, digital data in ATM cells are sent to a destination node over more than one transmission link in round robin fashion. This is called inverse multiplexing. At connection start-up, the source node informs the destination node of the specific round robin fashion of the transmission links so that the ATM cells are reassembled in a proper sequential order. Inverse multiplexing control cells are used to communicate between the source node and destination node for connectivity testing of transmission links. Cell stuffing is also provided in one embodiment to accommodate non-synchronized links among transmission links. In a particular embodiment, two consecutive control cells indicate a stuffing cell. A start-up procedure is described when not all the transmission links are usable.
Description
CA 02263478 1999-02-1~
IN VERSE M ULTIPLEXIN G OF DIGITAL D ATA
Field of the Invention The invention relates to a new mechanism for sending ATM
5 cells transparently over multiple slower transmission links. In particular, the invention is directed to a method of inverse multiplexing of a series of ATM cells transparently over N
transmission links (N being a positive integer) of slower speed.
10 Background of the Invention It has been recognized that the T1/E1 rate (1.544/2.048 Mbit/s) is a cost effective way of user access to an ATM network as well as connection between ATM network switches. However, as ATM
technology for wide area networks is deployed more and more, 15 demands for transmission links of a rate higher than T1/E1 are increasing. Links of higher rates, such as T3/E3 (44.736/34.368 Mbit/s), have been designed to meet these needs. However, the cost of T3/E3 links is still prohibitive in many cases and the ratio of cost versus realistic utilization of the entire rate is not always attractive and fully 20 justified for new ATM end users and service providers. ATM inverse multiplexers (AIMs) have been proposed to satisfy the need by using multiple T1/E1 links which are grouped collectively to provide the service at a higher rate.
Figure 1 and Figure 2 show two sample configurations in which 25 AIMs are used. Figure 1 depicts a user access to a network through user network interfaces (UNIs) and Figure 2 a link connection between ATM switches through broadband inter-carrier interfaces (BICIs) or private network to network interfaces (PNNIs).
Referring to the figures, the basic function of AIMs is to work in 30 pairs to take an ATM cell stream coming from the ATM layer, send it over the multiple links by spreading cells over the available links and ensure that the initial cell stream can be retrieved at the far end. Thus the AIMs preferably make the ATM traffic transparent to the ATM
layer over multiple links which connect them. As far as the ATM layer 35 is concerned, it should only see a pipe whose rate is now the sum of the multiple link rates. It is assumed that each link is run in clear-mode without the presence of intermediate ATM nodes processing ATM
..... . . ... .. ...
CA 02263478 1999-02-l~
cells. This means that there should be no cell discard by any intermediate transmission equipment.
Currently no ATM inverse multiplexing protocols have been proposed which can properly interwork existing ATM inverse 5 multiplexers or other ATM products which are already available on the market, and yet are flexible enough to fit into the current standard ATM specifications. Two proposals for an ATM inverse multiplexing protocol have so far been made and are described in detail below.
10 New Transmission Convergence Protocol Using GFC Bits This protocol was presented in "Physical Layer Sub-Working Group ATM Forum/94-0775, ATM Inverse Multiplexing Mechanism", September 1994, by StrataCom Inc. The protocol robs two of the Generic Flow Control (GFC) bits contained in each cell transmitted over the 15 multiple T1/E1 links to implement a new transmission convergence (TC~ layer. Figure 3 shows the ATM cell structure which is defined in the ITU Recommendation. The TC layer is defined by one GFC bit for framing and the other one for link control. The framing bit is used to determine relative link delays while the link control bit is used for 20 communication, control and administration between two TC points at two ends of the inverse multiplexer.
In order to establish the sequence of cells over the links in a round robin manner, one end is defined as being "master" and the other as "slave". The "master" decides and informs the slave about the 25 multiple link configuration using the control channel implemented through the link control bits.
This protocol is only applicable, however, for UNI application points because GFC bits that are robbed to implement the TC layer are only present in a cell defined for UNI. For NNI cells, the 30 corresponding bits are no longer available since they are captured under the VPI field. Service providers are interested in ATM inverse multiplexers for carrying ATM traffic at rates higher than T1/E1 and lower than T3/E3, but this protocol will not satisfy their need. It should also be noted that the protocol calls for a need to identify a "master"
35 and a "slave" TC point and that requires an additional setting to be performed by the network operator.
Bit Pipe Inverse Multiplexin~
This protocol was presented in "Physical Layer Sub-Working Group ATM
Forum/94-0956, Inverse Multiplexing of ATM cells over low speed UNIs such as Tl and El", September 1994, by Digital Link Corporation. It proposes a "bit 5 pipe" inverse multiplexing technique requiring the definition of a "bonding"
(bandwidth on demand) like specification for N (positive number) Tl/El inverse multiplexing.
It is not clear in the proposal how both ends of the links exchange information concerning the order of cells to be transferred from one end to another 10 over multiple links. The proposal mentions the existence and deployment of physical layer protocols that perform inverse multiplexing. The inverse multiplexer which can be used in this proposal is presumably the one defined by Digital Link Corporation in their "DL3800 DS1 Inverse Multiplexer Users Manual, 1993".
The inverse multiplexing protocol defined in the above user's manual relies on the definition of an extra bit taken from T1/E1 payload bits to configure the multiple links and adjust differential link delays. This protocol introduces the need for extra processing of data between devices dealing with T1/E1 frames and ATM cell delineation. It also causes the ATM cells to no longer be byte aligned with the DS 1/E 1 frame. This is a requirement by the ATM Forum UNI DS 1/E l Physical Layer specifications. Changes like this would not be welcome by end users, vendors and service providers who are already using and deploying ATM
equipment.
U. S. Patent No. 5,608,733, Mar. 4, 1997, Vallee et al, describes good ways of obviating the above noted problems. The patent uses ATM sequence number cells indicating a specific round robin order of a plurality of transmission links over which ATM data cells are transmitted. The ATM sequence number cells also indicate whether or not a destination is ready to receive ATM data cells in that specific round robin order.
In WO-A-96/08120, Stratacom, Inc describes an ATM inverse multiplexed communication system in which a series of communication cells are multiplexed over a set of communication links. Each communication cell includes a framing bit of a predetermined framing bit stream for each communication link and a control channel bit of a message for each communication link. Inbound communication cells from each communication link are aligned according to the corresponding framing bit stream. The control message specifies an ordered list P~Tlended July 28, 1998 AME~IDED S~IEE~
CA 02263478 1999-02-lS
of logical identifiers to indicate a multiplexed sequence of transfer of the communication cells over the communication links.
In the techniques described thus far, there are problems which may be encountered when multiples inverse multiplexing transmissions are being performed. When more than one inverse multiplexing connection exists, it is possible that confusion may arise among groupings and identities of participating nodes. It is therefore important to identify transmission links as their far endnodes and their groupings. Prior art techniques do not address these problems.
The present invention extends further variety of functionalities which are 10 useful in inverse multiplexing.
Obiects of the Invention It is therefore an object of the invention to provide a method of and apparatus for testing connectivity of transmission links used for inverse 15 multiplexing cells of digital data.
It is a further object of the invention to provide a method of preserving link integrity by periodically testing connectivity of transmission links.
It is a further object of the invention to provide a method of handling link addition, deletion and link reconfiguration for the purpose of inverse multiplexing.
It is still a further object of the invention to provide a method of stuffing cells to accommodate non-synchronized links during an inverse multiplexing transmission .
Sumrnary of the Invention Briefly stated, in accordance with one aspect, the invention is directed to a method of testing connectivity of transmission links used for inverse multiplexing cells of digital data and comprises steps of identifying a group of transmissionlinks over which cells of digital data are inverse multiplexed and sending a series of inverse multiplexing control cells containing a test message over one 30 transmission link within the group. The method further includes steps of receiving a series of inverse multiplexing control cells containing received test messages over any transmission links and verifying the received test messages todetermine the connectivity of said one transmission link within the group.
According to another aspect, the invention is directed to an apparatus for 35 testing connectivity of transmission links used for inverse multiplexing cells of digital data. The apparatus comprises a control cell generator for setting an identifier of a group of transmission links over which cells of digital data are AME~
Amended July 28, 1998 CA 02263478 1999-02-1~
inverse multiplexed and a transmitter for s~nding a series of inverse multiplexing control cells containing a test message over one transmission link within the group. The apparatus further includes a reeeiver for receiving a series of inverse multiplexing control cells containing received test message over any transmission 5 links; and a message control device for verifying the received test message todetermine the connectivity of said one transmission link within the group.
Brief Description of the Drawin s For a more complete understanding of the invention and for further objects 10 and advantages thereof, reference may now be made to the following description, taken in conjunction with the accompanying drawings, in which:
Figure l shows a sample configuration involving AIM UNIs;
Figure 2 shows a sample configuration involving AIM BICIs or PNNIs;
Figure 3 depicts the ATM cell structure defined in the ITU
15 Recommendation;
Figure 4 is a schematic illustration of multiplexing and de-multiplexing of ATM cells over AIMs and links;
Figure 5 shows preassigned cell header values for use by the physical layer;
P~nended July 28, 1998 AME~ED S~EEr CA 02263478 1999-02-1~
Figure 6 shows a header pattern of an AIM OAM cell, according to one embodiment of the invention;
Figure 7 indicates allocation of OAM functions in the information field according to one embodiment of the invention;
Figure 8 is a schematic illustration of multiplexing and demultiplexing of AIM OAM cells according to one embodiment of the invention; and Figure 9 is a schematic illustration of periodic multiplexing and demultiplexing of AIM OAM cells during transmission of ATM data 10 cells according to one embodiment of the invention.
Figure 10 is an ICP cell format used for implementing embodiments of the invention.
Figure 11 shows a circumstance where node A may be using a group of three links to send data to node B and another group of two 15 links to send data to node C.
Figure 12 shows a typical sequence of cells on a three link group.
Figures 13a and 13b show an algorithmic flow chart for the start-up procedure according to one embodiment.
Figure 14 indicates how Figures 13a and 13b should be connected.
Figure 15 shows a configuration when links with Link ID=1 are added to groups with active Link ID=0 links.
Figure 16 shows the timing diagram of the test procedure of the inventi on .
Figure 17 illustrates looping of a test pattern at node B.
Figure 18 depicts diagramatically a scenario where the test pattern procedure can be used to detect a link that is not connected to the expected IMA.
Figure 19 shows cases (1,...,7) when the ICP cell preceding the stuff event and the stuff ICP cells are corrupted.
Detailed Description of Preferred Embodiments There are requirements that have to be considered when defining a new ATM inverse multiplexing protocol. These requirements are:
35 ~ It must multiplex and demultiplex an ATM cell stream distributed in a round robin manner over multiple links such as T1/E1 links.
CA 02263478 1999-02-1~
- W 098t08355 PCT/CA97/00610 ~ It must adjust up to 32 milliseconds of differential link delays between individual links in a case where T1/E1 links are used.
~ It must reconfigure multiple links in the event that a link has to be added, deleted or is considered inadequate to provide service.
5 ~ It must be defined for not only UNIs but also for PNNIs and BICIs.
~ ~ It must be transparent to the devices handling the convergence of ATM cells into the PDH signal.
~ It must be transparent to the devices dealing with ATM layer cells.
The present invention achieves all of the above requirements and solves the problems discussed earlier. The invention relates to a new ATM inverse multiplexing scheme that makes use of a physical layer operation administration and maintenance (OAM) cell which has been properly defined. This OAM cell is defined to contain valuable information to allow proper operation of the ATM inverse multiplexing mechanism and also to provide opportunity for handling a link failure situation.
The newly defined OAM cell is called an AIM OAM cell or AIM
Sequence Number (SN) cell and is mainly designed to carry a cell sequence number and a feedback link status field. The sequence number in the SN cell is made available for the receiver end for recovering the initial cell stream from the incoming links. The feedback link status is made available for the receiver to inform the transmitter, by sending its own SN cells, that it is receiving cells and it is also an integral part of the same round robin mechanism, that is to say, the feedback link status value SN cells in either direction must agree with each other, although the sequence numbers at both ends may be different. When the receiver sends its own SN cells in response to the transmitter that it is receiving cells, it is in fact acknowledging that the receiver is ready to receive subsequent ATM data cells.
Figure 4 shows how the ATM cells are multiplexed and then demultiplexed over AIMs in one direction. At the transmitting node, an AIM 10 takes a series of ATM cells from an ATM layer device. It spreads ATM cells and transmits each cell over each of N transmission links, N being a positive integer. The order of transmission is in round robin fashion. This process is called an inverse multiplexing. At the receiving node, cells from N links are inverse demultiplexed (assembled) and sent to an ATM layer device by an AIM 14. The same CA 02263478 1999-02-l~
- W098/08355 PCT/CA97/0~610 order must be employed at this node to recover a proper sequence of cells. Both nodes must be aware of the round robin order which is to be employed. Upon initialization, therefore, both AIMs send a series of SN cells in round robin fashion over the links, e.g. T1/E1 links. This allows the receiver AIM at both nodes to establish the sequence in which to read cells from the incoming links as well as to adjust relative link delay.
As mentioned above, the SN cell also carries an extra field used by each T1/E1 link to indicate that both AIMs belong to the same link 10 round robin. This information can then be used locally to determine if at the corresponding local node a link should be added, removed or maintained in the round robin.
When a change of link configuration occurs by a link being added, removed or declared as being down, each node sends a series of 15 SN cells to allow the far-end node to reestablish the sequence of cells to read from the incoming links.
The protocol of the invention calls for a physical layer OAM cell that is defined to be exclusively processed by the ATM inverse multiplexers. The new cell structure has to be consistent with the cell 20 structure defined in ITU Recommendation I.361. Figure 3 shows that structure of UNI/NNI ATM cells that is defined in I.361. ITU
Recommendations I.361 and I.432 state that ATM cells consisting of a header whose VPI and VCI fields are set to zero are reserved for use by the physical layer. So far three preassigned values of the cell header are 25 reserved for use by the physical layer. They are shown in Figure 5.
The physical layer OAM cell according to one embodiment of the invention is then defined by using a non-assigned value by setting the PT field to "111" or some such code. This is shown in Figure 6.
The AIM OAM cell payload is then available for exchanging 30 information between AIMs. The cell payload consists of a series of fields whose locations are shown in Figure 7.
The following fields are identified for the AIM protocol according to one embodiment of the invention:
~ ATM inverse multiplexing remote defect indicator (AIMRDI) - one octet is allocated and the proposed coding is all "1".
~ ATM inverse multiplexing far-end receiver ready (AIMFERR) - one octet is allocated and the proposed coding is all "1".
CA 02263478 1999-02-1~
~ ATM inverse multiplexing cell sequence number (AIMCSN) - it is defined to contain the sequence number of the cells sent over the multiple links handled by the ATM inverse multiplexers. It is designed so as to have a sufficiently large cycle to allow the ATM
inverse multiplexer to absorb link delays of up to 32 milliseconds.
There are 16 bits allocated to the AIMCSN field. The counting is then done modulo 65536.
~ Cell error control (CEC) - is used to detect errors in the cell payload.
It is proposed to CRC-10 as proposed in ITU Recommendation I.432.
~ Reserve field (R) - contains the octet pattern of "01101010", which is the same as that of the idle cell as proposed in ITU Recommendation I.361.
Referring to Figure 8, the ATM inverse multiplexing protocol according to one embodiment is described in detail below. The figure 15 only shows one direction for clarity. It is shown that transmission links are all T1/E1 links but, of course, links can have a different speed from T1/E1, as long as all the links have the same speed. A
transmitting node 20 collects digital data consisting of a series of ATM
data cells from the ATM layer. An ATM inverse multiplexer (AIM) at 20 the transmitting node spreads over multiple links 24 for transmission to a receiving node 26. An AIM at the receiving node reassembles ATM data cells received from the links in proper order and sends them to the ATM layer.
25 Link Start-up Upon connection start-up, AIMs at both nodes start inserting AIM OAM cells (AIM SN cells) carrying cell sequence number over the available links in round robin fashion. The sequencing of cells is based on the order in which cells have to be transmitted on the virtual link 30 (composed of N physical links). However, the sequence number is only carried over the SN cells. This sequence number assignment allows the receiving AIM to retrieve the original cell sequence. The receiving node queues the received AIM SN cells until it determines the sequence in which to read the ATM data cells from the incoming links 35 as well as the differential delay among individual links. Then, it starts sending AIM SN cells of its own, with the AIMFERR field set to "one"
for each link which is now considered "ready" to receive ATM traffic.
CA 02263478 1999-02-1~
From that moment, the receiving node knows the sequence of cells coming from the links. A link is being considered available if cells are currently delineated and AIM-RDI is not received on the incoming link.
When the transmitting node starts sending the AIM SN cells, it starts a time-out of 100 milliseconds within which the receiving node determines the sequence of AIM SN cells which it is receiving from the links. The time-out expires unless the transmitting node receives the "ready" signal from all the links which were considered available at the initialization.
If there is no "ready" link when the time-out expires, the local node reevaluates the availability of the links (using cell delineation), starts sending AIM SN cells over the available links and re-starts the time-out. This procedure is repeated until at least one available link is declared ready.
When the time-out has been cancelled due to the reception of the "ready" signal from all the available links, or when there is at least one link ready when the time-out expires, the local end starts sending ATM layer cells over the "ready" link or links using the same round robin order used at the time of initialization.
Each ATM layer cell gets a sequence number assigned to it, but only the AIM SN cells carry that number across the links. After both nodes have started sending ATM layer cells, they periodically send a series of "n" AIM SN cells over links to allow the receiving node to readjust the differential delays among the links. The value of "n" is equal to the number of "ready" links used to carry ATM layer cells.
This means that the receiving node always scans for AIM SN cells in order to determine if it is always reading cells from the multiple links in the correct order. How often a burst of "n" AIM SN cells is sent depends upon the link utilization but the maximum period has been set to 50 milliseconds in one embodiment. An example of cells sent over a virtual link composed of a plurality of transmission links is shown in Figure 9.
Link Reconfiguration As mentioned above, the protocol according to the invention CA 02263478 1999-02-1~
- W O 98/083S~ PCT/CA97/00610 also deals with link reconfiguration. There are three possible cases in which reconfiguration can occur:
~ a new link has to be added to the round robin;
~ a link has to be intentionally removed from the round robin; and 5 ~ a link has been declared inadequate to provide service (e.g. link down by failure etc.).
In the first two cases, a node starts link reconfiguration by performing the same initialization process for a connection start-up, that is to say, it chooses a round robin order among the links and starts 10 sending AIM SN cells using the chosen round robin order. The receiving node, seeing the occurrence of AIM SN cells, will stop transmitting traffic and starts sending AIM SN cells of its own while adjusting itself to receive traffic from the incoming links. The rest of the protocol is as described earlier for start-up.
Two possible cases for reporting failure conditions are:
1) A medium problem reported through Loss of Delineation (LCD) failure condition. In this case, the corresponding link should not be used for service. When detecting LCD, SN cells with AIMRDI set to "1" should be sent over the corresponding outgoing link. SN cells 20 containing AIM-RDI do not carry a valid sequence number. At the far-end, the detection of AIM-RDI signals will indicate that the link is not to be used. Therefore, if LCD or AIM-RDI is detected, the link is no longer considered available and won't be allowed to be part of the round robin on both sides. When this has happens, SN cells are re-sent 25 over the remaining links to re-establish the connection between the two ends.
IN VERSE M ULTIPLEXIN G OF DIGITAL D ATA
Field of the Invention The invention relates to a new mechanism for sending ATM
5 cells transparently over multiple slower transmission links. In particular, the invention is directed to a method of inverse multiplexing of a series of ATM cells transparently over N
transmission links (N being a positive integer) of slower speed.
10 Background of the Invention It has been recognized that the T1/E1 rate (1.544/2.048 Mbit/s) is a cost effective way of user access to an ATM network as well as connection between ATM network switches. However, as ATM
technology for wide area networks is deployed more and more, 15 demands for transmission links of a rate higher than T1/E1 are increasing. Links of higher rates, such as T3/E3 (44.736/34.368 Mbit/s), have been designed to meet these needs. However, the cost of T3/E3 links is still prohibitive in many cases and the ratio of cost versus realistic utilization of the entire rate is not always attractive and fully 20 justified for new ATM end users and service providers. ATM inverse multiplexers (AIMs) have been proposed to satisfy the need by using multiple T1/E1 links which are grouped collectively to provide the service at a higher rate.
Figure 1 and Figure 2 show two sample configurations in which 25 AIMs are used. Figure 1 depicts a user access to a network through user network interfaces (UNIs) and Figure 2 a link connection between ATM switches through broadband inter-carrier interfaces (BICIs) or private network to network interfaces (PNNIs).
Referring to the figures, the basic function of AIMs is to work in 30 pairs to take an ATM cell stream coming from the ATM layer, send it over the multiple links by spreading cells over the available links and ensure that the initial cell stream can be retrieved at the far end. Thus the AIMs preferably make the ATM traffic transparent to the ATM
layer over multiple links which connect them. As far as the ATM layer 35 is concerned, it should only see a pipe whose rate is now the sum of the multiple link rates. It is assumed that each link is run in clear-mode without the presence of intermediate ATM nodes processing ATM
..... . . ... .. ...
CA 02263478 1999-02-l~
cells. This means that there should be no cell discard by any intermediate transmission equipment.
Currently no ATM inverse multiplexing protocols have been proposed which can properly interwork existing ATM inverse 5 multiplexers or other ATM products which are already available on the market, and yet are flexible enough to fit into the current standard ATM specifications. Two proposals for an ATM inverse multiplexing protocol have so far been made and are described in detail below.
10 New Transmission Convergence Protocol Using GFC Bits This protocol was presented in "Physical Layer Sub-Working Group ATM Forum/94-0775, ATM Inverse Multiplexing Mechanism", September 1994, by StrataCom Inc. The protocol robs two of the Generic Flow Control (GFC) bits contained in each cell transmitted over the 15 multiple T1/E1 links to implement a new transmission convergence (TC~ layer. Figure 3 shows the ATM cell structure which is defined in the ITU Recommendation. The TC layer is defined by one GFC bit for framing and the other one for link control. The framing bit is used to determine relative link delays while the link control bit is used for 20 communication, control and administration between two TC points at two ends of the inverse multiplexer.
In order to establish the sequence of cells over the links in a round robin manner, one end is defined as being "master" and the other as "slave". The "master" decides and informs the slave about the 25 multiple link configuration using the control channel implemented through the link control bits.
This protocol is only applicable, however, for UNI application points because GFC bits that are robbed to implement the TC layer are only present in a cell defined for UNI. For NNI cells, the 30 corresponding bits are no longer available since they are captured under the VPI field. Service providers are interested in ATM inverse multiplexers for carrying ATM traffic at rates higher than T1/E1 and lower than T3/E3, but this protocol will not satisfy their need. It should also be noted that the protocol calls for a need to identify a "master"
35 and a "slave" TC point and that requires an additional setting to be performed by the network operator.
Bit Pipe Inverse Multiplexin~
This protocol was presented in "Physical Layer Sub-Working Group ATM
Forum/94-0956, Inverse Multiplexing of ATM cells over low speed UNIs such as Tl and El", September 1994, by Digital Link Corporation. It proposes a "bit 5 pipe" inverse multiplexing technique requiring the definition of a "bonding"
(bandwidth on demand) like specification for N (positive number) Tl/El inverse multiplexing.
It is not clear in the proposal how both ends of the links exchange information concerning the order of cells to be transferred from one end to another 10 over multiple links. The proposal mentions the existence and deployment of physical layer protocols that perform inverse multiplexing. The inverse multiplexer which can be used in this proposal is presumably the one defined by Digital Link Corporation in their "DL3800 DS1 Inverse Multiplexer Users Manual, 1993".
The inverse multiplexing protocol defined in the above user's manual relies on the definition of an extra bit taken from T1/E1 payload bits to configure the multiple links and adjust differential link delays. This protocol introduces the need for extra processing of data between devices dealing with T1/E1 frames and ATM cell delineation. It also causes the ATM cells to no longer be byte aligned with the DS 1/E 1 frame. This is a requirement by the ATM Forum UNI DS 1/E l Physical Layer specifications. Changes like this would not be welcome by end users, vendors and service providers who are already using and deploying ATM
equipment.
U. S. Patent No. 5,608,733, Mar. 4, 1997, Vallee et al, describes good ways of obviating the above noted problems. The patent uses ATM sequence number cells indicating a specific round robin order of a plurality of transmission links over which ATM data cells are transmitted. The ATM sequence number cells also indicate whether or not a destination is ready to receive ATM data cells in that specific round robin order.
In WO-A-96/08120, Stratacom, Inc describes an ATM inverse multiplexed communication system in which a series of communication cells are multiplexed over a set of communication links. Each communication cell includes a framing bit of a predetermined framing bit stream for each communication link and a control channel bit of a message for each communication link. Inbound communication cells from each communication link are aligned according to the corresponding framing bit stream. The control message specifies an ordered list P~Tlended July 28, 1998 AME~IDED S~IEE~
CA 02263478 1999-02-lS
of logical identifiers to indicate a multiplexed sequence of transfer of the communication cells over the communication links.
In the techniques described thus far, there are problems which may be encountered when multiples inverse multiplexing transmissions are being performed. When more than one inverse multiplexing connection exists, it is possible that confusion may arise among groupings and identities of participating nodes. It is therefore important to identify transmission links as their far endnodes and their groupings. Prior art techniques do not address these problems.
The present invention extends further variety of functionalities which are 10 useful in inverse multiplexing.
Obiects of the Invention It is therefore an object of the invention to provide a method of and apparatus for testing connectivity of transmission links used for inverse 15 multiplexing cells of digital data.
It is a further object of the invention to provide a method of preserving link integrity by periodically testing connectivity of transmission links.
It is a further object of the invention to provide a method of handling link addition, deletion and link reconfiguration for the purpose of inverse multiplexing.
It is still a further object of the invention to provide a method of stuffing cells to accommodate non-synchronized links during an inverse multiplexing transmission .
Sumrnary of the Invention Briefly stated, in accordance with one aspect, the invention is directed to a method of testing connectivity of transmission links used for inverse multiplexing cells of digital data and comprises steps of identifying a group of transmissionlinks over which cells of digital data are inverse multiplexed and sending a series of inverse multiplexing control cells containing a test message over one 30 transmission link within the group. The method further includes steps of receiving a series of inverse multiplexing control cells containing received test messages over any transmission links and verifying the received test messages todetermine the connectivity of said one transmission link within the group.
According to another aspect, the invention is directed to an apparatus for 35 testing connectivity of transmission links used for inverse multiplexing cells of digital data. The apparatus comprises a control cell generator for setting an identifier of a group of transmission links over which cells of digital data are AME~
Amended July 28, 1998 CA 02263478 1999-02-1~
inverse multiplexed and a transmitter for s~nding a series of inverse multiplexing control cells containing a test message over one transmission link within the group. The apparatus further includes a reeeiver for receiving a series of inverse multiplexing control cells containing received test message over any transmission 5 links; and a message control device for verifying the received test message todetermine the connectivity of said one transmission link within the group.
Brief Description of the Drawin s For a more complete understanding of the invention and for further objects 10 and advantages thereof, reference may now be made to the following description, taken in conjunction with the accompanying drawings, in which:
Figure l shows a sample configuration involving AIM UNIs;
Figure 2 shows a sample configuration involving AIM BICIs or PNNIs;
Figure 3 depicts the ATM cell structure defined in the ITU
15 Recommendation;
Figure 4 is a schematic illustration of multiplexing and de-multiplexing of ATM cells over AIMs and links;
Figure 5 shows preassigned cell header values for use by the physical layer;
P~nended July 28, 1998 AME~ED S~EEr CA 02263478 1999-02-1~
Figure 6 shows a header pattern of an AIM OAM cell, according to one embodiment of the invention;
Figure 7 indicates allocation of OAM functions in the information field according to one embodiment of the invention;
Figure 8 is a schematic illustration of multiplexing and demultiplexing of AIM OAM cells according to one embodiment of the invention; and Figure 9 is a schematic illustration of periodic multiplexing and demultiplexing of AIM OAM cells during transmission of ATM data 10 cells according to one embodiment of the invention.
Figure 10 is an ICP cell format used for implementing embodiments of the invention.
Figure 11 shows a circumstance where node A may be using a group of three links to send data to node B and another group of two 15 links to send data to node C.
Figure 12 shows a typical sequence of cells on a three link group.
Figures 13a and 13b show an algorithmic flow chart for the start-up procedure according to one embodiment.
Figure 14 indicates how Figures 13a and 13b should be connected.
Figure 15 shows a configuration when links with Link ID=1 are added to groups with active Link ID=0 links.
Figure 16 shows the timing diagram of the test procedure of the inventi on .
Figure 17 illustrates looping of a test pattern at node B.
Figure 18 depicts diagramatically a scenario where the test pattern procedure can be used to detect a link that is not connected to the expected IMA.
Figure 19 shows cases (1,...,7) when the ICP cell preceding the stuff event and the stuff ICP cells are corrupted.
Detailed Description of Preferred Embodiments There are requirements that have to be considered when defining a new ATM inverse multiplexing protocol. These requirements are:
35 ~ It must multiplex and demultiplex an ATM cell stream distributed in a round robin manner over multiple links such as T1/E1 links.
CA 02263478 1999-02-1~
- W 098t08355 PCT/CA97/00610 ~ It must adjust up to 32 milliseconds of differential link delays between individual links in a case where T1/E1 links are used.
~ It must reconfigure multiple links in the event that a link has to be added, deleted or is considered inadequate to provide service.
5 ~ It must be defined for not only UNIs but also for PNNIs and BICIs.
~ ~ It must be transparent to the devices handling the convergence of ATM cells into the PDH signal.
~ It must be transparent to the devices dealing with ATM layer cells.
The present invention achieves all of the above requirements and solves the problems discussed earlier. The invention relates to a new ATM inverse multiplexing scheme that makes use of a physical layer operation administration and maintenance (OAM) cell which has been properly defined. This OAM cell is defined to contain valuable information to allow proper operation of the ATM inverse multiplexing mechanism and also to provide opportunity for handling a link failure situation.
The newly defined OAM cell is called an AIM OAM cell or AIM
Sequence Number (SN) cell and is mainly designed to carry a cell sequence number and a feedback link status field. The sequence number in the SN cell is made available for the receiver end for recovering the initial cell stream from the incoming links. The feedback link status is made available for the receiver to inform the transmitter, by sending its own SN cells, that it is receiving cells and it is also an integral part of the same round robin mechanism, that is to say, the feedback link status value SN cells in either direction must agree with each other, although the sequence numbers at both ends may be different. When the receiver sends its own SN cells in response to the transmitter that it is receiving cells, it is in fact acknowledging that the receiver is ready to receive subsequent ATM data cells.
Figure 4 shows how the ATM cells are multiplexed and then demultiplexed over AIMs in one direction. At the transmitting node, an AIM 10 takes a series of ATM cells from an ATM layer device. It spreads ATM cells and transmits each cell over each of N transmission links, N being a positive integer. The order of transmission is in round robin fashion. This process is called an inverse multiplexing. At the receiving node, cells from N links are inverse demultiplexed (assembled) and sent to an ATM layer device by an AIM 14. The same CA 02263478 1999-02-l~
- W098/08355 PCT/CA97/0~610 order must be employed at this node to recover a proper sequence of cells. Both nodes must be aware of the round robin order which is to be employed. Upon initialization, therefore, both AIMs send a series of SN cells in round robin fashion over the links, e.g. T1/E1 links. This allows the receiver AIM at both nodes to establish the sequence in which to read cells from the incoming links as well as to adjust relative link delay.
As mentioned above, the SN cell also carries an extra field used by each T1/E1 link to indicate that both AIMs belong to the same link 10 round robin. This information can then be used locally to determine if at the corresponding local node a link should be added, removed or maintained in the round robin.
When a change of link configuration occurs by a link being added, removed or declared as being down, each node sends a series of 15 SN cells to allow the far-end node to reestablish the sequence of cells to read from the incoming links.
The protocol of the invention calls for a physical layer OAM cell that is defined to be exclusively processed by the ATM inverse multiplexers. The new cell structure has to be consistent with the cell 20 structure defined in ITU Recommendation I.361. Figure 3 shows that structure of UNI/NNI ATM cells that is defined in I.361. ITU
Recommendations I.361 and I.432 state that ATM cells consisting of a header whose VPI and VCI fields are set to zero are reserved for use by the physical layer. So far three preassigned values of the cell header are 25 reserved for use by the physical layer. They are shown in Figure 5.
The physical layer OAM cell according to one embodiment of the invention is then defined by using a non-assigned value by setting the PT field to "111" or some such code. This is shown in Figure 6.
The AIM OAM cell payload is then available for exchanging 30 information between AIMs. The cell payload consists of a series of fields whose locations are shown in Figure 7.
The following fields are identified for the AIM protocol according to one embodiment of the invention:
~ ATM inverse multiplexing remote defect indicator (AIMRDI) - one octet is allocated and the proposed coding is all "1".
~ ATM inverse multiplexing far-end receiver ready (AIMFERR) - one octet is allocated and the proposed coding is all "1".
CA 02263478 1999-02-1~
~ ATM inverse multiplexing cell sequence number (AIMCSN) - it is defined to contain the sequence number of the cells sent over the multiple links handled by the ATM inverse multiplexers. It is designed so as to have a sufficiently large cycle to allow the ATM
inverse multiplexer to absorb link delays of up to 32 milliseconds.
There are 16 bits allocated to the AIMCSN field. The counting is then done modulo 65536.
~ Cell error control (CEC) - is used to detect errors in the cell payload.
It is proposed to CRC-10 as proposed in ITU Recommendation I.432.
~ Reserve field (R) - contains the octet pattern of "01101010", which is the same as that of the idle cell as proposed in ITU Recommendation I.361.
Referring to Figure 8, the ATM inverse multiplexing protocol according to one embodiment is described in detail below. The figure 15 only shows one direction for clarity. It is shown that transmission links are all T1/E1 links but, of course, links can have a different speed from T1/E1, as long as all the links have the same speed. A
transmitting node 20 collects digital data consisting of a series of ATM
data cells from the ATM layer. An ATM inverse multiplexer (AIM) at 20 the transmitting node spreads over multiple links 24 for transmission to a receiving node 26. An AIM at the receiving node reassembles ATM data cells received from the links in proper order and sends them to the ATM layer.
25 Link Start-up Upon connection start-up, AIMs at both nodes start inserting AIM OAM cells (AIM SN cells) carrying cell sequence number over the available links in round robin fashion. The sequencing of cells is based on the order in which cells have to be transmitted on the virtual link 30 (composed of N physical links). However, the sequence number is only carried over the SN cells. This sequence number assignment allows the receiving AIM to retrieve the original cell sequence. The receiving node queues the received AIM SN cells until it determines the sequence in which to read the ATM data cells from the incoming links 35 as well as the differential delay among individual links. Then, it starts sending AIM SN cells of its own, with the AIMFERR field set to "one"
for each link which is now considered "ready" to receive ATM traffic.
CA 02263478 1999-02-1~
From that moment, the receiving node knows the sequence of cells coming from the links. A link is being considered available if cells are currently delineated and AIM-RDI is not received on the incoming link.
When the transmitting node starts sending the AIM SN cells, it starts a time-out of 100 milliseconds within which the receiving node determines the sequence of AIM SN cells which it is receiving from the links. The time-out expires unless the transmitting node receives the "ready" signal from all the links which were considered available at the initialization.
If there is no "ready" link when the time-out expires, the local node reevaluates the availability of the links (using cell delineation), starts sending AIM SN cells over the available links and re-starts the time-out. This procedure is repeated until at least one available link is declared ready.
When the time-out has been cancelled due to the reception of the "ready" signal from all the available links, or when there is at least one link ready when the time-out expires, the local end starts sending ATM layer cells over the "ready" link or links using the same round robin order used at the time of initialization.
Each ATM layer cell gets a sequence number assigned to it, but only the AIM SN cells carry that number across the links. After both nodes have started sending ATM layer cells, they periodically send a series of "n" AIM SN cells over links to allow the receiving node to readjust the differential delays among the links. The value of "n" is equal to the number of "ready" links used to carry ATM layer cells.
This means that the receiving node always scans for AIM SN cells in order to determine if it is always reading cells from the multiple links in the correct order. How often a burst of "n" AIM SN cells is sent depends upon the link utilization but the maximum period has been set to 50 milliseconds in one embodiment. An example of cells sent over a virtual link composed of a plurality of transmission links is shown in Figure 9.
Link Reconfiguration As mentioned above, the protocol according to the invention CA 02263478 1999-02-1~
- W O 98/083S~ PCT/CA97/00610 also deals with link reconfiguration. There are three possible cases in which reconfiguration can occur:
~ a new link has to be added to the round robin;
~ a link has to be intentionally removed from the round robin; and 5 ~ a link has been declared inadequate to provide service (e.g. link down by failure etc.).
In the first two cases, a node starts link reconfiguration by performing the same initialization process for a connection start-up, that is to say, it chooses a round robin order among the links and starts 10 sending AIM SN cells using the chosen round robin order. The receiving node, seeing the occurrence of AIM SN cells, will stop transmitting traffic and starts sending AIM SN cells of its own while adjusting itself to receive traffic from the incoming links. The rest of the protocol is as described earlier for start-up.
Two possible cases for reporting failure conditions are:
1) A medium problem reported through Loss of Delineation (LCD) failure condition. In this case, the corresponding link should not be used for service. When detecting LCD, SN cells with AIMRDI set to "1" should be sent over the corresponding outgoing link. SN cells 20 containing AIM-RDI do not carry a valid sequence number. At the far-end, the detection of AIM-RDI signals will indicate that the link is not to be used. Therefore, if LCD or AIM-RDI is detected, the link is no longer considered available and won't be allowed to be part of the round robin on both sides. When this has happens, SN cells are re-sent 25 over the remaining links to re-establish the connection between the two ends.
2) Cells are lost without an LCD or AIM-RDI being reported. For instance, this would occur when a few cells are discarded by the physical layer device due to bit errors in cell headers. This would cause 30 the cell sequencing to be affected. One symptom would be the detection of SN cells whose number is no longer the same as that expected (since one or more of the previous cells are missing). In this case, the problem might be partially corrected by re-adjusting the receiver buffering system (assuming the difference between the SN cell number 35 and the expected number is small). The other symptom would be the absence of a SN cell on one link when getting a burst of SN cells on all the other links. In that case, the local end would have to force the links CA 02263478 1999-02-1~
- W 098t08355 PCT/CA97/00610 to be re-configured. If the symptoms described above reoccur over a given period, the bad link may have to be removed from the round robin.
A link reconfiguration also occurs when it takes too much time for one link to receive cells from the far-end (receiving) node, that is to say, no cells within, e.g., 32 milliseconds.
Cell Sequence Number Range Because an ATM inverse multiplexer must absorb a differential delay between individual links of up to 32 milliseconds in one embodiment, and because the system needs to deal with a maximum of 8 T1/E1 links, it is necessary to have a sequence number whose modulo is large enough to accommodate such delay.
As a practical example, the following parameters for E1 are considered:
~ full rates: 2.048 Mbit/s ~ payloadrates: 30/32~2.048Mbit/s=1.92Mbps ~ ATM cell: 53 bytes ~ ATM cell period time: 221 microseconds ~ ATM cells/32 milliseconds = 144 cells.
For a delay of up to 32 milliseconds on each link, there is a need to queue cells for at least the same length of time on each link.
Therefore, in this example, this means that a delay of up to a period of 144 cells between two links is possible. An ATM inverse multiplexer can handle a maximum of 8 T1/E1 links. Therefore up to 1008 cells (144~7 cells) must be queued at one time by one ATM inverse multiplexer. This requires a sequence number modulo large enough to cover this scenario. A simple case in one embodiment is to use a 16-bit count that has modulo 65536.
The ATM inverse multiplexing protocol according to the invention realizes the following characteristics:
~ it is applicable to UNIs, BICIs and PNNIs (any applicable points in an ATM network);
~ it does not affect the ATM cell header of currently defined cells;
~ it does not require a change to current ATM physical layer devices dealing with the convergence of ATM cells into T1/E1;
~ it operates transparently to the ATM layer;
CA 02263478 1999-02-l~
~ it does not require a change to current devices dealing with the processing of the ATM layer cell;
~ it is self-configuring among available links upon start-up and self-reconfiguring among the multiple links in the case when a new link has to be added, deleted or considered inadequate to provide servlce; and ~ it includes a sequence number whose modulo is large enough to meet the requirement of a large differential delay among the links.
According to an embodiment of the present invention, special Inverse mux Controller Processor (ICP) cells are created. The ICP cell format is shown in Figure 10. In this embodiment, ATM cells are transmitted over an N number of links, N being a positive integer.
Cell ID is set for ICP cell and Link ID identifies links being used. As seen in Figure 11, a node A may be using a group of three links to send data to node B and another group of two links to send data to node C.
Nodes A and B form one IMA group and nodes A and C form another.
IMA groups are identified by IMA ID (Tx and Rx IMA ID). ATM cells on each link are grouped in a certain number (e.g., M) of cells to form IMA frames which belong to substantially same time scale. An IMA
frame sequence number field counts cells in each group. Figure 12 shows a typical sequence of cells on a three link group. One ICP cell is sent at a set location in each group for each link. M can be any number, for example 32, 64,128 and 256. In the figure, on link 0, the ICP cells have their cell offset set to zero (i.e., they are the first cell in the IMA
frame). On link 1, the ICP cells have the ICP cell offset set to 3 and on link 2, the ICP cells have their ICP cell offset set to 1. In practice, these ICP cells should be distributed even more over the IMA frame but are shown closer for ease of illustration. The ICP cell also includes fields concerning with stuffing action and test control action, both of which will be described in detail below.
A status and control change indication field is used to indicate an update of the link status field value. The value is incremented to indicate a change on at least one of the link status fields. The field is also used as a tag to differentiate link status changes over time. The field will always remain set to the same value as long as there will be no change on any link status fields. If one or more link status fields CA 02263478 1999-02-1~
need to be modified, ICP cells with new link status values incremented will be sent over all the links.
A group status and control field is used to indicate status of the group of links at a connection start-up, link addition and abort procedures. In particular, the start-up procedure would become complicated if one of the links does not meet all the criteria to be part of the group (e.g. link cleared of defects, corresponding incoming/outgoing links in loss of delay synchronization). This requires intervention of the operator to remove the bad link(s) from the link group. Figures 13a and 13b as combined in the way shown in Figure 14 show an algorithmic flow chart for the start-up procedure according to one embodiment. Instead of requiring all N number of links in the group being good before starting up, the procedure of the invention proceeds as long as there is at least P out of N "good" link available for service. A good link is defined as a link that is not exhibiting link and loss-of-frame defects, recognized as being part of the group, and having an acceptable link differential delay. The value of P
could be any number less than N. The figure also shows cases where the group start-up is aborted and later resumed.
The ICP format also includes a field for link's connectivity testing at the time of start-up, link addition or link re-activation. In particular, a protocol must always ensure proper connectivity of the links which belong to a group. For example, Figure 15 shows when links with Link ID=1 are added to groups with active Link ID=0 links.
Two new links (Link ID=1 links) are inversely connected with respect to the expected configuration. The difficulty is then that both Link ID
and IMA ID are the same for two independent IMAs. This can cause an invalid configuration which will not be detected. This kind of problem can occur at a start-up, link addition or even at a link re-activation. For example, it is possible to reactivate a link which has exhibited a link failure since it has been accidentally inverted with another link vvith or without the same Link ID and IMA ID. IMA ID is also used to detect loopback situations. This problem occurs when both end nodes of the IMA virtual link wants to use the same IMA ID. The invention addresses this problem also.
According to a further embodiment, the above problems are solved by sending a test pattern contained in ICP cells over a link to be CA 02263478 1999-02-1~
- W O g8/08355 PCT/CA97/00610 validated. The test pattern will be looped back over all the other links in the group at the far end node. This ensures that the tested link is connected to the same end node as the other links.
When one IMA node wants to determine if one or more links are connected to the same far end IMA node, it selects one link for testing. Figure 16 shows the timing diagram of the test procedure of the invention. The transmit node sets the Tx Test control field for link test in an ICP cell. It identifies Link ID, Tx IMA ID, Rx IMA ID and inserts Test Pattern in the cell. It continues to send same ICPs. The receive end node receives the ICPs and copies Tx Test Pattern onto Rx Test Pattern. It keeps sending same test pattern copied on Rx Test Pattern field over its all outgoing links. Figure 17 illustrates looping of a test pattern at node B. The transmit node receives and verifies Rx Test Pattern returned over the other links. It now knows that all the links which belong to the same IMA group.
Figure 18 depicts diagramatically a scenario where the test pattern procedure can be used to detect a link that is not connected to the expected IMA. Links identified as Link ID=1 are being added to existing groups using links with Link ID=0. Link 30 carries the IMA B
Test Pattern to looped back by IMA A and links 32 and 34 carry the IMA
D Test Pattern to be looped back to IMA B. In this case, the wrong test pattern will be received by IMA B. If IMA B was not commanding a Test Pattern loopback, IMA B would simply not receive the right test pattern.
The Test Pattern procedure also allows to deal with some pathological cases. One of them is when two IMA connected to the same far end I~A node are trying to start-up at the same time. The far end (receive end) node will have to determine which set of links (corresponding to one end) it wants to be connected to. This will require the received end to select the link(s) to be part of the group. as mentioned above, the receive end shall only respond to one Test Pattern command at a time that has been validated over one or more links that are or likely to be recognized as part of the group.
In accordance with a further embodiment, a stuff cell is inserted to control cell rate decoupling between the links, in order to accommodate the use of links non-synchronized to each other within the link groups. The transmitting node may be locked to one clock CA 02263478 1999-02-1~
source or may be plesiochronous. When plesiochronous, one of the buffers at the transmitting node may be depleted. To prevent underrun, the cell stuffing procedure is invoked. When there is one clock source, the buffer will never deplete. The transmitting node send 5 ICP cells which indicate a cell is stuffed at a certain location within the IMA frame. Any cell can be used for stuffing as long as the location is indicated so that the receiving node can remove it. In actual embodiment, the transmitting node repeats the ICP cell containing the stuff code indicating that "this cell is 1 out of 2 stuff cells". The 10 receiving node uses the stuff indications over the ICP cells to determine when to remove stuff cells from the incoming cell stream.
The receiving node relies on at least one ICP cell with a correct CRC-10.
A more robust approach is to look for a majority of valid codes.
Figure 19 shows cases (1,...,7) when the ICP cell preceding the 15 stuff event and the stuff ICP cells are corrupted. Corrupted cells are indicated by crosses in the figure. SICP indicate stuffing control cells.
The receiving node maintains synchronization for cases 1, 2, and 3.
The receiving node optionally maintain synchronization for cases 4, 5, and 6. the receiving node optionally maintain synchronization for case 20 7 if b>2 and when passing stuff indication over more than one of the previous ICP cells. "b" is the number of invalid/corrupted ICP cells before declaring the link OIF (out-of-IMA frame).
- W 098t08355 PCT/CA97/00610 to be re-configured. If the symptoms described above reoccur over a given period, the bad link may have to be removed from the round robin.
A link reconfiguration also occurs when it takes too much time for one link to receive cells from the far-end (receiving) node, that is to say, no cells within, e.g., 32 milliseconds.
Cell Sequence Number Range Because an ATM inverse multiplexer must absorb a differential delay between individual links of up to 32 milliseconds in one embodiment, and because the system needs to deal with a maximum of 8 T1/E1 links, it is necessary to have a sequence number whose modulo is large enough to accommodate such delay.
As a practical example, the following parameters for E1 are considered:
~ full rates: 2.048 Mbit/s ~ payloadrates: 30/32~2.048Mbit/s=1.92Mbps ~ ATM cell: 53 bytes ~ ATM cell period time: 221 microseconds ~ ATM cells/32 milliseconds = 144 cells.
For a delay of up to 32 milliseconds on each link, there is a need to queue cells for at least the same length of time on each link.
Therefore, in this example, this means that a delay of up to a period of 144 cells between two links is possible. An ATM inverse multiplexer can handle a maximum of 8 T1/E1 links. Therefore up to 1008 cells (144~7 cells) must be queued at one time by one ATM inverse multiplexer. This requires a sequence number modulo large enough to cover this scenario. A simple case in one embodiment is to use a 16-bit count that has modulo 65536.
The ATM inverse multiplexing protocol according to the invention realizes the following characteristics:
~ it is applicable to UNIs, BICIs and PNNIs (any applicable points in an ATM network);
~ it does not affect the ATM cell header of currently defined cells;
~ it does not require a change to current ATM physical layer devices dealing with the convergence of ATM cells into T1/E1;
~ it operates transparently to the ATM layer;
CA 02263478 1999-02-l~
~ it does not require a change to current devices dealing with the processing of the ATM layer cell;
~ it is self-configuring among available links upon start-up and self-reconfiguring among the multiple links in the case when a new link has to be added, deleted or considered inadequate to provide servlce; and ~ it includes a sequence number whose modulo is large enough to meet the requirement of a large differential delay among the links.
According to an embodiment of the present invention, special Inverse mux Controller Processor (ICP) cells are created. The ICP cell format is shown in Figure 10. In this embodiment, ATM cells are transmitted over an N number of links, N being a positive integer.
Cell ID is set for ICP cell and Link ID identifies links being used. As seen in Figure 11, a node A may be using a group of three links to send data to node B and another group of two links to send data to node C.
Nodes A and B form one IMA group and nodes A and C form another.
IMA groups are identified by IMA ID (Tx and Rx IMA ID). ATM cells on each link are grouped in a certain number (e.g., M) of cells to form IMA frames which belong to substantially same time scale. An IMA
frame sequence number field counts cells in each group. Figure 12 shows a typical sequence of cells on a three link group. One ICP cell is sent at a set location in each group for each link. M can be any number, for example 32, 64,128 and 256. In the figure, on link 0, the ICP cells have their cell offset set to zero (i.e., they are the first cell in the IMA
frame). On link 1, the ICP cells have the ICP cell offset set to 3 and on link 2, the ICP cells have their ICP cell offset set to 1. In practice, these ICP cells should be distributed even more over the IMA frame but are shown closer for ease of illustration. The ICP cell also includes fields concerning with stuffing action and test control action, both of which will be described in detail below.
A status and control change indication field is used to indicate an update of the link status field value. The value is incremented to indicate a change on at least one of the link status fields. The field is also used as a tag to differentiate link status changes over time. The field will always remain set to the same value as long as there will be no change on any link status fields. If one or more link status fields CA 02263478 1999-02-1~
need to be modified, ICP cells with new link status values incremented will be sent over all the links.
A group status and control field is used to indicate status of the group of links at a connection start-up, link addition and abort procedures. In particular, the start-up procedure would become complicated if one of the links does not meet all the criteria to be part of the group (e.g. link cleared of defects, corresponding incoming/outgoing links in loss of delay synchronization). This requires intervention of the operator to remove the bad link(s) from the link group. Figures 13a and 13b as combined in the way shown in Figure 14 show an algorithmic flow chart for the start-up procedure according to one embodiment. Instead of requiring all N number of links in the group being good before starting up, the procedure of the invention proceeds as long as there is at least P out of N "good" link available for service. A good link is defined as a link that is not exhibiting link and loss-of-frame defects, recognized as being part of the group, and having an acceptable link differential delay. The value of P
could be any number less than N. The figure also shows cases where the group start-up is aborted and later resumed.
The ICP format also includes a field for link's connectivity testing at the time of start-up, link addition or link re-activation. In particular, a protocol must always ensure proper connectivity of the links which belong to a group. For example, Figure 15 shows when links with Link ID=1 are added to groups with active Link ID=0 links.
Two new links (Link ID=1 links) are inversely connected with respect to the expected configuration. The difficulty is then that both Link ID
and IMA ID are the same for two independent IMAs. This can cause an invalid configuration which will not be detected. This kind of problem can occur at a start-up, link addition or even at a link re-activation. For example, it is possible to reactivate a link which has exhibited a link failure since it has been accidentally inverted with another link vvith or without the same Link ID and IMA ID. IMA ID is also used to detect loopback situations. This problem occurs when both end nodes of the IMA virtual link wants to use the same IMA ID. The invention addresses this problem also.
According to a further embodiment, the above problems are solved by sending a test pattern contained in ICP cells over a link to be CA 02263478 1999-02-1~
- W O g8/08355 PCT/CA97/00610 validated. The test pattern will be looped back over all the other links in the group at the far end node. This ensures that the tested link is connected to the same end node as the other links.
When one IMA node wants to determine if one or more links are connected to the same far end IMA node, it selects one link for testing. Figure 16 shows the timing diagram of the test procedure of the invention. The transmit node sets the Tx Test control field for link test in an ICP cell. It identifies Link ID, Tx IMA ID, Rx IMA ID and inserts Test Pattern in the cell. It continues to send same ICPs. The receive end node receives the ICPs and copies Tx Test Pattern onto Rx Test Pattern. It keeps sending same test pattern copied on Rx Test Pattern field over its all outgoing links. Figure 17 illustrates looping of a test pattern at node B. The transmit node receives and verifies Rx Test Pattern returned over the other links. It now knows that all the links which belong to the same IMA group.
Figure 18 depicts diagramatically a scenario where the test pattern procedure can be used to detect a link that is not connected to the expected IMA. Links identified as Link ID=1 are being added to existing groups using links with Link ID=0. Link 30 carries the IMA B
Test Pattern to looped back by IMA A and links 32 and 34 carry the IMA
D Test Pattern to be looped back to IMA B. In this case, the wrong test pattern will be received by IMA B. If IMA B was not commanding a Test Pattern loopback, IMA B would simply not receive the right test pattern.
The Test Pattern procedure also allows to deal with some pathological cases. One of them is when two IMA connected to the same far end I~A node are trying to start-up at the same time. The far end (receive end) node will have to determine which set of links (corresponding to one end) it wants to be connected to. This will require the received end to select the link(s) to be part of the group. as mentioned above, the receive end shall only respond to one Test Pattern command at a time that has been validated over one or more links that are or likely to be recognized as part of the group.
In accordance with a further embodiment, a stuff cell is inserted to control cell rate decoupling between the links, in order to accommodate the use of links non-synchronized to each other within the link groups. The transmitting node may be locked to one clock CA 02263478 1999-02-1~
source or may be plesiochronous. When plesiochronous, one of the buffers at the transmitting node may be depleted. To prevent underrun, the cell stuffing procedure is invoked. When there is one clock source, the buffer will never deplete. The transmitting node send 5 ICP cells which indicate a cell is stuffed at a certain location within the IMA frame. Any cell can be used for stuffing as long as the location is indicated so that the receiving node can remove it. In actual embodiment, the transmitting node repeats the ICP cell containing the stuff code indicating that "this cell is 1 out of 2 stuff cells". The 10 receiving node uses the stuff indications over the ICP cells to determine when to remove stuff cells from the incoming cell stream.
The receiving node relies on at least one ICP cell with a correct CRC-10.
A more robust approach is to look for a majority of valid codes.
Figure 19 shows cases (1,...,7) when the ICP cell preceding the 15 stuff event and the stuff ICP cells are corrupted. Corrupted cells are indicated by crosses in the figure. SICP indicate stuffing control cells.
The receiving node maintains synchronization for cases 1, 2, and 3.
The receiving node optionally maintain synchronization for cases 4, 5, and 6. the receiving node optionally maintain synchronization for case 20 7 if b>2 and when passing stuff indication over more than one of the previous ICP cells. "b" is the number of invalid/corrupted ICP cells before declaring the link OIF (out-of-IMA frame).
Claims (7)
1. In an inverse multiplexing digital data over a connection consisting of a plurality of transmission links, said data containing a series of ATM data cells, a method of testing connectivity of the transmission links comprising steps of:
sending a series of inverse multiplexing control cells containing a test message over one of the transmission links;
receiving a series of inverse multiplexing control cells containing received test messages over all the remaining transmission links; and verifying the received test messages to determine the connectivity of the transmission links.
sending a series of inverse multiplexing control cells containing a test message over one of the transmission links;
receiving a series of inverse multiplexing control cells containing received test messages over all the remaining transmission links; and verifying the received test messages to determine the connectivity of the transmission links.
2. The method of testing connectivity of the transmission links according to claim 1 wherein the step of sending comprising further steps of:
setting a field within each of the series of inverse multiplexing control cells to identify a transmission link to be tested, and:
sending the series of inverse multiplexing control cells containing a preset test pattern over the transmission links.
setting a field within each of the series of inverse multiplexing control cells to identify a transmission link to be tested, and:
sending the series of inverse multiplexing control cells containing a preset test pattern over the transmission links.
3. The method of testing connectivity of the transmission links according to claim 2, comprising further steps of:
receiving a series of inverse multiplexing control cells to see if the test pattern are copied thereon, and sending the series of inverse multiplexing control cells over all the remaining transmission links.
receiving a series of inverse multiplexing control cells to see if the test pattern are copied thereon, and sending the series of inverse multiplexing control cells over all the remaining transmission links.
4. The method of testing connectivity of the transmission links according to claim 1, comprising further steps of:
setting a timeout period during which a series of inverse multiplexing control cells are continuously sent over the transmission links.
setting a timeout period during which a series of inverse multiplexing control cells are continuously sent over the transmission links.
5. The method of testing connectivity of the transmission links according to claim 1, wherein the step of verifying comprising further steps of:
monitoring the test message on the received inverse multiplexing control cells to determine which transmission links belong to one group.
monitoring the test message on the received inverse multiplexing control cells to determine which transmission links belong to one group.
6. A method of inverse multiplexing digital data over a connection consisting of a plurality of transmission links, said data containing a series of ATM data cells, comprising steps of:
sending a series of inverse multiplexing control cells indicating a specific round robin order in which the series of ATM data cells are to be transmitted over the connection;
receiving from the plurality of transmission links a series of inverse multiplexing control cells whose receive ready field is set;
sending each ATM data cell in said series of ATM data cells in said specific round robin order; and further sending two consecutive inverse multiplexing control cells in a frame, indicating cell stuffing.
sending a series of inverse multiplexing control cells indicating a specific round robin order in which the series of ATM data cells are to be transmitted over the connection;
receiving from the plurality of transmission links a series of inverse multiplexing control cells whose receive ready field is set;
sending each ATM data cell in said series of ATM data cells in said specific round robin order; and further sending two consecutive inverse multiplexing control cells in a frame, indicating cell stuffing.
7. In an inverse multiplexing digital data over a connection consisting of a plurality of transmission links, said data containing a series of ATM data cells, an apparatus for testing connectivity of the transmission links comprising:
a transmitter for sending a series of inverse multiplexing control cells containing a test message over one of the transmission links;
a receiver for receiving a series of inverse multiplexing control cells containing received test message over all the remaining transmission links; and a message control device for verifying the received test message to determine the connectivity of the transmission links.
a transmitter for sending a series of inverse multiplexing control cells containing a test message over one of the transmission links;
a receiver for receiving a series of inverse multiplexing control cells containing received test message over all the remaining transmission links; and a message control device for verifying the received test message to determine the connectivity of the transmission links.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US2402396P | 1996-08-16 | 1996-08-16 | |
US60/024,023 | 1996-08-16 | ||
PCT/CA1997/000610 WO1998008355A1 (en) | 1996-08-16 | 1997-08-14 | Inverse multiplexing of digital data |
Publications (1)
Publication Number | Publication Date |
---|---|
CA2263478A1 true CA2263478A1 (en) | 1998-02-26 |
Family
ID=21818450
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002263478A Abandoned CA2263478A1 (en) | 1996-08-16 | 1997-08-14 | Inverse multiplexing of digital data |
Country Status (6)
Country | Link |
---|---|
US (4) | US6205142B1 (en) |
EP (1) | EP0920784B1 (en) |
JP (1) | JP3819438B2 (en) |
CA (1) | CA2263478A1 (en) |
DE (1) | DE69738484T2 (en) |
WO (1) | WO1998008355A1 (en) |
Families Citing this family (78)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1906606A2 (en) | 1996-08-16 | 2008-04-02 | Nortel Networks Limited | Inverse multiplexing of digital data |
IT1289816B1 (en) * | 1996-12-30 | 1998-10-16 | Sip | INTERFACE DEVICE FOR ATM TYPE NETWORKS |
US6647028B1 (en) * | 1997-09-30 | 2003-11-11 | Cisco Technology, Inc. | System and method for recovering and restoring lost data in a N-channel coherent data transmission system |
JPH11275090A (en) * | 1998-03-20 | 1999-10-08 | Fujitsu Ltd | Wiretap preventing system and communication system thereof |
US6298043B1 (en) * | 1998-03-28 | 2001-10-02 | Nortel Networks Limited | Communication system architecture and a connection verification mechanism therefor |
JP3052940B2 (en) * | 1998-09-08 | 2000-06-19 | 日本電気株式会社 | Transmission path switching device |
IT1307016B1 (en) * | 1999-01-27 | 2001-10-11 | Cselt Centro Studi Lab Telecom | PROCEDURE AND DEVICE FOR THE TRANSMISSION OF NUMERICAL SIGNALS. |
US6222858B1 (en) * | 1999-02-10 | 2001-04-24 | Verizon Laboratories Inc. | Method of inverse multiplexing for ATM |
US6621794B1 (en) * | 1999-02-18 | 2003-09-16 | Nokia Corporation | Method and apparatus for measuring the timing difference between physical IMA links and for delivering a time difference to the IMA layer |
GB2347304B (en) * | 1999-02-25 | 2003-08-13 | Mitel Corp | Multitrunk ATM termination device |
US6678275B1 (en) | 1999-02-25 | 2004-01-13 | Zarlink Semiconductor Inc. | Multitrunk ATM termination device |
US6577653B1 (en) * | 1999-04-28 | 2003-06-10 | 3Com Corporation | Apparatus for and method of establishing a route utilizing multiple parallel segments in an asynchronous transfer mode network |
US6873630B1 (en) * | 1999-05-19 | 2005-03-29 | Sun Microsystems, Inc. | Method and apparatus for a multi-gigabit ethernet architecture |
US6985503B1 (en) | 1999-08-09 | 2006-01-10 | Zarlink Semiconductor Inc. | Inverse multiplexer |
GB2353174B (en) * | 1999-08-09 | 2003-09-10 | Mitel Corp | Inverse multiplexer |
CN1369038A (en) * | 1999-08-12 | 2002-09-11 | 内诺马斯尔公司 | Shape-memory alloy acutators and conrol methods |
US6687840B1 (en) * | 2000-04-21 | 2004-02-03 | Intel Corporation | Multi-link extensions and bundle skew management |
US6646991B1 (en) * | 1999-12-22 | 2003-11-11 | Intel Corporation | Multi-link extensions and bundle skew management |
JP2001244918A (en) * | 2000-02-28 | 2001-09-07 | Fujitsu Ltd | Network equipment |
US6326707B1 (en) | 2000-05-08 | 2001-12-04 | Mark A. Gummin | Shape memory alloy actuator |
US6832477B2 (en) | 2000-05-08 | 2004-12-21 | Mark A Gummin | Shape memory alloy actuator |
US6765910B1 (en) * | 2000-05-17 | 2004-07-20 | Intel Corporation | System and method for communicating information using inverse multiplex ATM(IMA) functionality |
US6775271B1 (en) * | 2000-05-17 | 2004-08-10 | Intel Corporation | Switching system and method for communicating information at a customer premises |
US6717960B1 (en) * | 2000-06-01 | 2004-04-06 | Agere Systems Inc. | Method for reconstructing an aggregate ATM cell stream and related device |
US7145908B1 (en) * | 2000-08-28 | 2006-12-05 | Agere Systems Inc. | System and method for reducing jitter in a packet transport system |
US7088737B1 (en) | 2000-10-27 | 2006-08-08 | Redback Networks Inc. | Method and apparatus for combining packets having different protocol encapsulations within a circuit |
US7020736B1 (en) | 2000-12-18 | 2006-03-28 | Redback Networks Inc. | Method and apparatus for sharing memory space across mutliple processing units |
US7006509B1 (en) | 2000-12-22 | 2006-02-28 | Cisco Technology, Inc. | Method and system for graceful slowlink deletion and subsequent fast link addition in an IMA group |
US6952434B1 (en) * | 2000-12-27 | 2005-10-04 | Cisco Technology, Inc. | System and method for processing control cells to prevent event missequencing and data loss in IMA groups |
US7065104B1 (en) * | 2000-12-28 | 2006-06-20 | Cisco Technology, Inc. | Method and system for managing inverse multiplexing over ATM |
US6928056B2 (en) * | 2000-12-29 | 2005-08-09 | Nokia Networks Oy | System and method for distribution of a data stream from high-to-low-to-high bandwidth links |
US6990121B1 (en) | 2000-12-30 | 2006-01-24 | Redback, Networks, Inc. | Method and apparatus for switching data of different protocols |
US6466591B1 (en) | 2000-12-30 | 2002-10-15 | Redback Networks Inc. | Method and apparatus for processing of multiple protocols within data and control channels in data transmission signals |
US6765916B1 (en) | 2000-12-30 | 2004-07-20 | Redback Networks Inc. | Method and apparatus for processing of multiple protocols within data transmission signals |
US6993047B1 (en) * | 2000-12-30 | 2006-01-31 | Redback Networks Inc. | Any size and location of concatenated packet data across SONET frames in a SONET signal |
US6798783B1 (en) * | 2001-01-23 | 2004-09-28 | Cisco Technology, Inc. | Method and apparatus for handling out of inverse multiplexing for asynchronous transfer mode frame error conditions |
DE60226160T2 (en) | 2001-02-22 | 2009-07-02 | Alfmeier Präzision AG Baugruppen und Systemlösungen | MEMBRANE OF MEMORY METAL WITH IMPROVED TEMPERATURE CONTROL |
US6959008B2 (en) * | 2001-03-31 | 2005-10-25 | Redback Networks Inc. | Alignment of TDM-based signals for packet transmission using framed and unframed operations |
US6510166B2 (en) | 2001-03-31 | 2003-01-21 | Redback Networks, Inc. | Stuffing filter mechanism for data transmission signals |
NL1017870C2 (en) * | 2001-04-18 | 2002-10-25 | Marc Van Oldenborgh | Method for inverse multiplexing. |
US20020181441A1 (en) * | 2001-04-24 | 2002-12-05 | Alcatel, Societe Anonyme | Facilitating inverse multiplexing over asynchronous transfer mode via communication links having disparate data transmission rates |
US7068657B2 (en) * | 2001-04-24 | 2006-06-27 | Alcatel | Facilitating inverse multiplexing over asynchronous transfer mode via communication links having disparate data transmission rates |
GB2375262B (en) * | 2001-04-30 | 2004-05-19 | Siemens Ag | Improvements in or relating to third generation cellular networks |
US6976096B1 (en) | 2001-06-02 | 2005-12-13 | Redback Networks Inc. | Method and apparatus for controlling the admission of data into a network element |
US6590868B2 (en) | 2001-06-02 | 2003-07-08 | Redback Networks Inc. | Method and apparatus for restart communication between network elements |
NL1018463C2 (en) * | 2001-07-04 | 2003-01-08 | Marc Van Oldenborgh | Method, layout and software for digitally inverse multiplexing. |
KR100392817B1 (en) * | 2001-08-07 | 2003-07-28 | 주식회사 케이티 | Parallel inverse multiplexing method and system for large capacity switching |
US7349401B2 (en) * | 2001-09-05 | 2008-03-25 | Symmetricom, Inc. | Bonded G.shdsl links for ATM backhaul applications |
AU2002340093A1 (en) | 2001-10-05 | 2003-04-22 | Aware, Inc. | Systems and methods for multi-pair atm over dsl |
US7310310B1 (en) * | 2001-11-07 | 2007-12-18 | Symmetricom, Inc. | Multi-link SAR for bonding ATM cell-streams |
US7286570B2 (en) * | 2001-11-21 | 2007-10-23 | Alcatel-Lucent Canada Inc | High speed sequenced multi-channel bus |
US7075951B1 (en) | 2001-11-29 | 2006-07-11 | Redback Networks Inc. | Method and apparatus for the operation of a storage unit in a network element |
US7385970B1 (en) | 2001-12-07 | 2008-06-10 | Redback Networks, Inc. | Method and apparatus for balancing bandwidth among multiple ports of a network element |
CA2390883C (en) * | 2001-12-20 | 2009-06-02 | Tropic Networks Inc. | Communication system with balanced transmission bandwidth |
US7266130B2 (en) * | 2001-12-28 | 2007-09-04 | Samsung Electronics Co., Ltd. | Apparatus and method for multiplexing multiple end-to-end transmission links in a communication system |
KR100810255B1 (en) * | 2002-01-09 | 2008-03-06 | 삼성전자주식회사 | Inverse multiplexing apparatus and method for atm |
US6879590B2 (en) * | 2002-04-26 | 2005-04-12 | Valo, Inc. | Methods, apparatuses and systems facilitating aggregation of physical links into logical link |
WO2003093615A1 (en) | 2002-05-06 | 2003-11-13 | Nanomuscle, Inc. | Reusable shape memory alloy activated latch |
AU2003267114A1 (en) | 2002-05-06 | 2003-11-11 | Nanomuscle, Inc. | High stroke, highly integrated sma actuators |
AU2003239367A1 (en) | 2002-05-06 | 2003-11-17 | Nanomuscle, Inc. | Actuator for two angular degrees of freedom |
US8127543B2 (en) | 2002-05-06 | 2012-03-06 | Alfmeier Prazision Ag Baugruppen Und Systemlosungen | Methods of manufacturing highly integrated SMA actuators |
US7212548B2 (en) * | 2002-06-21 | 2007-05-01 | Adtran, Inc. | Multiple T1 channel inverse multiplexing method and apparatus |
KR100446508B1 (en) * | 2002-06-26 | 2004-09-04 | 삼성전자주식회사 | Apparatus for processing packet data in a packet data communication system |
DE50211013D1 (en) * | 2002-09-11 | 2007-11-15 | Tektronix Int Sales Gmbh | Method and device for monitoring a data transmission |
US7047432B1 (en) * | 2003-01-17 | 2006-05-16 | Cisco Technology, Inc. | Method and system for synchronizing output from differently timed circuits |
JP4007313B2 (en) * | 2003-01-22 | 2007-11-14 | 株式会社村田製作所 | Angle sensor |
US20050030889A1 (en) * | 2003-08-04 | 2005-02-10 | Lucent Technologies Inc. | Method and system for transmiting in-band call processing-related traffic using bearer facilities |
US7852881B2 (en) | 2003-08-27 | 2010-12-14 | Telefonaktiebolaget L M Ericsson (Publ) | Inverse multiplexer with TDM bonding |
CN100403700C (en) * | 2004-01-05 | 2008-07-16 | 华为技术有限公司 | Asynchronous transmission mode reverse multiplex measuring method and device |
US7821948B2 (en) * | 2004-05-27 | 2010-10-26 | Alcatel Lucent | Network management system and method provisioning OAM support for multicast communications sessions |
US7460541B2 (en) * | 2004-09-24 | 2008-12-02 | Agilent Technologies, Inc. | Method and apparatus to monitor and analyze network information of an inverse multiplexed asynchronous transfer mode network |
US20100002727A1 (en) * | 2004-12-14 | 2010-01-07 | Telefonaktiebolaget Lm Ericsson (Publ) | Inverse Multiplex Protocol |
TWI253566B (en) * | 2004-12-23 | 2006-04-21 | Accton Technology Corp | Setting method to increase the throughput |
US8155156B2 (en) | 2006-09-15 | 2012-04-10 | Alcatel Lucent | Synchronization recovery for multiple-link communications |
JP2009033573A (en) * | 2007-07-27 | 2009-02-12 | Fujitsu Ltd | Ethernet(r) frame transmission system and ethernet frame transmission apparatus |
US20090296737A1 (en) * | 2008-06-03 | 2009-12-03 | Ram Arye | Method and system for connecting two nodes over multiple communication links |
CN102111334A (en) * | 2011-02-21 | 2011-06-29 | 华为技术有限公司 | Method, source line card and network card for processing cells in switched network |
JP6493756B2 (en) * | 2015-06-23 | 2019-04-03 | 富士ゼロックス株式会社 | Transmission device, reception device, transmission / reception system, and program |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4149038A (en) * | 1978-05-15 | 1979-04-10 | Wescom Switching, Inc. | Method and apparatus for fault detection in PCM muliplexed system |
US5313453A (en) * | 1991-03-20 | 1994-05-17 | Fujitsu Limited | Apparatus for testing ATM channels |
US5491695A (en) * | 1991-07-17 | 1996-02-13 | Digital Access Corporation | Means and method of dial up bridging of network for high bandwidth digital communication |
AU3416293A (en) * | 1991-12-23 | 1993-07-28 | Network Express | System for internetworking data terminal equipment through a switched digital network |
US5285441A (en) * | 1992-03-17 | 1994-02-08 | At&T Bell Laboratories | Errorless line protection switching in asynchronous transer mode (ATM) communications systems |
JPH05292114A (en) * | 1992-04-09 | 1993-11-05 | Fujitsu Ltd | Communication path setting device and its method |
DE59209115D1 (en) | 1992-08-28 | 1998-02-12 | Siemens Ag | Method and circuit arrangement for transmitting message cells within an ATM network |
KR960003505B1 (en) * | 1992-12-29 | 1996-03-14 | 재단법인 한국전자통신연구소 | Atm multiplexing processor |
JP3073856B2 (en) * | 1993-05-12 | 2000-08-07 | 三菱電機株式会社 | ATM cell processing equipment |
US5617417A (en) * | 1994-09-07 | 1997-04-01 | Stratacom, Inc. | Asynchronous transfer mode communication in inverse multiplexing over multiple communication links |
US5608733A (en) * | 1994-11-29 | 1997-03-04 | Valle; Richard | ATM inverse multiplexing |
US6972786B1 (en) * | 1994-12-30 | 2005-12-06 | Collaboration Properties, Inc. | Multimedia services using central office |
US7190681B1 (en) * | 1996-07-10 | 2007-03-13 | Wu William W | Error coding in asynchronous transfer mode, internet and satellites |
US5875192A (en) * | 1996-12-12 | 1999-02-23 | Pmc-Sierra Ltd. | ATM inverse multiplexing system |
-
1997
- 1997-08-14 US US08/909,060 patent/US6205142B1/en not_active Expired - Lifetime
- 1997-08-14 DE DE69738484T patent/DE69738484T2/en not_active Expired - Lifetime
- 1997-08-14 CA CA002263478A patent/CA2263478A1/en not_active Abandoned
- 1997-08-14 WO PCT/CA1997/000610 patent/WO1998008355A1/en active IP Right Grant
- 1997-08-14 EP EP97937388A patent/EP0920784B1/en not_active Expired - Lifetime
- 1997-08-14 JP JP51020998A patent/JP3819438B2/en not_active Expired - Lifetime
-
2000
- 2000-04-06 US US09/543,906 patent/US6894977B1/en not_active Expired - Lifetime
-
2005
- 2005-01-12 US US11/034,455 patent/US7570595B2/en not_active Expired - Lifetime
-
2009
- 2009-06-25 US US12/491,927 patent/US8125912B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0920784B1 (en) | 2008-01-23 |
US6205142B1 (en) | 2001-03-20 |
EP0920784A1 (en) | 1999-06-09 |
US7570595B2 (en) | 2009-08-04 |
US20100067386A1 (en) | 2010-03-18 |
JP2002512743A (en) | 2002-04-23 |
WO1998008355A1 (en) | 1998-02-26 |
DE69738484D1 (en) | 2008-03-13 |
DE69738484T2 (en) | 2008-05-21 |
JP3819438B2 (en) | 2006-09-06 |
US20050265243A1 (en) | 2005-12-01 |
US6894977B1 (en) | 2005-05-17 |
US8125912B2 (en) | 2012-02-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7570595B2 (en) | Inverse multiplexing of digital data | |
US5608733A (en) | ATM inverse multiplexing | |
US5345445A (en) | Establishing telecommunications calls in a broadband network | |
US5345446A (en) | Establishing telecommunications call paths in broadband communication networks | |
US5327421A (en) | Apparatus for interfacing between telecommunications call signals and broadband signals | |
EP0519954B1 (en) | Digital data transmission system | |
US5365524A (en) | Establishing telecommunications call paths between clustered switching entities | |
US6002670A (en) | Optimization and recovery techniques in IMA networks | |
EP0669067B1 (en) | Establishing telecommunications call paths in broadband communication networks | |
EP0955786B1 (en) | Asynchronous transfer mode layer automatic protection switching mechanism for ATM permanent virtual connections | |
KR20010013967A (en) | Segment performance monitoring | |
US6473397B1 (en) | Add/drop multiplexer and method, and Bi-directional line switcher ring featuring such multiplexers | |
EP1135001A2 (en) | Apparatus and method for automatic port identity discovery in hierarchical heterogenous systems | |
US20110182219A1 (en) | Base station modulator/demodulator and send/receive method | |
EP1906606A2 (en) | Inverse multiplexing of digital data | |
GB2334853A (en) | Engineering operations channel | |
JP3151768B2 (en) | Self-healing ring system for synchronous and asynchronous transfer modes | |
JP3577715B2 (en) | ATM communication system and ATM multi-link communication method | |
JP3712377B2 (en) | Method for managing SAAL resources in a distributed implementation environment | |
JPH0918490A (en) | Control line multiplexing device | |
AU641828B2 (en) | A method of transmitting data on a telecommunications network | |
JP2003198660A (en) | Failover device and method for ashychrnous data communication network |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
FZDE | Discontinued |