CA2230735A1 - Apparatus for waveform disturbance monitoring for an electric power system - Google Patents
Apparatus for waveform disturbance monitoring for an electric power system Download PDFInfo
- Publication number
- CA2230735A1 CA2230735A1 CA002230735A CA2230735A CA2230735A1 CA 2230735 A1 CA2230735 A1 CA 2230735A1 CA 002230735 A CA002230735 A CA 002230735A CA 2230735 A CA2230735 A CA 2230735A CA 2230735 A1 CA2230735 A1 CA 2230735A1
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- Prior art keywords
- waveform
- digital samples
- trigger signal
- generating
- trigger
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
- G01R19/2513—Arrangements for monitoring electric power systems, e.g. power lines or loads; Logging
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/44—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to the rate of change of electrical quantities
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/38—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to both voltage and current; responsive to phase angle between voltage and current
Abstract
A monitor/analyzer for an alternating current (AC) electrical system responds to power line disturbances by generating a trigger signal when a change in voltage with respect to time electrical parameter is greater than a programmed threshold. The monitor/analyser includes a sensor for sensing an AC waveform in the electrical system, an analog-to-digital converter for sampling the AC waveform, and a microcomputer. Firmware of the microcomputer cooperates with the A/D converterand provides a plurality of digital samples of the AC waveform for each of some of its AC cycles. The firmware generates each of plural dV/dt parameters of the AC
waveform from a corresponding adjacent pair of the digital samples within one of the waveform's AC cycles. A trigger signal is generated when one of the dV/dt parameters is greater than the programmed threshold. The digital samples of the AC
waveform before and after the power line disturbance are captured and output to a display in response to the trigger signal.
waveform from a corresponding adjacent pair of the digital samples within one of the waveform's AC cycles. A trigger signal is generated when one of the dV/dt parameters is greater than the programmed threshold. The digital samples of the AC
waveform before and after the power line disturbance are captured and output to a display in response to the trigger signal.
Description
.. .
- 1 - 9~PDC 447 APPARATUS FOR WAVEFORM DISTURBANCE MONlIOR~G
FOR AN ELECTRIC rOWER SY~
BACKGROUND OF T~IE lNVENTlON
Field of the Invention This invention relates to an apy&dl~s for monit~.;n~ electric power systems and, more particularly, to an app~dlus for digitally cay~uling a yortion of a waveform of an electric power system in l~ponse to a waveform disturbance trigger cQn~lition.
Background Il,Çoll"dlion State of the art monitors for alternating current (AC) yower systems incoryorate microcolllyute~ for calcul~ting various electrical parameters such as RMS
currents and voltages, peak cullents and voltages, power, energy, power factor and the like. One such monitor is disclosed in U.S. Patent No. 5,587,917. In addition tomonitoring the various electrical parameters of the AC system, this monitor alsodigitally captures portions of the waveform for harmonic analysis. This places a very high burden on the microcomputer in the monitor. Accordingly, this monitor uses a slow sampling rate for gathering the data needed for pelrol"ling the monitoling functions and operates at a second, higher rate for waveform capture in response to a manual colllllland or automatically in response to values of sel~ted ones of theelectri~l parameters which exceed predetermined thresholds.
A monitor/analyzer for an AC electrical system, disclosed in commonly owned U.S. Patent Application Serial No. 08/608,387, filed on February 28, 1996,responds to selçcted events by gencldting trigger signals when se1~t~d monitoredelectrical parameters, in-,lu-ling neutral current, exceed programmed thresholds. The trigger signals initiate simultaneous waveform capture of multiple waveforms in the AC
~' f system. Muldple trigger signals result in sequential waveform capture so that if a plurality of triggers are programmed for the same event, eYt~nded waveform data is c~lJlured for the event.
Commonly owned U.S. Patent Applic~tion Serial No. 08/608,386, filed on I~.u~y 28, 1996, ~ closes a .. ~ ;~r for an AC ~ ;e~l system which g~ne.dh,s on-line a display pl~-~t;r~, the values, dther in .~.-~n;l~.de or as a percent of the fi)n-ls...~ l of fifty h~...onics of any of the cull~ts and voltages in the system.
A circuit in~.~.lpter, di~1os~ in co.lll.lonly owned U.S. Patent Appli~tiol~ Serial No. 08/342,208, filed on No~e...~r 18, 1994, provides waveform capture in ~lil;on to ~ç~t~;1;0~ fim~fion~ Ihe circuit interrupter micr~co.,.~ut~r Op~dt~S in a protection mode to provide the protection functinn~ and in a waveform capture mode to record the waveform data.
It is also known to employ a rate of change of current, di/dt, in tripping a circuit breaker. See, for eAalllple, U.S. Patent Nos. 3,673,455; and 5,224,006.
Known monitors for AC electrical systems detect disturbances in such systems by employing information obtained from plural AC cycles.
There is a need, lh~.~,fol~, for an improved monitor for AC electrical systems which provides an improved capability for mon;~Q~ g sub-cycle disturbances in such systems.
SUMMAI~Y OF THE INVENTION
This need and others are s~tisfied by the invention, which is directed to an appa-dtus for monitoring an electric power system. This app~dlus gene.dtes a plurality of digital Sd ll~les of an ~lterr~tin~ current (AC) waveform having a plurality of AC cycles. The app~tlls captu.~s disturbances of the AC waveform as a function of changes in waveform m~g~itude with respect to time from a predeterrnined threshold and a pair of the digital samples of one of the AC cycles. In this manner, sub-cycle disturbances in the power system line or load which affect the AC waveform may be captured and output for analysis.
The appaldtlls includes sensing means for sensing an AC waveform in the electric power system; sampling means for sampling the AC waveform sensed bythe sensing means; and digital pr~.,~;ng means. The digital pr~in~ means includes means cooperating with the s~mpling means for providing a plurality of digital samples of the AC waveform for each of some of the AC cycles of the AC waveform, 3 9~PDC 447 means for gcn~,~aling a value ~pl~ ;ng a change in magr it lde with respect to time of the AC waveform from a pair of the digital samples of one of the AC cycles of the AC waveform, trigger means for g~e~ling at least one trigger signal, with the trigger signal being a function of the value lC~ P a change in ~n~n;l~Jde with respect S to time of the AC waveform and a pl~de~ in~d threshold, and capture means for car~t~ ;n~ the digital samples of the AC waveform in ~ o~-~ to the trigger signal.
The ~p~ s may .-.oll;lor the AC waveform by co.~.p~ lg ~ nt digital samples of the AC line voltage, the ... ~ udes of which are either too far apart or else are too close to ze~o. In this u~ , c.~ e voltage ~ lQ;"r~t~: or 10 ...o.n~t~ voltage rnt~ plions are ca~ d.
As another aspect of the invention, an arp~ s for .non;~o.;ng an electric power system in~ludes sensing means for sensing a waveform of the electric power system; ~...pli~g means for ~.npling the waveform sensed by the sensing means; and digital plocessing means. The digital p~oc~;ng means inc1lldes means coop~.~Ling with the sampling means for providing a plurality of digital salllples of the waveform, means for g~nelaLing a value lepr~nL;~g a change in magnitude with respect to time of the waveform from an ~ -t pair of the digital s~mples triggermeans for gen~ting at least one trigger signal, with the trigger signal being a function of the value 1ep-e~-r ~ g a change in maenihlde with respect to time of the waveform and a predetermined threshold, and capture means for capturing the digital samples of the waveform in response to the trigger signal.
BRIEF DESCRIPIION OF THE DRAW~GS
A full und~ 1in~ of the invention can be gained from the following descli~lion of the ~r~,fell~d embo~iments when read in conjunction with the acco,.,~anying drawings in which:
Figure 1 is a scl c~ ;c diagram primarily in block form of a monitor in accordance with the invention;
Figure 2 is an elevation view of a display on a front panel which forms part of the monitor of Figure l;
Figures 3A-3E are flow charts of software r~ulines imple,nented by a digital pr~cessor which forms part of the ,~,oni~or of Figure l; and Figure 4 is a plot of a waveform which is monilol~d and ou~ut by the monitor of Figure 1.
- 1 - 9~PDC 447 APPARATUS FOR WAVEFORM DISTURBANCE MONlIOR~G
FOR AN ELECTRIC rOWER SY~
BACKGROUND OF T~IE lNVENTlON
Field of the Invention This invention relates to an apy&dl~s for monit~.;n~ electric power systems and, more particularly, to an app~dlus for digitally cay~uling a yortion of a waveform of an electric power system in l~ponse to a waveform disturbance trigger cQn~lition.
Background Il,Çoll"dlion State of the art monitors for alternating current (AC) yower systems incoryorate microcolllyute~ for calcul~ting various electrical parameters such as RMS
currents and voltages, peak cullents and voltages, power, energy, power factor and the like. One such monitor is disclosed in U.S. Patent No. 5,587,917. In addition tomonitoring the various electrical parameters of the AC system, this monitor alsodigitally captures portions of the waveform for harmonic analysis. This places a very high burden on the microcomputer in the monitor. Accordingly, this monitor uses a slow sampling rate for gathering the data needed for pelrol"ling the monitoling functions and operates at a second, higher rate for waveform capture in response to a manual colllllland or automatically in response to values of sel~ted ones of theelectri~l parameters which exceed predetermined thresholds.
A monitor/analyzer for an AC electrical system, disclosed in commonly owned U.S. Patent Application Serial No. 08/608,387, filed on February 28, 1996,responds to selçcted events by gencldting trigger signals when se1~t~d monitoredelectrical parameters, in-,lu-ling neutral current, exceed programmed thresholds. The trigger signals initiate simultaneous waveform capture of multiple waveforms in the AC
~' f system. Muldple trigger signals result in sequential waveform capture so that if a plurality of triggers are programmed for the same event, eYt~nded waveform data is c~lJlured for the event.
Commonly owned U.S. Patent Applic~tion Serial No. 08/608,386, filed on I~.u~y 28, 1996, ~ closes a .. ~ ;~r for an AC ~ ;e~l system which g~ne.dh,s on-line a display pl~-~t;r~, the values, dther in .~.-~n;l~.de or as a percent of the fi)n-ls...~ l of fifty h~...onics of any of the cull~ts and voltages in the system.
A circuit in~.~.lpter, di~1os~ in co.lll.lonly owned U.S. Patent Appli~tiol~ Serial No. 08/342,208, filed on No~e...~r 18, 1994, provides waveform capture in ~lil;on to ~ç~t~;1;0~ fim~fion~ Ihe circuit interrupter micr~co.,.~ut~r Op~dt~S in a protection mode to provide the protection functinn~ and in a waveform capture mode to record the waveform data.
It is also known to employ a rate of change of current, di/dt, in tripping a circuit breaker. See, for eAalllple, U.S. Patent Nos. 3,673,455; and 5,224,006.
Known monitors for AC electrical systems detect disturbances in such systems by employing information obtained from plural AC cycles.
There is a need, lh~.~,fol~, for an improved monitor for AC electrical systems which provides an improved capability for mon;~Q~ g sub-cycle disturbances in such systems.
SUMMAI~Y OF THE INVENTION
This need and others are s~tisfied by the invention, which is directed to an appa-dtus for monitoring an electric power system. This app~dlus gene.dtes a plurality of digital Sd ll~les of an ~lterr~tin~ current (AC) waveform having a plurality of AC cycles. The app~tlls captu.~s disturbances of the AC waveform as a function of changes in waveform m~g~itude with respect to time from a predeterrnined threshold and a pair of the digital samples of one of the AC cycles. In this manner, sub-cycle disturbances in the power system line or load which affect the AC waveform may be captured and output for analysis.
The appaldtlls includes sensing means for sensing an AC waveform in the electric power system; sampling means for sampling the AC waveform sensed bythe sensing means; and digital pr~.,~;ng means. The digital pr~in~ means includes means cooperating with the s~mpling means for providing a plurality of digital samples of the AC waveform for each of some of the AC cycles of the AC waveform, 3 9~PDC 447 means for gcn~,~aling a value ~pl~ ;ng a change in magr it lde with respect to time of the AC waveform from a pair of the digital samples of one of the AC cycles of the AC waveform, trigger means for g~e~ling at least one trigger signal, with the trigger signal being a function of the value lC~ P a change in ~n~n;l~Jde with respect S to time of the AC waveform and a pl~de~ in~d threshold, and capture means for car~t~ ;n~ the digital samples of the AC waveform in ~ o~-~ to the trigger signal.
The ~p~ s may .-.oll;lor the AC waveform by co.~.p~ lg ~ nt digital samples of the AC line voltage, the ... ~ udes of which are either too far apart or else are too close to ze~o. In this u~ , c.~ e voltage ~ lQ;"r~t~: or 10 ...o.n~t~ voltage rnt~ plions are ca~ d.
As another aspect of the invention, an arp~ s for .non;~o.;ng an electric power system in~ludes sensing means for sensing a waveform of the electric power system; ~...pli~g means for ~.npling the waveform sensed by the sensing means; and digital plocessing means. The digital p~oc~;ng means inc1lldes means coop~.~Ling with the sampling means for providing a plurality of digital salllples of the waveform, means for g~nelaLing a value lepr~nL;~g a change in magnitude with respect to time of the waveform from an ~ -t pair of the digital s~mples triggermeans for gen~ting at least one trigger signal, with the trigger signal being a function of the value 1ep-e~-r ~ g a change in maenihlde with respect to time of the waveform and a predetermined threshold, and capture means for capturing the digital samples of the waveform in response to the trigger signal.
BRIEF DESCRIPIION OF THE DRAW~GS
A full und~ 1in~ of the invention can be gained from the following descli~lion of the ~r~,fell~d embo~iments when read in conjunction with the acco,.,~anying drawings in which:
Figure 1 is a scl c~ ;c diagram primarily in block form of a monitor in accordance with the invention;
Figure 2 is an elevation view of a display on a front panel which forms part of the monitor of Figure l;
Figures 3A-3E are flow charts of software r~ulines imple,nented by a digital pr~cessor which forms part of the ,~,oni~or of Figure l; and Figure 4 is a plot of a waveform which is monilol~d and ou~ut by the monitor of Figure 1.
4 9~PDC 447 nF~RTpI~oN OF 1~ p~FR~.RRF.r~ F~rRoDr~F~T
Referring to Figure 1, the analyzer/monitQr 1 of the invention is used to ...~n;tor and analyze an electric power system, such as the exem~l~ y power distribution system 3. The power distribution system 3 has three phase conductors 5A,SB,5C, a neutral conductor 5N co~n~t~d to an electri~l common of the analyzer/.~on;t~r 1, and a ground conductor 5G. Current tran~Çor,n_.~
7A,7B,7C,7N,7G sense current flowing in these l~Li~e conducto-~ while three phase-to-neutTal voltages are sensed by sensing resistors 9A,9B,9C. A ranging circuit 11 converts the sensed currents and sensed phase voltages to the a~r~p,ia~ range for conversion by a ~:lOV analog-to-digital (A/D) converter 13 for input to a digital pç~cess~r 15, such as, for eY~mrl~., a mic,oco."~ ter or microprocessor. The A/Dconverter 13 s~ 5 the analog signals, which co,l~ond to the sensed cullellts andsensed phase voltages, at intervals de~,l.ined by in~lu~ts gen~ ed by the digital pr~c~ssor lS. The current transformers 7A,7B,7C,7N,7G and sensing resistors 9A,9B,9C sense waveforms (e.g., alle~ g current (AC) waveforms having plural AC cycles) in the power distribution system 3, which may have one of various line-to-line AC power voltages (e.g., 120 Vu, 208 Vu, 480 VD~ 600 V~). For exarnple, theline-to-neutral voltages of the waveforms on the phase conductors SA,5B,SC are sensed by the ç~s~li~e sensing resistors 9A,9B,9C.
In the exemplary embodiment, the digital plocessor interrupts are generated selectively at a first, slow speed sampling rate, or a second, high speed sampling rate. Regardless of the sampling rate, on each interrupt, the A/D converter 13 samples and ~ligiti7~s all five sensed currents and all three sensed phase voltages.
The resulting digital samples of the waveforms, generated by the exemplary A/D
converter 13, are input to the digital processor lS, although the invention is applicable to one or more A/D converters which form part of a digital processor, such as a microcomputer. The ground to neutral voltage between conductors SG and SN is amplified by an input circuit 12 which outputs a ground to neutral voltage signal, Vc,,, to A/D converter 16 in the digital processor lS. The A/D converter 16 converts this analog signal to col.e~onding digital samples.
The digital processor 15 utilizes the digital sarnples of the A/D
converters 13,16 to generate values of two sets of electrical parameters. The first set of parameters is related to the monitoring function and includes metered parameters ( 9~PDC447 such as: RMS c~ e~ts and voltages, peakCIlll~ S and voltages, minimllm currents and voltages, power factor, watts, Vars, volt-amps, total harmonic distortion K-factor, CBEMA deradng factor, ch. nge in volt. ges with respect to dme (e.g., dV/dt values) and the like. The second set of pal~nct~ c-q-lc~lqt~ by the digit l pç~cessor 15S comr~s individual ha,luonic c4crr~c - ~~ts Data coll~tion a nd p~ s~n~, e~ ud the a~ q~;nt~ of the e,~c---p~ Dv/dt values, are o,E~ni~1 in the l~Ulrltr de~ibed in U.S. Patent No; 5,587,917, which is ~cG~ t~d herein by ~f~c~ , so that a m~ nU~ nu.nbcr of ~.ul.~ ~.s can be ~onitul~d cQn~;n~ou~l~ while ~so providing the cqphility for simllltvq~l~ous cqlcul-l;ol~ of h~ulllonic cont~.nt The digital ploces30r lS has . n input/output a/O) circuit 17 llu~ugh which such p~cessor is ~nn~t~d to a front panel 19. The front panel 19 serves asan interf~ with a user. The user can control the operation of the analyzer/..~onit~r 1 through the front panel 19 and monit~r the AC e~ic~l power system 3. The IIO
circuit 17 also int~.r~ the digital pr~ssor lS with contact inputs through digital lS inputs and with an external device (not shown) through relay outputs and analog outputs. The digital pr~cessor lS can also communicate with a remote processor (not shown) lh~o~ ) a co.. ~ ications link 21. Through this communi~tions link 21, the analyzer/...... .......~onilor 1 can provide infol"lalion to and/or be controlled by the remote ~l'~C~SSO~.
The digital processor lS generates its h~te.lupts to provide a slow rate for moniloling and a faster rate for data capture in order to control the burden on such processor so that all of the l~uil~d functions can be pe.~l,..ed. The exemplary sampling scheme used by the digital plocessor lS, e~tclllding the c~lcul~tion of Dv/dt values, is the same as that described in U.S. Patent No. S,587,917, referenced above, although the present invention is applicable to a wide variety of techniques forsampling a waveform and genel~dting a value repr~ g a change in m~gnil~lde with respect to time of the waveform from a pair of the digital samples of one of the AC
cycles of an AC waveform, (e.g., periodic sampling of digital samples, periodic or aperiodic sampling of digital samples along with coll~ ing time values).
As is known, waveform capture l~quir~s synchronous sampling at a rate that is at least twice that of the highest harmonic to be eAll~,~d. The monilolii g functions, on the other hand, do not require synchronous s~mpling. Hence, the technique known as equivalent sampling is used for the slow speed sampling in order f - 6 - 96-PDC~47 to inc~asc the effective $~..plin~ rate. In the equivalent s~..p~ technique, the AC
wavefo..lls are sqmrl~ a se1~t~d n~)mbPr of times per cycle with a delay of a fraction of a cycle before another cycle of s~llplcs is ta~en at the same sampling rate. Thus, the ~.npl;n~ inctqnt~ are ~bumped" each cycle by the selc~l~cl fraction of a cycle. The S data cQllect~d over a n~ of such '~bulllped'~ cycles are then used to c~lculqte various ~ t~
Equivalent ~...pli~-g at slow speed with s. t~ high speed 5~.,plil~
for waveform capture is implem~t~ by s--~ pli~ in frames. Each ~-"~l li--~ framecompri~,s a n~ l~r of r~ffffonc of ~ ling for a Sf,~C~t~YI num~,r of cycles followed 10 by a delay which is a fir~pQt~ of a cyde. In the ~ P1~Y system, the ~Pl~t~d ~-u-..be~ of cycles is two and the frame c~n~ ' 5 four repe-ffffon~ of s~mrling of two cycles each followed by a delay ~ . Thus, the ~xe~pl~ frame is equal to eight cycles plus 4 ~ . The slow speed ~mpling rate is 32 samples per cycle and ~ is made equal to 1/128 of a cycle so that the sampling frame is equal to 8 cycles plus 1/32 cycle of 15 the fimd~m~nt~l frequency of the waveforms. This provides an equivalent sa..,pling rate of 128 samples per cycle.
In the exemplary system, high speed sampling may be implemented in any one of the repetitions, although the invention is applicable to high speed sampling implem~nted in any two consecutive cycles of the sampling frame. In the exemplary 20 system, high speed sampling, when called for, may, for example, be implemP-nt~d in the fourth repetition within the frame (i.e., the seventh and eighth cycles). Any one of the repetitions can be used for high speed sampling, but it is always the same repetition within the frame. Since high speed sampling is pelror...ed for only one repetition, the ~mpling can be synchronous, a l~uil~lllent for Fourier analysis of the hallllonic content of the waveforms. By synchronous, it is meant that an integernumber of samples are taken per cycle. As the delay, ~, comes at the end of the repetition, it does not disturb the synchronous sampling pe.Çul...ed during only one repetition. The high speed sampling is carried out at a rate that is an integer multiple of the slow speed rate. In the exemplary embodiment, the high speed rate is 128 30 samples per cycle, which is four times the slow speed rate. This permits the slow speed data to be extracted from the high speed data, so that continuous data is available for the calculations pe~ru~lned during the slow speed sampling.
While the s~lP~t~d number of cycles in each repetition is two in the example, other numbers of cycles can be used. However, the number of cycles s~lçsted for each repetition sets the maximum number of cycles of high speed data that can be cQll~ct~ during a frame.
Sampling at the high speed rate for waveform capture can be implemented ~,lo~ y in rcs~oniG to col~ition~ in the AC ~le~ctrir~l power disllibuLon system 3, such as, for inst~n~, an OV~;U~ t con~liti~n~ a trip, a low voltage con-~itiQn~ or the like. In ~dition~ high speed ~?ling c~n be co~ An~
through the front panel 19 or remotely l~lr~ugh the co..~ nic~tions link 21. Also, 10 high speed c-...rlin~ can be in;~ ~ by a dmer (not shown).
Automadc high speed s~ lin~ is i.~ple...f~ ~l by triggers, which are progr~mm~ble. In the exF--..p1s.y analyzer/mo~itor 1, there are seven progr~mm~ble triggers. As shown in Figure 2, the triggers are programmable through the front panel 19 which includes an çl~empl~ry display 23 and four push buttons 25, which function 15 as soft switches in conjunction with associated switch functions that appear on the display 23. As shown, the left. button 25 is a select button as in~ic~t~ by the symbol SEL in the lower left hand corner of the display. Similarly, the second, third and fourth buttons 25 p~.rOlIn UP, DOWN and PGDN (page down) fun~ti~ ~ti~/ely.
The display 23 presents a series of menus. The UP and DOWN buttons permit the 20 user to highlight an item on the menu and then select that item by pushing the SEL
push button. The PGDN push button brings up ~ddition~l pages of the menu (e.g., displaying a waveform). After fully paging down, this soft-key becomes a PGUP push button. Similarly, at the bottom of a menu, this soft-key becomes a TOP push button.
The digital processor 15 runs routines that generate the inte~ )ts for the 25 digital sampling implçm~ntçd by the A/D converter 13. In between sampling, the digital processor 15 runs other routines (e.g., those that calculate the various electrical pararneters, ~~ l input/output functions). One of these additional routines is the check triggers routine 29, which is shown in Figure 3A. When called, the check triggers routine 29 checks each of the seven triggers in sequence. As shown, trigger-l 30 is chçc~çd at 31, by first setting the data pointer to the trigger-l settings at 33. The type of trigger is then deterrnined and the ~soci~ed parameter value is obtained at 35.
If the trigger-1 parameter value exc~s the trigger setting as determined at 37 and this is the first implementation of the routine in which this occurs as deter."ined at 39, then f ,, _ - 8 - 9~PDC~47 a trigger-l ACTIVE FLAG and a trigger-l IN PROCESS FLAG are set at 41 and 43, ~ specti~ely. If the trigger-l p~qr~qmetpr does not exceed the trigger setting and in fact is below the reset setting as determined at 45, then the active flag for trigger-l is cleared at 47. Similar functionc are pelro,l-lcd for trigger-2 through trigger-7 at 312 S through 317, ~ i./ely.
The digital pç~cessor 15 also pçrio~ qlly runs an events/relay routine 49 as shown in Figure 3B. At 51, the routine 49 checks to see if any trigger IN
PROCESS flags (e.g., a push button, a software flag) are set. If so, high speed S~q-mrling iS in;l;At~ at 53 to capture an event. In the eyemplqry system, three10 repetitinnc (six AC cycles) of digital ~qmpl,~5 of the wa~fol...s are ~q~ mlllqt~d before the trigger signal and one repetiti~n (two AC cycles) of digital sq r lrs is accumulated after the trigger signal. C-Apturing an event compricp~c ~qmpling at the high speed and storing the recorded samples. As mentiorle~ in the e~emrlqry system, this is implçmented in the fourth repetitiolt of the two cycle sequence in a sampling frame.
15 Capture is pelrolled sequentially in succeccive frames if more than one trigger is IN
PROCESS. Thus, if all of the triggers are IN PROCESS, the sel~t~d portion of each of the waveforms is captured in seven successive sampling frames. Also, the sameevent can be programmed into multiple triggers. Thus, for inctAnce~ if a particular event is of interest, it can be programmed into all seven triggers, and high speed samples in seven succeccive sampling frame will be recorded. As each trigger initiAtPS high speed sampling, a FAST DATA flag is set and the Accoci-qt~d IN
PROCESS flag is cleared at 53. If a relay is programmed to indicate a trigger at 55, and that trigger is active at 57, the relay is activated at 59. When the trigger is no longer active at 57, the relay is deactivated at 61.
Figure 3C is a flow chart for a timer interrupt routine 63 implemçnt~
by the digital processor 15. A significAnt purpose of the routine 63 is to detect the onset of a disturbance, such as a voltage transient or spike, in the AC waveform of the power distribution system 3 and, then, to capture digit.l samples of the waveform before and after the disturbance. The time of the onset of the disturbance is not known beforehand and, hence, it is important to detect and respond to the disturbance quickly to capture relevant information thereof in a timely manner. Digital samples before the disturbance are sampled at a first or slow rate, while digit~ samples after the disturbance are s. mpled at a second rate, faster than the first rate. The digit~ samples 9 9~PDC 447 are co!l~ct~d in a moving frame to provide a set of pùt~ l samples before the disturbance. After the onset of the distull,ancc is ~cb~t~ by COI~.p~ ;ng the ~gnit~de of ~ 1jA~-nt digital samples, the routine 63 quickly ~s~ s by c~ ll~ting s~s~ c~digital samples at the second fast rate.
Each time the routine 63 is called at 65, analog to digital conversion of the sensed CU~ S and voltages is if it;~ at 67. If s- ~pli~ is being p~ru~ edat the slow rate as d~te . n~d at 69 based on a FAST_DATA flag, the time interval for the next slow intcrrupt is set and the po~t~.~ for storing the slow speed data are set at 71. The ~;u~lcnts and voltages from the previous sample are then squalcd and the power c~lcul~ion from the ~)levious sample is p~rululed at 73. The power calc~ ti~ n is then added to an energy ~ ;on at 75. When eight cycles have been completed as de~v....in~l at 77, the p~c~-c~l values for this frame are saved at 79.
Then, the ~ iti7~ Cull~ lt~ and voltagec geS~e ~led by the A/D ~onve~tcr 13 on this h~t~llupt are saved by routine 81 (as ~i!cculc~d below in connP~1ion with Figure 3D).
15 These are the values that will be used at 73 on the next slow in~lupt to c~lcul~tç the power and rrns values. If this is an even sarnple (int~lupt) as det~.. ined at 83, then an apl,r~pliate "slow data" task is p~lroll..ed at 85.
In order to ~lÇullll Fourier analysis, one-half of the co-~-lJulalion dme available in the digital processor 15 is ~csign~ to pel~llll that fi)nctio~ These 20 colllpu~tions, which generate values for the individual harmonics as a percentage of the fi~n-l~mPnt~l for the analyzed waveforms, are only pe.rolllled during the slow speed sampling. Thus, ~lteTll~te intellupls, for inst~nce the odd intellupt~, initiate analog to digital conversion, and also trigger the col--p~ ions for the Fourier analysis. The le ~ g tasks are ~csigned to the even int~llup~s, which also inidate analog to digital 25 conversions. As the slow s~lll~ling rate is 32 samples per cycle, there are 16 even intellu~Jts per cycle to which tasks can be ~Csigne~. While there are eight cycles in a frame, only six of those cycles are gual~leed as being available to pe.rolll. tasks since the other two cycles must be available for high speed sampling. Therefore, there are 16 x 6 = 96 task slot always available during a frame. There are 16 x 2 = 32 30 additional task slots that will be available if there is no high speed sampling during the frarne. Tasks of lesser i---~l~nce, or requiring less frequency of updating, are~signed to these latter, con~itio~l task slots.
- 10 - 9~PDC 447 As anoll.~ w~; r'e, where high syeed 5~ ylinE is implc ~ ~ in the third ~ ;t;Qn (i.e., the fifth and si~tth cycles) during a frame, it is the task slots ~cci~ to the fourth repetition which are eli....n~l~d during a high speed sampling frame. Thus, the tasks ~sci~ed to even int~.lupts are delayed by high speed ~.~p!in~, 5 and those which normally would have been y~çolllled during the third repetition are instead yc~fûllllcd during the fourth l~pe~il;Qn. The tasks ~x.ru.---ed include c~lc~ tion of total h~.--onic distortion (I~). These c~lculqtiQnc are ye~ru~ ed on the eveninl~.~up~, as they are simple c~lc~llqtiQnC, which only require data ~e-~e~ l by low speed Q-..,pling, the tasks yc~çolllled during any given frame utilize data collPcte~ from 10 the previous frame.
If, on the other hand, this is an odd inte.lupl, a h~...onic data set calcul~tinn is ~lÇol---~ at 87. At 88, after either 85 or 87, a slow speed sample odd/even flag is toggled (for testing at 83) after which the routine 63 is then exited at 89.
During high speed salnpling, as dele~.llined at 69, the time for the next high speed intellupl and the data poil~ for storing high speed data are set at 91.
The point~ are in.;~ n~ and chc~L~d at 93 and on every fourth high speed int~.~u~t the slow speed data is saved. On each high speed inlt;llupt, the high speed data is saved and initial "slow data" procP-s~ing~ such as squaring the cwl~.lts or the 20 voltages, or pelfo~lning hdl--.onic calculations, is pelfolmed in a similar manner as at 85. If two cycles of high speed data have been collected as determined at 9S, the FAST DATA flag is reset at 97 so that the next time the timer int~ pl routine 63 is called, slow speed sampling will be rçsl~med.
The timer intt;llupl routine, during slow speed sampling, provides 32 25 digital samples for each of the ~mpl~ AC cycles of the waveforms. For e~a--.?le, in the exe..-pl~y embodiment for a 60 Hz power distribution system, the exemplary slow speed timer irlell.lpt occurs 60 x 32 = 1920 times per second, in order to provide the digital samples with a periodic time interval b~tw~~ an ~ cet t pair of the digital sa--,ples. Preferably, in order to accommodate an exemplary set of two diff~ellt line-to-line AC power voltages (e.g., 120 Vu and 480 - 600 Vu), the slow speed timer interrupt is set to provide at least about 32 digital samples per AC cycle, although diff~lent counts of s~-l~les per AC cycle are possible. During high speed , 5~mp~ , thc tdmer i~tc..upt roudnc provides 128 digital s~mrl~s for cach of the sampled AC cycles of the waveforms.
Figure 3D is a flow chart for the routine 81 of Pigure 3C which reads and saves the ~ iti7~l cull~nls and voltages ge--~e~ by the A/D converter 13 and5 genc~tcs a value r~le~ht;.~g a change in rnagnitu(le with respect to dme of the AC
waveform from a pair of the digital s rl~s of one of the AC cycles. At 99, the iti7,~ ~u~ ,nls are read and saved and, then, at 101, the ~ iti7~:1 voltages are read and saved. If the ~ligiti7f'd voltages are too large, then the ranging circuit 11 of Figure 1 is suitably adju~t~d. At 103, the newly read voltages are co,llp~,d with the 10 previously saved voltages to gene~ate a co..~p~ on value which is saved. Thiscom~ ;~n value, which in the rYPmpl~ry embo~limPnt is a dV/dt value, ~pr~.ll~ a change in mag~ibJde with respect to time of one of the waveforms as dete~ ed from an ~ Pnt pair of the co.l~po.lding digital samples. P~ef~ably~ the timer inte.lupt routine 63 of Figure 3C is perio~ic~lly eYecuted (i.e. ~ to provide a const~nt slow or 15 fa~st dt value) and a dirr~re.lce between the adjacent pair of digital samples is detel..lined at 103 (i.e.~ to provide a dV value).
A predetermined line-to-line voltage setting is programmed into the memory (not shown) of the digital pr~cessor 15 through the front panel 19 of Figure 1. If this setting (e.g., 120 V~,) is not greater than 125 VAC at 105 then, at 107, if the 20 co,pa ison value saved at 103is greater than a predetermined value, DV DT LMTl, a dV/dt flag is set and a hold-off timer (~ ucse~ below in connection with Figure 3E) is started. Also, at 109, if the sample saved at 103 and the sample saved in theprevious execution of the routine 81 are both less than a pr~detel.,.ined value,L_V_LMTl, then a low voltage flag is set.
On the other hand, if the predetermined line-to-line voltage setting (e.g., 480-600 Vu) is greater than 125 VAC at 105 then, at 111, if the col-~p~ison value saved at 103is greater than a predetermined value, DV DT LMT2, the dV/dt flag isset and the hold-off timer is started. Also, at 113, if the sample saved at 103 and the sample saved in the previous execution of the routine 81 are both less than a predetermined value, L V LMT2, then the low voltage flag is set. After either 109 or 113, the routine 81 returns. In the exemplary embodiment, the predetermined values are set as shown below in Table I.
- 12 - 9~PDC 447 TARLE I
PREDF.TF.~NED VALUE VALUE (V") DV DT LMTl 75 L V LMTl 4.5 L_V_LMT2 8.0 Although two e~ .pl~-y line-to-line pl~d. te.ll~ned voltage s~ffin~c are di~cuc.;ed, it will be ayp~iat~ that the invention is applicable to one, three or more of such setting~, and/or that reconfigurable voltage settings or ranges may be employed.Pigure 3E is a flow chart of a routine 115 for sefflng and cl~in~ trigger flags for either an excess dV/dt trigger (co.lcsponding to 107 or 111 of Figure 3D) or an low voltage trigger (coll~ponding to 109 or 113 of Figure 3D). The exemplary routine 115, which prei~nt~ the excess dV/dt or low voltage triggers from occurring more than once to avoid a continuous stream of triggered events, is called every two 15 line cycles by a slow data task of routine 63, although the invention is applicable to routines which are called at faster or slower rates. At 117, if the appr~pliate flag (i.e., the dV/dt flag of 107 or 111, or the low voltage flag of 109 or 113 of Figure 3D) is set, then, at 119, while the hold-offtimer is less than an exe...plal~ two s~onds, a co~resl~onding (i.e., dV/dt or low voltage) disturbance trigger "IN PROCESS" flag is 20 set. On the other hand, if the hold-off timer is greater than two but less than an exemplary ten seconds, the CG~ onding disturbance trigger "IN PROCESS" flag is not set and, instead, is perlllilled to retain its last set or reset state. Otherwise, at 117, if the a~>rol,liate flag is not set, then, at 121, while the hold-off timer is less than or equal to ten seconds, the co.l~l,onding disturbance trigger "IN PROCESS" flag is not 25 reset and, instead, is permitted to retain its last set or reset state. On the other hand, if the hold-off timer is greater than ten seconds, the corresponding disturbance trigger "IN PROCESS" flag is reset at 121.
The dV/dt or low voltage disturbance trigger "IN PROCESS" flags are employed at 51 as discussed above in connection with Figure 3B. In the exemplary30 embodiment, excess dV/dt triggers and low voltage triggers are generated for a disturbance on any of the phase conductors 5A,SB, 5C of Figure 1. Although predetermined two and ten second time periods are employed, any suitable predetermined and/or reconfigurable time periods may be used.
- 13- 9~PDC447 Figure 4 is a plot of a waveform which is di~iti7~, ~Onit~olu~ and output by thc analy_cr/moni~or 1 Figure 1. The digital processor 15 outputs the digital samples before and after the exe-mpl~ry dVldt event 123 on the front panel display 23 of Figure 2.
S The ex~- npl~y excess dV/dt and low voltage triggers .. o,-itor an AC
waveform for c~n~.~ e digital samples, within an AC cycle, the magnitlJdes of which are too far apart or too close to zcro, r~li~ely. In this ~l~anncr, excessive voltage !.,.fi~ are captulo~ in ~d;~;o~ to I~ .y voltage ih~ ;QI-~. It will be appl~t~ that such ~ ..tc or int~~ tions may be induc~d by line or load side power circuit dial.lplions (e.g., power sourcc pf~blc".s, s~ilching of power factor co.r~t,ng c~ tors, the sudden removal of a load, poor circuit c~n~tions) or by eYt~ l events (e.g., li~htning). By triggering on dV/dt (or voltage interruption), events may be captured and time-st~"pod that otherwise would be missed. In this manner, unusual oc~;u-le,~ces in the system employing the power circuit may be correlated to the power circuit disruption.
Although the exemplary dV/dt flag or trigger signal is set when it is greater than the app~op.iate pred~l~lmil~ed threshold, it will be appreciated that other equivalent trigger signals may be co,llpa~ed to be greater than or equal to a predetermined threshold or that negative logic may be employed. Similarly, although the exemplary low voltage flag or trigger signal is set when an ~dja~Pnt pair of digital samples are both less than the appropliate predetellllined threshold, it will beapl,lcciated that such pair of digital samples may be less than or equal to a predetermined threshold or that negative logic may be employed.
While for clarity of ~i~closure reference has been made herein to the exemplary display 23 for outputting or displaying digital samples, it will be a~l~iated that such samples may be output in analog form, stored, printed on hard copy, computer modified, or combined with other data. All such processing shall be deemed to fall within the terms "output", "outputting", "display" or "displaying" as employed herein.
While specific embodiments of the invention have been described in detail, it will be applcciated by those skilled in the art that various mo lific~tions and alternatives to those details could be developed in light of the overall te~ ing~ of the disclosure. Accordingly, the particular arrangements disclosed are meant to be f - 14 - 9~PDC 447 in~ vc only and not li.~ g as to ~e sco~c of .n~ ion, which i~ to be given thc full bread~ of the claims al pen~ed and any and all eqwvalents thereof.
Referring to Figure 1, the analyzer/monitQr 1 of the invention is used to ...~n;tor and analyze an electric power system, such as the exem~l~ y power distribution system 3. The power distribution system 3 has three phase conductors 5A,SB,5C, a neutral conductor 5N co~n~t~d to an electri~l common of the analyzer/.~on;t~r 1, and a ground conductor 5G. Current tran~Çor,n_.~
7A,7B,7C,7N,7G sense current flowing in these l~Li~e conducto-~ while three phase-to-neutTal voltages are sensed by sensing resistors 9A,9B,9C. A ranging circuit 11 converts the sensed currents and sensed phase voltages to the a~r~p,ia~ range for conversion by a ~:lOV analog-to-digital (A/D) converter 13 for input to a digital pç~cess~r 15, such as, for eY~mrl~., a mic,oco."~ ter or microprocessor. The A/Dconverter 13 s~ 5 the analog signals, which co,l~ond to the sensed cullellts andsensed phase voltages, at intervals de~,l.ined by in~lu~ts gen~ ed by the digital pr~c~ssor lS. The current transformers 7A,7B,7C,7N,7G and sensing resistors 9A,9B,9C sense waveforms (e.g., alle~ g current (AC) waveforms having plural AC cycles) in the power distribution system 3, which may have one of various line-to-line AC power voltages (e.g., 120 Vu, 208 Vu, 480 VD~ 600 V~). For exarnple, theline-to-neutral voltages of the waveforms on the phase conductors SA,5B,SC are sensed by the ç~s~li~e sensing resistors 9A,9B,9C.
In the exemplary embodiment, the digital plocessor interrupts are generated selectively at a first, slow speed sampling rate, or a second, high speed sampling rate. Regardless of the sampling rate, on each interrupt, the A/D converter 13 samples and ~ligiti7~s all five sensed currents and all three sensed phase voltages.
The resulting digital samples of the waveforms, generated by the exemplary A/D
converter 13, are input to the digital processor lS, although the invention is applicable to one or more A/D converters which form part of a digital processor, such as a microcomputer. The ground to neutral voltage between conductors SG and SN is amplified by an input circuit 12 which outputs a ground to neutral voltage signal, Vc,,, to A/D converter 16 in the digital processor lS. The A/D converter 16 converts this analog signal to col.e~onding digital samples.
The digital processor 15 utilizes the digital sarnples of the A/D
converters 13,16 to generate values of two sets of electrical parameters. The first set of parameters is related to the monitoring function and includes metered parameters ( 9~PDC447 such as: RMS c~ e~ts and voltages, peakCIlll~ S and voltages, minimllm currents and voltages, power factor, watts, Vars, volt-amps, total harmonic distortion K-factor, CBEMA deradng factor, ch. nge in volt. ges with respect to dme (e.g., dV/dt values) and the like. The second set of pal~nct~ c-q-lc~lqt~ by the digit l pç~cessor 15S comr~s individual ha,luonic c4crr~c - ~~ts Data coll~tion a nd p~ s~n~, e~ ud the a~ q~;nt~ of the e,~c---p~ Dv/dt values, are o,E~ni~1 in the l~Ulrltr de~ibed in U.S. Patent No; 5,587,917, which is ~cG~ t~d herein by ~f~c~ , so that a m~ nU~ nu.nbcr of ~.ul.~ ~.s can be ~onitul~d cQn~;n~ou~l~ while ~so providing the cqphility for simllltvq~l~ous cqlcul-l;ol~ of h~ulllonic cont~.nt The digital ploces30r lS has . n input/output a/O) circuit 17 llu~ugh which such p~cessor is ~nn~t~d to a front panel 19. The front panel 19 serves asan interf~ with a user. The user can control the operation of the analyzer/..~onit~r 1 through the front panel 19 and monit~r the AC e~ic~l power system 3. The IIO
circuit 17 also int~.r~ the digital pr~ssor lS with contact inputs through digital lS inputs and with an external device (not shown) through relay outputs and analog outputs. The digital pr~cessor lS can also communicate with a remote processor (not shown) lh~o~ ) a co.. ~ ications link 21. Through this communi~tions link 21, the analyzer/...... .......~onilor 1 can provide infol"lalion to and/or be controlled by the remote ~l'~C~SSO~.
The digital processor lS generates its h~te.lupts to provide a slow rate for moniloling and a faster rate for data capture in order to control the burden on such processor so that all of the l~uil~d functions can be pe.~l,..ed. The exemplary sampling scheme used by the digital plocessor lS, e~tclllding the c~lcul~tion of Dv/dt values, is the same as that described in U.S. Patent No. S,587,917, referenced above, although the present invention is applicable to a wide variety of techniques forsampling a waveform and genel~dting a value repr~ g a change in m~gnil~lde with respect to time of the waveform from a pair of the digital samples of one of the AC
cycles of an AC waveform, (e.g., periodic sampling of digital samples, periodic or aperiodic sampling of digital samples along with coll~ ing time values).
As is known, waveform capture l~quir~s synchronous sampling at a rate that is at least twice that of the highest harmonic to be eAll~,~d. The monilolii g functions, on the other hand, do not require synchronous s~mpling. Hence, the technique known as equivalent sampling is used for the slow speed sampling in order f - 6 - 96-PDC~47 to inc~asc the effective $~..plin~ rate. In the equivalent s~..p~ technique, the AC
wavefo..lls are sqmrl~ a se1~t~d n~)mbPr of times per cycle with a delay of a fraction of a cycle before another cycle of s~llplcs is ta~en at the same sampling rate. Thus, the ~.npl;n~ inctqnt~ are ~bumped" each cycle by the selc~l~cl fraction of a cycle. The S data cQllect~d over a n~ of such '~bulllped'~ cycles are then used to c~lculqte various ~ t~
Equivalent ~...pli~-g at slow speed with s. t~ high speed 5~.,plil~
for waveform capture is implem~t~ by s--~ pli~ in frames. Each ~-"~l li--~ framecompri~,s a n~ l~r of r~ffffonc of ~ ling for a Sf,~C~t~YI num~,r of cycles followed 10 by a delay which is a fir~pQt~ of a cyde. In the ~ P1~Y system, the ~Pl~t~d ~-u-..be~ of cycles is two and the frame c~n~ ' 5 four repe-ffffon~ of s~mrling of two cycles each followed by a delay ~ . Thus, the ~xe~pl~ frame is equal to eight cycles plus 4 ~ . The slow speed ~mpling rate is 32 samples per cycle and ~ is made equal to 1/128 of a cycle so that the sampling frame is equal to 8 cycles plus 1/32 cycle of 15 the fimd~m~nt~l frequency of the waveforms. This provides an equivalent sa..,pling rate of 128 samples per cycle.
In the exemplary system, high speed sampling may be implemented in any one of the repetitions, although the invention is applicable to high speed sampling implem~nted in any two consecutive cycles of the sampling frame. In the exemplary 20 system, high speed sampling, when called for, may, for example, be implemP-nt~d in the fourth repetition within the frame (i.e., the seventh and eighth cycles). Any one of the repetitions can be used for high speed sampling, but it is always the same repetition within the frame. Since high speed sampling is pelror...ed for only one repetition, the ~mpling can be synchronous, a l~uil~lllent for Fourier analysis of the hallllonic content of the waveforms. By synchronous, it is meant that an integernumber of samples are taken per cycle. As the delay, ~, comes at the end of the repetition, it does not disturb the synchronous sampling pe.Çul...ed during only one repetition. The high speed sampling is carried out at a rate that is an integer multiple of the slow speed rate. In the exemplary embodiment, the high speed rate is 128 30 samples per cycle, which is four times the slow speed rate. This permits the slow speed data to be extracted from the high speed data, so that continuous data is available for the calculations pe~ru~lned during the slow speed sampling.
While the s~lP~t~d number of cycles in each repetition is two in the example, other numbers of cycles can be used. However, the number of cycles s~lçsted for each repetition sets the maximum number of cycles of high speed data that can be cQll~ct~ during a frame.
Sampling at the high speed rate for waveform capture can be implemented ~,lo~ y in rcs~oniG to col~ition~ in the AC ~le~ctrir~l power disllibuLon system 3, such as, for inst~n~, an OV~;U~ t con~liti~n~ a trip, a low voltage con-~itiQn~ or the like. In ~dition~ high speed ~?ling c~n be co~ An~
through the front panel 19 or remotely l~lr~ugh the co..~ nic~tions link 21. Also, 10 high speed c-...rlin~ can be in;~ ~ by a dmer (not shown).
Automadc high speed s~ lin~ is i.~ple...f~ ~l by triggers, which are progr~mm~ble. In the exF--..p1s.y analyzer/mo~itor 1, there are seven progr~mm~ble triggers. As shown in Figure 2, the triggers are programmable through the front panel 19 which includes an çl~empl~ry display 23 and four push buttons 25, which function 15 as soft switches in conjunction with associated switch functions that appear on the display 23. As shown, the left. button 25 is a select button as in~ic~t~ by the symbol SEL in the lower left hand corner of the display. Similarly, the second, third and fourth buttons 25 p~.rOlIn UP, DOWN and PGDN (page down) fun~ti~ ~ti~/ely.
The display 23 presents a series of menus. The UP and DOWN buttons permit the 20 user to highlight an item on the menu and then select that item by pushing the SEL
push button. The PGDN push button brings up ~ddition~l pages of the menu (e.g., displaying a waveform). After fully paging down, this soft-key becomes a PGUP push button. Similarly, at the bottom of a menu, this soft-key becomes a TOP push button.
The digital processor 15 runs routines that generate the inte~ )ts for the 25 digital sampling implçm~ntçd by the A/D converter 13. In between sampling, the digital processor 15 runs other routines (e.g., those that calculate the various electrical pararneters, ~~ l input/output functions). One of these additional routines is the check triggers routine 29, which is shown in Figure 3A. When called, the check triggers routine 29 checks each of the seven triggers in sequence. As shown, trigger-l 30 is chçc~çd at 31, by first setting the data pointer to the trigger-l settings at 33. The type of trigger is then deterrnined and the ~soci~ed parameter value is obtained at 35.
If the trigger-1 parameter value exc~s the trigger setting as determined at 37 and this is the first implementation of the routine in which this occurs as deter."ined at 39, then f ,, _ - 8 - 9~PDC~47 a trigger-l ACTIVE FLAG and a trigger-l IN PROCESS FLAG are set at 41 and 43, ~ specti~ely. If the trigger-l p~qr~qmetpr does not exceed the trigger setting and in fact is below the reset setting as determined at 45, then the active flag for trigger-l is cleared at 47. Similar functionc are pelro,l-lcd for trigger-2 through trigger-7 at 312 S through 317, ~ i./ely.
The digital pç~cessor 15 also pçrio~ qlly runs an events/relay routine 49 as shown in Figure 3B. At 51, the routine 49 checks to see if any trigger IN
PROCESS flags (e.g., a push button, a software flag) are set. If so, high speed S~q-mrling iS in;l;At~ at 53 to capture an event. In the eyemplqry system, three10 repetitinnc (six AC cycles) of digital ~qmpl,~5 of the wa~fol...s are ~q~ mlllqt~d before the trigger signal and one repetiti~n (two AC cycles) of digital sq r lrs is accumulated after the trigger signal. C-Apturing an event compricp~c ~qmpling at the high speed and storing the recorded samples. As mentiorle~ in the e~emrlqry system, this is implçmented in the fourth repetitiolt of the two cycle sequence in a sampling frame.
15 Capture is pelrolled sequentially in succeccive frames if more than one trigger is IN
PROCESS. Thus, if all of the triggers are IN PROCESS, the sel~t~d portion of each of the waveforms is captured in seven successive sampling frames. Also, the sameevent can be programmed into multiple triggers. Thus, for inctAnce~ if a particular event is of interest, it can be programmed into all seven triggers, and high speed samples in seven succeccive sampling frame will be recorded. As each trigger initiAtPS high speed sampling, a FAST DATA flag is set and the Accoci-qt~d IN
PROCESS flag is cleared at 53. If a relay is programmed to indicate a trigger at 55, and that trigger is active at 57, the relay is activated at 59. When the trigger is no longer active at 57, the relay is deactivated at 61.
Figure 3C is a flow chart for a timer interrupt routine 63 implemçnt~
by the digital processor 15. A significAnt purpose of the routine 63 is to detect the onset of a disturbance, such as a voltage transient or spike, in the AC waveform of the power distribution system 3 and, then, to capture digit.l samples of the waveform before and after the disturbance. The time of the onset of the disturbance is not known beforehand and, hence, it is important to detect and respond to the disturbance quickly to capture relevant information thereof in a timely manner. Digital samples before the disturbance are sampled at a first or slow rate, while digit~ samples after the disturbance are s. mpled at a second rate, faster than the first rate. The digit~ samples 9 9~PDC 447 are co!l~ct~d in a moving frame to provide a set of pùt~ l samples before the disturbance. After the onset of the distull,ancc is ~cb~t~ by COI~.p~ ;ng the ~gnit~de of ~ 1jA~-nt digital samples, the routine 63 quickly ~s~ s by c~ ll~ting s~s~ c~digital samples at the second fast rate.
Each time the routine 63 is called at 65, analog to digital conversion of the sensed CU~ S and voltages is if it;~ at 67. If s- ~pli~ is being p~ru~ edat the slow rate as d~te . n~d at 69 based on a FAST_DATA flag, the time interval for the next slow intcrrupt is set and the po~t~.~ for storing the slow speed data are set at 71. The ~;u~lcnts and voltages from the previous sample are then squalcd and the power c~lcul~ion from the ~)levious sample is p~rululed at 73. The power calc~ ti~ n is then added to an energy ~ ;on at 75. When eight cycles have been completed as de~v....in~l at 77, the p~c~-c~l values for this frame are saved at 79.
Then, the ~ iti7~ Cull~ lt~ and voltagec geS~e ~led by the A/D ~onve~tcr 13 on this h~t~llupt are saved by routine 81 (as ~i!cculc~d below in connP~1ion with Figure 3D).
15 These are the values that will be used at 73 on the next slow in~lupt to c~lcul~tç the power and rrns values. If this is an even sarnple (int~lupt) as det~.. ined at 83, then an apl,r~pliate "slow data" task is p~lroll..ed at 85.
In order to ~lÇullll Fourier analysis, one-half of the co-~-lJulalion dme available in the digital processor 15 is ~csign~ to pel~llll that fi)nctio~ These 20 colllpu~tions, which generate values for the individual harmonics as a percentage of the fi~n-l~mPnt~l for the analyzed waveforms, are only pe.rolllled during the slow speed sampling. Thus, ~lteTll~te intellupls, for inst~nce the odd intellupt~, initiate analog to digital conversion, and also trigger the col--p~ ions for the Fourier analysis. The le ~ g tasks are ~csigned to the even int~llup~s, which also inidate analog to digital 25 conversions. As the slow s~lll~ling rate is 32 samples per cycle, there are 16 even intellu~Jts per cycle to which tasks can be ~Csigne~. While there are eight cycles in a frame, only six of those cycles are gual~leed as being available to pe.rolll. tasks since the other two cycles must be available for high speed sampling. Therefore, there are 16 x 6 = 96 task slot always available during a frame. There are 16 x 2 = 32 30 additional task slots that will be available if there is no high speed sampling during the frarne. Tasks of lesser i---~l~nce, or requiring less frequency of updating, are~signed to these latter, con~itio~l task slots.
- 10 - 9~PDC 447 As anoll.~ w~; r'e, where high syeed 5~ ylinE is implc ~ ~ in the third ~ ;t;Qn (i.e., the fifth and si~tth cycles) during a frame, it is the task slots ~cci~ to the fourth repetition which are eli....n~l~d during a high speed sampling frame. Thus, the tasks ~sci~ed to even int~.lupts are delayed by high speed ~.~p!in~, 5 and those which normally would have been y~çolllled during the third repetition are instead yc~fûllllcd during the fourth l~pe~il;Qn. The tasks ~x.ru.---ed include c~lc~ tion of total h~.--onic distortion (I~). These c~lculqtiQnc are ye~ru~ ed on the eveninl~.~up~, as they are simple c~lc~llqtiQnC, which only require data ~e-~e~ l by low speed Q-..,pling, the tasks yc~çolllled during any given frame utilize data collPcte~ from 10 the previous frame.
If, on the other hand, this is an odd inte.lupl, a h~...onic data set calcul~tinn is ~lÇol---~ at 87. At 88, after either 85 or 87, a slow speed sample odd/even flag is toggled (for testing at 83) after which the routine 63 is then exited at 89.
During high speed salnpling, as dele~.llined at 69, the time for the next high speed intellupl and the data poil~ for storing high speed data are set at 91.
The point~ are in.;~ n~ and chc~L~d at 93 and on every fourth high speed int~.~u~t the slow speed data is saved. On each high speed inlt;llupt, the high speed data is saved and initial "slow data" procP-s~ing~ such as squaring the cwl~.lts or the 20 voltages, or pelfo~lning hdl--.onic calculations, is pelfolmed in a similar manner as at 85. If two cycles of high speed data have been collected as determined at 9S, the FAST DATA flag is reset at 97 so that the next time the timer int~ pl routine 63 is called, slow speed sampling will be rçsl~med.
The timer intt;llupl routine, during slow speed sampling, provides 32 25 digital samples for each of the ~mpl~ AC cycles of the waveforms. For e~a--.?le, in the exe..-pl~y embodiment for a 60 Hz power distribution system, the exemplary slow speed timer irlell.lpt occurs 60 x 32 = 1920 times per second, in order to provide the digital samples with a periodic time interval b~tw~~ an ~ cet t pair of the digital sa--,ples. Preferably, in order to accommodate an exemplary set of two diff~ellt line-to-line AC power voltages (e.g., 120 Vu and 480 - 600 Vu), the slow speed timer interrupt is set to provide at least about 32 digital samples per AC cycle, although diff~lent counts of s~-l~les per AC cycle are possible. During high speed , 5~mp~ , thc tdmer i~tc..upt roudnc provides 128 digital s~mrl~s for cach of the sampled AC cycles of the waveforms.
Figure 3D is a flow chart for the routine 81 of Pigure 3C which reads and saves the ~ iti7~l cull~nls and voltages ge--~e~ by the A/D converter 13 and5 genc~tcs a value r~le~ht;.~g a change in rnagnitu(le with respect to dme of the AC
waveform from a pair of the digital s rl~s of one of the AC cycles. At 99, the iti7,~ ~u~ ,nls are read and saved and, then, at 101, the ~ iti7~:1 voltages are read and saved. If the ~ligiti7f'd voltages are too large, then the ranging circuit 11 of Figure 1 is suitably adju~t~d. At 103, the newly read voltages are co,llp~,d with the 10 previously saved voltages to gene~ate a co..~p~ on value which is saved. Thiscom~ ;~n value, which in the rYPmpl~ry embo~limPnt is a dV/dt value, ~pr~.ll~ a change in mag~ibJde with respect to time of one of the waveforms as dete~ ed from an ~ Pnt pair of the co.l~po.lding digital samples. P~ef~ably~ the timer inte.lupt routine 63 of Figure 3C is perio~ic~lly eYecuted (i.e. ~ to provide a const~nt slow or 15 fa~st dt value) and a dirr~re.lce between the adjacent pair of digital samples is detel..lined at 103 (i.e.~ to provide a dV value).
A predetermined line-to-line voltage setting is programmed into the memory (not shown) of the digital pr~cessor 15 through the front panel 19 of Figure 1. If this setting (e.g., 120 V~,) is not greater than 125 VAC at 105 then, at 107, if the 20 co,pa ison value saved at 103is greater than a predetermined value, DV DT LMTl, a dV/dt flag is set and a hold-off timer (~ ucse~ below in connection with Figure 3E) is started. Also, at 109, if the sample saved at 103 and the sample saved in theprevious execution of the routine 81 are both less than a pr~detel.,.ined value,L_V_LMTl, then a low voltage flag is set.
On the other hand, if the predetermined line-to-line voltage setting (e.g., 480-600 Vu) is greater than 125 VAC at 105 then, at 111, if the col-~p~ison value saved at 103is greater than a predetermined value, DV DT LMT2, the dV/dt flag isset and the hold-off timer is started. Also, at 113, if the sample saved at 103 and the sample saved in the previous execution of the routine 81 are both less than a predetermined value, L V LMT2, then the low voltage flag is set. After either 109 or 113, the routine 81 returns. In the exemplary embodiment, the predetermined values are set as shown below in Table I.
- 12 - 9~PDC 447 TARLE I
PREDF.TF.~NED VALUE VALUE (V") DV DT LMTl 75 L V LMTl 4.5 L_V_LMT2 8.0 Although two e~ .pl~-y line-to-line pl~d. te.ll~ned voltage s~ffin~c are di~cuc.;ed, it will be ayp~iat~ that the invention is applicable to one, three or more of such setting~, and/or that reconfigurable voltage settings or ranges may be employed.Pigure 3E is a flow chart of a routine 115 for sefflng and cl~in~ trigger flags for either an excess dV/dt trigger (co.lcsponding to 107 or 111 of Figure 3D) or an low voltage trigger (coll~ponding to 109 or 113 of Figure 3D). The exemplary routine 115, which prei~nt~ the excess dV/dt or low voltage triggers from occurring more than once to avoid a continuous stream of triggered events, is called every two 15 line cycles by a slow data task of routine 63, although the invention is applicable to routines which are called at faster or slower rates. At 117, if the appr~pliate flag (i.e., the dV/dt flag of 107 or 111, or the low voltage flag of 109 or 113 of Figure 3D) is set, then, at 119, while the hold-offtimer is less than an exe...plal~ two s~onds, a co~resl~onding (i.e., dV/dt or low voltage) disturbance trigger "IN PROCESS" flag is 20 set. On the other hand, if the hold-off timer is greater than two but less than an exemplary ten seconds, the CG~ onding disturbance trigger "IN PROCESS" flag is not set and, instead, is perlllilled to retain its last set or reset state. Otherwise, at 117, if the a~>rol,liate flag is not set, then, at 121, while the hold-off timer is less than or equal to ten seconds, the co.l~l,onding disturbance trigger "IN PROCESS" flag is not 25 reset and, instead, is permitted to retain its last set or reset state. On the other hand, if the hold-off timer is greater than ten seconds, the corresponding disturbance trigger "IN PROCESS" flag is reset at 121.
The dV/dt or low voltage disturbance trigger "IN PROCESS" flags are employed at 51 as discussed above in connection with Figure 3B. In the exemplary30 embodiment, excess dV/dt triggers and low voltage triggers are generated for a disturbance on any of the phase conductors 5A,SB, 5C of Figure 1. Although predetermined two and ten second time periods are employed, any suitable predetermined and/or reconfigurable time periods may be used.
- 13- 9~PDC447 Figure 4 is a plot of a waveform which is di~iti7~, ~Onit~olu~ and output by thc analy_cr/moni~or 1 Figure 1. The digital processor 15 outputs the digital samples before and after the exe-mpl~ry dVldt event 123 on the front panel display 23 of Figure 2.
S The ex~- npl~y excess dV/dt and low voltage triggers .. o,-itor an AC
waveform for c~n~.~ e digital samples, within an AC cycle, the magnitlJdes of which are too far apart or too close to zcro, r~li~ely. In this ~l~anncr, excessive voltage !.,.fi~ are captulo~ in ~d;~;o~ to I~ .y voltage ih~ ;QI-~. It will be appl~t~ that such ~ ..tc or int~~ tions may be induc~d by line or load side power circuit dial.lplions (e.g., power sourcc pf~blc".s, s~ilching of power factor co.r~t,ng c~ tors, the sudden removal of a load, poor circuit c~n~tions) or by eYt~ l events (e.g., li~htning). By triggering on dV/dt (or voltage interruption), events may be captured and time-st~"pod that otherwise would be missed. In this manner, unusual oc~;u-le,~ces in the system employing the power circuit may be correlated to the power circuit disruption.
Although the exemplary dV/dt flag or trigger signal is set when it is greater than the app~op.iate pred~l~lmil~ed threshold, it will be appreciated that other equivalent trigger signals may be co,llpa~ed to be greater than or equal to a predetermined threshold or that negative logic may be employed. Similarly, although the exemplary low voltage flag or trigger signal is set when an ~dja~Pnt pair of digital samples are both less than the appropliate predetellllined threshold, it will beapl,lcciated that such pair of digital samples may be less than or equal to a predetermined threshold or that negative logic may be employed.
While for clarity of ~i~closure reference has been made herein to the exemplary display 23 for outputting or displaying digital samples, it will be a~l~iated that such samples may be output in analog form, stored, printed on hard copy, computer modified, or combined with other data. All such processing shall be deemed to fall within the terms "output", "outputting", "display" or "displaying" as employed herein.
While specific embodiments of the invention have been described in detail, it will be applcciated by those skilled in the art that various mo lific~tions and alternatives to those details could be developed in light of the overall te~ ing~ of the disclosure. Accordingly, the particular arrangements disclosed are meant to be f - 14 - 9~PDC 447 in~ vc only and not li.~ g as to ~e sco~c of .n~ ion, which i~ to be given thc full bread~ of the claims al pen~ed and any and all eqwvalents thereof.
Claims (20)
1. An apparatus for monitoring an electric power system including an alternating current (AC) waveform having a plurality of AC cycles, said apparatus comprising:
sensing means for sensing said AC waveform;
sampling means for sampling said AC waveform sensed by said sensing means; and digital processing means comprising:
means cooperating with said sampling means for providing a plurality of digital samples of said AC waveform for each of some of the AC cycles of said AC waveform, means for generating a value representing a change in magnitude with respect to time of said AC waveform from a pair of the digital samples of one of the AC cycles, trigger means for generating at least one trigger signal, with said trigger signal being a function of said value representing a change inmagnitude with respect to time of said AC waveform and a predetermined threshold, and capture means for capturing said digital samples of said AC waveform in response to said trigger signal.
sensing means for sensing said AC waveform;
sampling means for sampling said AC waveform sensed by said sensing means; and digital processing means comprising:
means cooperating with said sampling means for providing a plurality of digital samples of said AC waveform for each of some of the AC cycles of said AC waveform, means for generating a value representing a change in magnitude with respect to time of said AC waveform from a pair of the digital samples of one of the AC cycles, trigger means for generating at least one trigger signal, with said trigger signal being a function of said value representing a change inmagnitude with respect to time of said AC waveform and a predetermined threshold, and capture means for capturing said digital samples of said AC waveform in response to said trigger signal.
2. The apparatus of Claim 1 wherein said sensing means includes means for sensing a voltage of said AC waveform; and wherein said means for generating a value includes means for generating a dV/dt value as said value generating a change in magnitude with respect to time of said AC waveform.
3. The apparatus of Claim 1 wherein said means cooperating with said sampling means provides at least about 32 digital samples for said each of some of the AC cycles of said AC waveform.
4. The apparatus of Claim 1 wherein said means cooperating with said sampling means includes means for providing said digital samples with a periodic time interval between an adjacent pair of said digital samples; and wherein said means for generating a value includes means for comparing the adjacent pair of said digital samples to determine said value representing a change in magnitude with respect to time of said AC waveform.
5. The apparatus of Claim 4 wherein said means for comparing includes means for determining a difference between the adjacent pair of said digital samples as said value representing a change in magnitude with respect to time of said AC waveform; and wherein said trigger means includes means for generating the trigger signal when said difference is about greater than the predetermined threshold.
6. The apparatus of Claim 1 wherein said digital processing means includes means for selecting one of a plurality of predetermined thresholds as said predetermined threshold.
7. The apparatus of Claim 6 wherein said electric power system includes at least two voltages; and wherein said trigger means includes a first predetermined threshold for a first voltage and a second predetermined threshold for a second voltage.
8. The apparatus of Claim 1 wherein said predetermined threshold is a first predetermined threshold; and wherein said trigger means includes means for generating a first trigger signal when said value representing a change in magnitude with respect to time of said AC waveform is about greater than the first predetermined threshold, and means for generating a second trigger signal when both of the pair of said digital samples are about less than a second predetermined threshold.
9. The apparatus of Claim 8 wherein said digital processing means includes means for selecting one of a plurality of predetermined thresholds as the second predetermined threshold.
10. The apparatus of Claim 9 wherein said electric power system includes at least two voltages; and wherein said trigger means includes a first one of the predetermined thresholds for a first voltage and a second one of the predetermined thresholds for a second voltage.
11. The apparatus of Claim 8 wherein said means for generating a second trigger signal generates the second trigger signal when both of the pair of said digital samples are less than the second predetermined threshold.
12. The apparatus of Claim 8 wherein said means for generating a second trigger signal generates the second trigger signal when both of the pair of said digital samples are less than or equal to the second predetermined threshold.
13. The apparatus of Claim 1 wherein said digital processing means includes means for outputting said digital samples.
14. The apparatus of Claim 13 wherein said means for outputting includes means for displaying said digital samples.
15. The apparatus of Claim 1 wherein said trigger means includes means for generating the trigger signal when said value representing a change inmagnitude with respect to time of said AC waveform is greater than the predetermined threshold.
16. The apparatus of Claim 1 wherein said trigger means includes means for generating the trigger signal when said value representing a change inmagnitude with respect to time of said AC waveform is greater than or equal to the predetermined threshold.
17. The apparatus of Claim 1 wherein the digital samples of said means cooperating with said sampling means includes a plurality of the digital samples before said trigger signal and a plurality of the digital samples after said trigger signal.
18. The apparatus of Claim 17 wherein said means cooperating with said sampling means includes means for saving the digital samples before said trigger signal at a first rate and means for saving the digital samples after said trigger signal at a second rate which is faster than the first rate.
19. An apparatus for monitoring an electric power system including a waveform, said apparatus comprising:
sensing means for sensing said waveform;
sampling means for sampling said waveform sensed by said sensing means; and digital predetermined means comprising:
means cooperating with said sampling means for providing a plurality of digital samples of said waveform, means for generating a value representing a change in magnitude with respect to time of said waveform from an adjacent pair of the digital samples, trigger means for generating at least one trigger signal, with said trigger signal being a function of said value representing a change inmagnitude with respect to time of said waveform and a predetermined threshold, and capture means for capturing said digital samples of said waveform in response to said trigger signal.
sensing means for sensing said waveform;
sampling means for sampling said waveform sensed by said sensing means; and digital predetermined means comprising:
means cooperating with said sampling means for providing a plurality of digital samples of said waveform, means for generating a value representing a change in magnitude with respect to time of said waveform from an adjacent pair of the digital samples, trigger means for generating at least one trigger signal, with said trigger signal being a function of said value representing a change inmagnitude with respect to time of said waveform and a predetermined threshold, and capture means for capturing said digital samples of said waveform in response to said trigger signal.
20. The apparatus of Claim 19 wherein said waveform is an alternating current (AC) waveform having a plurality of AC cycles; wherein said means cooperating with said sampling means includes means for providing said digital samples with a periodic time interval between the adjacent pair of said digital samples; and wherein said means for generating a value includes means for comparing the adjacent pair of said digital samples to determine said value representing a change in magnitude with respect to time within one of the AC cycles of said AC waveform.
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| US08/811,377 US5890097A (en) | 1997-03-04 | 1997-03-04 | Apparatus for waveform disturbance monitoring for an electric power system |
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| EP (1) | EP0863596B1 (en) |
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| US5627718A (en) * | 1994-11-18 | 1997-05-06 | Eaton Corporation | Apparatus providing protection and metering in an ac electrical system utilizing a multi-function sampling technique |
| US5600527A (en) * | 1994-12-22 | 1997-02-04 | Eaton Corporation | Circuit interrupter providing protection and waveform capture for harmonic analysis |
| US5706204A (en) * | 1996-02-28 | 1998-01-06 | Eaton Corporation | Apparatus for triggering alarms and waveform capture in an electric power system |
-
1997
- 1997-03-04 US US08/811,377 patent/US5890097A/en not_active Expired - Lifetime
-
1998
- 1998-02-19 EP EP98102939A patent/EP0863596B1/en not_active Expired - Lifetime
- 1998-02-19 DE DE69839289T patent/DE69839289T2/en not_active Expired - Lifetime
- 1998-03-03 CA CA002230735A patent/CA2230735A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| DE69839289T2 (en) | 2009-04-09 |
| US5890097A (en) | 1999-03-30 |
| DE69839289D1 (en) | 2008-05-08 |
| EP0863596B1 (en) | 2008-03-26 |
| EP0863596A1 (en) | 1998-09-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued |