CA2211083A1 - Address transformation in a cluster computer system - Google Patents

Address transformation in a cluster computer system

Info

Publication number
CA2211083A1
CA2211083A1 CA002211083A CA2211083A CA2211083A1 CA 2211083 A1 CA2211083 A1 CA 2211083A1 CA 002211083 A CA002211083 A CA 002211083A CA 2211083 A CA2211083 A CA 2211083A CA 2211083 A1 CA2211083 A1 CA 2211083A1
Authority
CA
Canada
Prior art keywords
space
cluster
external
internal
external memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002211083A
Other languages
French (fr)
Other versions
CA2211083C (en
Inventor
Russell W. Guenthner
Leonard Rabins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Bull Hn Information Systems Inc.
Russell W. Guenthner
Leonard Rabins
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull Hn Information Systems Inc., Russell W. Guenthner, Leonard Rabins filed Critical Bull Hn Information Systems Inc.
Publication of CA2211083A1 publication Critical patent/CA2211083A1/en
Application granted granted Critical
Publication of CA2211083C publication Critical patent/CA2211083C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache

Abstract

To integrate a plurality of processors (11-14), each capable of directly addressing a limited internal storage range, with a large external memory, processors are organized into clusters, each having a plurality of processors and a common secondary cache (7). An address translator (18) is provided to transform internal main memory space (8) addresses to external memory space addresses. External memory space is divided into private and shared areas. An internal address indicator bit, in conjuction with the cluster number form a requesting processor primary cache, is employed to set up the transformation either to the private external space of the cluster or the shared external space. In reverse external-to-internal transformation, a pair of indicator bits are used to generate the internal address and define the shared and private space of the designated cluster. A cluster member number assigned to each processor is used by the secondary cache to track with processor sends/receives information to/from the external memory.
CA002211083A 1995-10-06 1996-10-04 Address transformation in a cluster computer system Expired - Fee Related CA2211083C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/540,106 1995-10-06
US08/540,106 US5590301A (en) 1995-10-06 1995-10-06 Address transformation in a cluster computer system
PCT/US1996/015937 WO1997013191A1 (en) 1995-10-06 1996-10-04 Address transformation in a cluster computer system

Publications (2)

Publication Number Publication Date
CA2211083A1 true CA2211083A1 (en) 1997-04-10
CA2211083C CA2211083C (en) 2003-05-20

Family

ID=24154013

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002211083A Expired - Fee Related CA2211083C (en) 1995-10-06 1996-10-04 Address transformation in a cluster computer system

Country Status (6)

Country Link
US (1) US5590301A (en)
EP (1) EP0855057B1 (en)
JP (1) JPH11512857A (en)
CA (1) CA2211083C (en)
DE (1) DE69635865T2 (en)
WO (1) WO1997013191A1 (en)

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US5884098A (en) * 1996-04-18 1999-03-16 Emc Corporation RAID controller system utilizing front end and back end caching systems including communication path connecting two caching systems and synchronizing allocation of blocks in caching systems
US5940870A (en) * 1996-05-21 1999-08-17 Industrial Technology Research Institute Address translation for shared-memory multiprocessor clustering
US5933857A (en) * 1997-04-25 1999-08-03 Hewlett-Packard Co. Accessing multiple independent microkernels existing in a globally shared memory system
JP2001509610A (en) * 1997-07-02 2001-07-24 クリエイティヴ テクノロジー リミテッド Audio effects processor with decoupling instruction execution and audio data sequence
JP3866426B2 (en) * 1998-11-05 2007-01-10 日本電気株式会社 Memory fault processing method in cluster computer and cluster computer
US6314501B1 (en) 1998-07-23 2001-11-06 Unisys Corporation Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory
JP3976432B2 (en) * 1998-12-09 2007-09-19 エヌイーシーコンピュータテクノ株式会社 Data processing apparatus and data processing method
US6801937B1 (en) 2000-05-31 2004-10-05 International Business Machines Corporation Method, system and program products for defining nodes to a cluster
US7769823B2 (en) * 2001-09-28 2010-08-03 F5 Networks, Inc. Method and system for distributing requests for content
US6868483B2 (en) * 2002-09-26 2005-03-15 Bull Hn Information Systems Inc. Balanced access to prevent gateword dominance in a multiprocessor write-into-cache environment
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US7917658B2 (en) 2003-01-21 2011-03-29 Emulex Design And Manufacturing Corporation Switching apparatus and method for link initialization in a shared I/O environment
US8102843B2 (en) 2003-01-21 2012-01-24 Emulex Design And Manufacturing Corporation Switching apparatus and method for providing shared I/O within a load-store fabric
US8032659B2 (en) * 2003-01-21 2011-10-04 Nextio Inc. Method and apparatus for a shared I/O network interface controller
US8346884B2 (en) 2003-01-21 2013-01-01 Nextio Inc. Method and apparatus for a shared I/O network interface controller
US7046668B2 (en) * 2003-01-21 2006-05-16 Pettey Christopher J Method and apparatus for shared I/O in a load/store fabric
US7617333B2 (en) 2003-01-21 2009-11-10 Nextio Inc. Fibre channel controller shareable by a plurality of operating system domains within a load-store architecture
US7103064B2 (en) 2003-01-21 2006-09-05 Nextio Inc. Method and apparatus for shared I/O in a load/store fabric
US7836211B2 (en) 2003-01-21 2010-11-16 Emulex Design And Manufacturing Corporation Shared input/output load-store architecture
US7698483B2 (en) 2003-01-21 2010-04-13 Nextio, Inc. Switching apparatus and method for link initialization in a shared I/O environment
US7953074B2 (en) 2003-01-21 2011-05-31 Emulex Design And Manufacturing Corporation Apparatus and method for port polarity initialization in a shared I/O device
US7664909B2 (en) 2003-04-18 2010-02-16 Nextio, Inc. Method and apparatus for a shared I/O serial ATA controller
JP2007115223A (en) * 2005-09-20 2007-05-10 Sharp Corp Processor and method of configuring multiprocessor
TWI301270B (en) * 2006-06-30 2008-09-21 Winbond Electronics Corp Semiconductor memory and circuit and method of decoding address for the same
WO2014190486A1 (en) * 2013-05-28 2014-12-04 华为技术有限公司 Method and system for supporting resource isolation under multi-core architecture
WO2016159765A1 (en) * 2015-03-27 2016-10-06 Recore Systems B.V. Many-core processor architecture and many-core operating system
US20170031601A1 (en) * 2015-07-30 2017-02-02 Kabushiki Kaisha Toshiba Memory system and storage system
CN112804335B (en) * 2021-01-18 2022-11-22 中国邮政储蓄银行股份有限公司 Data processing method, data processing device, computer readable storage medium and processor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5197130A (en) * 1989-12-29 1993-03-23 Supercomputer Systems Limited Partnership Cluster architecture for a highly parallel scalar/vector multiprocessor system
US5265235A (en) * 1990-11-30 1993-11-23 Xerox Corporation Consistency protocols for shared memory multiprocessors
JPH04246745A (en) * 1991-02-01 1992-09-02 Canon Inc Memory access system
US5394555A (en) * 1992-12-23 1995-02-28 Bull Hn Information Systems Inc. Multi-node cluster computer system incorporating an external coherency unit at each node to insure integrity of information stored in a shared, distributed memory
WO1995025306A2 (en) * 1994-03-14 1995-09-21 Stanford University Distributed shared-cache for multi-processors

Also Published As

Publication number Publication date
EP0855057B1 (en) 2006-03-01
DE69635865D1 (en) 2006-04-27
DE69635865T2 (en) 2006-09-14
WO1997013191A1 (en) 1997-04-10
US5590301A (en) 1996-12-31
CA2211083C (en) 2003-05-20
JPH11512857A (en) 1999-11-02
EP0855057A4 (en) 1999-12-08
EP0855057A1 (en) 1998-07-29

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