CA2208637A1 - Logarithm/inverse-logarithm converter and method of using same - Google Patents
Logarithm/inverse-logarithm converter and method of using sameInfo
- Publication number
- CA2208637A1 CA2208637A1 CA002208637A CA2208637A CA2208637A1 CA 2208637 A1 CA2208637 A1 CA 2208637A1 CA 002208637 A CA002208637 A CA 002208637A CA 2208637 A CA2208637 A CA 2208637A CA 2208637 A1 CA2208637 A1 CA 2208637A1
- Authority
- CA
- Canada
- Prior art keywords
- value
- log
- input value
- memory
- parameter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/50—Conversion to or from non-linear codes, e.g. companding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/03—Digital function generators working, at least partly, by table look-up
- G06F1/035—Reduction of table size
- G06F1/0356—Reduction of table size by using two or more smaller tables, e.g. addressed by parts of the argument
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2101/00—Indexing scheme relating to the type of digital function generated
- G06F2101/10—Logarithmic or exponential functions
Abstract
A converter, which may be used for implementing either logarithmic or inverse-logarithmic functions, includes a memory (24), a multiplier (26), and an adder (28). The memory (24) stores a plurality of parameters which are derived using a least squares method to estimate a logarithmic or inverse-logarithmic function over a domain of input values.
Description
W096/24097 PCT~S96100146 LOGARITHM/INVERSE-LOGARITHM CONVERTER
AND METHOD OF USING SAME
Related Inventions The present invention is related to the following inventions which are assigned to the same assignee as the present invention:
(1) "Logarithm/Inverse-Logarithm Converter Utilizing a Second-order Term and Method of Using Same", having Serial No. 08/382,467, filed on 31 January 1995.
AND METHOD OF USING SAME
Related Inventions The present invention is related to the following inventions which are assigned to the same assignee as the present invention:
(1) "Logarithm/Inverse-Logarithm Converter Utilizing a Second-order Term and Method of Using Same", having Serial No. 08/382,467, filed on 31 January 1995.
(2) "Logarithm/Inverse-Logarithm Converter Utilizing a Truncated Taylor Series and Method of Use Thereof", having Serial No. 08/381,167, filed on 31 January 1995.
(3) "Logarithm/Inverse-Logarithm Converter Utilizing Linear Interpolation and Method of Using Same", having Serial No. 08/391,880, filed on 22 February 1995.
(4) "Neural Network Utilizing a Logarithmic Function and Method of Using Same", having Serial No. 08/176,601, filed on 03 January 1994.
(5) "Computer Processor Utilizing Logarithmic .Conversion and Method of Use Thereof", having Serial No.
08/403,158, filed on 13 March 1995.
The subject matter of the above-identified related inventions is hereby incorporated by reference into the disclosure of this invention.
Technical Field The present invention relates generally to computing circuits and, in particular, to a computing circuit which may be used to perform either a logarithmic or inverse-logarithmic conversion on an input value.
W 096124097 PCTnUS96)DD146 Background of the Invention Logarithmic converters are devices used t~ implement logarithmic functions and are most commonly found in items such as hand-held calculators and spread sheet software programs. Logarithmic functions, or log functions, belong to a class of mathematical functions called transcendental functions whlch are important in wide variety applications such as data communications, control systems, chemical processes, and computer simulation. A log function is abbreviated with the following mathematical equation: y =
logb(x). In this equation, x represents an lnput value which may be any number greater than or equal to zero; b represents a base number system; and y represents a logarithm value, or log value, which corresponds to the input value x.
Inverse-log converters are devices used to implement inverse-logarithmic, or inverse-log, functions.
Essentially, an inverse-log function is the reverse of a log function. What is meant by "reverse" is explained in the following discussion. A log function converts an input value, x, which is in a domain of input value into a definite log value which is in a range of log values.
Basically, the log function establishes a one-to-one correspondence between input values in the domain and log values in the range. This correspondence is represented symbolically by x -> y. An inverse-log function establishes a reverse correspondence between log values and input values which is represented by y -> x. An inverse-log function is abbreviated with the following mathematical equation: y = logb~1(x). In this equation, x represents an input value; b represents a base number system; and y represents an inverse-log value which corresponds to the input value x and may be any number W 096/24097 PCTnUS96100146 greater than or equal to zero. Like log functions, inverse log functions are important in a wide variety applications.
Two techniques of computing log and inverse-log values are commonly used today. Both techniques are analogously used to compute either log or inverse-log values; thus, for the sake of brevity, the following discussion will focus on using the techniques to compute log values, with the understanding that the techniques may be used in a like manner to compute inverse-log values.
The flrst technique involves storing a corresponding log value in a look-up table for every possible input value. This approach allows a log value to be computed relatively quickly and is practical for applications requiring limited precision and having input values within a small domain. However, in many applications this technique is impractical because it requires too great a memory space to store the look-up table. For example, in a digital system using an IEEE standard 32-bit floating point number, which has a 23-bit mantissa, such a look-up table would be required to store 223 log values -- one for every possible mantissa value. A computer memory for storing this number of log values would be prohibitively expensive, if not impossible, to build.
The second technique of computing log values involves computing a power series to approximate a log function. An example of a power series which approximates a log function is given as:
y = Log(1 + x) = x - x2/2 + x3/3 - x9/4 + . . (1) In this example, the log function is a specific type of log function known as a natural logarithm, which is widely used in science and engineering applications. The variables in Equation 1 are defined as follows: y represents a log value, and x represents an input value in the domain -1 < x W O 96/24097 PCTAUS96~00146 < 1. Although the technique of using a power series to approximate a log function allows a log value to be computed with a high degree of precision, it requires a large number of computer operations and therefore requires 5 a relatively long period of time to execute. In other o words, this technique is generally slow and negatively affects the throughput of a computer.
In summary, there is a need for a converter which can perform either a log or an inverse-log function quickly, 10 thus allowing a computer to operate with greater throughput. Such a converter should also reduce the amount of memory space required to perform the conversions, and it should produce log or inverse-log values which have a high degree of precision.
Brief Description of the Drawings The invention is pointed out with particularity in the 20 appended claims. However, other features of the invention will become more apparent and the invention will be best understood by referring to the following detailed description in conjunction with the accompanying drawings in which:
FIG. 1 illustrates a logarithm/inverse-logarithm converter in accordance with a preferred embodimen~ of the present invention.
FIG. 2 shows a graph of a logarithmic function.
FIG. 3 shows a graph of an inverse-logarithmic function.
FIG. 4 illustrates a flow chart diagram of a method of using the logarithm/inverse-logarithm converter shown in FIG. 1. ?
FIG. 5 illustrates one version of a computing device which incorporates an embodiment of the present invention.
W O 96/24097 PCT/U~3~nO146 FIG. 6 illustrates another version of a computing device which incorporates an embodiment of the present invention.
Detailed Description of a Preferred ~mbodiment It is an advantage of the present invention to provide a converter which can be used to perform either a logarithmic or inverse-logarithmic conversion in a computer, processor or circuit, without altering the design of the converter. A further advantage of the present invention is that it provides a converter which computes log and inverse-log values with a high degree of precision.
Yet another advantage of the present invention is that it 1~ provides a converter which requires a significantly reduced amount of memory space and may be efflciently implemented in an integrated circuit which consumes little power. An additional advantage of the present invention is to provide a method of using the converter to produce either log or inverse-log values.
Generally, the present invention provides a converter for computing either a log or an inverse-log functions.
The converter comprises a memory and an arithmetic means.
The memory stores a plurality of parameters, wherein the parameters are calculated using a least squares method to estimate either a log or an inverse-log function over a ~om~;n of input values. The arithmetic means generates a log or an inverse-log value, depending on the parameters stored in the memory, by performing arithmetic operations on an input value and ones of the parameters.
The converter may be easily re-configured to perform either log or inverse-log functions, or functions having a different base number system or domain of input values, by loading the memory with a different set of parameters.
FIG. 1 illustrates a logarithm/inverse-logarithm converter in accordance with a preferred embodiment of the CA 02208637 l997-06-24 W O 96/24097 PCTnUS96)00146 present invention. The converter comprises a memory 24, a multiplier 26, and an adder 28. The memory 24 stores a plurality of parameter pairs. Each parameter pair is calculated using a least squares method to estimate either S a log or an inverse-log function over an interval of input values. Each parameter pair has a zero-order parameter, which is stored in a zero-order look-up table 36, and a first-order parameter, which is stored in a first-order look-up table 34.
The converter operates as follows. An input value 20 provides an address 22 which is used to retrieve a corresponding parameter pair from the zero-order and first-order look-up tables 36, 34. In a preferred embodiment, the input value 20 is a binary value having a length of 16 lS bits, denoted by [15:0], wherein the most significant eight bits, [15:8], of the input value 20 are provided to the memory 24 as the address 22. Additionally, the zero-order and first-order parameters are located in the memory 24 at a common address which corresponds to the input value 20.
The memory 24 provides as output the zero-order parameter 32 and the first-order parameter 33 which correspond to the input value 20. In a preferred embodiment, the zero-order parameter 32 is a 17-bit binary value and the first-order parameter 33 is a 9-bit value. A
total of 256 parameter pairs are stored in the memory 24.
The multiplier 26 multiplies the first-order parameter 33 by the bit slice 21 to produce a proportional term. Although the bit slice 21 may include the entire input value 20, in a preferred embodiment, it includes the eight least significant bits, [7:0], of the lnput value 20.
The adder 28 sums the proportional term and the zero-order parameter 32 to produce an output value 30. In a preferred embodiment, the adder 28 generates an output which is one bit greater in length than the desired length of the output value 30. Thus, to generate the output value 30, which W096/24097 PCT~S96100146 preferably has a length of l6 bits, the adder generates a 17-bit output and the least significant bit of the output is discarded.
In one embodiment of the present invention, the ~ 5 converter is implemented with an integrated circuit.
However, one of ordinary skill will recognize that a programmable logic array, application specific integrated circuit (ASIC), or other digital logic device, as well as software running on a processor such as a microprocessor could also be used to implement the converter.
FIG. 2 shows a graph of a logarithmic function 50 over a domain of input values. The input values are given along the x-axis and the log values are given along the y-axis.
The domain of the input values is l to 2, and the range of the log values is 0 to l. Several intervals within the domain are indicated with vertical dotted lines at input values l.l, l.2, l.3. l.4, and l.5. Each interval contains data points between the dotted lines. The log function 50 uses a base number system of two.
FIG. 3 shows a graph of an inverse-logarithmic function 52 over a domain of input values. The input values are given along the x-axis and the inverse-log values are given along the y-axis. The domain of the input values is 0 to l, and the range of the inverse-log values is l to 2. Several intervals within the domain are indicated with vertical dotted lines at input values 0.l, û.2, û.3, and û.4. Each interval contains data points between the dotted lines. The inverse-log function 52 also uses a base two number system.
One of ordinary skill in the art will realize that the converter of the present invention may be used for computing any log or inverse-log function; however, in a preferred embodiment of the present invention, the converter computes the log function depicted in FIG. 2 and the inverse-log function depicted in FIG. 3. Input values W 096/24~97 PCTrUS961~146 are converted to a floating point binary word having one sign bit, a 16-bit mantissa, and a 6-bit exponent. Only the mantissa is provided to the converter as the input value 20. Both the sign bit and exponent bypass the converter and are later combined with the output value 30.
Essentially, the converter computes either y = log2~1(1.M) or y = log2~1(1.M), where y represents the output value and M represents the mantissa. The exponent of the floating point number is a base-two value, 2e, where e represents the exponent. A log or an inverse-log value corresponding to the floating point number is generated by summing of the output value 30 and the exponent value following conversion of the mantissa. This summation results in a value which is represented in a fixed point number format having a j-bit fractional portion and a k-bit integer portion. The integers j and k can vary, depending on the desired precision of the converter.
FIG. 4 illustrates a flow chart diagram of a method of using the logarithm/inverse-logarithm converter shown in FIG. 1. The method may be used for generating either a log value or an inverse-log value. In box 70, a plurality of parameters is calculated using a least squares method to estimate either a log or an inverse-log function. In box 72, the parameters are stored in the memory 24. Parameters corresponding to a single input value may be stored at the same address in the memory 24. In box 74, an input value 20 is received. Next, in box 76, parameters which correspond to the input value 20 are retrieve from the memory 24.
In box 78, arithmetic operations are performed on the retrieved parameters and the input value 20 to produce the output value 30. The retrieved parameters include the zero-order parameter 32 and the first-order parameter 33, and the arithmetic operations are performed as follows.
3~ First, the first-order parameter 33 is multiplied by the W096/24097 PCT~S96100146 input value 20 to produce a proportional term. In a preferred embodiment of the present lnvention, the first-- order parameter 33 is multiplied by a bit slice 21 of the input value 20. Next, the proportional term and the zero-S order parameter 32 are summed to produce the output value 30.
Referring now to box 70, the plurality of parameters are computed as follows. First, a domain of input values is selected for the function. The domain is then partitioned into a plurality of intervals. The function is approximated, over the domain of input values, with a first-order linear equation having a plurality of parameters. Next, the parameters for an interval are computed using a least squares method. The interval lS parameters are then stored in the memory 24.
In a preferred embodiment of the present invention, log and inverse-log functions are approximated with a first-order linear equation having the form:
y = bo + blx (2) where y represents the log or inverse-log value, bo represents the zero-order parameter, bl represents the first-order parameter, and x represents an input value.
The domain of input values is partitioned into 256 intervals which each contain 256 data points, or base points. For each interval, the parameters bo and bl are calculated using linear regression on the data points.
FIG. 5 illustrates one version of a computing device which incorporates an embodiment of the present invention.
The computing device comprises a processing unit 102 for executing a computer operation which utilizes a log/inverse-log value 106; a computer memory lO0 for storing a computer program which includes the computer operation; a bus lOl connecting the processing unit 102 and W O 96/24097 PCTIUS96JD~146 the computer memory 100; and a converter 108 which receives an input value 104.
The converter 108 may include the converter shown in FIG. 1. In the example shown, the converter 108 includes a memory 112 and an arithmetic means 110, such as a arithmetic logic unit or similar device, which is operatively coupled to the memory 112. The arithmetic means receives the input value 104 from the processing unit 102 and, in turn, generates either a log value or an inverse-log value depending on the parameters stored in the memory112.
FIG. 7 illustrates another version of a computing device which incorporates an embodiment of the present invention. The computing device comprises a processing unit 102 for executing a computer operation which utilizes a log/inverse-log value 106; a computer memory 100 for storing a computer program which includes the computer operation; a bus 101 connecting the processing unit 102 and the computer memory 100; and a converter 120 which receives an input value 104.
The converter 120 may include the converter shown in FIG. 1. In the example shown, the converter 120 includes a memory 124 and an arithmetic means 122 which is operatively coupled to the memory 124. The arithmetic means 122 receives the input value 104 and, in turn, generates either a log value or an inverse-log value depending on the parameters stored in the memory 124.
Thus there has been described herein a concept, as well as a preferred embodiment, of a converter which may be used to compute either log or inverse-log functions.
Because the embodiment of the converter as herein-described utilizes a first-order polynomial to approximate a function it can perform either a log or inverse-log conversion using single adder, a single multiplier, and a look-up table which allows a significant reduction in memory size. Such WO 96/24097 PCTnUS96J0~6 a converter allows both improved data throughput and computation precision with a vast reduction in the cost and complexity of implementation, whether on a semiconductor chip or in a computer program.
While the various embodiments of the present invention have been described in terms of the processing of an input value into an output value, the present invention should be construed to include circuits and methods implemented by these circuits for processing an input signal representative of the input value into an output signal representative of the output value.
While specific embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that the disclosed invention may be modified in numerous ways and may assume many embodiments other than the preferred form specifically set out and described above.
Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.
What is claimed is:
08/403,158, filed on 13 March 1995.
The subject matter of the above-identified related inventions is hereby incorporated by reference into the disclosure of this invention.
Technical Field The present invention relates generally to computing circuits and, in particular, to a computing circuit which may be used to perform either a logarithmic or inverse-logarithmic conversion on an input value.
W 096124097 PCTnUS96)DD146 Background of the Invention Logarithmic converters are devices used t~ implement logarithmic functions and are most commonly found in items such as hand-held calculators and spread sheet software programs. Logarithmic functions, or log functions, belong to a class of mathematical functions called transcendental functions whlch are important in wide variety applications such as data communications, control systems, chemical processes, and computer simulation. A log function is abbreviated with the following mathematical equation: y =
logb(x). In this equation, x represents an lnput value which may be any number greater than or equal to zero; b represents a base number system; and y represents a logarithm value, or log value, which corresponds to the input value x.
Inverse-log converters are devices used to implement inverse-logarithmic, or inverse-log, functions.
Essentially, an inverse-log function is the reverse of a log function. What is meant by "reverse" is explained in the following discussion. A log function converts an input value, x, which is in a domain of input value into a definite log value which is in a range of log values.
Basically, the log function establishes a one-to-one correspondence between input values in the domain and log values in the range. This correspondence is represented symbolically by x -> y. An inverse-log function establishes a reverse correspondence between log values and input values which is represented by y -> x. An inverse-log function is abbreviated with the following mathematical equation: y = logb~1(x). In this equation, x represents an input value; b represents a base number system; and y represents an inverse-log value which corresponds to the input value x and may be any number W 096/24097 PCTnUS96100146 greater than or equal to zero. Like log functions, inverse log functions are important in a wide variety applications.
Two techniques of computing log and inverse-log values are commonly used today. Both techniques are analogously used to compute either log or inverse-log values; thus, for the sake of brevity, the following discussion will focus on using the techniques to compute log values, with the understanding that the techniques may be used in a like manner to compute inverse-log values.
The flrst technique involves storing a corresponding log value in a look-up table for every possible input value. This approach allows a log value to be computed relatively quickly and is practical for applications requiring limited precision and having input values within a small domain. However, in many applications this technique is impractical because it requires too great a memory space to store the look-up table. For example, in a digital system using an IEEE standard 32-bit floating point number, which has a 23-bit mantissa, such a look-up table would be required to store 223 log values -- one for every possible mantissa value. A computer memory for storing this number of log values would be prohibitively expensive, if not impossible, to build.
The second technique of computing log values involves computing a power series to approximate a log function. An example of a power series which approximates a log function is given as:
y = Log(1 + x) = x - x2/2 + x3/3 - x9/4 + . . (1) In this example, the log function is a specific type of log function known as a natural logarithm, which is widely used in science and engineering applications. The variables in Equation 1 are defined as follows: y represents a log value, and x represents an input value in the domain -1 < x W O 96/24097 PCTAUS96~00146 < 1. Although the technique of using a power series to approximate a log function allows a log value to be computed with a high degree of precision, it requires a large number of computer operations and therefore requires 5 a relatively long period of time to execute. In other o words, this technique is generally slow and negatively affects the throughput of a computer.
In summary, there is a need for a converter which can perform either a log or an inverse-log function quickly, 10 thus allowing a computer to operate with greater throughput. Such a converter should also reduce the amount of memory space required to perform the conversions, and it should produce log or inverse-log values which have a high degree of precision.
Brief Description of the Drawings The invention is pointed out with particularity in the 20 appended claims. However, other features of the invention will become more apparent and the invention will be best understood by referring to the following detailed description in conjunction with the accompanying drawings in which:
FIG. 1 illustrates a logarithm/inverse-logarithm converter in accordance with a preferred embodimen~ of the present invention.
FIG. 2 shows a graph of a logarithmic function.
FIG. 3 shows a graph of an inverse-logarithmic function.
FIG. 4 illustrates a flow chart diagram of a method of using the logarithm/inverse-logarithm converter shown in FIG. 1. ?
FIG. 5 illustrates one version of a computing device which incorporates an embodiment of the present invention.
W O 96/24097 PCT/U~3~nO146 FIG. 6 illustrates another version of a computing device which incorporates an embodiment of the present invention.
Detailed Description of a Preferred ~mbodiment It is an advantage of the present invention to provide a converter which can be used to perform either a logarithmic or inverse-logarithmic conversion in a computer, processor or circuit, without altering the design of the converter. A further advantage of the present invention is that it provides a converter which computes log and inverse-log values with a high degree of precision.
Yet another advantage of the present invention is that it 1~ provides a converter which requires a significantly reduced amount of memory space and may be efflciently implemented in an integrated circuit which consumes little power. An additional advantage of the present invention is to provide a method of using the converter to produce either log or inverse-log values.
Generally, the present invention provides a converter for computing either a log or an inverse-log functions.
The converter comprises a memory and an arithmetic means.
The memory stores a plurality of parameters, wherein the parameters are calculated using a least squares method to estimate either a log or an inverse-log function over a ~om~;n of input values. The arithmetic means generates a log or an inverse-log value, depending on the parameters stored in the memory, by performing arithmetic operations on an input value and ones of the parameters.
The converter may be easily re-configured to perform either log or inverse-log functions, or functions having a different base number system or domain of input values, by loading the memory with a different set of parameters.
FIG. 1 illustrates a logarithm/inverse-logarithm converter in accordance with a preferred embodiment of the CA 02208637 l997-06-24 W O 96/24097 PCTnUS96)00146 present invention. The converter comprises a memory 24, a multiplier 26, and an adder 28. The memory 24 stores a plurality of parameter pairs. Each parameter pair is calculated using a least squares method to estimate either S a log or an inverse-log function over an interval of input values. Each parameter pair has a zero-order parameter, which is stored in a zero-order look-up table 36, and a first-order parameter, which is stored in a first-order look-up table 34.
The converter operates as follows. An input value 20 provides an address 22 which is used to retrieve a corresponding parameter pair from the zero-order and first-order look-up tables 36, 34. In a preferred embodiment, the input value 20 is a binary value having a length of 16 lS bits, denoted by [15:0], wherein the most significant eight bits, [15:8], of the input value 20 are provided to the memory 24 as the address 22. Additionally, the zero-order and first-order parameters are located in the memory 24 at a common address which corresponds to the input value 20.
The memory 24 provides as output the zero-order parameter 32 and the first-order parameter 33 which correspond to the input value 20. In a preferred embodiment, the zero-order parameter 32 is a 17-bit binary value and the first-order parameter 33 is a 9-bit value. A
total of 256 parameter pairs are stored in the memory 24.
The multiplier 26 multiplies the first-order parameter 33 by the bit slice 21 to produce a proportional term. Although the bit slice 21 may include the entire input value 20, in a preferred embodiment, it includes the eight least significant bits, [7:0], of the lnput value 20.
The adder 28 sums the proportional term and the zero-order parameter 32 to produce an output value 30. In a preferred embodiment, the adder 28 generates an output which is one bit greater in length than the desired length of the output value 30. Thus, to generate the output value 30, which W096/24097 PCT~S96100146 preferably has a length of l6 bits, the adder generates a 17-bit output and the least significant bit of the output is discarded.
In one embodiment of the present invention, the ~ 5 converter is implemented with an integrated circuit.
However, one of ordinary skill will recognize that a programmable logic array, application specific integrated circuit (ASIC), or other digital logic device, as well as software running on a processor such as a microprocessor could also be used to implement the converter.
FIG. 2 shows a graph of a logarithmic function 50 over a domain of input values. The input values are given along the x-axis and the log values are given along the y-axis.
The domain of the input values is l to 2, and the range of the log values is 0 to l. Several intervals within the domain are indicated with vertical dotted lines at input values l.l, l.2, l.3. l.4, and l.5. Each interval contains data points between the dotted lines. The log function 50 uses a base number system of two.
FIG. 3 shows a graph of an inverse-logarithmic function 52 over a domain of input values. The input values are given along the x-axis and the inverse-log values are given along the y-axis. The domain of the input values is 0 to l, and the range of the inverse-log values is l to 2. Several intervals within the domain are indicated with vertical dotted lines at input values 0.l, û.2, û.3, and û.4. Each interval contains data points between the dotted lines. The inverse-log function 52 also uses a base two number system.
One of ordinary skill in the art will realize that the converter of the present invention may be used for computing any log or inverse-log function; however, in a preferred embodiment of the present invention, the converter computes the log function depicted in FIG. 2 and the inverse-log function depicted in FIG. 3. Input values W 096/24~97 PCTrUS961~146 are converted to a floating point binary word having one sign bit, a 16-bit mantissa, and a 6-bit exponent. Only the mantissa is provided to the converter as the input value 20. Both the sign bit and exponent bypass the converter and are later combined with the output value 30.
Essentially, the converter computes either y = log2~1(1.M) or y = log2~1(1.M), where y represents the output value and M represents the mantissa. The exponent of the floating point number is a base-two value, 2e, where e represents the exponent. A log or an inverse-log value corresponding to the floating point number is generated by summing of the output value 30 and the exponent value following conversion of the mantissa. This summation results in a value which is represented in a fixed point number format having a j-bit fractional portion and a k-bit integer portion. The integers j and k can vary, depending on the desired precision of the converter.
FIG. 4 illustrates a flow chart diagram of a method of using the logarithm/inverse-logarithm converter shown in FIG. 1. The method may be used for generating either a log value or an inverse-log value. In box 70, a plurality of parameters is calculated using a least squares method to estimate either a log or an inverse-log function. In box 72, the parameters are stored in the memory 24. Parameters corresponding to a single input value may be stored at the same address in the memory 24. In box 74, an input value 20 is received. Next, in box 76, parameters which correspond to the input value 20 are retrieve from the memory 24.
In box 78, arithmetic operations are performed on the retrieved parameters and the input value 20 to produce the output value 30. The retrieved parameters include the zero-order parameter 32 and the first-order parameter 33, and the arithmetic operations are performed as follows.
3~ First, the first-order parameter 33 is multiplied by the W096/24097 PCT~S96100146 input value 20 to produce a proportional term. In a preferred embodiment of the present lnvention, the first-- order parameter 33 is multiplied by a bit slice 21 of the input value 20. Next, the proportional term and the zero-S order parameter 32 are summed to produce the output value 30.
Referring now to box 70, the plurality of parameters are computed as follows. First, a domain of input values is selected for the function. The domain is then partitioned into a plurality of intervals. The function is approximated, over the domain of input values, with a first-order linear equation having a plurality of parameters. Next, the parameters for an interval are computed using a least squares method. The interval lS parameters are then stored in the memory 24.
In a preferred embodiment of the present invention, log and inverse-log functions are approximated with a first-order linear equation having the form:
y = bo + blx (2) where y represents the log or inverse-log value, bo represents the zero-order parameter, bl represents the first-order parameter, and x represents an input value.
The domain of input values is partitioned into 256 intervals which each contain 256 data points, or base points. For each interval, the parameters bo and bl are calculated using linear regression on the data points.
FIG. 5 illustrates one version of a computing device which incorporates an embodiment of the present invention.
The computing device comprises a processing unit 102 for executing a computer operation which utilizes a log/inverse-log value 106; a computer memory lO0 for storing a computer program which includes the computer operation; a bus lOl connecting the processing unit 102 and W O 96/24097 PCTIUS96JD~146 the computer memory 100; and a converter 108 which receives an input value 104.
The converter 108 may include the converter shown in FIG. 1. In the example shown, the converter 108 includes a memory 112 and an arithmetic means 110, such as a arithmetic logic unit or similar device, which is operatively coupled to the memory 112. The arithmetic means receives the input value 104 from the processing unit 102 and, in turn, generates either a log value or an inverse-log value depending on the parameters stored in the memory112.
FIG. 7 illustrates another version of a computing device which incorporates an embodiment of the present invention. The computing device comprises a processing unit 102 for executing a computer operation which utilizes a log/inverse-log value 106; a computer memory 100 for storing a computer program which includes the computer operation; a bus 101 connecting the processing unit 102 and the computer memory 100; and a converter 120 which receives an input value 104.
The converter 120 may include the converter shown in FIG. 1. In the example shown, the converter 120 includes a memory 124 and an arithmetic means 122 which is operatively coupled to the memory 124. The arithmetic means 122 receives the input value 104 and, in turn, generates either a log value or an inverse-log value depending on the parameters stored in the memory 124.
Thus there has been described herein a concept, as well as a preferred embodiment, of a converter which may be used to compute either log or inverse-log functions.
Because the embodiment of the converter as herein-described utilizes a first-order polynomial to approximate a function it can perform either a log or inverse-log conversion using single adder, a single multiplier, and a look-up table which allows a significant reduction in memory size. Such WO 96/24097 PCTnUS96J0~6 a converter allows both improved data throughput and computation precision with a vast reduction in the cost and complexity of implementation, whether on a semiconductor chip or in a computer program.
While the various embodiments of the present invention have been described in terms of the processing of an input value into an output value, the present invention should be construed to include circuits and methods implemented by these circuits for processing an input signal representative of the input value into an output signal representative of the output value.
While specific embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that the disclosed invention may be modified in numerous ways and may assume many embodiments other than the preferred form specifically set out and described above.
Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.
What is claimed is:
Claims (10)
1. A logarithm converter, which comprises:
a memory for storing a plurality of parameters, wherein the parameters are calculated using a least squares method to estimate a logarithmic function over a domain of input values; and arithmetic means, operatively coupled to the memory, for generating a log value by performing arithmetic operations on an input value and ones of the plurality of parameters which correspond to the input value.
a memory for storing a plurality of parameters, wherein the parameters are calculated using a least squares method to estimate a logarithmic function over a domain of input values; and arithmetic means, operatively coupled to the memory, for generating a log value by performing arithmetic operations on an input value and ones of the plurality of parameters which correspond to the input value.
2. The logarithm converter of claim 1, wherein the logarithmic function is estimated with a first order linear equation having two parameters.
3. The logarithm converter of claim 2, wherein the ones of the plurality of parameters include a first-order parameter and a zero-order parameter, and the arithmetic means includes:
a multiplier for multiplying the input value with the first-order parameter to produce a proportional term; and an adder for summing the proportional term and the zero-order parameter to generate the log value.
a multiplier for multiplying the input value with the first-order parameter to produce a proportional term; and an adder for summing the proportional term and the zero-order parameter to generate the log value.
4. The logarithm converter of claim 2, wherein the ones of the plurality of parameters include a first-order parameter and a zero-order parameter, and the arithmetic means includes:
a multiplier for multiplying a bit slice of the input value with the first-order parameter to produce a proportional term; and an adder for summing the proportional term and the zero-order parameter to generate the log value.
a multiplier for multiplying a bit slice of the input value with the first-order parameter to produce a proportional term; and an adder for summing the proportional term and the zero-order parameter to generate the log value.
5. The logarithm converter of claim 1, wherein the input value is a binary value having a plurality of bits used to retrieve from the memory the ones of the plurality of parameters.
6. A logarithm converter for generating a log value corresponding to an input value, the logarithm converter comprising:
a memory for storing a plurality of parameter pairs, wherein each of the plurality of parameter pairs is calculated using a least squares method to estimate a logarithmic function over an interval of input values, the memory providing as output a parameter pair correspond ing to the input value, wherein the parameter pair has a first-order parameter and a zero-order parameter;
a multiplier for producing a proportional term by multiplying the input value with the first-order parameter;
and an adder for producing the log value by summing the proportional term and the zero-order parameter.
a memory for storing a plurality of parameter pairs, wherein each of the plurality of parameter pairs is calculated using a least squares method to estimate a logarithmic function over an interval of input values, the memory providing as output a parameter pair correspond ing to the input value, wherein the parameter pair has a first-order parameter and a zero-order parameter;
a multiplier for producing a proportional term by multiplying the input value with the first-order parameter;
and an adder for producing the log value by summing the proportional term and the zero-order parameter.
7. A computing device, which comprises:
a processing unit for executing a computer operation which utilizes a log value;
a computer memory for storing a computer program which includes the computer operation;
a bus for connecting the processing unit and the computer memory; and a logarithm converter which receives an input value and includes:
a memory for storing a plurality of parameters, wherein the plurality of parameters are calculated using a least squares method to estimate a logarithmic function over a domain of input values; and arithmetic means, operatively coupled to the memory, for generating the log value by performing arithmetic operations on the input value and ones of the plurality of parameters which correspond to the input value.
a processing unit for executing a computer operation which utilizes a log value;
a computer memory for storing a computer program which includes the computer operation;
a bus for connecting the processing unit and the computer memory; and a logarithm converter which receives an input value and includes:
a memory for storing a plurality of parameters, wherein the plurality of parameters are calculated using a least squares method to estimate a logarithmic function over a domain of input values; and arithmetic means, operatively coupled to the memory, for generating the log value by performing arithmetic operations on the input value and ones of the plurality of parameters which correspond to the input value.
8. A method for generating an inverse-log value, which method comprises the following steps:
receiving an input value;
retrieving from a memory at least one parameter which corresponds to the input value, wherein the at least one parameter is computed using a least squares method to estimate an inverse-logarithmic function; and performing arithmetic operations on the at least one parameter and the input value to produce the inverse-log value.
receiving an input value;
retrieving from a memory at least one parameter which corresponds to the input value, wherein the at least one parameter is computed using a least squares method to estimate an inverse-logarithmic function; and performing arithmetic operations on the at least one parameter and the input value to produce the inverse-log value.
9. An inverse-logarithm converter, which comprises:
a memory for storing a plurality of parameters, wherein the plurality of parameters are calculated using a least squares method to estimate an inverse-logarithmic function over a domain of input values; and arithmetic means, operatively coupled to the memory, for generating an inverse-log value by performing arithmetic operations on an input value and ones of the plurality of parameters which correspond to the input value.
a memory for storing a plurality of parameters, wherein the plurality of parameters are calculated using a least squares method to estimate an inverse-logarithmic function over a domain of input values; and arithmetic means, operatively coupled to the memory, for generating an inverse-log value by performing arithmetic operations on an input value and ones of the plurality of parameters which correspond to the input value.
10. A method for generating a log value, which method comprises the following steps:
receiving an input value;
retrieving from a memory at least one parameter which corresponds to the input value, wherein the at least one parameter is computed using a least squares method to estimate a logarithmic function; and performing arithmetic operations on the at least one parameter and the input value to produce the log value.
receiving an input value;
retrieving from a memory at least one parameter which corresponds to the input value, wherein the at least one parameter is computed using a least squares method to estimate a logarithmic function; and performing arithmetic operations on the at least one parameter and the input value to produce the log value.
Applications Claiming Priority (2)
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US08/381,368 | 1995-01-31 | ||
US08/381,368 US5642305A (en) | 1995-01-31 | 1995-01-31 | Logarithm/inverse-logarithm converter and method of using same |
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CA002208637A Abandoned CA2208637A1 (en) | 1995-01-31 | 1996-01-03 | Logarithm/inverse-logarithm converter and method of using same |
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US (2) | US5642305A (en) |
EP (1) | EP0807288A4 (en) |
AU (1) | AU4653996A (en) |
CA (1) | CA2208637A1 (en) |
WO (1) | WO1996024097A1 (en) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5642305A (en) * | 1995-01-31 | 1997-06-24 | Motorola, Inc. | Logarithm/inverse-logarithm converter and method of using same |
KR0174498B1 (en) * | 1995-10-13 | 1999-04-01 | 김광호 | Approximation Method and Circuit of Log |
US5963460A (en) * | 1996-12-17 | 1999-10-05 | Metaflow Technologies, Inc. | Apparatus for computing transcendental functions quickly |
US5951629A (en) * | 1997-09-15 | 1999-09-14 | Motorola, Inc. | Method and apparatus for log conversion with scaling |
US6249857B1 (en) * | 1997-10-20 | 2001-06-19 | Motorola, Inc. | Apparatus using a multiple instruction register logarithm based processor |
JPH11212768A (en) * | 1998-01-23 | 1999-08-06 | Sanyo Electric Co Ltd | Logarithmic value calculation circuit |
US6289367B1 (en) * | 1998-11-16 | 2001-09-11 | Texas Instruments Incorporated | Digital signal processing circuits, systems, and method implementing approximations for logarithm and inverse logarithm |
US7031993B1 (en) * | 2000-02-18 | 2006-04-18 | Ge Medical Systems Global Technology Company, Llc | Method and apparatus for fast natural log(X) calculation |
US7284027B2 (en) | 2000-05-15 | 2007-10-16 | Qsigma, Inc. | Method and apparatus for high speed calculation of non-linear functions and networks using non-linear function calculations for digital signal processing |
US6883012B1 (en) | 2001-03-19 | 2005-04-19 | Cisco Systems Wireless Networking (Australia) Pty Limited | Linear-to-log converter for power estimation in a wireless data network receiver |
US7072926B2 (en) * | 2001-06-08 | 2006-07-04 | Texas Instruments Incorporated | Blind transport format detection system and method with logarithm approximation for reliability figure |
US6950841B2 (en) * | 2001-07-16 | 2005-09-27 | Qualcomm Incorporated | Logarithmic lookup tables |
US6707865B2 (en) * | 2001-07-16 | 2004-03-16 | Qualcomm Incorporated | Digital voltage gain amplifier for zero IF architecture |
US20030086486A1 (en) * | 2001-07-31 | 2003-05-08 | Graziano Michael J. | Method and system for determining maximum power backoff using frequency domain geometric signal to noise ratio |
US7113491B2 (en) * | 2001-07-31 | 2006-09-26 | Conexant, Inc. | Method and system for varying an echo canceller filter length based on data rate |
US20030101206A1 (en) * | 2001-07-31 | 2003-05-29 | Graziano Michael J. | Method and system for estimating a base-2 logarithm of a number |
US20030099286A1 (en) * | 2001-07-31 | 2003-05-29 | Graziano Michael J. | Method and system for shaping transmitted power spectral density according to line conditions |
DE10163350A1 (en) * | 2001-12-21 | 2003-07-17 | Rohde & Schwarz | Method and device for generating an output signal as a mathematical function of an input signal |
US7266576B2 (en) * | 2002-12-24 | 2007-09-04 | Lockheed Martin Corporation | Circuits and methods for implementing approximations to logarithms |
US7042523B2 (en) * | 2003-06-30 | 2006-05-09 | Texas Instruments Incorporated | Video correction system and method using logarithmic conversion |
US20060015549A1 (en) * | 2004-07-13 | 2006-01-19 | Chren William A | Method and apparatus for generation of gaussian deviates |
US7606850B2 (en) * | 2005-03-30 | 2009-10-20 | Lockheed Martin Corporation | Method and apparatus for providing a base-2 logarithm approximation to a binary number |
DE102014200465A1 (en) * | 2014-01-14 | 2015-07-16 | Robert Bosch Gmbh | Apparatus and method for determining an estimate of the logarithm of an input |
BR112017001981B1 (en) * | 2014-07-30 | 2023-05-02 | Movidius Limited | METHOD FOR MANAGING RELATED INSTRUCTION BUFFER, SYSTEM AND COMPUTER READABLE MEMORY |
US20200125991A1 (en) * | 2018-10-18 | 2020-04-23 | Facebook, Inc. | Optimization of neural networks using hardware calculation efficiency |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4555768A (en) * | 1983-06-07 | 1985-11-26 | Rca Corporation | Digital signal processing system employing logarithms to multiply and divide |
US4922212A (en) * | 1989-06-05 | 1990-05-01 | Novatel Communications, Ltd. | Oscillator temperature compensating circuit using stored and calculated values |
US5068816A (en) * | 1990-02-16 | 1991-11-26 | Noetzel Andrew S | Interplating memory function evaluation |
DE69130025T2 (en) * | 1990-03-30 | 1999-03-25 | Canon Kk | Image processing method and device |
US5301138A (en) * | 1990-07-19 | 1994-04-05 | Motorola, Inc. | Device and method for evaluating logarithms |
US5343254A (en) * | 1991-04-25 | 1994-08-30 | Olympus Optical Co., Ltd. | Image signal processing device capable of suppressing nonuniformity of illumination |
US5331582A (en) * | 1991-12-16 | 1994-07-19 | Pioneer Electronic Corporation | Digital signal processor using a coefficient value corrected according to the shift of input data |
ATE168481T1 (en) * | 1992-02-29 | 1998-08-15 | Bernd Hoefflinger | CIRCUIT ARRANGEMENT FOR DIGITAL MULTIPLYING INTEGER NUMBERS |
US5703801A (en) * | 1995-01-31 | 1997-12-30 | Motorola, Inc. | Logarithm/inverse-logarithm converter utilizing second-order term and method of using same |
US5604691A (en) * | 1995-01-31 | 1997-02-18 | Motorola, Inc. | Logarithm/inverse-logarithm converter utilizing a truncated Taylor series and method of use thereof |
US5642305A (en) * | 1995-01-31 | 1997-06-24 | Motorola, Inc. | Logarithm/inverse-logarithm converter and method of using same |
US5600581A (en) * | 1995-02-22 | 1997-02-04 | Motorola, Inc. | Logarithm/inverse-logarithm converter utilizing linear interpolation and method of using same |
-
1995
- 1995-01-31 US US08/381,368 patent/US5642305A/en not_active Expired - Lifetime
-
1996
- 1996-01-03 AU AU46539/96A patent/AU4653996A/en not_active Abandoned
- 1996-01-03 CA CA002208637A patent/CA2208637A1/en not_active Abandoned
- 1996-01-03 WO PCT/US1996/000146 patent/WO1996024097A1/en not_active Application Discontinuation
- 1996-01-03 EP EP96902096A patent/EP0807288A4/en not_active Withdrawn
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1997
- 1997-06-25 US US08/881,903 patent/US5941939A/en not_active Expired - Fee Related
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US5642305A (en) | 1997-06-24 |
AU4653996A (en) | 1996-08-21 |
WO1996024097A1 (en) | 1996-08-08 |
US5941939A (en) | 1999-08-24 |
EP0807288A1 (en) | 1997-11-19 |
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