CA2189820C - Transmitter receiver for mobile communication system - Google Patents
Transmitter receiver for mobile communication system Download PDFInfo
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- CA2189820C CA2189820C CA002189820A CA2189820A CA2189820C CA 2189820 C CA2189820 C CA 2189820C CA 002189820 A CA002189820 A CA 002189820A CA 2189820 A CA2189820 A CA 2189820A CA 2189820 C CA2189820 C CA 2189820C
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/24—Radio transmission systems, i.e. using radiation field for communication between two or more posts
- H04B7/26—Radio transmission systems, i.e. using radiation field for communication between two or more posts at least one of which is mobile
- H04B7/2618—Radio transmission systems, i.e. using radiation field for communication between two or more posts at least one of which is mobile using hybrid code-time division multiple access [CDMA-TDMA]
Abstract
A transmitter receiver implementing both frequency division duplex and time division duplex in one device in a CDMA mobile communication system. In the FDD mode, data in an interleave memory in an interleaver is read at a predetermined read rate VR = VN, where VN is a normal rate. In the TDD mode, a transmitting carrier frequency is set identical to a receiving carrier frequency, and the read rate VR of the interleave memory and the write rate VW of the deinterleave memory are set at VR = VW > 2VN.
The transfer rate VT from column to column of the memories are set identical in the FDD mode and the TDD mode. This makes it possible to create a vacant duration while transferring from column to column, and to perform reception or transmission during the vacant duration. The remaining operation of the TDD mode is the same as the operation of the FDD mode.
The transfer rate VT from column to column of the memories are set identical in the FDD mode and the TDD mode. This makes it possible to create a vacant duration while transferring from column to column, and to perform reception or transmission during the vacant duration. The remaining operation of the TDD mode is the same as the operation of the FDD mode.
Description
2 1 8982~
The present invention relates to a CDM~ (Code Division Multiple Access) mobile communication system, and particularly to a transmitter receiver for a mobile communication system which achieves both frecIuency division duplex (FDD) and time division duplex (TDD) in one device.
In most public mobile communications, bidirectional communications is achieved by FDD. ~In this case, 10 different carrier fresLuencies are used to distinguish reverse link channels (from mobile stations to a base station) from forward link ~hilnnf~ (frQm the base station to the mobile stations). For example, in PDC (Personal Digital Cellular) utilizing an 800 MHz band, the carrier fre~auencies are s~aced 130 MHz apart (see, "Personal digital cellular telecommunication system RCR standard, RCR STD-27, Research & Development Center for Radio System) .
On the other hand, TDD can be em~loyed as another 20 bidirectio~al communication method. It assigns the same carrier fre~uency for the forward and reverse link r~hi lnn~ , and these rh;lnnPl ~: are distirlguished in the time domain. In other words, the same fre(auency is used alternately by the forward and reverse link channels. It is employed, fQr example, by PHS (Personal Handyphone System) (see, "Second generation codeless telecommunication system RCR standard, RCR STD-28r, Research ~ Development Center for Radio System).
~ 2 1 89820 It is therefore an object of the present invention to provide a transmitter receiver for a mobile communication system which achieves in one device both the frequency division duplex (FDD) and time division duplex (TDD) in a CDMP communication system.
According to an aspect of the present invention, there is provided a transmitter receiver for a C~A (Code Division Multiple Access ) mobile communication system including a transmitter and a receiver, the transmitter comprising:
an interleaver for interleaving each frame of transmitted data;
an interleave memory provided in the interleaver, the interleave memory being capable of writing and reading row by row and column by column, respecively;
modulation means for data modulating the interleaved transmitted data into a narrowband modulated signal; and spread modulation means for spread modulating the 20 narrowband modulated signal into a wideband modulated signal using a spreading sequence, wherein the interleaver writes the transmitted data into the interleave memory row by row, and reads the transmitted data from the interleave memory column by column, thereby carrying out the interleave, the receiver comprising:
despreading means for converting the wideband modulated signal into the narrowband modulated signal;
demodulation means for demodulating the narrowband signal into demodulated data;
a deinterleaver for deinterleaving the demodulated data frame by frame to recover the transmitted data; and a deinterleave memory provided in the deinterleaver, the deinterleave memory being capable of writing and reading column by column and row by row, respectively, wherein the interleaver writes the demodulated data into the deinterleave memory column by column, and reads the demodulated data from the deinterleave memory row by row, thereby carrying out the deinterleave, and the transmitter receiver comprising:
control means for controlli~g a transfer rate from column to column (columns/sec) at a E)redetermined fixed rate VT in reading data from the interleave memory and writing data into the deinterleave memory, and for variably controlling a read rate VR and a write rate Vw 20 (bits/sec) of data in each the column.
Here, the control means may set the read rate VR ~f each column of the interleave memory and the write rate Vw of each column of the deinterleave memory at VR = VW = VT-Ms in an FDD (Fre~uency Division Duplex) mode, where Ms is the number of bits in each the column, and VR > 2VT-Ms and Vw > 2V~-Ms in a TDD (Time Division Duplex) mode, and may switch in the TDD mode the _ _ , _ _, , , .... , . .. . . . .. . _ ... . .... .. . _ . ,, 2 ~ 8982Q
transmitter receiver from a transmitting mode to a receiving mode after reading a last bit of the column and keeps the receiving mode until starting reading of a next column.
The interleaver may write one or more pilot symbols at an initial position of the interleave memory.
The transmitter receiver for a mobile communication system may further comprise transmission power control means connected to an output side of the spread modulation 10 means for increasing transmission power of important data in the transmitted data.
The important data may comprise the pilot symbols and control data.
The above-mentioned column and row may be exchanged.
According to the present invention, the frequency division duplex (FDD) and the time division duplex (TDD) can be achieved in one device with a simple arrangement by simply controlling the read and write rates of the interleaver and deinterleaver in the CD~A mobile 2 0 communications .
In addition, writing pilot symbols at the initial position of an interleave memory obviates additional insertion of the pilot symbols thereafter.
The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiment thereof taken in conjunction ~ith the accompanying drawings .
~ 21~9820 Figs. lA-lC are schematic diagrams illustrating a transmission method used in an embodiment of a transmitter receiver for a mobile communication system in accordance with the present invention, wherein Fig. lA illustrates the arrangement of a transmitted data frame, Fig. lB
illustrates pilot symbols of a known pattern, and Fig. lC
illustrates the arrangement of a radio channel slot;
Fig. 2 is a schematic diagram illustrating the arrangement of an interleave memory 3A of the embodiment;
Fig. 3 is a schematic diagram illustrating a state of data stored in the memory 3A;
Fig. 4 is a schematic diagram illustrating an example of transmission power control in the embodimenti Fig. 5 is a schematic diagram illustrating FDD and TDD, in which Fig. 5 (A) illustrates the FDD mode, and Fig.
5 (B) illustrates the TDD mode;
Fig. 6 is a block diagram showing the embodiment of a transmitter receiver for a mobile communication system in accordance with the present invention; and Fig. 7 is a block diagram showing the configuration of a sub-controller of the embodiment.
The invention will now be described with reference to the accompanying drawings, First, the transmission method will be described of a CD~5A mobile communication system employed in the present invention .
~ 2t 8q820 Fig. lA illustrates a frame structure in a common mobile communications. A user data seguence to be transmitted is divided into frames of a predetermined fixed duration. Subseguently, control data is added to the initial position of each frame, and a check code (CRC
code, for example) of the user data in each frame is added to the final position of each frame, thereby forming one frame data. In Fig. lA, vacant portions in the frame takes place when the total transmission rate of the 10 control data, user data aRd check code is smaller than a mi~; possible rate.
One frame data is interleaved as illustrated in Fig.
3, and theR mapped onto a radio channel frame as shown in Fig. lB. Pilot symbols of a known patterR are periodically inserted into the frame. The pilot symbols are used at the receiving side for cohereRt detection.
This method is disclosed, for example, in S. Sampei, "Fading Compensation for 16QAM in Land Mobile Communications~, The Transactions of the Institute of 20 ElectroRics, Information and Communication Engineers of Japan B~ Tol. J72-B-II pp. 7-15, January 1989, or its revised English version, S. Sampei, et al. ~Rayleigh Fading Compensation for QAM in Land Mobile Radio Communications", IEEE Transactions on Vehicular TechRology, VOL. 42. No. 2, MAY 1993.
In Fig. lB, a section sandwiched between the pilot symbols is called a slot. If one frame consists of Ns -~ 2 t 89~20 slots, and one slot consists of Ms bits, then one frame consists of Ns-Ms bits.
The symbol sequence thus arranged undergoes primary modulation, followed by secondary modulation which spreads it using a spreading code sequence with a chip rate of an integer multiple of (tens to hundreds times) the modulated symbol rate, and is transmitted.
When the data is transmitted with the pilot symbols of a known pattern inserted periodically, the receiver 10 estimates the state of a transmission link at each data position in the slots by using the pilot symbols, and employs the estimate as the refererLce signals of the coherent ~t~t;~n (see the foregoing SamE?ei paper).
On the other hand, the transmitter is provided with an interleaver for assembling the transmitted data. Fig.
2 is a schematic diagram illustrating an interleave memory 3A for one frame used by the interleaver. The num~er of bits per row (that is, the number of columns) of the memory e(auals the number of slots, Ns, constituting one 20 frame, and the number of bits per column (that is, the number of rows) e~luals the ~-~r;mllm bit number Ms constituting one slot. The transmitted data of one frame is written bit by bit in the row of the interleave memory, whereas it is read in the colllmn.
Fig. 3 illustrates a state in which the data is written in the interleave memory 3A. As shown in Fig. 3, one frame data ;nc~lu~;n~ the check code (CRC) for error detection is written in the interleave memory 3A. The - ~ 21 89820 data thus written into the interleave memory 3A is read in the vertical direction (column by column), so that the data is sequentially mapped onto the slots. Thus, the column number ( l-Ns ) corresponds to the slot number in Fig. lB. By reading the data from the interleave memory in this way, the individual slots are arranged as shown in Fig. lC. The vacant portions in Fig. lC correspond to the vacant area in each frame.
The above is the configuration for preparing data at 10 the transmitter. The receiver, on the other hand, has a deinterleaver for reassembling the interleaved transmitted data into its original order. The deinterleaver also comprises a deinterleave memory with an arrangement similar to that of Fig. 2, except that the write and read directions are inverted to those of the interleaver. That is, the receiver obtains the original data by writing column by column direction and by reading row by row.
The transmission thus carried out enables the power of the mobile station to be reduced. Fig. 4 illustrates 20 this. The pilot symbols and control data next to them are transmitted with greater power. The vacant portion is not sent. The transmission method is disclosed in Japanese patent application No. 7-35702 (PCT/,JP96/00419) "Transmission method, transmitter and receiver used for implementing the method", which was filed by the present assignee .
An embodiment of a transmitter receiver for a mobile system in accnr~;ln~- with the ?resent invention will now r ~ 2 1 8 9 8 2 0 be described, which implements the frequency division duplex (FDD) and time division duplex (TDD) in one device in such a transmission system.
First, the frequency division duplex (FDD) and time division du?lex (TDD) will be described with reference to Fig. 5. Fig. 5 is a schematic diagram illustrating transmission behavior of the FDD and TDD for one frequency, wherein Fig. 5 (A) illustrates transmitted data in the FDD mode, and Fig. 5 (B) illustrates transmitted 10 data in the TDD mode.
First, Fig. 5 (A) illustrates a state in which the transmitter of the transmitter receiver transmits using the assigned carrier frequency. The receiver of the transmitter receiver receives data using another carrier frequency .
On the other hand, Fig. 5 (B) illustrates a state in which the transmission and receptio~ are switched in accordance with time using the same carrier frequency. In this case, it is preferable that the transmission and 20 reception be altered at each slot because the pilot symbols are inserted in each slot.
Fig. 6 shows the configuration of the transmitter receiver which implements the FDD and TDD in one radio device. In Fig. 6, a framiny block 1 divides the transmitted data ses~uence into frames. An error correcting encoder 2 generates error correcting check bits in terms of each frame data. An interleaver 3 includes interleave memory 3A as shown in Fig. 2 for assembling the _ g _ -~ 2~89~20 frame data into data consisting of individual slots. In reading data from the interleave memory 3A, although the transfer rate VT (columns/sec) from column to column is constant, the read rate VR (bits/sec) at which the data in each column (Ms bits/sec) is read out is switched in response to the FDD or TDD mode. This will be described in further detail later.
A data modulator 4 carries out primary modulation of the data read out from the interleave memory 3A. A spread 10 modulator 5 carries out secondary modulation of the output of the data modulator 4 to produce a wideband signal from the narrowband signal, thereby outputting a spread signal.
A frequency converter 6 converts the spread signal into the transmitted signal at a assigned carrier frequency.
The carrier frequency is fed to the frequency converter 6 from a carrier freguency generator 9. The transmitted signal thus formed is radiated into air from an antenna 15 through a diplexer 7.
If the transmission power control is necessary as 20 shown in Fig. 4, a transmission power controller 17 is placed between the frequency converter 6 and the diplexer 7 to co~Ltrol the transmission power. In this case, the lengths of the pilot symbols, control data and quasi-important user data are each determined in advance so that the transmission power is controlled in accordance with the data lengths.
Next, the configuration of the receiver will be described. A received signal received through the antenna , . . .. . . _ . _ .. _ . . . . . ....... .. . .. .
~ 2 1 89820 15 and the diplexer 7 is fed to a fre~auency converter 14.
The received signal undergoes fres~uency conversion by the fre~luency converter 14 using a signal from the carrier fre~auency generator 9. The fresluency converted signal is converted into a narrowband modulation signal from a wideband spread signal by a spread signal demodulator 13, and then restored into the original data by a data demodulator 12.
A deinterleaver 11 recovers the original data frames 10 using a deinterleave memory llA. The write rate Vw (bits/sec) of data in each column of the deinterleave memory llA is switched in response to the FDD or TDD mode while keeping fixed the transfer rate VT from column to column. An error correcting decoder 10 carries out error correcting of each frame output from the deinterleaver 11, thereby outputting it as received data.
The transmitter and receiver are controlled by a main controller 20 and a sub-controller 21.
Fig. 7 is a block diagram showing a configuration of 20 the sub-controller 21. In this figure, a read clock generator 22 generates a read clock signal of the memory 3A of ~ the interleaver 3 and a read clock signal of the memory llA of the deinterleaver 11. On the other hand, a write clock generator 23 generates write clock signals of the memories 3A and llA. The fre~[uencies of the clock signals are controlled by a clock controller 24 such that both the read rate VR of the memory 3A and the write rate Vw of the memory llA become greater than twice a normal -9~20 rate VN = MS-VT (bits/sec) in the TDD mode, where Ms is the number of bits per column (bits/column) of the memories 3A and llA, and VT is a transfer rate (columns/sec: fixed) from column to column. The reason for setting in the TDD mode the read rate VR of the memory 3A and the write rate Vw of the ~nemory llA greater t~an twice the normal rate is to create a vacant time period in the output of the interleaver 3. For example, setting VR
= 2 . 5VN can create a vacant time period of 0 . 6 slot 10 duration in each slot. The vacant time period can be used to switch the transmission and reception.
More specifically, the clock controller 24 in the sub-controller 21 controls, in the FDD mode, the clock generators 22 and 23 such that they generate the clock signals of a frequency which causes the read rate VR of the memory 3A and the write rate Vw of the memory llA to be set at the normal rate VN. On the other hand, in the TDD mode, the clock controller 24 controls the clock generators 22 and 23 such that they generate the clock 20 signals of a fre~uency which causes the read rate VR in the read duration of the memory 3A to be set at greater than twice the normal rate, at 2 . 5VN, for example, and the write rate Vw in the write duration of the memory llA to be set at s~reater than twice the normal rate, at 2 ~ 5VNI
for example. The write rate to the memory 3A and the read rate from the memory llA are fixed at the normal rate VN
in both the FDD a~d TDD modes.
~ 2 ~ ~820 A carrier frequency controller 25 controls the frequency of the carrier generated by the carrier frequency generator 9 in response to the instructions of the main controller 20. Specifically, in the FDD mode, it controls the carrier frequency generator 9 such that the transmitting carrier frequency fT and the receiving carrier frequency fR take predet~ n~r~ different freguencies, whereas in the TDD mode, it controls the carrier frequency generator 9 such that the transmitting 10 carrier frequency fT coincides with the receiving carrier frequencY fR-With such an arrangement, the operation of theembodiment will now be described for implementing the FDD
and TDD in a single transmitter receiver.
A data sequence to be transmitted is fed to the framing block 1. The framing block 1 divides the transmitted data sequence into data of predetermined one frame duration (Tf ), thereby structuring frames . The error correcting encoder 2 error correcting encodes the 20 transmitted data in each frame to be fed to the interleaver 3. The interleaver 3 writes the transmitted data into each row ( in the horizontal direction) of the interleave memory 3A consisting of Ms rows and Ns columns at the normal rate VN. In this case, writing the pilot symbols in the first row will obviate the need for addi~g the pilot symbols later. The interleaver 3, after having written the transmitted data of one frame, reads out the written transmitted data from each column (in the vertical _ _ _ _ _ _ _ , .. . .. . , . . . . .... . .. .. .. .. . .. . . _ . _ . . . _ - -~ 2 1 ~982~
direction) from the memory 3A. The operation thereafter will be descri~ed separately under the h,,~1; n~s of the FDD
mode and TDD mode.
( 1 ) The operation of the FDD mode In the FDD mode, the interleaver 3 in the transmitter reads the transmitted data from column to column in the interleave memory 3A at the normal rate VN (=~S'VT) bits/sec in accordance with the clock signal fed from the read clock generator 22. Thus, the read rate of the 10 memory 3A is VR = VN in the FDD mode. Since each column of the memory 3A constitutes one slot, one slot consists of ~s bits (including the pilot symbols).
The transmitted data seguence produced by the interleaver 3 undergoes data modulation by the data modulator 4, followed by the spread modulation by the spread modulator 5. The spread signal is converted into a signal with a predetermined transmission carrier freguency ~f f r by the freguency converter 6 to be transmitted. The transmitter receiver has the diplexer 7 which separates 20 the signals associated with the transmission and the reception, carrier frequencies On the other hand, the freguency converter 14 of the receiver freguency converts the received signal using a predet~rm; ne(l freguency fR. The freguency converted received signal is despread by the spread signal demodulator 13, and then data demodulated by the data demodulator 12. The demodulated data is fed to the deinterleaver 11. The deinterleaver 11 writes the _ _ _ _ _ _ . .. , . . . .. _ . , ... . _ . .. .
--- 21 8982~
demodulated data into the deinterleave memory llA column by column ( in the vertical direction) at the write rate Vw = VN (normal rate) in accordance with the clock signal fed from the write clock generator 23. The written data is read out from the deinterleave memory llA row by row (in the horizontal direction) at the normal rate VN.
Thus, in the FDD mode, although the write rate of the deinterleave memory llA eguals the read rate of the interleave memory 3A, that is, the normal rate VN, the write direction and read direction of the deinterleave memory llA are inverse to those of the interleave memory 3A. In addition, the area in the deinterleave memory llA
corresponding to the area occupied by the pilot symbols in the interleave memory 3A is vacant. The deinterleaver 11 differs from the interleaver 3 in these two points. The data out~ut from the deinterleaver 11 undergoes error correcting decoding by the error correcting decoder 10, so that the original data is restored.
( 2 ) The operation of the TDD mode In the TDD mode, the carrier freguency controller 25 of the sub-controller 21 sets the transmitting carrier frequency fT and the receiving carrier freguency fR at the same freguency (fT = fR). In addition, the read rate VR
of the interleave memory 3A is set at VR > 2VN, and the write rate Vw of the deinterleave memory llA is set at Vw ~ 2VN. For example, VR of the interleave memory 3A and Vw of the deinterleave memory llA are set at VR = VW = 2 ~ 5VN~
thereby creating a vacant duration of 0 . 6 slot in each .. .. . ... .... . .. _ . . . . .. .. _ . . , _ _ _ _, ~ 2 1 89820 slot. The transmission and reception can be switched in the vacant duration. The r~ ; n; ~ operation is the same as that of the FDD mode.
The spread modulation, which modulates the signal after the data modulation using a spreading se(Iuence with a rate higher than the bit rate of the transmitted data, can set the rate (chip rate) of the spreading se~uence of the TDD mode at that of the FDD
mode, or at the higher rate by the factor of the read rate 10 of the FDD mode.
The present invention has been described in detail with respect to an embodiment and it will now be apparent from the foregoing to those skilled in the art that changes and modifications may be made without departing from the invention in its broader aspects, and it is the intention, therefore, in the appended claims to cover all such changes and modifications as fall within the true spirit of the invention.
The present invention relates to a CDM~ (Code Division Multiple Access) mobile communication system, and particularly to a transmitter receiver for a mobile communication system which achieves both frecIuency division duplex (FDD) and time division duplex (TDD) in one device.
In most public mobile communications, bidirectional communications is achieved by FDD. ~In this case, 10 different carrier fresLuencies are used to distinguish reverse link channels (from mobile stations to a base station) from forward link ~hilnnf~ (frQm the base station to the mobile stations). For example, in PDC (Personal Digital Cellular) utilizing an 800 MHz band, the carrier fre~auencies are s~aced 130 MHz apart (see, "Personal digital cellular telecommunication system RCR standard, RCR STD-27, Research & Development Center for Radio System) .
On the other hand, TDD can be em~loyed as another 20 bidirectio~al communication method. It assigns the same carrier fre~uency for the forward and reverse link r~hi lnn~ , and these rh;lnnPl ~: are distirlguished in the time domain. In other words, the same fre(auency is used alternately by the forward and reverse link channels. It is employed, fQr example, by PHS (Personal Handyphone System) (see, "Second generation codeless telecommunication system RCR standard, RCR STD-28r, Research ~ Development Center for Radio System).
~ 2 1 89820 It is therefore an object of the present invention to provide a transmitter receiver for a mobile communication system which achieves in one device both the frequency division duplex (FDD) and time division duplex (TDD) in a CDMP communication system.
According to an aspect of the present invention, there is provided a transmitter receiver for a C~A (Code Division Multiple Access ) mobile communication system including a transmitter and a receiver, the transmitter comprising:
an interleaver for interleaving each frame of transmitted data;
an interleave memory provided in the interleaver, the interleave memory being capable of writing and reading row by row and column by column, respecively;
modulation means for data modulating the interleaved transmitted data into a narrowband modulated signal; and spread modulation means for spread modulating the 20 narrowband modulated signal into a wideband modulated signal using a spreading sequence, wherein the interleaver writes the transmitted data into the interleave memory row by row, and reads the transmitted data from the interleave memory column by column, thereby carrying out the interleave, the receiver comprising:
despreading means for converting the wideband modulated signal into the narrowband modulated signal;
demodulation means for demodulating the narrowband signal into demodulated data;
a deinterleaver for deinterleaving the demodulated data frame by frame to recover the transmitted data; and a deinterleave memory provided in the deinterleaver, the deinterleave memory being capable of writing and reading column by column and row by row, respectively, wherein the interleaver writes the demodulated data into the deinterleave memory column by column, and reads the demodulated data from the deinterleave memory row by row, thereby carrying out the deinterleave, and the transmitter receiver comprising:
control means for controlli~g a transfer rate from column to column (columns/sec) at a E)redetermined fixed rate VT in reading data from the interleave memory and writing data into the deinterleave memory, and for variably controlling a read rate VR and a write rate Vw 20 (bits/sec) of data in each the column.
Here, the control means may set the read rate VR ~f each column of the interleave memory and the write rate Vw of each column of the deinterleave memory at VR = VW = VT-Ms in an FDD (Fre~uency Division Duplex) mode, where Ms is the number of bits in each the column, and VR > 2VT-Ms and Vw > 2V~-Ms in a TDD (Time Division Duplex) mode, and may switch in the TDD mode the _ _ , _ _, , , .... , . .. . . . .. . _ ... . .... .. . _ . ,, 2 ~ 8982Q
transmitter receiver from a transmitting mode to a receiving mode after reading a last bit of the column and keeps the receiving mode until starting reading of a next column.
The interleaver may write one or more pilot symbols at an initial position of the interleave memory.
The transmitter receiver for a mobile communication system may further comprise transmission power control means connected to an output side of the spread modulation 10 means for increasing transmission power of important data in the transmitted data.
The important data may comprise the pilot symbols and control data.
The above-mentioned column and row may be exchanged.
According to the present invention, the frequency division duplex (FDD) and the time division duplex (TDD) can be achieved in one device with a simple arrangement by simply controlling the read and write rates of the interleaver and deinterleaver in the CD~A mobile 2 0 communications .
In addition, writing pilot symbols at the initial position of an interleave memory obviates additional insertion of the pilot symbols thereafter.
The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiment thereof taken in conjunction ~ith the accompanying drawings .
~ 21~9820 Figs. lA-lC are schematic diagrams illustrating a transmission method used in an embodiment of a transmitter receiver for a mobile communication system in accordance with the present invention, wherein Fig. lA illustrates the arrangement of a transmitted data frame, Fig. lB
illustrates pilot symbols of a known pattern, and Fig. lC
illustrates the arrangement of a radio channel slot;
Fig. 2 is a schematic diagram illustrating the arrangement of an interleave memory 3A of the embodiment;
Fig. 3 is a schematic diagram illustrating a state of data stored in the memory 3A;
Fig. 4 is a schematic diagram illustrating an example of transmission power control in the embodimenti Fig. 5 is a schematic diagram illustrating FDD and TDD, in which Fig. 5 (A) illustrates the FDD mode, and Fig.
5 (B) illustrates the TDD mode;
Fig. 6 is a block diagram showing the embodiment of a transmitter receiver for a mobile communication system in accordance with the present invention; and Fig. 7 is a block diagram showing the configuration of a sub-controller of the embodiment.
The invention will now be described with reference to the accompanying drawings, First, the transmission method will be described of a CD~5A mobile communication system employed in the present invention .
~ 2t 8q820 Fig. lA illustrates a frame structure in a common mobile communications. A user data seguence to be transmitted is divided into frames of a predetermined fixed duration. Subseguently, control data is added to the initial position of each frame, and a check code (CRC
code, for example) of the user data in each frame is added to the final position of each frame, thereby forming one frame data. In Fig. lA, vacant portions in the frame takes place when the total transmission rate of the 10 control data, user data aRd check code is smaller than a mi~; possible rate.
One frame data is interleaved as illustrated in Fig.
3, and theR mapped onto a radio channel frame as shown in Fig. lB. Pilot symbols of a known patterR are periodically inserted into the frame. The pilot symbols are used at the receiving side for cohereRt detection.
This method is disclosed, for example, in S. Sampei, "Fading Compensation for 16QAM in Land Mobile Communications~, The Transactions of the Institute of 20 ElectroRics, Information and Communication Engineers of Japan B~ Tol. J72-B-II pp. 7-15, January 1989, or its revised English version, S. Sampei, et al. ~Rayleigh Fading Compensation for QAM in Land Mobile Radio Communications", IEEE Transactions on Vehicular TechRology, VOL. 42. No. 2, MAY 1993.
In Fig. lB, a section sandwiched between the pilot symbols is called a slot. If one frame consists of Ns -~ 2 t 89~20 slots, and one slot consists of Ms bits, then one frame consists of Ns-Ms bits.
The symbol sequence thus arranged undergoes primary modulation, followed by secondary modulation which spreads it using a spreading code sequence with a chip rate of an integer multiple of (tens to hundreds times) the modulated symbol rate, and is transmitted.
When the data is transmitted with the pilot symbols of a known pattern inserted periodically, the receiver 10 estimates the state of a transmission link at each data position in the slots by using the pilot symbols, and employs the estimate as the refererLce signals of the coherent ~t~t;~n (see the foregoing SamE?ei paper).
On the other hand, the transmitter is provided with an interleaver for assembling the transmitted data. Fig.
2 is a schematic diagram illustrating an interleave memory 3A for one frame used by the interleaver. The num~er of bits per row (that is, the number of columns) of the memory e(auals the number of slots, Ns, constituting one 20 frame, and the number of bits per column (that is, the number of rows) e~luals the ~-~r;mllm bit number Ms constituting one slot. The transmitted data of one frame is written bit by bit in the row of the interleave memory, whereas it is read in the colllmn.
Fig. 3 illustrates a state in which the data is written in the interleave memory 3A. As shown in Fig. 3, one frame data ;nc~lu~;n~ the check code (CRC) for error detection is written in the interleave memory 3A. The - ~ 21 89820 data thus written into the interleave memory 3A is read in the vertical direction (column by column), so that the data is sequentially mapped onto the slots. Thus, the column number ( l-Ns ) corresponds to the slot number in Fig. lB. By reading the data from the interleave memory in this way, the individual slots are arranged as shown in Fig. lC. The vacant portions in Fig. lC correspond to the vacant area in each frame.
The above is the configuration for preparing data at 10 the transmitter. The receiver, on the other hand, has a deinterleaver for reassembling the interleaved transmitted data into its original order. The deinterleaver also comprises a deinterleave memory with an arrangement similar to that of Fig. 2, except that the write and read directions are inverted to those of the interleaver. That is, the receiver obtains the original data by writing column by column direction and by reading row by row.
The transmission thus carried out enables the power of the mobile station to be reduced. Fig. 4 illustrates 20 this. The pilot symbols and control data next to them are transmitted with greater power. The vacant portion is not sent. The transmission method is disclosed in Japanese patent application No. 7-35702 (PCT/,JP96/00419) "Transmission method, transmitter and receiver used for implementing the method", which was filed by the present assignee .
An embodiment of a transmitter receiver for a mobile system in accnr~;ln~- with the ?resent invention will now r ~ 2 1 8 9 8 2 0 be described, which implements the frequency division duplex (FDD) and time division duplex (TDD) in one device in such a transmission system.
First, the frequency division duplex (FDD) and time division du?lex (TDD) will be described with reference to Fig. 5. Fig. 5 is a schematic diagram illustrating transmission behavior of the FDD and TDD for one frequency, wherein Fig. 5 (A) illustrates transmitted data in the FDD mode, and Fig. 5 (B) illustrates transmitted 10 data in the TDD mode.
First, Fig. 5 (A) illustrates a state in which the transmitter of the transmitter receiver transmits using the assigned carrier frequency. The receiver of the transmitter receiver receives data using another carrier frequency .
On the other hand, Fig. 5 (B) illustrates a state in which the transmission and receptio~ are switched in accordance with time using the same carrier frequency. In this case, it is preferable that the transmission and 20 reception be altered at each slot because the pilot symbols are inserted in each slot.
Fig. 6 shows the configuration of the transmitter receiver which implements the FDD and TDD in one radio device. In Fig. 6, a framiny block 1 divides the transmitted data ses~uence into frames. An error correcting encoder 2 generates error correcting check bits in terms of each frame data. An interleaver 3 includes interleave memory 3A as shown in Fig. 2 for assembling the _ g _ -~ 2~89~20 frame data into data consisting of individual slots. In reading data from the interleave memory 3A, although the transfer rate VT (columns/sec) from column to column is constant, the read rate VR (bits/sec) at which the data in each column (Ms bits/sec) is read out is switched in response to the FDD or TDD mode. This will be described in further detail later.
A data modulator 4 carries out primary modulation of the data read out from the interleave memory 3A. A spread 10 modulator 5 carries out secondary modulation of the output of the data modulator 4 to produce a wideband signal from the narrowband signal, thereby outputting a spread signal.
A frequency converter 6 converts the spread signal into the transmitted signal at a assigned carrier frequency.
The carrier frequency is fed to the frequency converter 6 from a carrier freguency generator 9. The transmitted signal thus formed is radiated into air from an antenna 15 through a diplexer 7.
If the transmission power control is necessary as 20 shown in Fig. 4, a transmission power controller 17 is placed between the frequency converter 6 and the diplexer 7 to co~Ltrol the transmission power. In this case, the lengths of the pilot symbols, control data and quasi-important user data are each determined in advance so that the transmission power is controlled in accordance with the data lengths.
Next, the configuration of the receiver will be described. A received signal received through the antenna , . . .. . . _ . _ .. _ . . . . . ....... .. . .. .
~ 2 1 89820 15 and the diplexer 7 is fed to a fre~auency converter 14.
The received signal undergoes fres~uency conversion by the fre~luency converter 14 using a signal from the carrier fre~auency generator 9. The fresluency converted signal is converted into a narrowband modulation signal from a wideband spread signal by a spread signal demodulator 13, and then restored into the original data by a data demodulator 12.
A deinterleaver 11 recovers the original data frames 10 using a deinterleave memory llA. The write rate Vw (bits/sec) of data in each column of the deinterleave memory llA is switched in response to the FDD or TDD mode while keeping fixed the transfer rate VT from column to column. An error correcting decoder 10 carries out error correcting of each frame output from the deinterleaver 11, thereby outputting it as received data.
The transmitter and receiver are controlled by a main controller 20 and a sub-controller 21.
Fig. 7 is a block diagram showing a configuration of 20 the sub-controller 21. In this figure, a read clock generator 22 generates a read clock signal of the memory 3A of ~ the interleaver 3 and a read clock signal of the memory llA of the deinterleaver 11. On the other hand, a write clock generator 23 generates write clock signals of the memories 3A and llA. The fre~[uencies of the clock signals are controlled by a clock controller 24 such that both the read rate VR of the memory 3A and the write rate Vw of the memory llA become greater than twice a normal -9~20 rate VN = MS-VT (bits/sec) in the TDD mode, where Ms is the number of bits per column (bits/column) of the memories 3A and llA, and VT is a transfer rate (columns/sec: fixed) from column to column. The reason for setting in the TDD mode the read rate VR of the memory 3A and the write rate Vw of the ~nemory llA greater t~an twice the normal rate is to create a vacant time period in the output of the interleaver 3. For example, setting VR
= 2 . 5VN can create a vacant time period of 0 . 6 slot 10 duration in each slot. The vacant time period can be used to switch the transmission and reception.
More specifically, the clock controller 24 in the sub-controller 21 controls, in the FDD mode, the clock generators 22 and 23 such that they generate the clock signals of a frequency which causes the read rate VR of the memory 3A and the write rate Vw of the memory llA to be set at the normal rate VN. On the other hand, in the TDD mode, the clock controller 24 controls the clock generators 22 and 23 such that they generate the clock 20 signals of a fre~uency which causes the read rate VR in the read duration of the memory 3A to be set at greater than twice the normal rate, at 2 . 5VN, for example, and the write rate Vw in the write duration of the memory llA to be set at s~reater than twice the normal rate, at 2 ~ 5VNI
for example. The write rate to the memory 3A and the read rate from the memory llA are fixed at the normal rate VN
in both the FDD a~d TDD modes.
~ 2 ~ ~820 A carrier frequency controller 25 controls the frequency of the carrier generated by the carrier frequency generator 9 in response to the instructions of the main controller 20. Specifically, in the FDD mode, it controls the carrier frequency generator 9 such that the transmitting carrier frequency fT and the receiving carrier frequency fR take predet~ n~r~ different freguencies, whereas in the TDD mode, it controls the carrier frequency generator 9 such that the transmitting 10 carrier frequency fT coincides with the receiving carrier frequencY fR-With such an arrangement, the operation of theembodiment will now be described for implementing the FDD
and TDD in a single transmitter receiver.
A data sequence to be transmitted is fed to the framing block 1. The framing block 1 divides the transmitted data sequence into data of predetermined one frame duration (Tf ), thereby structuring frames . The error correcting encoder 2 error correcting encodes the 20 transmitted data in each frame to be fed to the interleaver 3. The interleaver 3 writes the transmitted data into each row ( in the horizontal direction) of the interleave memory 3A consisting of Ms rows and Ns columns at the normal rate VN. In this case, writing the pilot symbols in the first row will obviate the need for addi~g the pilot symbols later. The interleaver 3, after having written the transmitted data of one frame, reads out the written transmitted data from each column (in the vertical _ _ _ _ _ _ _ , .. . .. . , . . . . .... . .. .. .. .. . .. . . _ . _ . . . _ - -~ 2 1 ~982~
direction) from the memory 3A. The operation thereafter will be descri~ed separately under the h,,~1; n~s of the FDD
mode and TDD mode.
( 1 ) The operation of the FDD mode In the FDD mode, the interleaver 3 in the transmitter reads the transmitted data from column to column in the interleave memory 3A at the normal rate VN (=~S'VT) bits/sec in accordance with the clock signal fed from the read clock generator 22. Thus, the read rate of the 10 memory 3A is VR = VN in the FDD mode. Since each column of the memory 3A constitutes one slot, one slot consists of ~s bits (including the pilot symbols).
The transmitted data seguence produced by the interleaver 3 undergoes data modulation by the data modulator 4, followed by the spread modulation by the spread modulator 5. The spread signal is converted into a signal with a predetermined transmission carrier freguency ~f f r by the freguency converter 6 to be transmitted. The transmitter receiver has the diplexer 7 which separates 20 the signals associated with the transmission and the reception, carrier frequencies On the other hand, the freguency converter 14 of the receiver freguency converts the received signal using a predet~rm; ne(l freguency fR. The freguency converted received signal is despread by the spread signal demodulator 13, and then data demodulated by the data demodulator 12. The demodulated data is fed to the deinterleaver 11. The deinterleaver 11 writes the _ _ _ _ _ _ . .. , . . . .. _ . , ... . _ . .. .
--- 21 8982~
demodulated data into the deinterleave memory llA column by column ( in the vertical direction) at the write rate Vw = VN (normal rate) in accordance with the clock signal fed from the write clock generator 23. The written data is read out from the deinterleave memory llA row by row (in the horizontal direction) at the normal rate VN.
Thus, in the FDD mode, although the write rate of the deinterleave memory llA eguals the read rate of the interleave memory 3A, that is, the normal rate VN, the write direction and read direction of the deinterleave memory llA are inverse to those of the interleave memory 3A. In addition, the area in the deinterleave memory llA
corresponding to the area occupied by the pilot symbols in the interleave memory 3A is vacant. The deinterleaver 11 differs from the interleaver 3 in these two points. The data out~ut from the deinterleaver 11 undergoes error correcting decoding by the error correcting decoder 10, so that the original data is restored.
( 2 ) The operation of the TDD mode In the TDD mode, the carrier freguency controller 25 of the sub-controller 21 sets the transmitting carrier frequency fT and the receiving carrier freguency fR at the same freguency (fT = fR). In addition, the read rate VR
of the interleave memory 3A is set at VR > 2VN, and the write rate Vw of the deinterleave memory llA is set at Vw ~ 2VN. For example, VR of the interleave memory 3A and Vw of the deinterleave memory llA are set at VR = VW = 2 ~ 5VN~
thereby creating a vacant duration of 0 . 6 slot in each .. .. . ... .... . .. _ . . . . .. .. _ . . , _ _ _ _, ~ 2 1 89820 slot. The transmission and reception can be switched in the vacant duration. The r~ ; n; ~ operation is the same as that of the FDD mode.
The spread modulation, which modulates the signal after the data modulation using a spreading se(Iuence with a rate higher than the bit rate of the transmitted data, can set the rate (chip rate) of the spreading se~uence of the TDD mode at that of the FDD
mode, or at the higher rate by the factor of the read rate 10 of the FDD mode.
The present invention has been described in detail with respect to an embodiment and it will now be apparent from the foregoing to those skilled in the art that changes and modifications may be made without departing from the invention in its broader aspects, and it is the intention, therefore, in the appended claims to cover all such changes and modifications as fall within the true spirit of the invention.
Claims (12)
1. A transmitter receiver for a CDMA (Code Division Multiple Access) mobile communication system including a transmitter and a receiver, said transmitter comprising:
an interleaver for interleaving each frame of transmitted data;
an interleave memory provided in said interleaver, said interleave memory being capable of writing and reading row by row and column by column, respectively;
modulation means for data modulating the interleaved transmitted data into a narrowband modulated signal; and spread modulation means for spread modulating said narrowband modulated signal into a wideband modulated signal using a spreading sequence, wherein said interleaver writes said transmitted data into said interleave memory row by row, and reads said transmitted data from said interleave memory column by column, thereby carrying out the interleave, said receiver comprising:
despreading means for converting said wideband modulated signal into said narrowband modulated signal;
demodulation means for demodulating said narrowband signal into demodulated data;
a deinterleaver for deinterleaving said demodulated data frame by frame to recover said transmitted data; and a deinterleave memory provided in said deinterleaver, said deinterleave memory being capable of writing and reading column by column and row by row respectively, wherein said interleaver writes said demodulated data into said deinterleave memory column by column, and reads said demodulated data from said deinterleave memory row by row, thereby carrying out the deinterleave, and said transmitter receiver comprising:
control means for controlling a transfer rate from column to column (columns/sec) at a predetermined fixed rate VT in reading data from said interleave memory and writing data into said deinterleave memory, and for variably controlling a read rate VR and a write rate VW
(bits/sec) of data in each said column.
an interleaver for interleaving each frame of transmitted data;
an interleave memory provided in said interleaver, said interleave memory being capable of writing and reading row by row and column by column, respectively;
modulation means for data modulating the interleaved transmitted data into a narrowband modulated signal; and spread modulation means for spread modulating said narrowband modulated signal into a wideband modulated signal using a spreading sequence, wherein said interleaver writes said transmitted data into said interleave memory row by row, and reads said transmitted data from said interleave memory column by column, thereby carrying out the interleave, said receiver comprising:
despreading means for converting said wideband modulated signal into said narrowband modulated signal;
demodulation means for demodulating said narrowband signal into demodulated data;
a deinterleaver for deinterleaving said demodulated data frame by frame to recover said transmitted data; and a deinterleave memory provided in said deinterleaver, said deinterleave memory being capable of writing and reading column by column and row by row respectively, wherein said interleaver writes said demodulated data into said deinterleave memory column by column, and reads said demodulated data from said deinterleave memory row by row, thereby carrying out the deinterleave, and said transmitter receiver comprising:
control means for controlling a transfer rate from column to column (columns/sec) at a predetermined fixed rate VT in reading data from said interleave memory and writing data into said deinterleave memory, and for variably controlling a read rate VR and a write rate VW
(bits/sec) of data in each said column.
2. The transmitter receiver for a mobile communication system as claimed in claim 1, wherein said control means sets the read rate VR of each column of said interleave memory and the write rate VW of each column of said deinterleave memory at VR = VW = VT ~ MS in an FDD (Frequency Division Duplex) mode, where MS is the number of bits in each said column, and VR > 2VT ~ Ms and VW > 2VT ~ Ms in a TDD (Time Division Duplex) mode, and switches in said TDD mode said transmitter receiver from a transmitting mode to a receiving mode after reading a last bit of said column and keeps the receiving mode until starting reading of a next column.
3. The transmitter receiver for a mobile communication system as claimed in claim 1, wherein said interleaver writes one or more pilot symbols at an initial position of said interleave memory.
4. The transmitter receiver for a mobile communication system as claimed in claim 2, wherein said interleaver writes one or more pilot symbols at an initial position of said interleave memory.
5. The transmitter receiver for a mobile communication system as claimed in claim 1, further comprising transmission power control means connected to an output side of said spread modulation means for increasing transmission power of important data in said transmitted data.
6. The transmitter receiver for a mobile communication system as claimed in claim 5, wherein said important data comprises said pilot symbols and control data.
7. A transmitter receiver for a CDMA (Code Division Multiple Access) mobile communication system including a transmitter and a receiver, said transmitter comprising:
an interleaver for interleaving each frame of transmitted data;
an interleave memory provided in said interleaver, said interleave memory being capable of writing and reading row by row and column by column, respectively;
modulation means for data modulating the interleaved transmitted data into a narrowband modulated signal; and spread modulation means for spread modulating said narrowband modulated signal into a wideband modulated signal using a spreading sequence, wherein said interleaver writes said transmitted data into said interleave memory column by column, and reads said transmitted data from said interleave memory row by row, thereby carrying out the interleave, said receiver comprising:
despreading means for converting said wideband modulated signal into said narrowband modulated signal;
demodulation means for demodulating said narrowband signal into demodulated data;
a deinterleaver for deinterleaving said demodulated data frame by frame to recover said transmitted data; and a deinterleave memory provided in said deinterleaver, said deinterleave memory being capable of writing and reading column by column and row by row respectively, wherein said interleaver writes said demodulated data into said deinterleave memory row by row, and reads said demodulated data from said deinterleave memory column by column, thereby carrying out the deinterleave, and said transmitter receiver comprising:
control means for controlling a transfer rate from column to column (column/sec) at a predetermined fixed rate VT in reading data from said interleave memory and writing data into said deinterleave memory, and for variably controlling a read rate VR and a write rate VW
(bits/sec) of data in each said row.
an interleaver for interleaving each frame of transmitted data;
an interleave memory provided in said interleaver, said interleave memory being capable of writing and reading row by row and column by column, respectively;
modulation means for data modulating the interleaved transmitted data into a narrowband modulated signal; and spread modulation means for spread modulating said narrowband modulated signal into a wideband modulated signal using a spreading sequence, wherein said interleaver writes said transmitted data into said interleave memory column by column, and reads said transmitted data from said interleave memory row by row, thereby carrying out the interleave, said receiver comprising:
despreading means for converting said wideband modulated signal into said narrowband modulated signal;
demodulation means for demodulating said narrowband signal into demodulated data;
a deinterleaver for deinterleaving said demodulated data frame by frame to recover said transmitted data; and a deinterleave memory provided in said deinterleaver, said deinterleave memory being capable of writing and reading column by column and row by row respectively, wherein said interleaver writes said demodulated data into said deinterleave memory row by row, and reads said demodulated data from said deinterleave memory column by column, thereby carrying out the deinterleave, and said transmitter receiver comprising:
control means for controlling a transfer rate from column to column (column/sec) at a predetermined fixed rate VT in reading data from said interleave memory and writing data into said deinterleave memory, and for variably controlling a read rate VR and a write rate VW
(bits/sec) of data in each said row.
8. The transmitter receiver for a mobile communication system as claimed in claim 7, wherein said control means sets the read rate VR of each row of said interleave memory and the write rate VW of each row of said deinterleave memory at VR = VW - VT~Ms in an FDD (Frequency Division Duplex) mode, where MS is the number of bits in each said row, and VR > 2VT ~ Ms and VW > 2VT ~ MS in a TDD (Time Division Duplex) mode, and switches in said TDD mode said transmitter receiver from a transmitting mode to a receiving mode after reading a last bit of said row and keeps the receiving mode until starting reading of a next row.
9. The transmitter receiver for a mobile communication system as claimed in claim 7, wherein said interleaver writes one or more pilot symbols at an initial position of said interleave memory.
10. The transmitter receiver for a mobile communication system as claimed in claim 8, wherein said interleaver writes one or more pilot symbols at an initial position of said interleave memory.
11, The transmitter receiver for a mobile communication system as claimed in claim 7, further comprising transmission power control means connected to an output side of said spread modulation means for increasing transmission power of important data in said transmitted data.
12. The transmitter receiver for a mobile communication system as claimed in claim 11, wherein said important data comprises said pilot symbols and control data.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP291,475/1995 | 1995-11-09 | ||
| JP29147595 | 1995-11-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2189820A1 CA2189820A1 (en) | 1997-05-10 |
| CA2189820C true CA2189820C (en) | 2000-07-25 |
Family
ID=17769362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002189820A Expired - Fee Related CA2189820C (en) | 1995-11-09 | 1996-11-07 | Transmitter receiver for mobile communication system |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5850393A (en) |
| EP (1) | EP0773639B1 (en) |
| KR (1) | KR100219339B1 (en) |
| CN (1) | CN1086522C (en) |
| CA (1) | CA2189820C (en) |
| DE (1) | DE69630095T2 (en) |
Families Citing this family (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2934185B2 (en) * | 1996-03-15 | 1999-08-16 | 松下電器産業株式会社 | CDMA cellular radio base station apparatus, mobile station apparatus, and transmission method |
| JPH09271070A (en) * | 1996-03-29 | 1997-10-14 | Matsushita Electric Ind Co Ltd | Digital mobile object communication equipment |
| JPH1051354A (en) * | 1996-05-30 | 1998-02-20 | N T T Ido Tsushinmo Kk | Ds-cdma transmission method |
| US5987010A (en) * | 1997-05-15 | 1999-11-16 | Advanced Micro Devices, Inc. | System and method for providing FDD and TDD modes of operation for a wireless communications device |
| US6351458B2 (en) * | 1997-09-22 | 2002-02-26 | Matsushita Electric Industrial Co., Ltd. | CDMA cellular wireless communication system |
| DE19747367C2 (en) * | 1997-10-27 | 2003-06-26 | Siemens Ag | Method and arrangement for the transmission of data via a radio interface in a radio communication system |
| US6529492B1 (en) * | 1997-12-30 | 2003-03-04 | Matsushita Electric Industrial Co., Ltd. | CDMA radio multiplex transmitting device and a CDMA radio multiplex receiving device |
| JP3881770B2 (en) | 1998-03-10 | 2007-02-14 | 松下電器産業株式会社 | Mobile station apparatus and communication method |
| WO1999048227A1 (en) * | 1998-03-14 | 1999-09-23 | Samsung Electronics Co., Ltd. | Device and method for exchanging frame messages of different lengths in cdma communication system |
| JP3166705B2 (en) * | 1998-04-16 | 2001-05-14 | 松下電器産業株式会社 | Wireless device and transmission method |
| JP3359291B2 (en) * | 1998-07-17 | 2002-12-24 | 株式会社ケンウッド | Deinterleave circuit |
| EP0975184A1 (en) * | 1998-07-20 | 2000-01-26 | Motorola, Inc. | Method of allocating resources and allocation scheme therefor |
| EP1826938A1 (en) * | 1998-07-24 | 2007-08-29 | Matsushita Electric Industrial Co., Ltd. | CDMA radio communication system and method |
| DE19842039B4 (en) * | 1998-09-14 | 2014-09-04 | Siemens Aktiengesellschaft | Method for transmitting signaling information in a radio communication system |
| US6411649B1 (en) * | 1998-10-20 | 2002-06-25 | Ericsson Inc. | Adaptive channel tracking using pilot sequences |
| KR100326045B1 (en) * | 1999-02-03 | 2002-03-07 | 윤종용 | Method for modulation and demodulation in CDMA/FDD transceiver and apparatus thereof |
| EP1914895B1 (en) * | 1999-05-10 | 2017-11-01 | NTT DoCoMo, Inc. | Data multiplexing method and data multiplexer, and data transmitting method and data transmitter |
| DE10001491A1 (en) * | 2000-01-14 | 2001-07-19 | Bosch Gmbh Robert | Method and device for the synchronization of data transmission devices |
| CN1377142B (en) * | 2001-03-22 | 2010-06-16 | 中兴通讯股份有限公司 | Method and device for implementing fast deinterleave |
| TW572534U (en) * | 2001-04-16 | 2004-01-11 | Interdigital Tech Corp | A time division duplex/code division multiple access (FDD/CDMA) user equipment |
| TWI245512B (en) | 2002-04-15 | 2005-12-11 | Interdigital Tech Corp | Apparatus capable of operating in both time division duplex (TDD) and frequency division duplex (FDD) modes of wideband code division multiples access (CDMA) |
| US7289459B2 (en) * | 2002-08-07 | 2007-10-30 | Motorola Inc. | Radio communication system with adaptive interleaver |
| JP3877215B2 (en) * | 2003-10-10 | 2007-02-07 | 株式会社インテリジェント・コスモス研究機構 | Transmission device, communication system, and communication method |
| JP2007115099A (en) * | 2005-10-21 | 2007-05-10 | Toshiba Corp | Memory system and recording media |
| CN101192197B (en) * | 2006-11-20 | 2011-10-26 | 深圳迈瑞生物医疗电子股份有限公司 | De-interleaver, deinterleaving method and doppler's ultrasonic diagnosis apparatus adopting same |
| US20080133997A1 (en) * | 2006-12-01 | 2008-06-05 | Broadcom Corporation, A California Corporation | Turbo decoder employing ARP (almost regular permutation) interleave and inverse thereof as de-interleave |
| US8514129B1 (en) * | 2010-04-12 | 2013-08-20 | Marvell International Ltd. | Buffering techniques for rapid processing of samples of signals modulated with periodic waveforms |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4063038A (en) * | 1975-11-24 | 1977-12-13 | Digital Communications Corporation | Error coding communication terminal interface |
| US4217660A (en) * | 1978-07-17 | 1980-08-12 | Motorola, Inc. | Method and apparatus for the coding and decoding of digital data |
| GB8826918D0 (en) * | 1988-11-17 | 1988-12-21 | Motorola Inc | Power amplifier for radio frequency signal |
| US5103459B1 (en) * | 1990-06-25 | 1999-07-06 | Qualcomm Inc | System and method for generating signal waveforms in a cdma cellular telephone system |
| US5341396A (en) * | 1993-03-02 | 1994-08-23 | The Boeing Company | Multi-rate spread system |
| FI97661C (en) * | 1993-12-10 | 1997-01-27 | Nokia Mobile Phones Ltd | Procedures for data communication, CDMA transmitters and receivers |
| JP3169522B2 (en) * | 1995-01-19 | 2001-05-28 | 沖電気工業株式会社 | Data receiving device |
| US5689502A (en) * | 1995-06-05 | 1997-11-18 | Omnipoint Corporation | Efficient frequency division duplex communication system with interleaved format and timing adjustment control |
-
1996
- 1996-11-05 DE DE69630095T patent/DE69630095T2/en not_active Expired - Lifetime
- 1996-11-05 US US08/743,192 patent/US5850393A/en not_active Expired - Lifetime
- 1996-11-05 EP EP96308016A patent/EP0773639B1/en not_active Expired - Lifetime
- 1996-11-07 CA CA002189820A patent/CA2189820C/en not_active Expired - Fee Related
- 1996-11-07 KR KR1019960052569A patent/KR100219339B1/en not_active IP Right Cessation
- 1996-11-08 CN CN96114536A patent/CN1086522C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| EP0773639B1 (en) | 2003-09-24 |
| US5850393A (en) | 1998-12-15 |
| CN1156352A (en) | 1997-08-06 |
| DE69630095D1 (en) | 2003-10-30 |
| CA2189820A1 (en) | 1997-05-10 |
| DE69630095T2 (en) | 2004-07-08 |
| CN1086522C (en) | 2002-06-19 |
| EP0773639A2 (en) | 1997-05-14 |
| EP0773639A3 (en) | 1998-05-20 |
| KR100219339B1 (en) | 1999-09-01 |
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