CA2189661A1 - Large aperture ratio array architecture for active matrix liquid crystal displays - Google Patents
Large aperture ratio array architecture for active matrix liquid crystal displaysInfo
- Publication number
- CA2189661A1 CA2189661A1 CA002189661A CA2189661A CA2189661A1 CA 2189661 A1 CA2189661 A1 CA 2189661A1 CA 002189661 A CA002189661 A CA 002189661A CA 2189661 A CA2189661 A CA 2189661A CA 2189661 A1 CA2189661 A1 CA 2189661A1
- Authority
- CA
- Canada
- Prior art keywords
- liquid crystal
- crystal display
- active matrix
- source
- drain means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2202/00—Materials and properties
- G02F2202/10—Materials and properties semiconductor
- G02F2202/105—Materials and properties semiconductor single crystal Si
Abstract
An active matrix array for liquid crystal displays which provides for a large aperture ratio. A layer (10) of single crystal silicon is disposed over a glass substrate and etched and doped to form multiple source and drain regions (16) for an array of thin film transistors (TFTs). Multiple gate buses (14) are laid across the source and drain regions to form the TFTs. The drain regions each electrically contact a transparent electrode (18) used in switchting an individual pixel in a liquid crystal display. The TFTs formed do not encroach significantly into the pixel aperture and the conduction lines are constructed at minimal photolithographical requirements.
Description
, 2189661 LARGL API~RTURE RATIO ARRAY ARCHITECTURl~
FOR ACTIVE MATRIX LIQUID CRYSTAL DISPLAYS
Fr~.l .r) OF T~ INY:F NTIQN
The present illYcntion pertains to actiYe matri.~ Iiquid crystal displays (AMLCD's), and molc particularly, to providing a larger aperture ratio in an AMLCD.
BACK('.ROUNI) QF T~F INYl~ TIQN
LCD tech~ology is being developed as a possible successor to cathode ray (CRT
technology for many applications. LCD technology offers important advantages, sucll as lligh reliability an l reduced power, size and weight. However, in the current state of lo development, LCD iull~ge rendering capabilities fall short of that achievable from the use of CRrs.
rhere is a greaL lleed for high resolution thin film transistor/liquid crystal displays in a wide rarge of possible applications ranging from portable computers and test equipment to higll resolution projection TV's. Such displays typically consist of a large number of pict~re elements (pixel) arramged in an active matri~c. For a display system where the elcctro-optica~ medium is liquid crystal, each pi:Yel is defined by a dedicated electrode ol~ one side of two opposite trarlsparent substrates and another electrode, which is common to all pixels and faces the viewer.
Figure I illustrates in circuit form a prior att TFT liquid crystal display device.
Each pi.cel in the active matrix is comprised of a TFT switch and a liquid crystal capacitor. The TFT gale electrodes for all the cells in a row are connected to a common horizontal gate bus, ~vhile tlle TFT sources in all the cells of each column are connected to a vertical data bus. The cells are addressed in a "line-at-a-time" or by line-by-line mode. By pulsing a ~ate bus to a positive potential relative to the source potential ~5 during the addressing interval for a particular row, the TFT's in that ro-v are switched on. At the same time, Llle data signal voltages on the source busses are transferred to the TFT output elecLrodes (drains) and the liquid crystal capacitors. ~'ihen the gate bus is s~vitched off as thc ne:<t row is addressed, the data signals are stored on tbe capacitors until the next addressing cycle for a particular row in tlle succeeding frame.
In the above described display system, the number of row and column conductors needed ~ b to the nurnber of rows n and columns m for n X m pixels. In addition to the need to devote a portion of area of the display device to _ _ _ . _ _ . _ __ -- = , . , ,, , , _ _._,, , ~ . = .
A~ENUEO SH~E~
accomrnodate the row i~lld column conductors there is also a possibility that, in view of the large number of collduclors used, olle or more of these conductors may be defective, rendering the display d.:vice unusable. This problem is quite common ae the crossovers of row and colunln coll iuctors. Obviously, the more conductors employed the greater 5 this possibi~ity becomes to adversely affect the yield of a large area display device.
Furthemlore, tilc large number of row and column conductors causes problems with the production of smrlil area display devices which are used for projectiondisplays. Large area displays can be obtained from small area TFT liquid crystaldisplays by using a projection system in which the image produced by the small area 10 display is projected oll~o a large area screen. However, in order to provide the desired display resolution aftcr projection, the dispiay device generating image should have an adequate number of row and columns of pixel density. If the number of the row and column conductors is large, a large portion of the display area is occupied by the conductors amd the aperture ratio (i.e., display area where light can ~ it/t~ Li area) 15 on the display is small. Then the display e~chibits low light levels.
Figure 2 illustrates cnnfi~llr~ti~ n of a typical prior art liquid crystal display array. Included in the array are gate bus lines 4 and source bus lines 6 which intersect in a grid-like pattern. Between the bus lines are picture elements ~vhich is usually liquid crystai held bctween two transparent electrodes 2. In one comer of the picture 20 elemerlt is the switching element, a thin fii~n transistor ~TFT) 5, which either adds or removes the voltage from the liquid crystal thus maicing the picture element either clear or opaque. The TFT is comprised of the gate electrode 8, tile drairl electrode ~ as well as the drain. In this ~onFi~llr~tinn~ the 11/1111. ~ for the TFT encroaches upon the nommaily rectangular picture element. Beciluse of the need of hard contacts between the 25 different bus lines, this large of a structure is necessary.
The largest reduction in aperture area for conventional AMLCD layouts is due to the need for the il.t ,l~,ul .~ and contacts. Specifically, the source databus and the gate databus dramaticrllly reduce the pixel aperture. These busses must be made larger than the minimum phvtolithographic~l dimcnsion duc to thc prescncc of sourcc alld 30 drain contacts at each pixel. Also, a major cause of failure of the prior art devices during their operatillg life is due to the contacts separating.
AMENDED SHEET
~ 3 2189661 A further disadvantage of tlle prior art metllods is the processing method used to construct the army: In order to provide properly conductive bus lines, metal must be used to end the array. Metal/indium tin oxide (}TO) ron~ lnnin~ n is n maior source of yield loss. Also, the desi~n of the prior Qrt is complicated by tlle need for multiple 5 layers of metal.
A prior art rcrerence of ci~nifir~nre is European Fatent application 103,523 which discloses a metllod of ~ ..ur~l~,Lu.~ of electronic circuits based on thin-film transistors and capQcitors. According to the method of the invention, conductive, photogravure, and insulating are layed down on a substrate in a particular order to 10 create a matrix of thin film transistors and capQCitors which has applications in liquid crystQI displays.
The present invention offers the advantages of providing a larger aperture ratioand greatly simplifying the design Qnd fabrication of active matrix liquid crystal displays.
SITMM~RY OF TT~li' IN~ENTION
The invention described herein is an active matrix which provides a large aperture ratio in a liq~lid crystal display. The liquid crystal display is comprised of a lower substrate with multiple parallel source lines disposed thereon. Also disposed on the lower substrate are drain means for a thin film transistor (TFT). An insulating layer 20 is disposed over botll the data line and the drain means. Multiple gate lines are disposed over the insulating layer so as to intersect the data lines and drain means. The int~rcer~inn of these ~llree elemenOE forms an array of TFTs, proximate to each of TFTs is a transparent electrode which is ill ul,u~ ;d into the picture elements for the liquid crystal display. The drain means of each TFT contacOE the transparent electrode to 25 provide individual switching of the picture elements within the LCD.
The large aperture ratio for tlle AMLCD is possible for a variety of reasons.
First, the source and 8ate lines for the switching elements in the array can be u~d using minimum photol,~ imPn~irJn~ Also, the gate and sourcc can be ,u~ u-L~d of transparent conductive material thus improving the light ~0 trnn~mic~ir~n Also, the removal of the metal contacts eliminates the ~ va~L~ t of the switching element into the picture element, thus increasing its aperture ratio. The reduction of contacts in tl1e array also improves display ~eliability. These _ _ _ _ , .. .. _ .. . . , _ , .. . .. . . .
AMEI`IûED SHEET
~ 4 218966 1 improvements enllallce tlle ~ of t~le high perrormancc ~ctive matrix liquid crystal displays BRII~,~ DF..S~RIPTIQN OF T~l~. nRAWllYGS
Figure I sl~ows a circuit diagram for a prior art AMLCD device.
Figu~e 2 is a pixel configuration for a prior art AMLCD device.
Figure 3a is a ~vp view of a contactless array, Figure 3b is a view of the contactless array alon~ the ~ate bus, Figure 3c is a view of the contactless array parallel to the gate bus, Figurc 3d is a view of the contactless array along the drain, and Figure 3e is a view of the gale bus along the source bus.
o Figure 4 is a Lop view of the source and drain regions in the single crystal silicon layer for the contacLless array.
Figure 5 is a cross sectional view of a pixel in the large aperture ration ~MLCD.
Figure 6a is a top view of the contactless array in the half tone confi~..r~ri~ n, and Figure 6b is a cross sectional view of the llalf tone version of the contætless array along the gate bus.
Figure 7 is a top view of the source and drain regions in the single crystal silicon layer for the halftone contactless array.
Figure 8a is a top view of the shared contact array, Figure 8b is a cross sectional view of a shared contact, and Figure 8c is a cross sectional view of the source bus.
Figure 9 is a top view of the source and drain regions in the single crystal silicon layer for the shared source array Figure 10 is a top view of the shared source array in a half tone configuration.Figure 11 is a top view of the source and drain regions in the single crystal silicon layer for the shared source halftone array.
DT~`SCRIPTION OF TTT~ PRF,T~'ERR~T~ EMT~ODTMlilNTS
Figure 3a discloses a partial top view for a contactless array ~ iL~ c for a large aperture ratio active matrix liquid crystal display (AMLCD). The array in the first ~;lllbodil~ of tlle invention is comprised of source buses 12 which run vertically and are in electrical contact with display drivers ~not shown~ that provide the image signals. The source buses 12 intersect gate buses 14 which run horizontally. The gate buses are also in elec~rical contact with the display drivers (not shown). ~n~Pr~r~''Pd between the intersectivns of the gate and source buses are the transparent electrodes 18 AME~ S S~ ~
~ 5 2189661 for each pixel in the liquid crystal display. Tlle pi,~el elcctrodes 18 are in electrical contact with drain re~ions 16. All the elements shown in Figure 3a are disposed on a common substrate. The in~ersection of tlle source bus, drain region, and gnte bus form a thin film transistor (TFT) which is the switching element for the pixels ill the display.
5 A better llnd~rctrln~ling of the construction of the TFT can be understood by study of Figures 4 and 3b-3e.
Figure 4 is a vicw of just the source bus nnd drains deposited on a clear glass substrate which serves as the base layer for tlle entire active matrix. The source buses 12 are defined in a buricd layer of single erystal silieon 10 that hns been heavily doped l o n+ to reduee line resis~anee. The region deflned by the drain 16 has also been heavily doped n+. The region bet-~een the source IZ and the drain 16 ~vhich is part of the silicon layer 10 is left undoped. The souree buses and drains may also be constructed of a strip of refractory metal silieide sueh as titanium, or Tungsten, laid on top of a layer of polysilieon. This eaul be done in the eases where a lower resistanee is required.
5 Further, the gate buses and drains may also be eonstrueted oftransferred silieon through a teehnology provided by the Kopin Corporation. Referring again to Figure 3a the gaîe buses are then Inid over the source buses and the transparent electrodes are interspaced between the int~rcectinn of the buses. The gate bus in the preferred embodiment is constructed from indiuull tin oxide (ITO) which is transparent and conductive. This 20 material has the propem,ulld~ ivi~y to carry the gate signal. Other possibilities for gate bus materials are polysilicon or a refractory metal silicide like titanium as Tungsten.
The gate and drain buses may also inelude a layer of refrnetory metal silicide such as titanium, whieh eould be laid on the top of the silieon. This can be done in the cases where a lower resistance is required.
From the eross seetion along the gate bus shown in Figure 3b, the ~:~ul:,lul,LiJof the TFT is apparent. After the silieon layer whieh defines the souree bus nnd the drain bus is laid, a layer of oxide is then deposited over these eo~ "J~ The gate bus is then deposited Oll the oxide layer so as to interseet the souree bus. The souree region 12 of the silieon layer 10 is proximale to the drain portion 16, and eurrent through the transistor is eontrolled by the signal traveling over the gate bus 14. The eross seetion shown in l~igure 3c whieh is a eut through the tr~nsparent eleetrode shows the proximity of the pi:cel eleetrode 18 to the souree bus 12.
r ~r~~
. ~ 6 ~189661 The cross section shown in Figurc 3~ is ~aken il1 a direction parnllel to the drain 16. Sl1o~va in pnrticul~r is Llle electrical contnct between the drain and tlle pixel elcctrode 18 ns well .as the pro:<imity of tlle dr~in to the gate bus. The nature of the connection betw~en t~lC drain and tl~e pi.~el electrode is clcnrly evidcnt. This contnct is made through well kno-~n Sf~n~ir~r~ r fabrication techaiques rather thna a metalcontact. The cross seclion showa in Figure 3e is along the source bus. Shown in particular is tlle relatiollship between the source bus nad tlle gate bus.
The elemcnts in Figure 3a combine to forra the active Mntrix for a liquid crystal display. Image signnls are transmitted along tlle gate and source buses so ns to0 selectively provide a cllnrge at the pixel electrodes. As will be described in more detail below, the absence or l~resence of a charge at the phcel electrode controls whether that pixel is eitller on or olf. As is well known in the art, the turaing on or off of that pixel is in response to the switchiag of a transistor which is proximate to the pixel. In prior art AMLCD's, thesc transistors require metal contacts between the source bus line and the traasistor as weLI as a metal contact between the drain of the transistor aad the drain electrode. These n~etal contacts are a weak link in the LCD becnuse it is well kaown in CMOS technology tlmt one of the first thing to fail in tllese transistors is tlle metal contacts. The matrix shown in Figure 3a has no metal contacts conaecting the bus liaes to the transistor aad the transistor to the drain electrode. Furtller, the use of traasistors ~o wita metal contacts requires that the transistor be located in a comer of the pixel aperture. The t~ ,lu~l.hl~ of the transistor into the aperture can be clearly seen in the prior art matrix shown in Figure 2. In the present invention, the ~olla~lu~Lioa of the traasistoris ul~,u.rul_~.linto theconstructionofthebuslines, thus ,~ ;"l;,~ the pixel aperture.
The incorporation of the matri.x shown in Figure 3a into a liquid crystal display picture element is shown in Figure 5. Figure 5 is a cross sectiorl all view of the active portion of a liquid cryatal display tl~rough the middle of a single pixel. Included in the active portion of khe display are the glass subskates 30 which enclose the elements described above. Laid over the lower substrate 30 is a layer of single crystnl silicon 10 This silicon layer is masked off in a pattern as shown in Figure 4 aad the unmasked portion is oxidized auld the nikide is removed. With the source aad drain regions defined, these areas rlre henvily doped through plloa~ ul~Jua imp~ant. A gate oxide .. . . .. . ~
~ ~t~r~
,~ . ., 2~8~561 layer is tllen laid ovcr Lhc sourcc and drain regions and a gate made of ITO or polysilicon is depo::ited oYer this gate oxide. The gate ma~erial is then implanted witl boron and the sour-e lincs are counter doped. Tlle transparent electrode ITO is then laid ovcr the oxidL so as to be located between the in~Prsl cti~n.~ of the gate and bus 5 lines and to be in eleL trical contact with the drain region. As seen again in Figure S, a layer of oxide is tllen .Icposited over the gate line as well as the pixel ITO. In order to define the pixel a spoccr post 32 is deposited over the gate line and source lines. A
nichrome block 34 i~ positioned between the spacer post and the comrnon electrode 36 which is also made Or ITO. This common electrode has been deposited previously 10 upon the upper glass substrate 30. As in all liquid crystal displays, liquid crystal fills the gap between tLle lower electrode 18 and the upper electrode 36.
As is knowll ill the art, the largest reduction in the aperture area of conventional AMLCD layouts is due to ill~L L~,olLL~e~ and contacts. Specifically, the source and gate bus lines dramatically reduced the pixel aperture. nhese buses must be made larger than the minimum photolithographical dimension due to the presence of source anddraul contacts at each pixel. ln the embodiment described above, contacts are eliminated in t_e array. This results in a s4~1~LL~ ILl~ly greater aperture ratio than is available with most couventional LLL~ LlL~
nhe ~mho~innent described above also has certain processing advantages. One 20 inparticulariseliminationofallmetalinthearray. Metal/lTO~ ;"~;",lisa major source of yield loss. Additionally, there is no longer any need for tLWo layers of metal in the fabricatioll process. This greatly simplifies the design and fabrication of AMLCD's.
The unique T~T confiLL llr~tinn disclosed above ~ s a mode of operation 25 for the active matrix ~vhich is different from what is known in the art. The operation will be described in terms of a single pixel receiving signals over a gate and a source bus lines. As is well known in liquid crystal technology, a charge across liquid crystal in a pixel controls whether tlle pixel is turned on or off. Under tlle biasing scheme for the TFTs of the rl I~I-CI~ of the invention described herein, the pi.~el is turncd on 30 by first setting the source data line voltage to -5 volts and the gate line voltage to +5 volts. With the transis~or turned on, current flows from the source to the drain and as the drain voltage gets Illore negative, the potential between the source and the drain ,. ....
~ 8 2189661 goes to zero. At a di~fen:lltial voltage of zero volts, tlle process stops. In order to discllarge or turn off tlle pixel, tlle soulce line voltage is set to +5 volts and the gate line voltage is set to +5 volts. With tlle transistor tumed on again the current flows from tlle drain to the sourcc vf the transistor. As the drain voltage gets more positive, tlle 5 difference between dlc source voltage and the gQte voltQge reduces to zero. When this occurs, the transistor turns off and the current no longer flows.
This type of olleration is different from the prior art since two different physical ",~ ~1, ..,;~",.~; are used Lo control the Qmount of charge moved to or from a pQrticular pixel. Both of these voltages are controlled, resulting in superior l~,.rv~llld.l~,~ of the 10 pixel. To inhibit modification of ~UIIVUIIdillg pixels during switching of a particular pixel the gate source bus or datQ lines of the ~U~IUUIId;llg pixels are set to tristate. The bias on the surroundin~ pixel transistûrs adjust to limit current flow to leakage current only, thus not affectin~ the status of the ~uul~ulldillg pixels. This type of transistor .e is superior because it better guarantees unifomm charge movement during 15 both phases of A~LCD operation, it is easier to m~n~lf~tllre since only two masking layers are required, a~ld the removal of contacts increases the transistor reliability.
The contactless array described above can be modified to provide gray scale in AMLCD's. Ahalftonei""li~,,l,,,l;,~,~forthefirst~mho~im~ntoftheactivematrixis shown in Figure 6a. In this ~nFiellr~ion half tones are L~ . .,."I,li~l,. d by breaking up a 20 large pixel into sma~lcr subpixels. In the emho~imrnt shown, the transparent electrode for a particular pixel is broken up into four electrodes, 48, 50, 56 and 58. Each electrode has a drain clectrode 48, 50, 52 and 4O Ic~r~Liv~,ly. As with tlle above described ronfiellr~ti~n source bus lines 44, intersect gate bus 42. The COnStrUCtiOrl of this matrix is sllhstr~llti~lly similar to that described above. However, in building this 25 ~r~nfi~llr:lrinn, the masking of the sinFle crystal silicon layer 44 is more intricate. As shown in Figure 7, four different electrodes 46, 4Si and 50 run off a single source line 44. The source and the drains are heavily doped to provide the proper ollvu~tiviLy.
Undoped regions of ~he silicon layer 62 are left between the drain electrodes and the source.
The relative locations of the drain electrodes, the source and gate bus lines are shown in Figure 6b wllich is Q cross section taken parallel to the gate line. The gate bus is laid over tlle source Qnd drain regions with a gate oxide layer in between. The view 9 218~661 in ~igure 6b can bc e.Y~cnded out to include drains 46 and 50. In tlle hal~tone configuration eacll sub l)ixel has its own transistor to control current flow to the subelectrode. Tlle co~ll;gu~ation of tlle drain contact and tlle subelectrode ITO is identical to tllat as des~ribed in the contactless al-lliLcl~ulc above.
The relative r rea of each ~llhelf~ctrodl~ determines its final switching voltage. In tlle present embodim~l1t the pixel voltage is controlled by the width to ~ength ratio of the ætive switchil1g c~ement. This ratio is kno~vn as the shape factor of the transistor.
By changing this lellg~tll to width ratio, the current which the transistor supplies is changed. In the presellt invention this is done so that the picture elements which o incorporate subelectrodes 56 and 60 turn on at a particular source voltage and the picture elements whi~ ll incorporate subelectrodes 54 and 58 turn on at a higher voltage.
The source and gate ~ oltages are varied in order to provide the desired half tone for a particular pixel. This sccond rl.,hO.l;".. ." is dd~ .uU:~ in that it allows for the uSe of half tones in an AMLCD while still achieving maximum pixel aperture ratio which is 5 a benefit of the contactless dl~lliLc~Lulc.
In a third ell.~o.lil,l~,lL of the invention, a sllared source contact ~clliLc.~ulc is disclosed for a large ilrca AMLCD's. ln some AMLCD ,~, ~llit~ ulca, it may be necessary to maYimizc the aperture ratio for each pixel while also reducing the source bus line resistance. A solution for this problem is to provide a series of evenly spaced ~o contacts along the source buses to provide current to the individual pixel transistors.
This . . ."1~, .. "1 ;,~l- offers significant advantages over the prior art which has electrical contacts at each pixel transistor.
The top view for the third c",~ ;",. ..1 of the active matrix ~cl~ ulc is shown in Figure 8a. I~1cluded in this matrix is source bus 70 assembly, which is25 intersected by gate bu~ 74. Proximate to the intr~rntin~n of the source and gate lines are pixel electrodes 76 wllich are in electrical contact with tlle drain electrode 78. The main difference between tllis clllI,o~ of the invention and the first clllb.)dilll~.lL
described above, are the electrical contacts ?2 which are evenly spaced along the source bus. As mentioned above, the contacts are placed at regular intervals along the sourcc 30 line in order to reduce tlle source line resistance. The number of gate lines between Source contacts is typically on the order of 32. The actual number depends on the , . , .~.: . .
~ 21896~1 cap~citive time collstant during c~larging of tlle source bus lines during the AMLCD
operat;on.
Figure 9 is a ~nr view of the single crystal silicon laycr 80 whicll tllrougll maslcing and doping !~ls been modified to include source bus assembly 70 as wel~ as 5 drain electrode 78. Also included are electrical contacts 72 which are evenly spaced along the source lille. As seen in Figure 8b, tllese electrical contacts 72 provide an electrical connection beLween an aluminum strip 75 of the source bus assembly 70which runs from ~he LCD driver (not shown) over the single crystal silicon layer 77.
An insulating layer is rrovided between the silicon layer and the aluminum strip. The Liu~ J between tllc aluminum strip 75 and the single crystal silicon layer 77 can be seen clearly in Figu~e 8c. nhe transistor ~clnfiel-r~inn for this embodiment is identical to that sllown in the first embodiment described above. Ille only difference between the third embodiment and the first rmhodim~nf is the inclusion of the contact 72 along the source lim:. n~e contacts 72 only encroach on the pixel aperture at a preset 15 interval while allowiny, the maximum aperture ratio for tlle rclnaining pi.Yels. This provides tlle maximum nperture ratio for a given rhntf~lithn~r~rllic resolution while m~inf:~inine superior dynamic ~ . r""" ~
In the fourth ,Ind final ?mho~im~-nt of the invention, the shared source contactCU~Il;~t~LUlCi describe~ in the third embodiment is combined with the half tone 20 rnnf i~urz~tinn described in the second embodiment. As shown in Figure l O, each electrode is broken clown into four subpixels 102, 104, l06 ;~nd 108. Each subelectrode is in contact with a ~l ain 96, 94, lO0 and 98, respectively. Along with source line 90 and gate line 92, the drain regions form a series of transistors for each ~ub~ Llod~ as waS described in the second embodiment. Included in this cnnfi~ur~tinn are shared zs contacts 93 which are evenly spaced between the gate lines, commonly in the order of 32. As was described ~bove, tnis shared source contact appro~ch reduces line resistance while minillli7inp ~he area devoted to contacts.
Figure l l is a top view of the single crystal silicon layer l lO which has beenmasked and doped to form the various drain regions as well as a source bus. As can be 30 seen, the electrieal contaets 93 are spaeed along the souree bus. As with tlle third ...,..riy,."..,.~ an aluminum strip runs from the driver over an insulating Irlyer whieh has been deposited on the souree bus and this contact allows lldll~ ;ull of the data ... . ..
21~9661 signâl from the driver to tlle individual subpixel transistors. This shared source hal~
tonc configuratioll acl~icYcs maximum pixcl aperture ratio rOr a ~iYc~l photolitllographic resolution while provi~ g superior large display ~.rulll.a..ce.
The foregoing i:; a description of a novel and nonobvious AlvILCD arcllitecturc.5 The applicant does not intend to liMit the invention to the foregoing description, but instead to define the in~ cntion through the claims appended hereto.
.... . , . , , _ , . _ . _ _ . _ _, _ _ _ _ _ . ., . _ .. . _
FOR ACTIVE MATRIX LIQUID CRYSTAL DISPLAYS
Fr~.l .r) OF T~ INY:F NTIQN
The present illYcntion pertains to actiYe matri.~ Iiquid crystal displays (AMLCD's), and molc particularly, to providing a larger aperture ratio in an AMLCD.
BACK('.ROUNI) QF T~F INYl~ TIQN
LCD tech~ology is being developed as a possible successor to cathode ray (CRT
technology for many applications. LCD technology offers important advantages, sucll as lligh reliability an l reduced power, size and weight. However, in the current state of lo development, LCD iull~ge rendering capabilities fall short of that achievable from the use of CRrs.
rhere is a greaL lleed for high resolution thin film transistor/liquid crystal displays in a wide rarge of possible applications ranging from portable computers and test equipment to higll resolution projection TV's. Such displays typically consist of a large number of pict~re elements (pixel) arramged in an active matri~c. For a display system where the elcctro-optica~ medium is liquid crystal, each pi:Yel is defined by a dedicated electrode ol~ one side of two opposite trarlsparent substrates and another electrode, which is common to all pixels and faces the viewer.
Figure I illustrates in circuit form a prior att TFT liquid crystal display device.
Each pi.cel in the active matrix is comprised of a TFT switch and a liquid crystal capacitor. The TFT gale electrodes for all the cells in a row are connected to a common horizontal gate bus, ~vhile tlle TFT sources in all the cells of each column are connected to a vertical data bus. The cells are addressed in a "line-at-a-time" or by line-by-line mode. By pulsing a ~ate bus to a positive potential relative to the source potential ~5 during the addressing interval for a particular row, the TFT's in that ro-v are switched on. At the same time, Llle data signal voltages on the source busses are transferred to the TFT output elecLrodes (drains) and the liquid crystal capacitors. ~'ihen the gate bus is s~vitched off as thc ne:<t row is addressed, the data signals are stored on tbe capacitors until the next addressing cycle for a particular row in tlle succeeding frame.
In the above described display system, the number of row and column conductors needed ~ b to the nurnber of rows n and columns m for n X m pixels. In addition to the need to devote a portion of area of the display device to _ _ _ . _ _ . _ __ -- = , . , ,, , , _ _._,, , ~ . = .
A~ENUEO SH~E~
accomrnodate the row i~lld column conductors there is also a possibility that, in view of the large number of collduclors used, olle or more of these conductors may be defective, rendering the display d.:vice unusable. This problem is quite common ae the crossovers of row and colunln coll iuctors. Obviously, the more conductors employed the greater 5 this possibi~ity becomes to adversely affect the yield of a large area display device.
Furthemlore, tilc large number of row and column conductors causes problems with the production of smrlil area display devices which are used for projectiondisplays. Large area displays can be obtained from small area TFT liquid crystaldisplays by using a projection system in which the image produced by the small area 10 display is projected oll~o a large area screen. However, in order to provide the desired display resolution aftcr projection, the dispiay device generating image should have an adequate number of row and columns of pixel density. If the number of the row and column conductors is large, a large portion of the display area is occupied by the conductors amd the aperture ratio (i.e., display area where light can ~ it/t~ Li area) 15 on the display is small. Then the display e~chibits low light levels.
Figure 2 illustrates cnnfi~llr~ti~ n of a typical prior art liquid crystal display array. Included in the array are gate bus lines 4 and source bus lines 6 which intersect in a grid-like pattern. Between the bus lines are picture elements ~vhich is usually liquid crystai held bctween two transparent electrodes 2. In one comer of the picture 20 elemerlt is the switching element, a thin fii~n transistor ~TFT) 5, which either adds or removes the voltage from the liquid crystal thus maicing the picture element either clear or opaque. The TFT is comprised of the gate electrode 8, tile drairl electrode ~ as well as the drain. In this ~onFi~llr~tinn~ the 11/1111. ~ for the TFT encroaches upon the nommaily rectangular picture element. Beciluse of the need of hard contacts between the 25 different bus lines, this large of a structure is necessary.
The largest reduction in aperture area for conventional AMLCD layouts is due to the need for the il.t ,l~,ul .~ and contacts. Specifically, the source databus and the gate databus dramaticrllly reduce the pixel aperture. These busses must be made larger than the minimum phvtolithographic~l dimcnsion duc to thc prescncc of sourcc alld 30 drain contacts at each pixel. Also, a major cause of failure of the prior art devices during their operatillg life is due to the contacts separating.
AMENDED SHEET
~ 3 2189661 A further disadvantage of tlle prior art metllods is the processing method used to construct the army: In order to provide properly conductive bus lines, metal must be used to end the array. Metal/indium tin oxide (}TO) ron~ lnnin~ n is n maior source of yield loss. Also, the desi~n of the prior Qrt is complicated by tlle need for multiple 5 layers of metal.
A prior art rcrerence of ci~nifir~nre is European Fatent application 103,523 which discloses a metllod of ~ ..ur~l~,Lu.~ of electronic circuits based on thin-film transistors and capQcitors. According to the method of the invention, conductive, photogravure, and insulating are layed down on a substrate in a particular order to 10 create a matrix of thin film transistors and capQCitors which has applications in liquid crystQI displays.
The present invention offers the advantages of providing a larger aperture ratioand greatly simplifying the design Qnd fabrication of active matrix liquid crystal displays.
SITMM~RY OF TT~li' IN~ENTION
The invention described herein is an active matrix which provides a large aperture ratio in a liq~lid crystal display. The liquid crystal display is comprised of a lower substrate with multiple parallel source lines disposed thereon. Also disposed on the lower substrate are drain means for a thin film transistor (TFT). An insulating layer 20 is disposed over botll the data line and the drain means. Multiple gate lines are disposed over the insulating layer so as to intersect the data lines and drain means. The int~rcer~inn of these ~llree elemenOE forms an array of TFTs, proximate to each of TFTs is a transparent electrode which is ill ul,u~ ;d into the picture elements for the liquid crystal display. The drain means of each TFT contacOE the transparent electrode to 25 provide individual switching of the picture elements within the LCD.
The large aperture ratio for tlle AMLCD is possible for a variety of reasons.
First, the source and 8ate lines for the switching elements in the array can be u~d using minimum photol,~ imPn~irJn~ Also, the gate and sourcc can be ,u~ u-L~d of transparent conductive material thus improving the light ~0 trnn~mic~ir~n Also, the removal of the metal contacts eliminates the ~ va~L~ t of the switching element into the picture element, thus increasing its aperture ratio. The reduction of contacts in tl1e array also improves display ~eliability. These _ _ _ _ , .. .. _ .. . . , _ , .. . .. . . .
AMEI`IûED SHEET
~ 4 218966 1 improvements enllallce tlle ~ of t~le high perrormancc ~ctive matrix liquid crystal displays BRII~,~ DF..S~RIPTIQN OF T~l~. nRAWllYGS
Figure I sl~ows a circuit diagram for a prior art AMLCD device.
Figu~e 2 is a pixel configuration for a prior art AMLCD device.
Figure 3a is a ~vp view of a contactless array, Figure 3b is a view of the contactless array alon~ the ~ate bus, Figure 3c is a view of the contactless array parallel to the gate bus, Figurc 3d is a view of the contactless array along the drain, and Figure 3e is a view of the gale bus along the source bus.
o Figure 4 is a Lop view of the source and drain regions in the single crystal silicon layer for the contacLless array.
Figure 5 is a cross sectional view of a pixel in the large aperture ration ~MLCD.
Figure 6a is a top view of the contactless array in the half tone confi~..r~ri~ n, and Figure 6b is a cross sectional view of the llalf tone version of the contætless array along the gate bus.
Figure 7 is a top view of the source and drain regions in the single crystal silicon layer for the halftone contactless array.
Figure 8a is a top view of the shared contact array, Figure 8b is a cross sectional view of a shared contact, and Figure 8c is a cross sectional view of the source bus.
Figure 9 is a top view of the source and drain regions in the single crystal silicon layer for the shared source array Figure 10 is a top view of the shared source array in a half tone configuration.Figure 11 is a top view of the source and drain regions in the single crystal silicon layer for the shared source halftone array.
DT~`SCRIPTION OF TTT~ PRF,T~'ERR~T~ EMT~ODTMlilNTS
Figure 3a discloses a partial top view for a contactless array ~ iL~ c for a large aperture ratio active matrix liquid crystal display (AMLCD). The array in the first ~;lllbodil~ of tlle invention is comprised of source buses 12 which run vertically and are in electrical contact with display drivers ~not shown~ that provide the image signals. The source buses 12 intersect gate buses 14 which run horizontally. The gate buses are also in elec~rical contact with the display drivers (not shown). ~n~Pr~r~''Pd between the intersectivns of the gate and source buses are the transparent electrodes 18 AME~ S S~ ~
~ 5 2189661 for each pixel in the liquid crystal display. Tlle pi,~el elcctrodes 18 are in electrical contact with drain re~ions 16. All the elements shown in Figure 3a are disposed on a common substrate. The in~ersection of tlle source bus, drain region, and gnte bus form a thin film transistor (TFT) which is the switching element for the pixels ill the display.
5 A better llnd~rctrln~ling of the construction of the TFT can be understood by study of Figures 4 and 3b-3e.
Figure 4 is a vicw of just the source bus nnd drains deposited on a clear glass substrate which serves as the base layer for tlle entire active matrix. The source buses 12 are defined in a buricd layer of single erystal silieon 10 that hns been heavily doped l o n+ to reduee line resis~anee. The region deflned by the drain 16 has also been heavily doped n+. The region bet-~een the source IZ and the drain 16 ~vhich is part of the silicon layer 10 is left undoped. The souree buses and drains may also be constructed of a strip of refractory metal silieide sueh as titanium, or Tungsten, laid on top of a layer of polysilieon. This eaul be done in the eases where a lower resistanee is required.
5 Further, the gate buses and drains may also be eonstrueted oftransferred silieon through a teehnology provided by the Kopin Corporation. Referring again to Figure 3a the gaîe buses are then Inid over the source buses and the transparent electrodes are interspaced between the int~rcectinn of the buses. The gate bus in the preferred embodiment is constructed from indiuull tin oxide (ITO) which is transparent and conductive. This 20 material has the propem,ulld~ ivi~y to carry the gate signal. Other possibilities for gate bus materials are polysilicon or a refractory metal silicide like titanium as Tungsten.
The gate and drain buses may also inelude a layer of refrnetory metal silicide such as titanium, whieh eould be laid on the top of the silieon. This can be done in the cases where a lower resistance is required.
From the eross seetion along the gate bus shown in Figure 3b, the ~:~ul:,lul,LiJof the TFT is apparent. After the silieon layer whieh defines the souree bus nnd the drain bus is laid, a layer of oxide is then deposited over these eo~ "J~ The gate bus is then deposited Oll the oxide layer so as to interseet the souree bus. The souree region 12 of the silieon layer 10 is proximale to the drain portion 16, and eurrent through the transistor is eontrolled by the signal traveling over the gate bus 14. The eross seetion shown in l~igure 3c whieh is a eut through the tr~nsparent eleetrode shows the proximity of the pi:cel eleetrode 18 to the souree bus 12.
r ~r~~
. ~ 6 ~189661 The cross section shown in Figurc 3~ is ~aken il1 a direction parnllel to the drain 16. Sl1o~va in pnrticul~r is Llle electrical contnct between the drain and tlle pixel elcctrode 18 ns well .as the pro:<imity of tlle dr~in to the gate bus. The nature of the connection betw~en t~lC drain and tl~e pi.~el electrode is clcnrly evidcnt. This contnct is made through well kno-~n Sf~n~ir~r~ r fabrication techaiques rather thna a metalcontact. The cross seclion showa in Figure 3e is along the source bus. Shown in particular is tlle relatiollship between the source bus nad tlle gate bus.
The elemcnts in Figure 3a combine to forra the active Mntrix for a liquid crystal display. Image signnls are transmitted along tlle gate and source buses so ns to0 selectively provide a cllnrge at the pixel electrodes. As will be described in more detail below, the absence or l~resence of a charge at the phcel electrode controls whether that pixel is eitller on or olf. As is well known in the art, the turaing on or off of that pixel is in response to the switchiag of a transistor which is proximate to the pixel. In prior art AMLCD's, thesc transistors require metal contacts between the source bus line and the traasistor as weLI as a metal contact between the drain of the transistor aad the drain electrode. These n~etal contacts are a weak link in the LCD becnuse it is well kaown in CMOS technology tlmt one of the first thing to fail in tllese transistors is tlle metal contacts. The matrix shown in Figure 3a has no metal contacts conaecting the bus liaes to the transistor aad the transistor to the drain electrode. Furtller, the use of traasistors ~o wita metal contacts requires that the transistor be located in a comer of the pixel aperture. The t~ ,lu~l.hl~ of the transistor into the aperture can be clearly seen in the prior art matrix shown in Figure 2. In the present invention, the ~olla~lu~Lioa of the traasistoris ul~,u.rul_~.linto theconstructionofthebuslines, thus ,~ ;"l;,~ the pixel aperture.
The incorporation of the matri.x shown in Figure 3a into a liquid crystal display picture element is shown in Figure 5. Figure 5 is a cross sectiorl all view of the active portion of a liquid cryatal display tl~rough the middle of a single pixel. Included in the active portion of khe display are the glass subskates 30 which enclose the elements described above. Laid over the lower substrate 30 is a layer of single crystnl silicon 10 This silicon layer is masked off in a pattern as shown in Figure 4 aad the unmasked portion is oxidized auld the nikide is removed. With the source aad drain regions defined, these areas rlre henvily doped through plloa~ ul~Jua imp~ant. A gate oxide .. . . .. . ~
~ ~t~r~
,~ . ., 2~8~561 layer is tllen laid ovcr Lhc sourcc and drain regions and a gate made of ITO or polysilicon is depo::ited oYer this gate oxide. The gate ma~erial is then implanted witl boron and the sour-e lincs are counter doped. Tlle transparent electrode ITO is then laid ovcr the oxidL so as to be located between the in~Prsl cti~n.~ of the gate and bus 5 lines and to be in eleL trical contact with the drain region. As seen again in Figure S, a layer of oxide is tllen .Icposited over the gate line as well as the pixel ITO. In order to define the pixel a spoccr post 32 is deposited over the gate line and source lines. A
nichrome block 34 i~ positioned between the spacer post and the comrnon electrode 36 which is also made Or ITO. This common electrode has been deposited previously 10 upon the upper glass substrate 30. As in all liquid crystal displays, liquid crystal fills the gap between tLle lower electrode 18 and the upper electrode 36.
As is knowll ill the art, the largest reduction in the aperture area of conventional AMLCD layouts is due to ill~L L~,olLL~e~ and contacts. Specifically, the source and gate bus lines dramatically reduced the pixel aperture. nhese buses must be made larger than the minimum photolithographical dimension due to the presence of source anddraul contacts at each pixel. ln the embodiment described above, contacts are eliminated in t_e array. This results in a s4~1~LL~ ILl~ly greater aperture ratio than is available with most couventional LLL~ LlL~
nhe ~mho~innent described above also has certain processing advantages. One 20 inparticulariseliminationofallmetalinthearray. Metal/lTO~ ;"~;",lisa major source of yield loss. Additionally, there is no longer any need for tLWo layers of metal in the fabricatioll process. This greatly simplifies the design and fabrication of AMLCD's.
The unique T~T confiLL llr~tinn disclosed above ~ s a mode of operation 25 for the active matrix ~vhich is different from what is known in the art. The operation will be described in terms of a single pixel receiving signals over a gate and a source bus lines. As is well known in liquid crystal technology, a charge across liquid crystal in a pixel controls whether tlle pixel is turned on or off. Under tlle biasing scheme for the TFTs of the rl I~I-CI~ of the invention described herein, the pi.~el is turncd on 30 by first setting the source data line voltage to -5 volts and the gate line voltage to +5 volts. With the transis~or turned on, current flows from the source to the drain and as the drain voltage gets Illore negative, the potential between the source and the drain ,. ....
~ 8 2189661 goes to zero. At a di~fen:lltial voltage of zero volts, tlle process stops. In order to discllarge or turn off tlle pixel, tlle soulce line voltage is set to +5 volts and the gate line voltage is set to +5 volts. With tlle transistor tumed on again the current flows from tlle drain to the sourcc vf the transistor. As the drain voltage gets more positive, tlle 5 difference between dlc source voltage and the gQte voltQge reduces to zero. When this occurs, the transistor turns off and the current no longer flows.
This type of olleration is different from the prior art since two different physical ",~ ~1, ..,;~",.~; are used Lo control the Qmount of charge moved to or from a pQrticular pixel. Both of these voltages are controlled, resulting in superior l~,.rv~llld.l~,~ of the 10 pixel. To inhibit modification of ~UIIVUIIdillg pixels during switching of a particular pixel the gate source bus or datQ lines of the ~U~IUUIId;llg pixels are set to tristate. The bias on the surroundin~ pixel transistûrs adjust to limit current flow to leakage current only, thus not affectin~ the status of the ~uul~ulldillg pixels. This type of transistor .e is superior because it better guarantees unifomm charge movement during 15 both phases of A~LCD operation, it is easier to m~n~lf~tllre since only two masking layers are required, a~ld the removal of contacts increases the transistor reliability.
The contactless array described above can be modified to provide gray scale in AMLCD's. Ahalftonei""li~,,l,,,l;,~,~forthefirst~mho~im~ntoftheactivematrixis shown in Figure 6a. In this ~nFiellr~ion half tones are L~ . .,."I,li~l,. d by breaking up a 20 large pixel into sma~lcr subpixels. In the emho~imrnt shown, the transparent electrode for a particular pixel is broken up into four electrodes, 48, 50, 56 and 58. Each electrode has a drain clectrode 48, 50, 52 and 4O Ic~r~Liv~,ly. As with tlle above described ronfiellr~ti~n source bus lines 44, intersect gate bus 42. The COnStrUCtiOrl of this matrix is sllhstr~llti~lly similar to that described above. However, in building this 25 ~r~nfi~llr:lrinn, the masking of the sinFle crystal silicon layer 44 is more intricate. As shown in Figure 7, four different electrodes 46, 4Si and 50 run off a single source line 44. The source and the drains are heavily doped to provide the proper ollvu~tiviLy.
Undoped regions of ~he silicon layer 62 are left between the drain electrodes and the source.
The relative locations of the drain electrodes, the source and gate bus lines are shown in Figure 6b wllich is Q cross section taken parallel to the gate line. The gate bus is laid over tlle source Qnd drain regions with a gate oxide layer in between. The view 9 218~661 in ~igure 6b can bc e.Y~cnded out to include drains 46 and 50. In tlle hal~tone configuration eacll sub l)ixel has its own transistor to control current flow to the subelectrode. Tlle co~ll;gu~ation of tlle drain contact and tlle subelectrode ITO is identical to tllat as des~ribed in the contactless al-lliLcl~ulc above.
The relative r rea of each ~llhelf~ctrodl~ determines its final switching voltage. In tlle present embodim~l1t the pixel voltage is controlled by the width to ~ength ratio of the ætive switchil1g c~ement. This ratio is kno~vn as the shape factor of the transistor.
By changing this lellg~tll to width ratio, the current which the transistor supplies is changed. In the presellt invention this is done so that the picture elements which o incorporate subelectrodes 56 and 60 turn on at a particular source voltage and the picture elements whi~ ll incorporate subelectrodes 54 and 58 turn on at a higher voltage.
The source and gate ~ oltages are varied in order to provide the desired half tone for a particular pixel. This sccond rl.,hO.l;".. ." is dd~ .uU:~ in that it allows for the uSe of half tones in an AMLCD while still achieving maximum pixel aperture ratio which is 5 a benefit of the contactless dl~lliLc~Lulc.
In a third ell.~o.lil,l~,lL of the invention, a sllared source contact ~clliLc.~ulc is disclosed for a large ilrca AMLCD's. ln some AMLCD ,~, ~llit~ ulca, it may be necessary to maYimizc the aperture ratio for each pixel while also reducing the source bus line resistance. A solution for this problem is to provide a series of evenly spaced ~o contacts along the source buses to provide current to the individual pixel transistors.
This . . ."1~, .. "1 ;,~l- offers significant advantages over the prior art which has electrical contacts at each pixel transistor.
The top view for the third c",~ ;",. ..1 of the active matrix ~cl~ ulc is shown in Figure 8a. I~1cluded in this matrix is source bus 70 assembly, which is25 intersected by gate bu~ 74. Proximate to the intr~rntin~n of the source and gate lines are pixel electrodes 76 wllich are in electrical contact with tlle drain electrode 78. The main difference between tllis clllI,o~ of the invention and the first clllb.)dilll~.lL
described above, are the electrical contacts ?2 which are evenly spaced along the source bus. As mentioned above, the contacts are placed at regular intervals along the sourcc 30 line in order to reduce tlle source line resistance. The number of gate lines between Source contacts is typically on the order of 32. The actual number depends on the , . , .~.: . .
~ 21896~1 cap~citive time collstant during c~larging of tlle source bus lines during the AMLCD
operat;on.
Figure 9 is a ~nr view of the single crystal silicon laycr 80 whicll tllrougll maslcing and doping !~ls been modified to include source bus assembly 70 as wel~ as 5 drain electrode 78. Also included are electrical contacts 72 which are evenly spaced along the source lille. As seen in Figure 8b, tllese electrical contacts 72 provide an electrical connection beLween an aluminum strip 75 of the source bus assembly 70which runs from ~he LCD driver (not shown) over the single crystal silicon layer 77.
An insulating layer is rrovided between the silicon layer and the aluminum strip. The Liu~ J between tllc aluminum strip 75 and the single crystal silicon layer 77 can be seen clearly in Figu~e 8c. nhe transistor ~clnfiel-r~inn for this embodiment is identical to that sllown in the first embodiment described above. Ille only difference between the third embodiment and the first rmhodim~nf is the inclusion of the contact 72 along the source lim:. n~e contacts 72 only encroach on the pixel aperture at a preset 15 interval while allowiny, the maximum aperture ratio for tlle rclnaining pi.Yels. This provides tlle maximum nperture ratio for a given rhntf~lithn~r~rllic resolution while m~inf:~inine superior dynamic ~ . r""" ~
In the fourth ,Ind final ?mho~im~-nt of the invention, the shared source contactCU~Il;~t~LUlCi describe~ in the third embodiment is combined with the half tone 20 rnnf i~urz~tinn described in the second embodiment. As shown in Figure l O, each electrode is broken clown into four subpixels 102, 104, l06 ;~nd 108. Each subelectrode is in contact with a ~l ain 96, 94, lO0 and 98, respectively. Along with source line 90 and gate line 92, the drain regions form a series of transistors for each ~ub~ Llod~ as waS described in the second embodiment. Included in this cnnfi~ur~tinn are shared zs contacts 93 which are evenly spaced between the gate lines, commonly in the order of 32. As was described ~bove, tnis shared source contact appro~ch reduces line resistance while minillli7inp ~he area devoted to contacts.
Figure l l is a top view of the single crystal silicon layer l lO which has beenmasked and doped to form the various drain regions as well as a source bus. As can be 30 seen, the electrieal contaets 93 are spaeed along the souree bus. As with tlle third ...,..riy,."..,.~ an aluminum strip runs from the driver over an insulating Irlyer whieh has been deposited on the souree bus and this contact allows lldll~ ;ull of the data ... . ..
21~9661 signâl from the driver to tlle individual subpixel transistors. This shared source hal~
tonc configuratioll acl~icYcs maximum pixcl aperture ratio rOr a ~iYc~l photolitllographic resolution while provi~ g superior large display ~.rulll.a..ce.
The foregoing i:; a description of a novel and nonobvious AlvILCD arcllitecturc.5 The applicant does not intend to liMit the invention to the foregoing description, but instead to define the in~ cntion through the claims appended hereto.
.... . , . , , _ , . _ . _ _ . _ _, _ _ _ _ _ . ., . _ .. . _
Claims (13)
1. An active matrix for a liquid crystal display comprising:
a substrate;
a plurality of parallel source lines (12) disposed on said substrate;
a plurality of drain means (16) disposed proximate to said source lines (12);
a transparent insulating layer (20) disposed over said source lines (12) and drain means (16);
a plurality of parallel gate lines (14) disposed over the insulating layer (20) so as to intersect said source lines (12) and said drain means (16) to form a plurality of contactless thin film transistors (TFT's); and a plurality of transparent electrodes (18) disposed over the insulating layer (20), each of the transparent electrodes (18) in electrical contact with one of the plurality of drain means (16).
a substrate;
a plurality of parallel source lines (12) disposed on said substrate;
a plurality of drain means (16) disposed proximate to said source lines (12);
a transparent insulating layer (20) disposed over said source lines (12) and drain means (16);
a plurality of parallel gate lines (14) disposed over the insulating layer (20) so as to intersect said source lines (12) and said drain means (16) to form a plurality of contactless thin film transistors (TFT's); and a plurality of transparent electrodes (18) disposed over the insulating layer (20), each of the transparent electrodes (18) in electrical contact with one of the plurality of drain means (16).
2. The active matrix for a liquid crystal display of Claim 1 wherein each of the drain means (16) is located proximate to an intersection of the gate line and the source line.
3. The active matrix for a liquid crystal display of Claim 1 wherein four of the drain means (16) are located proximate to an intersection of the gate lines (14) and the source lines (12) so as create four of the TFTs, each of the drain means (16) is in electrical contact with one of the plurality of transparent electrodes (18) so as to provide a half tone configuration for the liquid crystal display.
4. The active matrix for a liquid crystal display of Claim 3 wherein a cascading effect is achieved by adjusting width to length ratios of the TFT's.
5. The active matrix for a liquid crystal display of Claim 1 wherein each of the source lines (12) runs parallel to a conductor line, electrical contacts are provided between the conductor lines and the plurality of source lines (12) at predetermined intervals.
6. The active matrix for a liquid crystal display of Claim 5 wherein four of the drain means (16) are located proximate to an intersection of the gate lines (14) and the source lines (12) so as create four of the TFTs, each of the drain means (16) is in electrical contact with one of the plurality of transparent electrodes (18) so as to provide a half tone configuration for the liquid crystal display.
7. The active matrix for a liquid crystal display of Claim 6 wherein a cascading effect for switching the TFT's is achieved by adjusting width to length ratios of the drains.
8. The active matrix for a liquid crystal display of Claim 1 wherein the plurality source lines (12) and drain means (16) are formed from a layer of single crystal silicon which has been etched and selectively doped.
9. The active matrix for a liquid crystal display of Claim 1 wherein the plurality of source lines (12) and drain means (16) are formed from a strip of refractory metal silicide disposed over a layer of poly silicon.
10. The active matrix for a liquid crystal display of Claim 1 wherein the plurality source lines (12) and drain means (16) are formed from transferred silicon.
11. The active matrix for a liquid crystal display of Claim 1 wherein the plurality gate lines (14) are comprised of indium tin oxide (ITO).
12. The active matrix for a liquid crystal display of Claim 1 wherein the plurality gate lines (14) are comprised of polysilicon.
13. The active matrix for a liquid crystal display of Claim 1 wherein the plurality gate lines (14) are comprised of a refractory metal silicide.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/249,408 US5546204A (en) | 1994-05-26 | 1994-05-26 | TFT matrix liquid crystal device having data source lines and drain means of etched and doped single crystal silicon |
| US08/249,408 | 1994-05-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2189661A1 true CA2189661A1 (en) | 1995-12-07 |
Family
ID=22943357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002189661A Abandoned CA2189661A1 (en) | 1994-05-26 | 1995-05-26 | Large aperture ratio array architecture for active matrix liquid crystal displays |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5546204A (en) |
| EP (1) | EP0760966B1 (en) |
| JP (1) | JP3869463B2 (en) |
| CA (1) | CA2189661A1 (en) |
| DE (1) | DE69510793T2 (en) |
| WO (1) | WO1995033225A1 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07199150A (en) * | 1993-12-28 | 1995-08-04 | Canon Inc | Liquid crystal display device |
| FR2721428B1 (en) * | 1994-06-17 | 1996-09-13 | France Telecom | Active matrix display screen with multiplexed control. |
| US5677745A (en) * | 1994-12-21 | 1997-10-14 | Kabushiki Kaisha Toshiba | LCD with electrostatic discharge projections |
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| JP3747336B2 (en) * | 1996-05-08 | 2006-02-22 | 株式会社半導体エネルギー研究所 | Method for manufacturing liquid crystal display device and liquid crystal panel |
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| JPS5910988A (en) * | 1982-07-12 | 1984-01-20 | ホシデン株式会社 | Color liquid crystal display |
| FR2533072B1 (en) * | 1982-09-14 | 1986-07-18 | Coissard Pierre | METHOD FOR MANUFACTURING ELECTRONIC CIRCUITS BASED ON THIN FILM TRANSISTORS AND CAPACITORS |
| FR2593632B1 (en) * | 1986-01-27 | 1988-03-18 | Maurice Francois | ACTIVE MATRIX DISPLAY SCREEN AND METHODS OF MAKING SAME |
| JPH0823640B2 (en) * | 1986-09-12 | 1996-03-06 | セイコーエプソン株式会社 | Liquid crystal display |
| WO1989004505A1 (en) * | 1987-11-13 | 1989-05-18 | Honeywell Inc. | Apparatus and method for providing a gray scale in liquid crystal flat panel displays |
| US5245452A (en) * | 1988-06-24 | 1993-09-14 | Matsushita Electronics Corporation | Active matric drive liquid crystal display device using polycrystalline silicon pixel electrodes |
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| JP3350045B2 (en) * | 1990-10-11 | 2002-11-25 | 株式会社日立製作所 | Semiconductor storage device |
| US5237436A (en) * | 1990-12-14 | 1993-08-17 | North American Philips Corporation | Active matrix electro-optic display device with light shielding layer and projection and color employing same |
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| US5319480A (en) * | 1993-03-19 | 1994-06-07 | Honeywell Inc. | Liquid crystal half-tone display with gray level uniformity |
-
1994
- 1994-05-26 US US08/249,408 patent/US5546204A/en not_active Expired - Lifetime
-
1995
- 1995-05-26 DE DE69510793T patent/DE69510793T2/en not_active Expired - Lifetime
- 1995-05-26 CA CA002189661A patent/CA2189661A1/en not_active Abandoned
- 1995-05-26 JP JP50109496A patent/JP3869463B2/en not_active Expired - Fee Related
- 1995-05-26 EP EP95921462A patent/EP0760966B1/en not_active Expired - Lifetime
- 1995-05-26 WO PCT/US1995/006746 patent/WO1995033225A1/en active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10501347A (en) | 1998-02-03 |
| EP0760966A1 (en) | 1997-03-12 |
| EP0760966B1 (en) | 1999-07-14 |
| US5546204A (en) | 1996-08-13 |
| JP3869463B2 (en) | 2007-01-17 |
| DE69510793T2 (en) | 1999-12-23 |
| WO1995033225A1 (en) | 1995-12-07 |
| DE69510793D1 (en) | 1999-08-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued |