CA2188882A1 - Atm architecture and switching element - Google Patents

Abstract

An ATM switching system architecture of a switch fabric type (20) is built of a plurality of ATM switch element circuits (40) and routing table circuits (30) for each physical connection to/from the switch fabric (20). A shared pool of memory (100) is employed to eliminate the need to provide memory at every crosspoint. Each routing table (30) maintains a marked interrupt linked list for storing information about which ones of its virtual channels are experiencing congestion. This linked list is available to a processor in an external workstation to alert the processor when a congestion condition exists in one of the virtual channels.
The switch element circuit (40) typically has up to eight 4-bit-wide nibble inputs (10-17) and eight 4-bit-wide nibble outputs (O0-07) and is capable of connecting cells received at any of its inputs (10-17) to any of its outputs (00-07), based on the information in a routing tag uniquely associated with each cell.

Description

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ATM ARCHITECTURE AND ~W~ ~l~G ELEMENT
BACKGROUND OF THE INVENTION
This invention relates to a class of digital communication systems known as a,,y..~llLu..ous transfer mode 10 (ATM) switching systems and generally to int~L _I er i cations architectures. r~Ore particularly, this invention relates to switch f abric-type architecture of an ATM
switching element. The invention is not to be confused with a bus-type architecture of an ATM switching element. This 15 invention is useful in tel~c, ; cations systems which require real-time routing and switching of digitized cells of data . A particular application is in the f ield of ISDN data switching at telephone central of f ices .
There is a need for high-speed switching and 20 throughput in a tolPr ications switch for digital -( ; cation applications wherein the primary usage is switching data between an external source or input I eS~ UL ~,e and an external output or destination resource. Two types of architectures are known: bus architectures and switch-fabric 25 architectures. Bus architectures provide multiple-point-to-muitiple-point connectlons. Switch fabric architectures provide single-point-to-single-point connections.
A b~lilfl;ng block in a switch-fabric architecture ATM
switch system is a structure known as a switch element. A
30 switch element provides packet signal routing from one of a plurality of input ports to one or more of a plurality of output ports by maintaining an array of crosspoints for connecting any input port to any output port. Switch elements may be aggregated in various patterns to provide an 35 arbitrarily large N by N possible interconnections of input ports to output ports, each via a unique path.
Problems arise where the receiving port cannot ac,:;m; late information as fast as it is delivered or where the W095130294 2 1 8 8 ~ 8 ~ 2 priority of the traffic varies. ~ "brute-force" t~hn;qll~ for hF~nr~l ;nq the gueuing problèm is to provide 6ufficient data storage at each possible crosspoint in the switch element wherein if the amount of data ~ ^llr~ ted at the crosspoint 5 exceeds capacity of the data storage, data is discarded, thus forcing the destination port to request that data be resent.
Such a solution is of f ered in the ATM self -routing switeh element Model ~B86680, an integrated circuit available from Fujitsu Microelectronics, Inc. of San Jose, California. A
lo representation of this prior art switch element 1 is shown in Fig. 1. Tlle element has a number of input t^r~in~l~ I1 to In ~3, 5, 7) connected via crosspoints 31-39 to a number of output terminals 01 to On (9, 11, 13) through buffer memories 2, 4, 6, 8, lo, 12, 14, 16, and 18. The 601ution employed by 15 prior art switch element 1 is very wasteful of cros6point memory because each memory element i5 connected to just one crosspoint. Memory element 6, for example, can only store and buffer data traveling from input In to output 01. DPr-^n~in^j on packet traffie through the switch element 1, memory at many 20 of the crosspoints in the switch element 1 will not be needed, ~hile at high traffic crosspoints more memory will be reguired than is provided in the switch element 1, and data packets will therefore have to be discarded. Discarding data packets is extremely wasteful of network resources because of the time 25 ~nd processing involved in the destination element reguesting that the data packet be resent, and the subsequent retran6mission of the data paekets by the 60uree element.
What i6 needed i6 an arehiteeture and switching element that optimally uses available memory for gueuiny and 30 buffering data packets zt high-traffic crosspoints without slowing switching operations.
SI~RY OF THE INVENTION
According to the invention, an ATM switching system 35 arehiteeture of a switch fabric-type compri6e6 two different type6 of ^nt6, namely, a plurality of ATM switch element circuit means which make up the switch fabric, and a routing W0 9~30294 2 1 8 8 ~ ~ 2 P~
table circuit mean6 for each phycical connection from the switch fabric to a workstation. In a specific ~mho~ L of the invention, these two components are contained in two separate integrated circuit packages and there is a shared pool of memory.
The routing table circuit means of the present invention is by way of example a self-contained circuit that is operative to receive standard 53-byte ATM packets or cells from a source on up to 2048 "Virtual rhAnn~ " defined by a header of an ATM packet. A standard ATM cell has 48 bytes of data and a 5-byte header which defines the source, destination, and priority of the cell. The routing table circuit means is operative to implement a routing table that uses the address f ield in the header of the ATM packet to look up the intended address in its RAM. The routing table then adds a six-byte routing tag to the cell and causes the resultant cell to be output to the switch fabric. The routing tag det~rm;nF~s the exact path the cell is to take through the switch fabric and also specifies other characteristics about the cell, such as its priority and its type, i.e., whether or not it is a multicast cell being transmitted to more than one output. The routing table is also used to control a queuing function in which queued cells are stored in an ~ -nying SR~ before being placed on the switch fabric.
According to the invention, there is one routing table for each physical connection into the switch fabric.
The routing table maintains a marked interrupt linked list for storing information about which ones of its virtual rhAnnPl ~
are experiencing congestion. This linked list is available to 3 0 a processor in the external workstation to alert the processor when a congestion condition exists in one of the virtual ~h~nnc~
A specif ic switch element circuit according to the present invention is a circuit that has eight 4-bit-wide nibble inputs and eight 4-bit-wide nibble outputs and is capable of connecting cells received at any of its inputs to any of its outputs, based on the information in a routing tag uniquely associated with each cell. A switch fabric-based W095l30294 ~18~82 r "~ 1~
"~ 1,, ~ , architecture built according to the pre~ent invention includes a plurality of 6witch element circuit means interconnected together in any number of known network wiring conf igurations such as the Clos Network, Delta Network, or Reversed Delta 5 Network.
A switch element circuit means of the present invention inc~ c a shared cell buffer pool. The shared cell buffer pool is a memory shared by all of the inputs to the switch element and connected to all of the outputs. The 10 shared cell buffer pool memory provides a similar function to the crosspoint memories of prior art circuits but i5 far more efficient and flexible because of its unique design. The switch element further includes an input controller connected to input crosspoints, an output controller connected to output 15 crosspoints, and a multi-priority buffer pool controller (MPBPC). All cells passing through the switch element are written into the cell buffer pool during a first cell cycle, which is equivalent to 118 clock cycles. Cells may be sent to a switch element output during the next cell cycle, or if the 20 destination output of the cell is not available, the cell may remain in the buffer pool for several cell cycles before being conne ::ted to the switch element output. The lqPBPC reads tags from the input controller and directs the storage of cells in the cell buffer pool. The MPBPC also, through the output 25 controller, directs when cells are read out of the cell buffer pool and sent to the output lines through the output I/0 crosspoints. The MPBPC includes circuitry for generating and r~cpon~lin~ to back-pressure signals generated when a receiving channel cannot receive data at a rate fast enough to keep up 30 with the transmitter. The back-pressure signals first notify the routing table, and then the workstation to which it is attached, to halt data transmission to allow the receiver an opportunity to catch up with the transmitted data stream. The back-pressure signal handling circuitry allows the switch 35 element of the present invention to be employed in "closed-loop" ATM systems that can r~ ;m; 7e data thLvuyll~uL through the switch without losing cells.

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The switch element also has a single bit per set of four inputs and per set of four outputs, known as an aggregate bit that, when set, directs the switch element to treat the f our inputs as one input f or the purposes of routing and FIFO
5 queuing. The NPBPC of the switch element also ~U,U~UUL~
proportional bandwidth queuing, which ensures that Yirtual rhAllllPl F that are assigned to different bandwidths receive a fair share of the available bandwidth in proportion to other ~-hAllnPl F .
In accordance with one aspect of the invention, the switch elements and routing tables support multicast trAnFmi Fsion. During multicast transmission, data from one source is distributed to several destinations , i . e., the multicast group, which comprise some, but not nPcP~s~rily all, of the possible switch fabric outputs. An example of such an application is a video conference over a network in which several workstations are connected by a switch fabric, and voice and image data are transmitted from each workstation to each of the other workstations.
In accordance with one aspect of the invention, each switching element conserves available cell memories and thereby avoids dropping cells by issuing back-yL-as UL-:
cn~ n~l~ to inputs on a per-input, per-priority basis to halt the flow of cells having a given priority from a given input.
Back-pressure is asserted for a given input and given priority whenever the number of currently enqueued cells of the given priority supplied by the given input exceeds a predetermined threshold. Back-pressure for a given priority is asserted for all inputs whenever the number of available cell memories falls below a threshold associated with that priority.
The invention will be better understood upon reference to the following detailed description taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram of a prior art ATM switch element of an ATM switch fabric 2rchitecture.

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Fig. 2 is a block diagram of ~n ArM ~witch ~abric architecture implemented in accordance to the invention.
Fig. ~ is a block diagram illustrating an example of a portion of a switch fabric architecture with ATM routing table 5 circuits and switch element circuits configured according to the invention in an ATM switch f abric architecture .
Fig. 4 is a block diagram of an ATM switch element circuit with external SRAM according to the invention.
Fig. 5 is a block diagram of an ATM switch element 10 circuit with a cell buffer pool according to the invention.
Fig. 6 is a block diagram showing an address multiplexer coupled to a linked list controlling a buffer pointer according to the invention.
Fig. 7 is a block diagram of a back-pressure 15 controller according to the invention.
Fig. 8A and Fig. 8B are block diagrams of conf igurations f or switch elements circuits with back-pressure control .
Fig. 9 is a block diagram of an aggregate bit 20 controller.
Fig. 10 is a table illustrating service order for one service order period.
Fig. 11 is a block diagram showing the source cell duplication multicasting of the prior art.
Fig. 12 is a block diagram showing mid-cell duplication multicasting according to the prior art.
Fig. 13 is a block diagram showing mid-switch duplication multicasting according to the prior art.
Fig. 14 is a block diagram showing tree-based duplication multicasting according to the prior art.
Fig. 15 is a block diagram showing tree-based duplication multicasting according to a specif ic c '~ L of the present invention.
Fig. 16 is a tabular illustration of per-priority 35 queuing with per VPC cell counts in a routing table according to the invention.
Fig. 17 is a tabular illustration of a per VC count of queued cells according to the invention.
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WO 9~130294 ~ ~ 8 ~ ~ 8 2 A ~, 1 /1.) ~.. _ _ 1 '1 DESCRIPTION OF S~ECIFIC EMBODIMENTS
SWITCH FABRIC
Fig. 2 is a block diagram of an ATM switch fabric architecture 2 0 according to the invention . Shown in the 5 figure is a 4 x 5 array of switch element circuit blocks (SE) 40. Each switch element 40 accepts eight 4-bit-wide input lines and has eight 4-bit-wide output lines. The switch fabric 20 thus has a total of thirty-two 4-bit-wide input lines shown at the left side of the switch fabric 20. In an 10 operating switch, each of these thirty-two four-bit-wide input lines is connected from a separate routing table circuit, and each such routing table circuit is connected to a workstation or other digital device. The switch fabric has thirty-two four-bit-wide output lines shown at the right side of the 15 figure. Each of the output lines is connected to individual further routing table circuits, each of which is connected to a workstation. Thus the switch fabric shown in Fig. 2 may provide a physical connection to up to thirty-two workstations and may connect data from any one of those thirty-two 20 workstations to any other one of those or other thirty-two workstations .
It will be seen that the interconnections among the switch elements 4 0 are such that data entering any one of the switch fabric input lines may be routed to any one of the 25 switch fabric output lines after passing through a total of four stages of switch elements. The switch fabric architecture 20 as shown in Fig. 2 is known as a Reversed Delta Network architecture. The switch element circuits of the present invention may be used in any number of other known 3 o network wiring conf igurations such as the Clos network or the Delta network, and the switch array may be ~Yr~n~d to provide any number of input lines and any number of output lines.
(Not shown in Fig. 2 is a configuration bus connected to each one of the switch elements . The conf iguration bus is used by 35 a configuration processor of the switch system to set up a number of switch parameters in a memory in the switch element. ) W0 95/30294 2 1 8 8 ~ 8 2 ~ s.0 1~13 ~8 Fig. 3 show~ a pcrtion of a ~witch fabric made up of four switch elements 40. One of the switch element6 is shown with interconnections through eight routing tables 30, to a number of workstations 50, and to a server ~UII~pULtlL 52. As 5 shown in the figure, in a typical application for the present invention, each input to a switch fabric is connected to a routing table circuit 30. A routing table circuit 30 i5 typically connected to some type of digital workstation 50, which may transmit and receive voice, vldeo, and digital dat~
10 via the switch fabric.
Also shown in Fig. 3 is an agyleyt.te input connection to a switch element in accordance with one specific ~m- oflir -~t of the invention. In an aggregate connection, four of the input lines of the switch fabric are grouped together and act 15 as one input to receive and transmit data to a high-speed data device such as server computer 52 . With the ayy, ~yate input feature according to the invention, the same switch element and switch fabric can handle two speeds of packet data, the ~irst speed being the speed of one input line and the second 2 o speed being f our times f aster or the speed of the aggregated input lines.
Rou~TNG T~PiT,T.:
Fig. 4 is a block diagram of a routing table circuit 25 42 according to the present invention. The routing table circuit 42 is a combination storage and control device that is used with e~ternal memory, e.g., S~AM 90, and includes a receive queue controller 80 which sends data to the switch fabric and receives a back-pressure signal from the switch 30 fabric, and a transmission buffer controller 82 which receives data from the switch fabric after that data has been processed by the multicast header translation circuit 84 and asserts back pressure to the switch fabric. The tr~nPmi ~Rion buffer controller 82 also includes a small buffer memory 86 for 35 storing cells received from the switch fabric. A further controller, called a connection table controller 88, is for reading header information from the workstation interface and i5 operative to use that header information to add an ~ W0 9~/30Z94 2 ~ ~ 8 ~ ~ 2 . ~ 13 ~JUL U,UL iate switch tag to the cells bef ore they are transmitted to the switch fabric. Controller 88 stores information about switch tags and buffers data in external SR~M 90 . Further included are an interrupt ~ acessol 92 and 5 processor interface 94, which are for sending control signals to the workstation. Optionally included is an OAM\BECN cell transmit circuit 96 for inserting control cells to the outgoing data stream.
The routing table circuit 42 in each instance operates 10 by receiving one 8-bit-wide segment of data via connection from a workstation as input and provides one 8-bit-wide workstation output. The routing table includes one 4-bit output to the switch fabric and receives one 4-bit input from the switch f abric .
SWITCH FT~FM~NT
Fig. 5 is a block diagram of the structure of switch element circuit 40 according to the present invention. The switch element circuit 40 includes a very small cell buffer 20 pool memory 100 for storing and queuing cells being transmitted through the switch element, input I/O crosspoint block 110 for connecting any input line to any cell memory in the cell buffer pool, output I/O crosspoint block 120 for Cnnnp~t; n~ any output line to any cell memory in the cell 25 buffer pool, input bus controller 130 for controlling data f low on the input bus to the cell memories, output bus controller 140 for controlling data flow from the cell memories to the output lines, and multipriority buffer pool controller (MPBPC) 150 for controlling assignment of cell 3 0 memories to connections def ined by the cross-point blocks .
The switch element circuit 40 is connected to a configuration bus 41 which supplies configuration data to controller 150.

Wo9sl30294 ~ 1 8 ~ 8 ~ 2 The F:witch eleme~nt 4 0 has eight input interf aces, labeled I0 through I7, and eight output interfaces, labeled oo through 07. Each ~of the eight inputs and eight outputs i5 a four-bit or nibble-wide interface capable of operating at for example up to 50 Mhz, i.e., sufficient to E;upport digital communications at the current AT~ OC-3 standard. Each of the inputs receives cells from another switch element in the switch fabric or from a routing table, as previously outlined.
ATM cells of data are transf erred as one hundred and eighteen four-bit nibbles. This allows the standard fifty-three AT~
byte cells to be transferred along with six overhead bytes. A
cell start signal goes high every one hundred and eighteen clock cycles to indicate the start of a cell.
Cell buffer pool 100 is a pool of random access memory. The pool contains thirty-two individual cell memories, each capable of storing an entire cell of one hundred and eighteen nibbles. The thirty-two memories can be connected to any one of the eight inputs by input crosspoint block 110 which is controlled by input bus controller 130.
crosspoint block 110 contains a plurality of multiplexers 112 f or connecting input buses to any of the cell memories .
Multiplexers 112 are controlled by signals from the input bus controller 13 0 that are transmitted on six-bit wide connection control bus lines 132.
Any of the cell memories may be cnnn~-ted to any of the output lines via output crosspoint block 120. Output crosspoint block 120 is controlled by the output bus controller 140 via output connection control bus lines 142.

~ WO 9~/30294 ~ 1 8 ~ ~ 8 2 r~ 13 MPsPc 150 contains a link list RAM 152 for storing queue assignment information about the cell buffer pool memories, a service order table 154 for controlling the service order of the proportional bandwidth queues, a memory 5 for multicast group bits 156 for storing information about multicast cell transmission, and a back-pressure control circuit 158 for asserting multipriority back-~res,,uLt: on the eight back-~L~s~uLe lines of the switch element.

10 LTNKFn LISTS
Referring to Fig. 5, ~PBPC 150 uses its linked list RAM 152 to maintain five First-In/First-Out (FIFO) queues by means of lists of pointers to the next entry in the cell memory for each of the five output lines for a total of 40 15 possible virtual queues. Fig. 6 is a representation of the linked-list RAM 152 and associated head register set 153 and tail register set 155 for the forty queues defined for the 32 cell memories accounted for in the list RAM 152. For each of the forty queues, a buffer pointer is constructed from the 20 head address of the queue and tail address of the queue for one of the f orty queues stored in the head register set 153 and the tail register set 155. A head pointer and a tail pointer is kept for each one of the forty queues. The forty queues share a linked list of up to thirty-two entries. Each 25 entry can identify one of the thirty-two cell memories in cell buffer pool 100. The linked-list thereby specifies which cell memories are part of each queue in FIFO order. Cells are enqueued onto the tail of the proper queue and dequeued from the head of the proper queue in accordance with a queue _ _ _ _ _ _ _ _ . ...

WO gs/30294 ~ 2 r ~ 1613 service procedure which generates the Q--~equeue pointer value to the head register set 155 and the Iqueue pointer to the tail register set 155. A muY`157 switches between register sets, rlPrPn~;n~ on whether the procedure calls for enqueuing 5 or dequeuing a cell. An input buffer pointer specifies where the input cell is currently stored, and the output pointer designates where the cell is to be directed.
The queue6 for one output line are ~CCi~n~d five different priorities. Three of the queues are proportional 10 bandwidth queues of egual priority but having an illCci~np~
bandwidth of 5/8, 2/8 (1/4), or 1/8. of the rr--~inin~ two queues, one is designated a high-priority queue which may be used for very time derpnrlpnt data such as voice, and the other a multicast queue which is used for data being sent from one 15 transmitting workstation to more than one receiving workstation which might be the case in video conferences.
It will be seen that while there are forty possible virtual queues definable by MPBPC 150, only up to thirty-two queues may be active at any one time because there are only 20 thirty-two available cell buffer pool memories. In practice fewer than thirty-two queues may be active at any one time, because it is likely that there will always be some queues which are using more than one cell memory.
Multipriority buffer pool controller (MPBPC) 150 25 controls the overall function of the switch element 40 as follows. During each cell cycle, cells having a length of 118 nibbles may be received on any or all of the eight input lines. Prior to the start of a cell cycle, the controller 150 has specif ied which input line is connected to which cell ~ W095130294 ~ 3g 2 r~ o~rl~

memory via input crosspoint block 110 by setting bits in input controller 130. The first twelve of the 118 nibbles from each input line are read by input bus controller 13 0 and transmitted to the multipriority buffer pool controller 150 5 while the ATM cell is being stored in its designated cell memory. From these tags, MPBPC 150 det~rm;n~c the priority and destination of the cell that has just been stored in each of the eight cell memories connected to one of the input interfaces. The MPBPC 150 then adds the cell memories to 10 their appropriate queues by updating its linked lists. The MPBPC 150 then det~rm; n~ which of the output interfaces to which cells are directed can receiYe the cells during the next clock cycle. An output interface may be unavailable to receive all of the data which is directed towards it during a 15 cycle when more than one input lines are directing cells to a single output interface, or when the output interface has asserted back-pressure to the ~PBPC 150. The MPBPC 150 handles the problem of output interfaces being unavailable to receive cells by est~hl;~hinq queues for the connections for 2 0 which output lines are temporarily unavailable in the cell buffer pool 100. Cells may be stored in these queues in a first-in-first-out FIFO fashion for some number of cell cycles until the output interfaces are available for outputting the cells. Once the MPBPC 150 has made determinations regarding 25 which cells can be transmitted to their destination output interfaces during the next clock cycle and which cells will be stored in queues in the cell buffer pool 100, it directs the output interfaces to receive data from cell memories in the cell buffer pool by sending control signals to output bus _ _ _ ,,,, , . .... , , ,_ .

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controller 140. It also dirécts the input interfaces to available clall memories by sending input control signals to input bus controller 130.

5 BACK-PRESSURE CONTROI, One problem that may arise in a switch element 40 as packets are being routed through cell memories from input lines to output lines is the unavailability of cell memories for queuing prior to a clock cycle when new cells may be 10 received on the input interfaces. If a cell is received at an input inter~ace to the switch element when no cell memory is available to receive the cell, the cell must be dropped and the data resent.
In accordance with one aspect of the invention, each 15 switching element 150 avoids dropping cells by issuing back-pl~:6auL~ signals to each connection to each of its input interfaces on a per-input, per-priority basis to halt the flow of cells having a given priority to a given input. Back-pressure is asserted for a given input and given priority 2 0 whenever the number of currently enqueued cells of the given priority supplied by the given input exceeds a pr~et-l-rm;nc.
threshold. Back-pressure for~ a given priority is also asserted for all inputs whenever the total number of available cell memorie6 falls below a threshold associated with that 25 priority.
By employing a shared buffer pool, the switching element of the present invention virtually eliminates the deletion of cells due to exhaustion of available memory. In many ATM applications, even infrequent cell drops are harmful Wo 9~l30294 2 ~ 8 8 8 8 2 r~~
in that the loss of one cell necessitates the retrAncm; I=~ i on of many cells, substantially reducing network ef f iciency .
Furth,- e, in the event of excessive cell traffic through a switching fabric, it is preferable that cell drops occur at a 5 routing table rather than at a switching element, since routing tables employ sophisticated congestion management strategies unavailable at a switching element when dropping cells. (one such sophisticated congestion management strategy is the standard ATM Adaption Layer 5 (AAL5) early frame 10 discard technique, AAL5 being a technique for segmenting frames into cells. ) Fig. 7 is a simplified representation of the elements within back-~es,.uLa controller 150 used to implement the back-pressure GAr~h; 1 ity. Back-pressure controller 150 includes a time domain multiplexer 402, a state machine 404, a time domain demultiplexer 406, a queue service controller 408, an index memcry 410, a variable delay circuit 412, and a variable delay register 414. Back-pressure signals are generated by state machine 404 based on criteria as discussed 20 below. Back-pressure signals from other switching elements or a routing table are received by a queue service controller 4 08 which selects cells for output.
Back-ples,,uL~ iS asserted for a given input and given priority whenever the number of currently-enqueued cells of 25 the given priority supplied by the given input exceeds a predet~r-m--;ne~ threshold. A problem is posed in that queues, with the exception of the multicast queue, are organized by output rather than input. To maintain a count of enqueued cells for each input and priority, index memory 410 is _ _ _ _ _ _ _ _ _ Wo 9sl30294 2 ~ 8 ~ ~ 8 2 p "~
, ~; 16 malntained within the back-~Lt:sau, ~ controller 158 with an entry for each cell memory location which identifies the 60urce of the cell stored there. When a new cell is enqueued, index memory 410 is updated and a counter, internal to state 5 machine 404 and as60ciated with the source and priority of the cell, is incremer~ted. When a cell is de~ueued for output, the index entry for th2t cell is read to identify the source for that cell and the appropriate counter is then decremented. To determine the necessity of back-pressure for a given input and 10 priority, the counter for that input and priority is compared to a predetP~m; nPrl threshold.
The predetPrm;nP~ threshold i5 the same for each input and priority. Thus, back-pressure is allocated among inputs so that no one input blocks ;nc-~m;n~ traffic from other inputs 15 by occupying a disproportionate share of the cell memory locations. When inputs are aggregated, a counter is maintained for each priority for the aggregated inputs as a group rather than f or each input .
To assure that availability of cell memories is also 20 properly allocated among priorities, a count of empty cell memories is maintained within state machine 404 and compared to thresholds stored for each priority. When the number of empty cell memories falls below the threshold associated with a given priority, back-pressure is asserted for that priority 25 for every input. The higher priorities have lower thresholds set so that high priority traf f ic is impeded last as the count of available cell memories decreases. In addition, the thresholds are normally set so that high-priority traffic has strict priority over lower priority traffic.

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Tn one ~mho~;r-nt of the present invention, back-pressure signals for the various priorities are time-domain multiplexed together by time-domain multiplexer 402 so that each input is provided with a single back-pressure signal.
5 Received back-pressure signals are demultiplexed by time domain demultiplexer 406. Each priority then coLL~o~ds to a different time slot within the l-ir-~ ~' ;n multiplexed back-pressure signal.
A switching element and an associated input device 10 (switching element or routing table) may or may not be on the same printed circuit board. A problem arises in that if the devices are on the same printed circuit board, no delay is required on the interconnecting data or back-pressure lines while if the devices are on separate printed circuit boards, 15 the interconnecting lines may be retimed with D f lip-f lops .
Fig. 8A and Fig. 8B are a simplified representation of these two situations. A set of retiming bu~ers 51--54 ~te for inter-card delays. To ~nmr~n~Ate for the resulting delays, a switching element 40 according to one ~mho~liT 1 of 20 the present invention is provided with internal means for est~hl;~h;n~ a variable delay in the back-pressure line. Fig.
7 shows variable delay circuit 412 inserted in one of the back-pressure lines. I'he variable delay is selected by writing to variable delay register 414 within the switching 25 element.

Ar-r-R13r~ATE BITS
Ref erring to Fig . 9, a switch element 4 0 includes two aggregate input bits, agg_in(0) 151 and agg_in(1) 153 and two wo g5,30294 ~ ~ 8 ~ ~ ~ 2 , ~I/L _ ~fil3 aggregate output bits, agg_out(0~ 155 and ~Igg_out(1~ 157, which may be set by the configuration controller (not shown) to allow for aggregating either ~he group of inputs I0 to I3, the group of inputs I4 to I7, the group of outputs 00 to 03, or the group of outputs 04 to 07. Referring back to Fig. 3, some types of digital devices, particularly other switching systems, such as server computer 52, may need to transmit data through the switch f abric at a higher rate than may be provided by one switch element input, e.g., at the 622 Mbps rate provided by a conventional OC-12 ATM interface. Fig. 9 shows the groupings of inputs and outputs of a switch element 40 when the signals agg_in(0) and agg_in(1) and agg_out(0) and agg_out(1) are set. Switch element 40 ha6 two bits for input lines and two bits for output lines that signal the switch element when a set of four of its input lines is being configured as a single input which receives four cells at once and retains FIF0 order. Input bits agg_in(0) and agg_in(l) are set in the multipriority buffer pool controller 150 via the conf iguration bus When bit agg_in(0) is set true, inputs 0 through 3 are treated as if they are a single stream of cells. This makes the input capable of l~An~l in~ data at an effective rate four times higher than possible on one input line, which in one specific embodiment is 622 Mbps. With this feature, a switch element 40 can support a mixture of data rates on its inputs.
A key problem that must be addressed when aggregating input lines is maintaining FIF0 order between the cells that arrive simultaneously. When the inputs are not aggregated, the cells from each input are enqueued separately. When the 4 ~ ~L g g ~ g 2 P~ C13 inputs are aggregated, then the cells are enqueued as if they were from a single input with the cell received on input 0 placed in the single aggregated FIFO queue first, the cell received on input 1 placed in the single FIFO queue 6econd, 5 and so on. In the absence of the aggregate bit, FIF0 order could be violated as the NPBPC 150 uses a round-robin procedure to enqueue multicast cells to improve fairness.
This procedure intentionally chooses cells from the inputs in differing orders from cell time to cell time.
A second problem that the invention addresses is that cells bound for an aggregated output can go out any one of the outputs in the aggregated output, flPp~n~lin~ on av~ hi 1 ity.
When the aggregate bit is set, cells bound for the ayyL~y~-~ed output are dequeued for any one of its outputs. The MPBPC 150 also uses the aggregate bit to determine how to assert back-e to an output from the previous stage in an ayyl ~yclted input. Back-~e:s~,u, e is given if cells from a given input are queued excessively.
When inputs are aggregated to boost effective speed from 155 Nbps to 622 Mbps, the NPBPC 150 measures the counts of the cells from any of the inputs in the aggregated input, rather than from the individual inputs. The back-pressure is then applied to ~ of the inputs in the aggregated input, rather than the individual inputs. Nore sp~ific~lly, to aggregate, in the first level of the switch fabric (Fig. 2), the agg_in value is set for all inputs actually connected to a high speed input. Agg_out is set for all possible destinations of the inputs that agg_in is set for. In subsequent levels, agg_in is set for those links which have WO 95130294 ~ ~ 8 8 ~ ~ 2 F~-/~ 'I) ICl3 agg_out set in the previous level. Thus agg_out is set ~or all possible destinations of an input in which agg_in has been set. In the last level, agg_in is set for those links which have agg_out set in the previous level . Agg_out is set f or those links which are actually connected to a 622 Mbps output port .

VKllONAL BANDWIDl'll OUEUES
Switch elements 40 and the routing table circuit6 30 10 can also support proportional bandwidth queues. Proportional bandwidth queues solve a problem that arises when data traffic from sources of drastically different bandwidths coexist on an int~ te link. In one specific ~mhorlir L of the invention, the switch element 40 and routing table circuit 30 15 can support for example three queues that are of equal priority but which have bandwidths of 1/8, 1/4 and 5/8 of the available bandwidth. MPBPC 150 maintains a service order table 154 (Fig. 10) which Pnh~nr-~c fairness among connections having different bandwidths. The assigned proportions can be 20 adjusted by externally altering the contents of the service order table 154.
The proportional bandwidth queues are implemented by the MPBPC 150 by ha~ing a service order table 154 for the dequeuing process that specif ies the order of queue service 25 for each of the output queues. The schedule in each stage is delayed by one cell period which tend6 to minimize queuing and thus the cell memories required by trying to dequeue a cell from a given queue just after a cell from that queues is likely to have arrived. MPBPC 150 must make sure that all of ~ Wo 95/30294 ~ ) 8 ~ 8 8 2 . ~
the possible competitions between differing bandwidth queues turn out as predicted. For example, if cells only in the 1/8th and 1/4th queues arrive, then the 1/8th queue should get 1/3rd of the available bandwidth on the output channel, and 5 the 1/4th queue should get 2/3rd of the bandwidth. Similar results should apply for all of the possible x-way competitions. These issues have been addressed by a careful design of the service order table 154 stored within MPBPC 150.
This table 154 provides each of the participants in the 10 possible competitions with approximately the proper bandwidth while reducing overhead processing that must be done by the MPBPC 150 to determine dequeuing order. Additionally, the MPBPC 150 can update the service order table 154 on the fly so that moment-by-moment adjustments may be made by certain types 15 of switching systems that will use these devices to enhance fairness in competition.
As a further detail, Fig. lo shows a service order table 154 stored in MPBPC 150 for det~rm;n;n~ dequeuing from cell buffer pool 100 when more than one proportional bandwidth 20 queue is queued for a given output. The MPBPC 150 defines a service order interval of eight cell transmission cycles for det~rm;nin~ the priority of serving the proportional bandwidth queues. These cycles are represented by the eight columns labelled 0 to 7 in Fig. 10. During any given cycle, MPBPC 150 25 ~YAmin~S which queues for a given output wish to transmit data to that output. It will be seen that during any given cycle there is a queue service order listing the priority with which bandwidth queues will be serviced. During any cycle, only one queue is serviced and that queue is the queue having the ~8~82 highest priority, 1st through 3rd, as listed in the service order table during that cycle. For example, during cell cycle 4, the priority list is 3, 4 and 2. Should cells frDm two proportion21 bandwidth queues both be ready to transmit during 5 cycle 4, the cell from the queue having bandwidth of the higher priority will be transmitted. During the next clock cycle, cycle 5, if both of those queues wish to transmit, the next bandwidth queue will be transmitted because the queue service order table shows that it has a higher priority during 10 that cell cycle.

ULTICAST
One data transmission application which the present invention may be employed to support is multicast 15 transmission. During multicast transmission, data from one source is distributed to several destinations, i . e ., the multicast group, which comprise some, but not n~ s~rily all, of the possible switch fabric outputs. An example of such an application is a video conference over a network in which 2 0 several workstations are connected by a switch f abric, and voice and image data are transmitted from each workstation to each of the other workstations.
Generally, multicast may be 6upported in a variety of ways. Source cell duplication is a simple, but brute-force 25 solution to the multicast support problem. Fig. 11 is a simplified representation of the source cell duplication solution 60 known in the prior art. With source cell duplication, the source 62 o~ the data cells creates copies of each cell for transmission to each destination. This solution WO 95/30294 2 ~ 8 ~ ~ 8 2 ~ s 1~

~uffers from a number of significant disadvantages. Not only does the task of duplication place a severe load on the source 60, it also places limits on the number of destinations 64, 66, 68 in the multicast group connected by a switch element 40. As a result, the size of the multicast group for a network which supports multicast may be drastically limited (e.g., to half the size of connection for the network).
Additionally, expensive bandwidth is wasted. For example, in cases where more than one destination is at the same distant location, redundant copies of the information are transmitted over the entire distance, thereby llnn-~cP~sArily contributing to system traffic.
Mid-switch cell duplication 70 is an alternate multicast support solution. A simplified representation of a mid-switch duplication 70 solution iB shown in Fig. 12.
According to a typical mid-switch duplication 70 solution, a module 72 is provided at some point in the switching system which duplicates the transmitted cells from a source 74 as necessary for distribution to destinations 64, 66, 68 in the multicast group. Although this solution doe6 not suffer from all of the disadvantages of the source cell duplication solution 60, bandwidth is still l]nn~cF~Arily consumed by the transmission of the cell duplicates through the ~, ; n~lF.r of the system.
The optimal solution for supporting multicast, made practicable by the present invention, is referred to as tree-based cell duplication. A simplified representation of a tree-based cell duplication system 76 according to the invention is provided in Fig. 13. With a tree-based cell WO95/30294 2 ~ 8 ~ 8~ 2 ~ o, ~ ~

duplication system 76, the transmitted cells are not duplicated until the last point6 of div~Lgel~ce 77, 79 to the destinations 64, 66, 68, e.g., by means of cell replication within the switch element 4 0, represented herein as a serial 5 redirector 78. This avoids the ~lnn~r/~cci~ry cnn Lion of bandwidth encountered with the previously described solutions.
One possible complication of this solution, however, is that all destinations 64, 66, 68 of a multicast cell may not be reachable with a cell having the same address.
The present invention implements a tree-based cell duplication system 76 using a specific ~mhoA;- L of the switch element 4 0 described above . The solution is described with reference to Fig. 14. An eight-bit field in the routing tag of each transmitted cell det~rm;nps what is called the multicast group for that cell. As described above, the routing tag, a twelve-nibble field placed on the front of a cell by the routing table circuit based on the content of a multicast group bit register 81, dictates the path of the cell through the switch f abric . The multicast group consists of 2 0 the group of network destinations to which the cell is to be transmitted. For each switch element, the multicast group field det~rm; n~c which switch element outputs upon which a received cell is to be placed in order to get the inf ormation to the desired des~inations.
The switch element of the present invention stores an array of multicast group bits in its RAM, the array ;nrlllA;n~
one eight-bit word for each of the multicast groups. Each bit in each word represents one switch element output. When the multicast queue of the switch element is selected and a data ~ WO 95/30294 ~ l 8 8 ~ 8 ~ IC13 cell placed therein (as determined by a one nibble field in the routing tag), the multicast group f ield in the cell is used as an index into the ~ulticast group bits array, pointing to a particular word in the array. Any bits which are set in 5 the sPl ectPd word correspond to the switch element outputs on which the cell in the multicast queue is to be placed.

ULTICAST coMpr~r~IoN
One dif f iculty encountered in multicast transmissions 10 is that it is often not possible to place a given cell on all of the desired outputs simultaneously. Thi6 is referred to as the problem of multicast completion. Such a situation might arise, for example, if a cell from a higher priority queue has already been placed on the selected output. This situation 15 can also occur if a subsequent switch element has exerted back-~L~s~uLe on the selected output, thereby preventing the transmission of cells from that output. some open loop switching systems simply allow cells to be dropped if congestion causes cell buffers to overflow. If this occurs 20 with the transmission of video information, for example, the penalty incurred from such a drop is relatively high. An entire video frame might be lost due to the loss of just one cell. Other penalties are incurred i~ the system protocol requires the retransmission of the entire frame or a series of 25 frames .
The switch element 40 of the present invention solves this problem by keeping a record of the switch element outputs upon which the cell in the multicast queue has been successfully placed. Referring to Fig. 15, multicast queue $ ~8 2 ~ - ~ r ~ r C~

controller 156 of switch element 40 set6 bits in a multicast queue completion register 83 for each output on which the cell is actually placed. The ATM cell in the multicast queue is dequeued only when the bits in the completion register 83 match the bits in the word selected from the multicast group bits array stored in the multicast group bits register 81. As indicated by the multicast group bits word, cell M 85 in the multicast queue is to be placed on outputs (2), (3), and (5) 89, 91, 93. However, cell H 87 in the higher priority ~ueue has already been placed on output (3) 93, thereby preventing immediate placement of cell M 85 on that output 93. This is re Elected by the f act that bit number 3 in the completion register 83 (corrPep~n~in~ to output (3) 93) has not yet been set. When cell M 85 is eventually placed on output (3) 93, this bit 3 is set. The word in the completion register 83 then matches the word from the multicast group oits array 81, allowing cell M 85 to be de~ueued.
PER PRIoRITY OI~ING ~ITH PER CONNECTION COUNTS
As described above, the routing table circuit 30 of the present invention receives a cell from a source, looks up the intended address in its RAM, adds the appropriate routing tag to the cell, and then puts the cell out onto the switch f abric via the switching elements . The routing table circuit 30 also performs a ~ueuing function in which it stores queued cells in an ~c_ nying SR~M before placing them on the switch fabric. The routing table circuit 30 of each source queues the cells on a per priority basis, but also keeps track of how many cells from each connection are in the queue at any ~ Wo 95/30294 - 2 1 ~ 8 8 8 2 , .,~ c 1~13 given time. Unlike a strict per cnnneC~; nn queuing discipline, a transmission scheduler is not required.
Fig. 16 is a table which illustrates the manner in which the routing table queues i nrnm; n~ cells . In the 5 illustrated example, cells having priorities 0, 2, and 5 have been queued by the routing table. Within each of the priorities, cells from different connections have been queued.
The count of r~ueued cells per connection is maintained as shown in Fig. 17, showing the number of queued cells for each 10 VPC. The routing table uses the connection count to perform closed loop functions such as sending a back-~L~sDuLe signal to a particular data cell source. Thus, with the present invention, the simplicity of per priority queuing is enjoyed, while at the same time per connection queue depths are kept so 15 that congestion r-n~; ~ techniques can be employed.
MAR~n I r~ ;~ku~ll LINT~n ~T.~T
It is one of the functions of the routing table to alert the external processor that a virtual channel is 20 experiencing congestion. One method for doing this is to generate an interrupt signal each time a congestion condition is encountered. However, it is not desirable to generate an interrupt every time a data cell is queued for a congested channel, especially if the processor has already been notified 25 of the congestion on that channel. Also, more than one channel may experience congestion before the processor is able to respond to a congestion interrupt. It is therefore n~C-~cezlry to keep track of r h~nn~ experiencing congestion so that the processor may take cl~uLu~Liate action for all such _ _ _ _ _ _ _ _ _ _ _ _ _, . .. .

w0 95l30294 ~ ~ 8 ~ ~ 8 ~ C lCl3 ~

rh;~nnPl ~ when it ls ready to do so. One method for keeping track of congested rh~nnPl c includes as6igning a bit for each of the rhAnnPlc, and setting the bits corrpcprn~lin~ to rh~nnPl c which experience congestion. The processor then 5 checks the bits for all of the rh;-nnPlc to ~PtP~m;nP which rh~nnPl ~: are congested. However, because of the number of rh~nnPl c made possible by the present invention, such a solution is undesirably slow, cr,n~ m;nr~ valuable ~L~cessoL
time .
Therefore, according to a specific Pmhorl;r-nt of the invention, the routing table maintains a linked list of currently congested rh~nnPl ~: . Each channel in the list is also marked (i . e., a "congestion" bit is set) 50 that the queuing of further data cells for those rh~nnPl c does not 15 generate additional interrupts. When a data cell is queued for a particular channel, the current queue depth for that channel is compared with the conf igured congested queue depth .
If the current queue depth is longer and the channel is not marked, the routing table generates an interrupt and the 20 channel is marked and added to the end of the linked list. If the channel is already marked, nothing happens.
When the processor is able to respond to an interrupt, it f irst looks at the interrupt head pointer which points to an address which represents the f irst virtual channel in the 25 linked list. The processor then reads from that channel the address for the next channel experiencing congestion. The processor continues to read the addresses for the rhi~nnPl c experiencing congestion until it reaches the end of the linked list. The processor then takes appropriate action for each of WO 95/30294 2 1 8 8 8 ~ 2 r~

the rh:~nn~ in the li6t to resolve the congestion. Such action might include, for example, sending an appropriate f eedback message, or changing the gueue depth which causes interrupts .
A congestion-relieved threshold is det~rm;n~d by multiplying the congestion threshold by a fractional constant (e.g., 0.75). And whenever a cell is dequeued, and the current queue depth falls below the congestion-relieved threshold, a second interrupt is generated, and the congestion is cleared.
A global "enable" for interrupts allows the system processor to read the linked list of congested rh~nn~l atomically. If a channel becomes congested while the interrupts are disabled, once the interrupts are re-enabled, the next cell queued for that channel will cause an interrupt if the channel is still congested.
The invention has now been explained with reference to specific ~mhQ~l;r~nts. Other ~mho-l;r-nts will be apparent to those of ordinary skill in the art upon review of this description. It is therefore not intended that the invention be limited, except as indicated by the appended claims.

Claims (42)

CLAIMS:

1. An asynchronous transfer mode (ATM) switching system using a switch fabric architecture comprising:
a backplane having a plurality of distinguishable locations for supporting interface functions, switching functions and control functions from said distinguishable locations; and a plurality of ATM switch modules for connection to the backplane at said switching function locations, each one of said ATM switch modules including a closed loop switch element.

2. A switch element comprising:
a plurality of input interfaces for receiving cells of data;
a plurality of output interfaces for transmitting cells of data;
a shared pool memory comprised of a plurality of cell memories;
an input crosspoint circuit capable of connecting any of said plurality of input interfaces to any one of said plurality of cell memories;
an output crosspoint circuit for connecting any one of said plurality of cell memories to any one of said output interfaces and;
controller means for controlling which of said inputs is connected to which of said cell memories and for controlling which of said outputs is connected to which of said cell memories.

3. The device according to claim 2 wherein said controller means further comprises:
a linked-list random access memory;
a set of multipriority queues for each of said output interfaces each one of said queues in said set residing in said random access memory and comprising:
a connection address;
a queue priority identifier; and a first-in/first-out linked list of identifiers to said cell memories in said shared pool memory.

4. The device according to claim 2 wherein there are eight input lines each capable of receiving four-bit wide nibbles and eight output lines each capable of transmitting four-bit wide nibbles and wherein the shared pool memory is comprised of 32 cell memories.

5. The device according to claim 4 wherein there are five multipriority queues for each of said eight output lines making a total of 40 virtual queues.

6. The device according to claim 3 wherein each of said active queues represents one connection through a switch fabric, said connection defined as connecting one data transmitter to one data receiver at a specified priority over a determined and fixed path in said switch fabric.

7. In a switch element comprising a plurality of input interfaces, a plurality of output interfaces, a shared pool memory having a plurality of cell memories, a controller, and means responsive to the controller for connecting any of said input lines and any of said output interfaces to any one of said cell memories, a method for switching a cell of data from any input interface to any output interface comprising the steps of:
receiving the cell of data over one input interface and storing the cell in a cell memory designated by said controller for that input interface;
using the controller to examine a tag portion of said cell, said tag portion identifying the output interface to which the cell must be directed;
using the controller to enqueue the cell by adding an identifier for the cell memory in which the cell has been stored to a linked list;
using the controller to dequeue the cell when its desired output is available by connecting the cell memory in which the cell is stored to the cell's desired output interface; and transmitting the cell over its desired output interface.

8. The method according to claim 7 further capable of sending to one output interface cells of data having different priorities further comprising the steps of:

using the controller to examine said tag portion of said cell, said tag portion additionally identifying the priority at which the cell is being transmitted;
using the controller to enqueue the cell at its appropriate priority by adding an identifier for the cell memory in which the cell has been stored to a linked list having a specified priority; and using the controller to dequeue the cell when its desired output interface is available to receive a cell of that cell's priority by connecting the cell memory in which the cell is stored to the cell's desired output interface.

9. The device according to claim 8 wherein said multipriority queues further comprise a means for designating a bandwidth assignment associated with each of a subset of said plurality of queues.

10. The device according to claim 9 wherein said controller further comprises a queue service order table for determining, during a cell cycle, the service order for said plurality of bandwidth queues.

11. In a switch element having a plurality of queues for storing cells of data being routed from an input interface to an output interface and having a controller, a method for determining which of the queues will be connected to the output interface during a given cell cycle in accordance with a proportional bandwidth scheme comprising the steps of:

designating a specified number of cell cycles as a service order interval;
constructing a service order table that, for each of the cell cycles within the service order interval, lists the queues in accordance with the service order priority they will have during that cell cycle;
using the controller to determine which of the plurality of queues contain a cell ready to be transmitted to the output interface during a given cell cycle; and using the controller to decide, by reference to the service order table, which of the queues needing service during that cell cycle will be connected to the output interface.

12. The method according to claim 11 wherein the queues are assigned a proportional bandwidth that is a fraction consisting of a numerator and a denominator common to each queue and wherein the service order interval has a number of cell cycles equal to said denominator.

13. The method according to claim 11 wherein there are three queues assigned proportional bandwidths 1/8, 2/8 and 5/8 and there are seven cell cycles in each service order interval.

14. The method according to claim 7 further capable of sending to one output interface cells of data having different priorities and cells having different assigned proportional bandwidths at the same priority further comprising the steps of:
using the controller to examine said tag portion of said cell, said tag portion additionally identifying the assigned proportional bandwidth at which the cell is being transmitted;
using the controller to enqueue the cell at its appropriate assigned proportional bandwidth by adding an identifier for the cell memory in which the cell has been stored to a linked list defining a queue having a specified proportional bandwidth;
using the controller to determine by reference to a service order table the service order for the proportional bandwidth queues; and using the controller to dequeue the cell when its desired output is available to receive a cell of that cells priority and when that cell is in the highest service order during a cell cycle according to the service order table by connecting the cell memory in which the cell is stored to the cell's desired output interface.

15. The switch element of claim 2 further comprising:
a plurality of aggregate input control bits;
a plurality of aggregate output control bits;
means within said controller responsive to an active state of one of said aggregate bits and capable of causing said controller to treat cells received on a subset of said plurality of input interfaces as though the cells were received on one input interface.

16. The switch element of claim 3 further comprising:
a plurality of aggregate input control bits;
a plurality of aggregate output control bits;
means within said controller responsive to an active state of one of said aggregate bits and capable of causing said controller to treat cells received on a subset of said plurality of input interfaces as though the cells were received on one input interface by establishing in said linked-list random access memory a set of aggregated multipriority queues for receiving cells from all of the subset of input interfaces.

17. The switch element of claim 16 wherein said control means is operative to respond to one of said aggregate input signals by preserving FIFO order on cells received over said subset of said input interfaces.

18. In a switch element comprising a plurality of input interfaces, a plurality of output interfaces, a shared pool memory comprised of a plurality of cell memories, a controller, aggregate bits, and means responsive to the controller for connecting any of said input interfaces and any of said output interfaces to any one of said cell memories, a method for switching cells of data from a designated aggregate subset of input interfaces to any available interfaces of a designated aggregate subset of output interfaces comprising the steps of:

receiving cells of data over said aggregate subset of input interfaces and storing the cells in cell memories designated by said controller for each of said subset of input interfaces;
using the controller to examine a tag portion of said cells, said tag portion identifying the output interface to which the cell must be directed;
using the controller to enqueue the cells from the aggregate input interfaces by adding in FIFO order an identifier for each of the cell memories in which aggregate input interface cells have been stored to a single linked list for the aggregate output;
using the controller to dequeue the cells when any of the desired aggregate output interfaces are available by connecting the cell memories in which the cells are stored to the available output interfaces; and transmitting the cells over the desired aggregated output interfaces.

19. The method according to claim 18 further capable of receiving, via aggregated input interfaces, cells of data having different priorities, said method further comprising the steps of:
using the controller to examine said tag portions of said cella, said tag portions additionally identifying the priority at which the aggregated cells are being transmitted;
using the controller to enqueue the cells at their appropriate priority by adding an the identifies for the cell memories in which the cells have been stored to a aggregate linked list having a specified priority; and using the controller to dequeue the cells when any of the desired aggregate output interfaces are available to receive cells at the aggregated queue's priority by connecting the cell memories in which the cells are stored to the available aggregate output interfaces.

20. An ATM switching element comprising:
a data input coupled to an ATM cell output of a source;
a back-pressure output coupled to said source for issuing a back-pressure signal to block transmission of cells to said data input; and control means coupled to said back-pressure output for asserting back-pressure responsive to congestion within said switching element.

21. The ATM switching element of claim 20 wherein said control means comprise a state machine.

22. The ATM switching element of claim 20 further comprising:
variable delay means for delaying said back-pressure signal responsive to a delay value stored in a register within the ATM switching element; and input port means for externally adjusting said delay value.

23. An ATM switching element comprising:
a cell output for transmitting cells having one of a plurality of priorities;
a first back-pressure input for receiving an indication of back-pressure necessity for cells having a first priority;
means, coupled to said cell output and said first back-pressure input, for blocking transmission of cells having said first priority responsive to said indication of back-pressure necessity received on said first back-pressure input;
a second back-pressure input for receiving an indication of back-pressure necessity for cells having a second priority; and means, coupled to said cell output and said second back-pressure input, for blocking transmission of cells having said second priority responsive to said indication of back-pressure necessity received on said second back-pressure input.

24. The ATM switching element of claim 23 wherein said first back-pressure input and said second back-pressure input are derived from a single time-domain multiplexed back-pressure input.

25. In an ATM switching element employing a cell memory pool, a method for providing back-pressure to a plurality of inputs and a plurality of priorities, comprising the steps of:

receiving a cell having one of said plurality of priority levels from one of said plurality of inputs;
thereafter enqueuing said cell by recording said cell in a first memory location in the cell memory pool;
using an address of said first memory location to obtain an address of a second memory location within an index memory;
recording a reference specifying said one plurality level and said one input at said second memory location;
incrementing a cell count indicator associated with said one priority level and said one input; thereafter comparing said cell count indicator to a predetermined threshold to obtain an indication of back-pressure necessity for said one priority level and said one input; and thereafter upon a positive indication of back-pressure necessity, asserting a back-pressure signal associated with said one input and said one priority.

26. The method of claim 25 further comprising the steps of:
dequeuing the cell by transferring the cell from said first memory location to an output of the switching element;
using said address of said first memory location to obtain said address of said second memory location; thereafter retrieving said reference specifying said one plurality level and said one input from said second memory location;

using said reference to identify said cell count indicator associated with said one input; and thereafter decrementing said cell count indicator associated with said one priority level and said one input.

27. In an ATM switching element employing a cell memory pool, a method for providing back-pressure to a plurality of priorities, comprising the steps of:
receiving a cell via an input of the switching element; thereafter enqueuing said cell by recording said cell in a first memory location in the cell memory pool;
decrementing an empty cell indicator, said empty cell counter being an enumeration of empty cells within said cell memory pool;
comparing said empty cell indicator to a threshold associated with a first priority to obtain an indication of back-pressure necessity for said first priority;
upon a positive indication of back-pressure necessity for said first priority, asserting a back-pressure signal associated with said first priority;
comparing said empty cell indicator to a threshold associated with a second priority to obtain an indication of back-pressure necessity for said second priority; and upon a positive indication of back-pressure necessity for said second priority, asserting a back-pressure signal associated with said second priority.

28. The method of claim 27 further comprising the step of time-domain multiplexing said back-pressure signal associated with said first priority with said back-pressure signal associated with said second priority.

29. A switching device for transmitting a data cell, the data cell comprising a first data field, the switching device comprising:
plurality of outputs;
a queue for temporarily storing the data cell; and a memory for storing a plurality of data words, each data word comprising a plurality of first bits, each of said first bits corresponding to one of said outputs;
wherein the data cell is placed on selected ones of the outputs, the selected ones of the outputs corresponding to first bits which have been set in a first data word selected from the plurality of data words, the first data word being selected in response to the first data field in the data cell.

30. The switching device of claim 29 wherein there are up to eight outputs and eight first bits in each data word.

31. The switching device of claim 29 wherein the memory comprises random access memory (RAM).

32. The switching device of claim 29 wherein the data cell comprises up to 118 nibble wide segments.

33. The switching device of claim 29, further comprising a queue completion register, the queue completion register comprising a plurality of second bits, each of the second bits corresponding to one of the outputs, the second bits being set when the data cell is placed on the outputs corresponding to the second bits, the data cell remaining in the queue until the second bits set in the queue completion register match the first bits set in the first data word.

34. The switching device of claim 33 wherein there are up to eight outputs and eight second bits.

35. A method for transmitting a data cell to a plurality of destinations using a switch element having a plurality of outputs, the data cell having a first data field, the method comprising the steps of:
storing the data cell in a queue;
using the first data field to select a first data word from a memory, the first data word comprising first bits, each of the first bits corresponding to one of the switch element outputs; and placing the data cell on selected ones of the switch element outputs corresponding to first bits in the first data word which have been set.

36. The method of claim 35, further comprising the steps of:
setting second bits in a queue completion register, each of the second bits set in the queue completion register corresponding to the outputs upon which the data cell has been placed;
comparing the second bits in the queue completion register to the first bits in the first data word; and dequeuing the data cell when the second bits set in the queue completion register match the first bits set in the first data word.

37. A method for queuing incoming data cells in a switching system, the data cells being received from a plurality of connections, each of the data cells having an associated priority, the method comprising the steps of:
queuing the incoming data cells with respect to each other in a queue according to the associated priority of each of the incoming data cells; and maintaining a count of the incoming data cells from each of the connections which remain in the queue.

38. The method of claim 37, further comprising the step of generating feedback signals to selected data cell sources when the count for connections corresponding to the selected data cell sources exceeds a first number.

39. A method for monitoring congestion on channels in a switching system, comprising the steps of:
storing a first data cell in a queue, the first data cell comprising a routing tag field, the routing tag field corresponding to a first channel;

comparing an actual data cell count for the first channel to a predetermined count;
generating an interrupt signal if the actual data cell count is greater than the predetermined count and the first channel is not marked;
marking the first channel by setting a bit if the first channel is not marked; and placing the first channel on a linked list of congested channels if the first channel is not already on the linked list.

40. The method of claim 39, further comprising the steps of:
receiving the interrupt signal;
reading the congested channels in the linked list; and taking action to resolve the congestion for the congested channels in the linked list.

41. The method of claim 40 wherein the step of taking action comprises sending a feedback message to selected sources of data cells.

42. The method of claim 40 wherein the step of taking action comprises changing the predetermined count.