CA2187876A1 - Atm switching system - Google Patents

Abstract

A communication system comprising a hub slot adapted to receive any one of a plurality of hub cards for receiving and transmitting data cells a plurality of universal card slots a plurality of interface cards insertable into any one of said plurality of universal card slots for receiving incoming ones of said data cells containing data and transmitting outgoing ones of said data cells containing data; an add bus having respective data links connected between individual ones of said universal card slots and said hub slot for receiving said outgoing ones of said data cells from said plurality of interface cards and transmitting said outgoing ones of said data cells to said hub slot; a drop bus having a single data link connected between all of said universal card slots and said hub slot for transmitting said incoming ones of said data cells from said hub slot to said plurality of interface cards; and means within each of said interface cards for filtering said incoming ones of said data cells from said drop bus and thereby routing said data cells to an appropriate one or more of said plurality of interface cards.

Description

W~ 9!i/30318 PCT/CA95~00Z48 ~ t ~ 7 8 7 6 ATM SWITCHING Sysl~M
Fi~ f th~ Tnv~ntinn This invention relates in generAI to digital ~ systems, and more ~alLi~ulally to a novel switching system using ai~yll~h.ul~uua transfer mode ~ATM) and switching of ' Bzck~round of the Invention The emergence of high-speed aa~ l.-u..u..~ transfer mode (ATM) 1û ~ is a recent result of the diverse demands now being made on enterprise backbone networks. Early enterprise networks were dominated by voice traffic with only a relatively small amount of circuit bandwidth devoted to data and other ~ More recently, a range of new ~ has evolved resulting in significant changes to existing backbone networks. High-bandwidth video telephony and video ~ ~ f ~ e, for example, are rapidly becoming essential , in digital . systems. Similarly, the bandwidth for LAN (Local Area Network) across multiple sites is also increasing as established prior art LAN systems such as EthernetTM and Token Ring are upgraded to meet the demands of faster ~ and more 2û , ,u., &
For example, Fibre Distributed Data Interface (FDDI) LANs operating at lOO
Mbps are presently being deployed while even higher bit rates LAN types are emerging as a result of text-based personal computers being replaced by ~ I;a 25 work stations and associated servers. Typically, multi-media work statiûns and their associated servers support document .. I,:~r. 1. ~ ~ that comprise not only text but also high resolution still images and moving images with sound. Thus, instead of inter-Site LAN traffic being dominated by file transfers of textual ;..r.- . -li-- as in the prior art, LAN file transfers in newer systems are migrating towards higher volume, 3û high bit-rate mixed-media traff~c.
The combined effect of such ~u~lvlu~ b has ' the d~ ~.lv~
of a mûre flexible method for the allocation of ~ bandwidth in order to _ . _ , _ . _ . . . . . . . ... .. .. . .. . . .. . . , .. . . . _ . .

WO 95/30318 ~ ~ ~ 7 ~ 7 ~ PCT/CA9S/00248 efficiently utilize inter-site leased circuits associated with enterprise networks.
The d~, ' . discussed above are not limited to private networks, but are occurring in public carriers as well.
In order to meet these new d~emands in private and public digital systems, an . ,t ~ standard operating mode has been developed for use with broadband integrated services digital networks (BISDN) based on the~ ,Iu, transfer mode (ATM) of i and switching. The aim of the 10 ATM protocol is to provide a more flexible facility for the i and switching of mixed-media traffic comprising data, voice, still and moving images and video.
T ' 'Iy, constant bit rate traffic such as voice has been transmitted and switched using pre-assigned time slots, whereas data is normaUy transmitted in the form of variable length frames which are "i' ' together on a statistical basis.
15 According to the ATM protocol, i and switching is performed on fixed-sized units referred to as Rcells". Cells from different sources (eg. voice, data, video, etc.), are '`i ' ' together on a statistical basis for ~ A purposes.

2 o Each standard ATM cell is 53 bytes in length, comprising a 48-byte ;..r.... - - '..,. field (also referred to as the "payloadn), and a five-byte headercontaining routing and other fields.
Like packet and frame switching, ATM operates on a virtual call/connection 25 basis. This means that prior to any user i r~,.,. -~;.~A cells being sent, a virtual connection is first placed through the network. During this phase, a vir~ual connection identifier (VCI) is assigned to the call at each ~ ' ~ link along theroute. The assigned identifier, however, has only local 5;~;, ;r,. - ~ to a link and changes from one link to the next as the cells relating to a connection pass 3o lI.~.e~u.,~61,. Thismeans,therefore,thattherouting; r.. -- ~ carriedineachcell header can be relatively small.

WO 95130318 2 ~ X ~ ~ 7 ~ PCT/CA95100248 In particular, each incoming link/port has associated therewith a routing table that contains the 4,.,~q.,~.1..E output link/port and a new VCI to replace the incoming VCI for the subsequent link/port. The routing of cells in both directions along a r ~ route is therefore extremely fast as it involves only a simple 5 look-up operation. As a result, cells from each link can be switched ;.,.1. ~ ly and at very high rates. This allows parallel switch to be used and high-speed circuits (ie. in the gigabit-per-second range), each operating at its maximum capacity.
In practice, the VCI is made up of two sub-fields: a virtual path identifier (VPI) and a virtual channel identifier (VCI). The VPI field relates to statically assigned whereas the VCI field relates to dynamically assigned Routing can be performed using one or the other, or a . ' of the VPI and VCI subfieqds. For example, a virtual path may be set up through the15 network on a semi-permanent basis (by network p ., bet veen each pair of network endpoints. The cells relating to multiple (ie. . '., calls between theseend points are then ." ~ l ~ together and then routed along the same assigned path. In this example, therefore, the routing of cells within the network is performed using the VPI field and the VCI field would be used at the end point to relate cells 2 o to a particular call.
The ATM reference model defines three protocol layers, as follows: (l) ATM
adaphtion layer which overlies the (2) ATM layer which overlies the (3) physicallayer.
The ATM adaptation layer (AAL) provides a range of alternative service classes for r r ~ an adaptation function between the class of service proYided to the user (e.g. for the transport of data frames between two LANs), and the cell-based service provided by the ATM layer.
The ATM layer provides the required ' ~ of cells relating to different c,,- -- I; - into a single stream of cells, and the subsequent ~ ' of the cell wo 95/30318 218 7 8 7 6 PCT/CA95/00248 streams. The ATM layer also effects the required ~ lay ~ of cells based on the VPI and/or VCI fields.
The physical layer interfaces with the particular l ~ C~ medium which 5 carries the actual cells (eg., fibre optic, coaxial cable, etc.), and may be;~ ..t. .
via a number of different ~. h ~1~1~;. ` depending on the type of being used (eg- 1' ' ~ or ~ For the former, the tlansmitter establishes a frame structure over the bitlbyte stream that exactly matches the ATM cell. The receiver then processes the incoming byte stream on a byte-by-10 byte basis until a valid S-byte cell header is formed. The incoming byte stream is then processed on these f~ed cell ~ In the case of a ~,luu~ Iink (e.g.
OC31STMl), the frame payload field is not a multiple of the cell size and hence the cell boundaries will change from one frame to the next. With this type of link, therefore, a pointer in the overhead channels is used to identify the start of the frst 15 cell boundary im the payload field while cell delineation is performed based on the E[EC byte (discussed in greater detail below).
As discussed above, the ATM layer performs all of the functions relating to the routing and ,....11;1.1..;1~, of cells over virtual ~ which may be semi-2o permanent or set up on demand. For the latter, a signalling protocol is;, ,.l. ,.. ,t. .which is similar to that used with ISDN.
There are two different header formats for standard ATM cells commonly referred to as UNI and NNI. Each format ill~,UIl. ' a VPI field aS the first byte.
25 However, for the format used over a user-network access link intended for use by user devices that generate and rc~ceive cells directly, the four most significant bits of the first header byte are replaced by a generic flow control (GFC) field that has only local ciæ,; 1; ~ over the link and is included to allow cells to be allocated different priorities. This field is not present within the network, however, and instead the VPI

3 o field is extended across the entire byte.
The second byte of the header comprises a first nibble which is an extension WO 95/30318 21~ ~ 8 7 ~ PCT/CA95/00248 of the VPI field. Thus, for the format used over a user-network access link, the VPI
field is eight bits, whereas within the network the VPI fidd is twelve bits. The least significant four bits in the second byte of header r. " .~ comprises a first porlion of the VCI field. The third byte of the header continues the VCI field and the frst 5 four most significant bits of the fourth byte of the header complete the VCI field.
Thus, the VCI field in a standard ATM header consists of sixteen bits. The four least significant bits of the fourth header byte include (l) a payload type (P~ field which is used to enable cells relating to the C and M planes associated with the ATM
reference model to be j rr " ' ~ from cells containing user ;..f... ,...~;,)A, and (2) 10 a cell-loss priority (CLP) bit. The CLP bit is used to allow a user to indicate those cells associated with a connection which should be discarded first. This is useful because an ATM nettvork operates by '`i ' P on a statistical basis so that it ispossible for cell buffers to overflow within an exchange.
Finally, a header error control (HEC) field is provided as a va~iation of an eight-bit cyclic ' ' ~ check (CRC) pvl.~ ' for detecting errors in vhe header. If the CRC ~l~ ' fails, the cell is discarded. However, for single-bit errors, hardware may be provided to correct the error based on ' from the HEC field.
There are a number of areas in the design of existing ATM-based systems where substantial , v.. may be made in signal routing efficiency, diagnosvic support and hardware ~
Firstly, it is desirable to provide a system which can flexibly: ' a variable number of interface circuits per switch fabric interface, depending on interface card bandwidth. Prior art systems have been provided with fixed bandwidth for each interface card within such systems.
Secondly, while the virtual connection identifier (VCI) may be used to establish routing of a cell from link-to-link on a point-to-point basis or "shared" from one point to several l ~ (i.e. point-to-multipoint), it ~an only do so at the .

expense of costly and complex circuitry. Similarly, only a ludi~ uy level of cell priority queuing is possible using standard ATM cell headers. Also, according tomany prior art systems, intershelf: - has been via parallel busses which a¢e of hnherently low speed and low bandwidth. Therefore, there is a need for ~ , enhanced routing capability of ATM ceUs both inter-node and intra-node ~vithin such - systems.
ThirtUy, since ceU streams in an ATM: system are essentiaUy point-to-point and tern~indte hn queuing pointS, there is normaUy no need to maintain ~ timing throughout the switching fabric. However, since some interface cards require a standard timing reference, it is desirable to maintain system timing hl such a system. The standard method for "~ intra-node system ~ J~ in an _i~J~.,hlu~lu~ serial link (eg. intershelf link), is to run a s~ ' timing link throughout the system. However, such systems suffer from jitter transfer problems resulting from ~JIl.,IU, '!~ ~c~ l timing signals due to instability of chaining phase locked-loops (PLL).
Alt~ dt;~,ly, some prior art systems maintain ~., ~ by providing a dedicated timing wire from the system ~ unit (SSU) to all timing ' This effectively restricts the location of the SSU to a L " ' slot in the system which is specificaUy wired to receive it.
A~ , there is a need to maintAain system ~. ~ without extrd timing wires and without suffering from loss of sync and other problems inherent in prior art PLL i~ll,;uoll;~t;ull sy~tems.
Fourthly, in prior art systems debug access to th.e operating software in the syskm is provided by a special softwcre load with debugging code built in, and ad~dicated hardware debug jport must be provided onto which debug equipment must 3 o bc attached hn order to gain access to the debug software. It is desirable to provide a system in which the debug software is always in place and hn which the tl~ stem su~rt ~e hntegra~d Inu t~ A~ fa~

WO 95130318 ~ ~ 8 ~ 8 ~ 6 PCT/CA95/a0248 Fin. lly, it is desirable to provide system ' ' ~ for improved reliability of critical system functions.
.
Other u~u~L~...;tiw exist for the illllJlU.. ' of ATM ~
systems design, such as in the areas of control queue servicing ql" ' node ~ etc.
ty of the Invention According to the present invention, an improved ATM ~ system 1û is provided the design of which has been directed by the desire to address the prior art problems discussed above.
Firstly, the maximum utilization of the switching core is achieved in the system of the present invention by providing a variable number of Universal Card15 Slots (UCS) per Inter Shelf Link (ISL), depending on the interface card bandwidth.
For example, a large number of low-speed UCS cards may be provided in one ' ' t, while fewer high-speed UCS cards may be provided in another t, and in each case switching core efficiency may be optimally rqil~tqin~A
2û Secondly, with respect to the problem of routing ATM cells within the system, according to the present invention a plurality of overhead bytes are pre-pended to the standard 53 byte ATM cell in order to facilitate cost-efficient cell routing on a point-to-point ba~is or a point-to '~ basis within the system, with cell priority queuing, simplified egress statistics gathering, and error detection across the pre-pended bytes and the four bytes of the ATM header (with the HEC field omitted).
Thirdly, with respect to the problem of ~ system a,~ ' ' " , according to the present invention an 8 Khz timing signal is embedded in Ordered3 0 Sets (discussed in greater detail below) which are transported over the ISLs and can appear anywhere in a ~Supercell" framing structure (the concept of a "Supercell" is di~cussed in greater detail below). Therefore, the timing signal is ' . ' of any WO 95/30318 ~ PCT/CA9S/00248 2187876 .~. --serial data clock, as contrasted with prior art ~ u..~u~ systems. No special jitter reducing circuitry or wiring is required, and the timing source and SSU can be located anywhere within the switching fabric to which the ATM cells may be directed, in contrast with prior art ~II~ UlLiLClfiUll systems using a dedicated timing 5 wire.
Fourthly, with respect to d. ~ system support, according to the present invention an integrated real-time d, .~l~..l~..l system is provided wherein the debug software is 1 I~, installed in the system and in which the d. ~luy~ system0 support ~ are integrated imto the ATM fabric, such that the prior art for special debug equipment at a customer site is minimized, if not entirely eliminated.
Finally, the system ' of the present invention allows for switch 15 fabric ~
RnPf D~crri,ptir~n nf th~- Drawin~L
A det iled description of the preferred ~ ;". l is provided herein below with reference to the following drawings, in which:
Figure 1 is a block diagram of an exemplary digital . system the method and apparatus of the present invention;
Figure 2 is a block diagram showing the cell switching core in greater detail 2s connected to an exemplary peripheral shelf of the system illustrated in Figure 1;
Figure 3 is a diagram of the modified ATM cell format for point-to-point according to a first . b~ ' of the invention;
3 o Figure 4 is a diagram showing the modified ATM cell format for point-to-nultipoint according to a second ~ I.~ ", : of the invention;

-Figure S shows a card address forlnat according to the preferred ~. . ,l .~. l; . ~, Figure 6 is a block diagram of an interface circuit for connection to a universal card slot and to external signal carrying media, including circuitry for 5 generating and filtering the IJlU~ ,kLl,y All~ header data according to the preferred .. .;
Figure 7 is a block diagram of a switching ASIC used on a hub card of the peripheral shelf shown in Figure 2;

Figure 8 is a block diagram showing a cell queuing core of the ASIC shown in Figure 7;
Figure 9 is a block diagram of a standard interface ASIC in the interface 15 circuit of Figure 6 for receiving and i forlnatted ATM cells to and from the switching fabric;
Figure lO is a flowchart showing operation of a receive filter in the interface circuit of Figure 9;
2û
Figure ll is a flowchart showing details of a ... l~ , cell sorting procedure in the flowchart of Figure lO;
Figure 12 is a flowchart showing operation of a first filter sorting algorithm 25 in the flowchart of Figure lO;
Figure 13 is a flowchart showing operation of a second filter sorting algorithm in th~ flowchart of Figure lO;
3 0 Figure 14 is a functional schematic diagram of an intershelf link according to the present invention; and 218~876 Figure l5 is a block diagram showing ~ ' of timing ;,.r..", ~
through the, system of Figures l and 2, according to the present inYention.
D~il~ De~cr~ntinn of thP Pr~ofP~I F.mhn~im~
With reference to Figure l, a bloclc diagram is provided of a switching for ,' l" the method and apparatus of the present invention in with one; ' - " The system comprises a cell switching core 1 connected to a plurality of interface card access or peripheral shelves 3A, 3B, etc., via respective 800 Mbps inter-shelf links (ISL) 5. In the present disclosure, the terms 'access shdf" and "peripheral shelf" will be used ' l, "y i' ~' In a multi-shdf access - ~ such as shown with reference to bloclcs 3D and 3E, a further ISL 5A may be provided directly between the access shelves. r... Ih. . " ,. .. I
in some system ~stand-alone" c- .1;~;".~ a single interface card peripheral shelf 15 may be provided without the .~lu.,~ ~ - of a cell switching core l. Alternatively, a multi-shelf access ." ..~,...,..,l such as shown with reference to blocks 3D and 3E
may be provided in stand-alone c~ r;~ with a switching circuit in.
directly into each peripheral shelf.
All external interfaces (e.g. OC-3, video, FDDI, etc.) terminate on interface cards located in twelve universal card slots (UCS) located on each peripheral shelf 3B, 3C and/or 3D, as discussed in greater detail below with reference to Figure 2.
In the multi-shelf access: ~ 3D and 3E, up to ninety-six (96) universal card slots may be provided for each inter-shelf linlc (ISL) 5. F Ih , ~ according to the present invention the number of UCS interface cards sharing an ISL may be made variable depending on the interface card bandwidth. For example, a large number of low-speed UCS cards may be provided in one L ' (eg. 3D), while fewer high-speed UCS cards may be provided in another . L " (eg. 3B). This flexibility provides better utilization of the cell switching core l and provides more control of statistical gain.
Each 800 Mbps ISL S is adapted to transmit ATM cells between the cell 218~87G 11 sviitching core 1 and associated ones of the access shelves 3A, 3B, etc. using either electrical or optical, full duplex, fibre channel (FC~ and FC-I only) interfaces, in a well known manner.
Turning to Figure 2, the cell switching core 1 is shown ' "~, as providing inter-shelf cell switching for respective ones of the access shelves 3A, 3B, etc. The switching core 1 uses an imput cell filtering and output queuing ~ t~ ~ t to implement a cell space switch (i.e. cells can be switched to any output from any input). In the preferred b~ ' t, the switching core 1 can range from 2 to 256 ISL ports per system. Therefore, the maximum switching capacity is 256 ISL/system x 800 Mbps/ISL = 204.8 Cl~/~ The cell switching core 1 i r ' a plurality of dual switching cards (such as lA, lB and lC shown in Figure 16). Each such dual switching card has access to the switching core 1, and provides two output ISLs 5 for connecting up to two peripheral shelves 3A, 3B, etc.
In Figure 2, a r ' "~ peripheral shelf 3C is shown connected to the switching core 1 via respective ISLs 5. As discussed above, the peripheral shelf 3C
twelve universal card slots (UCS) for receiving respective interface cards 21 for ,' _ all interface (ie. between the switching fabric and the outside world via IIO interfacing to optical, coax, or otha physical medium), control and resource functions. For the purpose of describing the present invention, the terms "interface card" and "UCS card" may be used , ' _ ' '~,. Each peripheral shelf, such as the shelf 3C shown in Figure 2, includes two special purpose hub cards (only one hub card 23 being shown for ease of ill~lctr~ti~n), which for!n part of the entire switching fabric. The switching fabric of the prefared: ' " is fully duplicated for ~ , one hub card is provided for each half of the fully duplicated switching fabric. The hub card 23 "i ' and ~ ~ cells from multiple interface cards 21 onto the 800 Mbps intershelf links (ISLs 5) connected to the switching core 1. Each UCS housing an interface card 21 has a 200 Mbps interface to the hub card Z3, designated as an add bus 25. As discussed above, the hub card 23 terminates an ISL 5 from the switching core 1 and drives a further 800 Mbps shared bus on the backplane, this bus being designated as the drop bus 27 .... _ _ _ _ . . .. . . . . . _ _ wo 95/30318 2 1 8 7 8 7 6 12 Pcr/c~ss/0024s from which the UCS cards 21 filter received ATM cells. The hub card 23 also includes a loop-baek circuit 29 which is normally provided for diagnostic purposes.
I~owever, in a stand-alone ~",ri~. ,l;...~ of the access or peripheral shdf 3C, the loop-back 29 can be used for directing the 800 Mbps data which is ' from 5 the add bus 25 back to the 8 )O Mbps drop bus 27.
Ille system has a duplicated ATM switehing fabrie for fault tolerance. The major c~ l~ .. t~ of the switching fabric are the hub cards 23, switching shelf 1, and the ISL cables 5. The interface cards 21 put customer data onto both fabrics.

According to a further possible stand alone ~",r,~ ;.... of the peripheral shelf 3C, the switching core 1 may be effectively i,..-..~ .1 into the peripherAI
shelf itself where two or more such peripheral shelves with internal switch core are conneeted together (such as peripheral shelves 3D and 3E eonnected via ISL SA in15 Figure 1). The number of ports connected to the switehing core 1 can be made fle ~ible (eg. a large number of low bandwidth ports may be added) to fully utilize available bandwidth.
Interfaces which re~uire greater than 200 Mbps of system switching eapacity 20 are interfaced direetly with the switching eore 1 via assoeiated ISLs 5 (e.g. high speed interface 3A in Figure 1).
As discussed in greater detail below, according to the present invention data on each of the dru-. ' 8J0 Mbps links (ie. ISLs 5, drop busses 27, etc.) is 25 assembled as a succession of "Supercells", each comprising an Ordered Set (ie. 32 bit longword aligned data structure for control ;..r.- . ~ ) followed by 128 6û byte ~IU~ ATM cells. The use of these supercells results in ~ ru.w~ud eell delineation and supports a simple protocol for relaying valious types of system level status r In operation, for simplified data flow in the ~r.. l;.. ~.l stand-alone . .. rll;",~;.,.. of the peripheral shdf 3C (i.e. without routing through the switehing WO 95130318 ~ 8 78 ~ PCI~/CA9~/00248 core 1), each UCS or interface card 21 provides the -~r, ' ' line tl .,..,..,.I;.."
performs AAL/ATM layer processing of received data, adds additional routing ;..r~,. ,.. ~;,~,~ to the ATM cell to create a formatted cell header in accordance with the principles of the present invention, and sends the formatted cells to the hub card 23 s over the 200 Mbps add bus 25. As discussed in greater detail below, the formatted cell of the present invention has seven additional overhead bytes pre-pended to the standard 53 byte ATM cell, to form a 60 byte formatted cell.
For 800 Mbps peripheral shelves 3C, the hub card 23 "i,' and the formatted cells from the individual UCS cards 21 onto an 800 Mbps cell stream which is looped back via the ~ ~ ' embedded switching core (not shown), or via the loop-back 29 to all of the UCS slots on the common drop bus 27. For other than 800 Mbps peripheral shelves, the loop-back function may or may not be provided internally on the hub card 23. Each interface card 21 filters the cells from the 800 Mbps drop bus 27 using the routing r " which was added to the cell header, queues the cells, performs AALIATM layer processing on the transmitted data and drives the associated line interfaces via the interface card 21.
For data flow through a larger node which uses switching core 1, the system 2 o operates in an identical manner as discussed above in connection with a small node except that instead of looping back the data to the drop bus 27 through the embedded switching core or loop-back 29 of hub card 23, the 800 Mbps cell stream is encoded within hub card 23 with an 8BlOB code (as per fibre channel FC-I standard) and converted to a 1 Gbaud serial stream which is then sent to the switching core I via 2 5 ISL 5. The cell stream is received by switching core 1 and the cells within the ISL
5 are routed to the proper ISL outputs of switching core 1.
The hub card 23 on the ~ . peripheral shelf (e.g. shelf 3C, etc.), receives the cell stream from the switching core 1 via ISL 5 and in response drives 3 O the 800 Mbps shared drop bus 27 on the backplane of the peripheral shelf. Then, as discussed above in connection with the smaller node i..t .~" ... 1;,~.- each UCShousing an interface card 21 filters the cells from the 800 Mbps drop bus 27 using ~he routing ~ that was added to the cell header, queues the cells, performs AAL/ATM layer processing on the transmitted data and drives the associated line ;nterface via the interface card 21.
The ~ ~l, of add bus 25 and drop bus 27 results in a "star bus"
topology which provides unique advantages over the prior art in the r I ' '-of a high speed, system. It is known that high speed data h is most easily ~ .~ with point-to-point i lines. Therefore, by splitting the add bus 25 into a plurality of point-to-point links in the present invention, significant advances are made over prior art .;o.. ~ t;.a.~al point-to.. ~lhl,u.. L
(e.g. using multi-party bi-directional busses). Such prior art systems suffer from the following problems:
- low impedance and ~ lines due to card loading - difficult line i - high speed busses requiring parallel ~ ;n~\~ that consume significantpower - the effective speed at which the busses can operate is limited by factors suchas arbitration for bus The point-to-point provided by the add bus 25 in the star-bus topology of the present invention overcomes these problems.
In the "drop" direction (i.e. drop bus 27) since all the UCS cards 21 are 25 required to receive all of the incoming data cdls, a I " ' bus 27 is utilized.
Since the bus 27 is L- -~ ; --- -l, the topology of the present invention benefits from simple ~ - Iine i Accordingtothepresentinvention,y~ ~yoverhead ;~.r.-,., ~;- isadded 3 o to the standard 53 byte ATM cedl in order to assist in the routing of the cells through the switching fabric. The cell format of the present invention is used on all links Ibetween various cards of the system. This includes the links from the UCS cards to _ .. ... .. . _ ~ . . ... _ . . . .. .... .... ..... ... .... . ... .. . . .

WO 9S/30318 . PCT/CA95/00248 ~ 2187876 the hub card 23, linL~s to and from the switching core 1, and from the hub card 23 to the UCS cards 21.
As discussed above, in ~rf flrfl~nf~ with the preferred L, ~ seven bytes 5 are pre-pended to the standard 53 byte ATM cell in order to form a 60 byte formatted cell. The additional header ;~r.~ , is used to uniquely address any "port" on any UCS housing an interface card 21 and to identify the priority of the attached ATM
cell. The additional header i"r.- .~ f is also used to support a multi-casting capability where the address field identifies a group of UCS interface ports. Use of the additional header ;.. r.. ~ pre-pended to the standard ArrM cell allows for improved cell routing over prior art ATM-based switching systems. Unused bits inthe header may be used for other control functions (eg. providing signalling '- at the discretion of software).
As discussed in greater detail below, there are two cell types defined by the additional header r '- according to the principles of the present invention, as follows: (I) point-to-point; and (2) point-to "ij Sending cells to a specific card within the system requires that the cells be 20 routed to the drop bus 27 to which the particular UCS interface card 21 is coMected.
The card then must filter the cells destined for it from the remaining cells present on the drop bus 27.
When a cell is addressed to a particular UCS interface card 21, the drop bus 25 27 that the particular card "listens" to is referred to as a "terminal bus~ (i.e. the data on the bus is not routed to a subsequent bus). If, on the other hand, a cell is addressed to a card that is part of the switching fabric, the bus that is "listened" to by that card may be an - bus whose data is routed to other buses. In a~f",~l ~ with the present invention, the definition of the routing of the cell through 30 the fabric is identical in both cases. As discussed in greater detail below with reference to Figure 9, circuitry is provided in each UCS interface card 21 for filtering the cells on the monitored bus in order to recognize correct cells destined for the WO 95/3~318 PCT/CA95/00~48 2~78~6 particular card.
Figure 3 illustrates a formatted ATM cell in - ' with the present invenaon, for , ' ~ roint-to-point ~ The fields pre-pended to 5 the standard ATM cell are defined in Table A below.
It should be noted that for all field definitions throughout this disclosure, bits are assumed to be tr~n~rnrtPd in the order of left to right and top to bottom. In multi-bit fields, the most significant bit is transported first.

TA~T ~ A
eld Name Description MT When this bit is low the cell is considered to be an empty cell. The CRC value is checked to determine if any bit errors occurred, otherwise the cell is discarded without any processing being done.
Pt-Pt Indicates addressing is either for a point-to-roint or for a point-to .. lti~~ , " 1 " = point-to-point;
~o~' = point-to i NCT Newbridge Cell Type. These bits are used by the interface ASIC to determine if the cell is part of tbe nor~nal data stream or if it should be routed to the internal control or RDS queues.
RFU Reserved for Future Use. These bits should be set to ~0" to guarant~e rnmr~ihility with future .' ~ which may use them.
Priority Indicates cell priority. Supports 8 priorities. "000" =
Lowest Priority; " l l l " = Highest Priority.
AAL5 Identifies this cell as being part of an AAL5 frame.
Source Port Indicates the cell's ingress port. Range: 1.. 3. Zero is illegal.
Stage l/Stage 2~Shge 3 These fields each allow the selection of one output out Address of sixteen from a switching shelf, with the capability of having three stages of switching shelf. This per~nits the r-~ of p~rrprtjn~ lly large switching systems.
Card Address This field uniquely identifies a destination element within an ISL.

WO 95130318 ~ ~ 8 ~ g ~ PcTrc~51no248 Egress Connection lnis field is set on ingress on the cell relay cards and Identifier identifies the connection at thc egress point. It is used for ~r.,... I~b address translation and statistics gathering on egress. It permits the ~ - of an identifier which is easier and more ~ ' ' to use when updating statistics than the entire VP/VC field of the ATM address.
Port Used by multi-port interface cards to address a port (from up to sixteen). In cells sent to the switching fabric this field is RFU.
NCC Newbridge C~ Channel. This 4-bitwill provide for ~ ;.. exchange between cdl processing elements in a switch node. r ~ y use may include bits for local switch congestion indication.
5 CRC - 8 Cyclic r ~ ' y Check. Provides error detection for the combined Newbridge and ATM header. The ' used is x'+x2+x'+1.
As indicated in Table A, the card address field is used to select a destination dement within an ISL. One possible definition of this field is shown in Figure ~, Wo 95130318 2~ rl G 18~ PCTlCAs~/00~48 TABLE; B
Fi~ld N~me ~ t'-l~
Rangc # I ne Rar ge number idel)~ifies the typ of eard, ~rtd ~he ran~e o~ location:~ tO which Ihe addrer~s appli~s. It is cncodcf in hcfo,lo~ingfo.~lutt:
O~nO- JC~ ~-c~#l. ntcr'aceA C~.
~ l1 - ~~C ' le ' #2, nter'ace A C #
00. 0 - T~C lC '#3, mer:'ace A C #
~0 . - JC ' . ' lc ' #', ntef. aee A ' C n O QO - ~JC ' lC '#.', Dlcf. aee A C #.
0 ~ -JC' lc '#n, nter'aceA .C#
~:~ O - UC le ' #, ' nterl'acc A . C ~
- JC ..lc #, ntcr'a~e A ':C#
. OUO - UC ~ lc ' # . . meface A C #~
~10 _ TJC ~C '#~, nteface A ' C #_ . ~ 0 - 'JC 'nc ~#~, ntcr'ace A C #' - A'~' ' ub Card, 00 - UC ~clf #1, nterface ASIC #3 01 - UC" .: lclf #2, nterface ASlC 03 : . 0 - UC lelf #3, ntcrface ASIC #3 I - A=_ ~SC Cart s In this format, Ranges 0-7 corr-spond to thc UCS cards in shclves 1-8. Ranges 8-]5 are ightly morc ~ '' t.
Location # 1 ttc Location # identifies a un uc locathm within a range.
It is encodcd in the ~ollowing rmat:
UCS Rsn~es: (Ranges 0~ , 12,13,14) Slot #
Slot # 0-15 identify the pcripheral shelf slots I -16.
HUB R~nges: (Range 11) Shelf # ¦ X/Y ¦
Shelf ~7 identify !he chained shelf numbcrs 1-8.
X~ identifies the fabric with 0 = X, I = Y
DSC RYnges: (Range 15~

¦ RFU ¦ Slage# ¦ X/Y ¦
~FU, set - 0 until defincd.
~tage IK}2 identifies th~ swi~ching stge ~ 3, with (slagc ~3 is an RFU) XN identifies the fabric with O X, I=Y.

WO 9S/30318 2 ~ 8 7 8 ~ 6 PCT/CA95100248 T. .. ~ cells whieh are part of a point-t~multipoint connection requires that t~te cell be routed to every drop bus 27 which has a card that is part of the multi-c2st group. The cell must also contain a multi-c2st identifier that each c2rd ehecks to determine if the c2rd is part of the ~.c ~ ' `A multi-cast group 5 for the cell. This group can tnen be used to determine which ports of the UCS
c2rds 2re to use the cell (ie. which interf2ce c2rds 21 are to receive the data).
The cell format of a point-to ' ~ - cell is given in Figure ~. The field definitions are provided in Table D below.

i ~eld N~me D
When Ihis bit is low the celiis considered to be an emply cell. The CRC value is checked to determine if any bi~
errurs occurred otherwise the cell is discarded without 2ny ~ocessing being done.
Pt-Pt ndicales addressing is either for a point-t~point or for a point-to '~i' ' connection. "I ' = point-to-point; "O`' - point-lo-multipoint.
N( l Newbndge Cell l`ype. l hese bits are used by the interface ASIC lo determine if the ccll is part of Ihe norrr~l dala stream or if it should be routed to the internal control or RDS queues.
R~U Reserved for Future Use. These bits should be set lO "O"
to guarantee ~ , wilh futu~ ' which may use them.
Priority Indicates cell priority. Suppons 8 priorities. "000" =
Lowest Priodty; " ~ l l" = Highest Priority.
RPU Reserved for Puture Usc. These bits should ee sct to "O"
to u3rantee; " "'~.~ wilh fu~ure i ' ' w~ clmayusethemwilch Shelf Output ~ilmap A I~ llicast cell may be rouled to multiple drop busses.
Th s s " ' ' by bil mappin-~ the OUlpUt ports of the sw tc~ing sheif thsl the cell is l~ l k-.
Multicast Gro~ p CoMeclion l n s field is set on ingress on th e rclay ard and ]dent fler 'dentifies a system wide uni4ue ~ u .icast ' '~oup.
AA_S iendfies Ihis cell as i~eing palt a AAL fr3!ne.
Z Sourc~ Pon '~dicates the cell's ingress pon. ~a~ge: .. 3. 7.ero is Icf,al.
NCC ~ewbddger~ ' ' Ch3nlul. Irlis4-bitwill provide for infonnation exchange between cell processing elements in a switch node. Preliminary use may include bits for local switeh congestion indication.
CRC - 8 Cyclic R~ y Check. Provides error detection for the combined Newbridge and ATM header. The polynomial used is x8+x2+xl+1.

WO 95130318 PCTICA9510a248 .
21~876 20 The cell header describes a number of diffetFent cell types including data cells, control cells and RDS cells. This allows control and RDS to be 5 carried in-band within the data switching fabric. Many systems use an out-of-band control channel which restricts the control card to a specific location in the system.
Allowing the control and RDS to be carried in-band within the data switching fabric allows scalability to very high ~ 'w;dLl.~ and increases reliability.
In-band - means that no special hardware or software is required at the 10 local site and debugging can be done remotely.
Turning now to Figure 6, the functional blocks of a ,r~ l;v~ UCS
interface card 21 are illustrated. The illustrative example shown in Figure 6 is an OC-3/STM-1 interface card for connection to a peripheral shelf 3B, 3C, 3D or 3E
15 (Figure 1). Interface cards which are ~ r ' ' for , a high speed interface or an 800 Mbps interface may be devised using similar functional elements as shown in Figure 6.
As discussed above, the basic function of the OC3/STM-1 UCS iulterface card 20 21 is to transport ATM cell data between the switching fabric and the SONET/SDH
network link. The blocks required to perform this function may be identified as follows:
(1) Control/status block 71;
(2) S,~.. ,l.lu.u~Liùn block 73;
(3) Backplane interface block 75;

(4) ATM block 76;

(5) SONEI/STM-1 block 77; and

(6) Transport medium and interface block 78.
The control/status block 71 provides ~o~ of interface functions and establishes node control via the backplane interface block 75.

21 8 7~ 76 21 The D,~ h ~ "~ block 73 accepts and/or generates a system Dy... I.lu..i~ reference, as discussed in greater detail below. This block generates timing signals required for all functional blocks of the UCS card 21, including tne provision of timing signals whereby the SONET/STM-1 meets 5 ~ ~ ~ ' jitter and accuracy , if a S~ Unit (SU) is located on the UCS card 21.
The backplane interface block 75 processes the specially formatted ATM cells (ie. ATM cells having àdditional pre-pended bytes) that are transmitted to and from 10 the switching fabric, and provides data integrity checking, ~ ~ily checking and conversion of cells between the specially formatted ATM cells and standard ATM
cells. The functional ~ , . n- ~t` for this block are discussed in greater detail below with reference to Figure 9.
The ATM block 76 processes the ATM cells that pass between the backplane interface block 75 and the SONET/STM-1 block 77, including VPVVCl[ mapping, usage parameter control (UPC) policing, and per VPVVCI statistics gathering. ATMblock 76 comprises an ingress ATM logic block 76C, an egress ATM logic bloclc 76A, an ingress UPC 76B and ingress l~ I context memory interface 76D.

The ingress ATM logic block 76C or Ingress Cell Controller (~l.lci~idt~l as ICC) provides the following ATM layer r ~ y, (1) VPI/VCI address ~ . (2) cell counters, (3) OAM control cell processing, (4) OAM cell 25 extraction, and (5) ~le~.ldlll~ of the seven header octets to the ATM cell (Figures 3 and 4). A 64Kx16 SRAM 1702 provides the ICC with per connection OAM
J and VPVVCI n, tables.
There is a global bit located in the ICC 76C which is ~ cd upon 3 0 to signal an internal address . . block whether the link is UNI
or NNI. When the link is UNI, an 8bit VPI and 16bit VCI is ~ to 12bits.
When the link is NNI, a 12bit VPI and 16bit VCI is s~ to 12bits (referred , , WO 95/30318 - PCTICA9~i/00248 218787~ ~

to herein as ICI).
The 12bit resultant ICI allows the OC-3 Card to support up to 4~ of using any VPI and a VCI within the range of 0 to 4095.
When a cell is receiYed, the VPI is used to index a VP Table. The result is a 16 bit word which determines if this VPI has been enabled and whether it's a 'VPC or VCC. If the coMection is VPC, the VP Table entry also contains a 12 bit ICI. If the coMection is VCC, the VP Table contains a VC Table pointer and 10 a VCI Masl~. The VC Table pointer points to one of 17 2K VC Sub Tables. The ~CI Mask is used to determine how many of the VCI bits will be used to index the VC Sub Table. This mask must be either 11 or 12. The OC-3 doesn't support any other mask selections. The unused VCI bits are compared to zero. If ~hey contain non-zero values, the cell is considered invalid and the a~
15 actions occur. Otherwise, the VC Sub Table entry contains an ICI for the VC
Once ICI has been generated, it is used to point into the ICC's context memory 76D. A bit is checked to verify validity of the - If it isn't a 20 valid: ICI ~s ignored, the ingress UPC 76B is advised that it has an invalid cell and the connection's VPI/VCI values are stored mto the ICC
memory's Invalid Table. If the connection is enabled, ICI is passed to the ingress UPC 76B.
The memory accessed by ingress UPC 76B is the 64Kx32 memory 76F
residing on the ingress UPC's host port. This memory provides the ingress UPC
with; UPC ;..r..,. ~ .., per connection statistics, NATM header octets (ie. internal Newbridge ATM cell formats in a~ rtl~n~- with Tables A and D), and VPVVCI
translation bytes.
The Context Table within memory 76F contains 4K data structures. Each data structure represents ;, r~ for a VP or VC switching, The .. _ . . . .. . _ . .

WO 95130318 2'~ & 78 76 PCT/C~95/01)248 UPC table contains 1.5x41K (6K) data structures which each represent the necessary: r.... ~ ;.... for a bucket.
NATM header registers are provided as memory locations in 76F which 5 contain the seven octets ~ the NATM header. These fields are prepended to the beginning of the cell header for use throughout the switching fabric. Included within these fields are port addresses, ECI (Egress ~t-nn~tinn Identifier), MGI (Multicast Group Identifier) etc.
The SONET (S~ UllU~la Optical Network)/STM-I block 77 adapts the ATM cells received from and i ' to the OC-3/STM-I physical layer, and provides overhead processing for the section, line and path layers. It also provides line (egress) and diagnostic (ingress) lûop back capability. Mûre k~ll~ly~ the SONETISTM-I interface block 77 provides both an 8-bit 19.44Mhz and a serial 155Mhz access to the Transport Medium Interface 78 and 8-bit 25Mhz access to the ATM block 76. Multiple serial interfaces are also provided for an optional NN~ module.
The interface block 77 also provides (either directly or via the NNI
20 module) full access to SONl~T/STM-I framing ;..r..,.. - ;.... and provides four-deep receive and transmit FIFOs (not shown) for the ATM layer interface 76. It also delineates ATM cells and provides HEC checking and correctiûn.
The transport medium interface 78 provides optical (or coax) interfaces, 25 clock recovery and data timing between an optical medium 79 such as fibre optic cable (or coax medium 79A). The transport medium interface 78 also provides dectro-optical, ~a;U..~ required to pass the ATM cells to and from the optical OC-3/STM-I link. The functional , for transport medium interface block 78 are discussed in greater detail below.
For signal flow in the egress direction, the backplane interface block 75 monitors the type of formatted ATM cells, and .' between data, RDS, WO 95/30318 218 7 8 7 6 PCT/CA95/~0~48 control and empty oells. The cell type is ~ rn i~ by its NCT and MT bits (see Figures 3 and 4).
Data cells are passed by the backplane interface 75 to the ATM block 76.
5 The destination address of each active cell is checked before the cell is passed to the ATM block. The egress ATM logic 76A strips off the seYen formatted ATM
cell header octets from each active oell before passing it to the interfaoe 77. The seven formatted ATM cell header octets are generated and added to each cell reoeived in the ingress direction by ingress ATM logic 76C, before i to 10~he switching fabric, as discussed in greater detail below.
The RDS and control oells ~e not transmitted to the ATM block 76.
Instead, these cells are stored for use by the control/status block 71. In the ;ngress direction, RDS and control oells are created by the control processor 71A
15 and inserted into the ingress ATM oell stream for i through the switching fabric.
Empty oells passing in the egress direction through backplane interface 75 arc discarded. In the ingress direction, a nibble is added to the cell to indicate the 20 start of a oell. If there are no oells to be transmitted to the switching fabric, the link remains idle.
In the egress direction, multicast oells are received and used to look up an enable bit in a multi-cast look-up table (discussed in greater below with reference 25 to Figure 10). If a match occurs, the cell is accepted; otherwise, it is discarded.
r.,.LI..,ll.lulc, point-to-point cells in the egress direction are received and compared to a pair of filter registers (discussed in greater detail below with referenoe to Figures 12 and 13). An exact match is required for the cells to be accepted.
Otherwise, the oells are discarded.
Cells passing in the egress direction are placed in one of four priority queues. CLP discard can be enabled and is performed when a ~

WO 95130318 ~ 8 7 fi PCT/CA95100248 discard threshold is matched or exceeded. These queues also provide forward congestion r- ~ -" if enabled through the PTI bit field of the ATM header.
The ASIC .... u.~ J into backplane interface 75 (discussed in greater detail below with reference to Figure 9) provides statistics for the number of cells 5 arriving (16 bit); the number of cells discarded CLP=0 (16 bit); the number ofcells discarded with CLP=I (16 bit) and the number of cells arriving congested (16 bit). Status flags are also available for full and empty queues; discard state and congested state.
lo The backplane interface 75 also provides a variety of features.
Firstly, by def~ning invalid point-to-point filters for the cell , the control processor 71A is capable of detecting incorrect destination addresses ofcells passing through the backplane interface 75 in the egress direction. Also, a loop back function may be provided to the loop ingress path entering the 15 backplane interface block 75 to the egress data path exiting the backplane block.
This provides a means to test the ATM block 76 and SONET/STM-I block 77 dudng power up ~ ns~;~5 It is necessary for the control/statu~ 1 u~,w~ul 71A to access the 20 memory 1702 in order to initialize and "dp down" - Instead of using a dual port memory: ' the ICC 76C directly controls the memory.
Whenever the l~ U~lU~ aaUl 71A requires access to the memory, it tells the ICC
what it wants to do, and the ICC execut^w the necessary ~ on behalf of the u~ ~. 71A. This way the ICC 76C knows when it isn't using the 25 memory dudng a cell time and can allot that time for the -r interface 1703.
In addition, the backplane interface 75 is capable of declaring certain alarm 30 conditions. As discussed above, redundancy is provided by means of duplicateddrop busses in each perdpheral shelf 3A, 3C, etc. Each of the two drop busses provides a loss of clock indicator for the egress cells coming from the switching , fabric. A hardware indicator is active when no transition has been detected on the interface clock for 140 ' This time is derived from 14 clock cycles of the C 100 M clock utilized by the ASIC discussed below with reference to Figure 9. The UCS card software monitors ATM receive clock failures for the redundant ATM switch fabrics. The UCS card software provides an alarm indication when this failure is alarmed on the active ATM interface.
The UCS card hardware also monitors the level of the four queues for the ~gress cells received from the switching fabric. In the event that the buffer fills, the event is counted and aggregated as a statistic value.
According to the preferred ~ " t, ATM cell processing is performed by means of a pair of application specific integrated circuits (ASlCs) within the switching core 1, hub cards 23 and UCS cards housing interface cards 21. The first ASIC is shown in Figure 7 for ~ a dual purpose switching function.
In one ~ ti~n, the circuit of Figure 7 is used in hub cards 23 of the access shelves 3B, etc., for '~' 3 the 20n Mbps data on add bus 25 into a single 800 Mbps cell stream for application to inter-shelf links 5. In the second a~lir~ti~n the circuit of Figure 7 is utilized in the switching core I to filter (i.e.
2 0 switch) a p~ur of 800 Mbps input cell streams into a single 800 Mbps outputstream. The 8'`0 Mhps output stream can then be shared by multiple additional ASICs of the form shown in Figure 7 to provide filtering (i.e. switching) of thesame 800 Mbps output link from multiple input links in the switching fabric.
In the "multiplex mode" of operation, six input processors 81 receive respective 200 Mbps signal streams from respective UCS cards housing interface cir_uits 21. Thus, by using two of the switching and, ~ g circuits of Figure 7, the desired ' ' '.~1 of the hub card 23 may be ' ' for _ twelve 200 Mbps cell streams carried by the add bus 25 into a single 3 o shared 800 Mbps output stream. Each 200 Mbps input data stream is processedvia a respective processor 81 for cell delineation and for CRC checking. The addbus links 25 from the UCS cards to the hub card 23 consist of a data nibble (i.e. 4 WO 95130318 PCTrCA95/00248 ~7876 27 bits ) and clock signal only, so that cell delineation may be performed based on a simple algorithm which recognizes cells being preceded by a unique start-of-cellnibble, or other suitable technique.
Each of the format ~t~l '~ ' 83 gathers the three 200 Mbps streams output from processor 81 and converts them to a single 800 Mbps input stream for further processing by a cell queuing core 85. The cell queuing core 85 is discussed in greater detail below with reference to Figure 8. A pair of 86 co~li-~l~ select one of either the 800 Mbps input (switching 0 mode) or the three 200 Mbps cell streams output from forlnat co.,~..t~/ '~ ' 83 (multiplex mode) for input to the cell queuing core 85.
Thus, the system provides sufficient flexibility to have one of the 800 Mbps inputs to the cell queuing core 85 configured as three 200 Mbps inputs (ie. ~
mode) while tne other 800 Mbps input is configured as a direct 8vO Mbps input 15 ~le. switch mode).
Slot monitor FIFO 87 provides a ~ v~ r ~ interface to "monitor" a specific 200 Mbps input or a specific 800 Mbps input from the . ~ 86.
The circuit of Figure 7 captures a cell from the a~ ' ' input link when so 20 directed via the ~ -o~-o~OO.,. port. The . Ul,cooUI then directly reads the full 6û byte formatted ATM cell from FIFO 87.
The cell queuing core 85 is shown in greater detail with reference to Figure 8: , _ 800 Mbps processing blocks 91 which perform clock detection, link ~r.. ,.' -~ , CRC checking and cell filtering functions. When an 800 Mbps input stream to the cell queuing core 85 is sourced from three 200 Mbps inputs (ie.
multiplex mode) the cell filtering function of processors 91 is typically disabled.
This allows all cells in the input streams to be queued. As per the 200 Mbps inputs, each 800 Mbps input can be enabled or disabled from having their 3 o respective cells enter queue memory 93.
Memory manager 95 controls four cell queues within memory 93, for WO 95/30318 ~ 8 ~ 6 2B PCT/CA95/00248 providing a total of 256 cells of queuing space which can be flexibly allocated bet veen the four queues. Memory manag~ 95 operates on the data contained within the four queues to process each cell in accordance with all aspects of the ArrM cell header, including CLP discard and PrI congestion nntifif~rinn An arbitration control 97 provides; ~f ~ - on the current state of the cell queues to an extemal arbiter (not shown). When multiple circuits share the same 8~0 Mbps output link, the external arbiter is required to decide which circuit source is the next cell and at which priority. The arbitration control 97 provides 10 the extemal arbiter with all of the necessary; '~ required to implement any queue service algorithm which can be d~ .. ' ' 3 and is ~ , ' ' at any time.
The output formatter 98 creates a fommatted 800 Mbps link (as well as 15 inserting the ~ r ' ' priority cell when so instructed by the extemal arbiter), in the fomm of a "supercell", as discussed in greater detail below.
Insertion FIFO 99 is provided to allow control and real-time d~. IU~II....L
system (RDS) cells to be i ' onto the 800 Mbps output link. Details of 20 the RDS r " 1 ~ are provided below. As discussed in greater detail below, the interface circuit of Figure 9 provides a standard RDS and control interface to the local IIII~,IU~JIU~Ul. The circuit of Figure 7 provides an interface to the circuit of Figure 9 to transmit these controVRDS cells onto the 800 Mbps output port. The 800 Mbps input processors 91 contain a plurality of registers which are 25 used for cell filtering. Specifically, point-to-point and point-to-multipoint cell filtering is _ ~" ' ' using internal ~mask" and "value" registers against which input values may be compared and must be matched (or alternatively masked) in order for a point-to-point or point-to '~i, cell to enter an internal queue from the 800 Mbps interface. In this regard, all cell filtering in the system of the 30 present invention is conducted via pattern matching.
Before turning to Figure 9, a brief description is provided herein of the _ _ _ _ _ _ RDS (Real-Time D~ System) r '~ 1 of the ATM switching system according to the present invention.
RDS is used ~tc~ l.y in the system according to the present invention, to develop and debug software. Debugging can take place in a range of from a d~ Iab to a customer site where it can be used on live equipment without impacting service or customer data. As discussed below, the RDS function of the present invention operates in ar. event mode and in a command mode.

RDS events are embedded in the actual software at d. ~. Io~ L time and in most cases are not ' , '.~ removed for two reasons: (I) events can assist in tracing subsequent problems, (2) taking them out would affect the real time execution of code, which may have real functional effects, even though the code 15 has been designed so as to not be sensitive to execution speed.
An RDS event is simply a set of writes to an RDS event port, embedded in the software at significant software interfaces and points of interest. The data that is written to the port includes an event identifier and a variable length sequence of 2 0 data bytes that define what software event is occurring. It is similar in concept to putting a "print" statement within the software to indicate ~hat this portion of code is executing and using the print data to indicate exactly what is happening.
In the ATM switching system, RDS events are generated by nearly all of 25 the processors in the system and the event data is placed on the ATM switching fabric along with control messaging and customer data. To reduce the amount of bandwidth consumed on the ATM switching fabric, the ASIC (Figure 9) contains a hardware filter that can discard RDS events based on the event identifier. In normal operation of the ATM switching system according to the present invention,3 0 all of the events generated by all the processors in the system are discarded using the hardware filter of the ASIC in Figure 9.

21g~876 30 The events can be enabled onto the switching fabric by changing the state of these hardware filters. This can be done selectively for each interface ASIC
(Figure 9) in the system and for each of the 256 events that the ASIC supports.
This allows someone with knowledge of the RDS events in the system to enable 5 selective events to aid in diagnosis of problems.
RDS events can be displayed on a VTlO0 terminal or a ~.JlLL~tiu...
Generally an additional card is installed into the system for filtering the RDS
events off the switching fabric and formatting them for display on the VTlO0 or WUl~ iUI~. The ATM cells that carry the RDS event data indicate the source address and using this knowledge, the event identifier and the event data, text can be formatted and displayed on the VTlO0 terminal or ~.Jl~ iUII that c~
to the event which has occurred in the software. The control card of the ATM
switching system is also capabb of filtering the RDS event cells and formatting 15 &em for display. This allows remote debugging of a live system since access to &is control card is available across the network.
Since the events are left in the code, the priorities of code design are to keep the size of the event code to a minimum, to keep the processing load of event 20 generation to a minimum, and to ensure that the proper events are within the code to allow the diagnosis of problems and visibility into the operation of the system.
As discussed above with reference to Figures 3 and 4, the contents of the header field of the cell are completely l., . ", ~ F including the ATM header 2s VCI/VPI fields. The CRC header protection field is calculated and inserted into the cell header lly, and a two byte field is provided for a RDS source address to be used by the receiving end to identify the source of the cell. As discussed in greater detail below, an address mapped set of registers that store the fields of the cell header are provided in the interface ASIC of Figure 9. This 30 allows ~ n.l;li~ ~;...~c to be made to portions of the header field without re-writing the whole header each time a small change is needed, (e.g. priority changes).
With control over the ATM VCI/VPI fields, event cells can be routed directly out . = . _ . _ . _ .. _ . _ . . . . .

2'~Q~ ~
WO 95130318 ~L U ~ 8, 6 PCT/CA95100248 .

of the switching system as true ATM cells to a destination outside the node, without having to be relayed by the control complex or an RDS card. This featureallows event cells to be transmitted to a remote debug location directly, assuming that a connection to the network is available. However, it should be noted that the 5 pre-pended bytes of Figures 3 and 4 (including the NCT bits) are lost when the cell exits the node, but this ~ is not usually needed if the receiving entity is expecting only RDS event cells.
In command mode, RDS is used to actively debug processors in the system by allowing source and assembly level debugging as well as memory read and write operations. According to this mode of operation, a host generates one or more RDS command cells, each comprising a command identifier and a variable length identifier for defining the command, to a target system. The target system responds by returning to the host an RDS event cell containing the results. The commands are very simple (eg. read memory at a giwn address, write memory to a given address with provided data, identify target processor type, return values of target processor registers, etc.) Using these simple command operations, the host system is capable of I ~ an adv~nced fi-r~rhnn~lity such as source level ~leb~ine assembly level debugging, breakpoint insertion and stack hacing, etc.
When an RDS command cell is filtered off of the backplane by an interface ASIC (ie. the ASIC shown in Figure 9), it queues the cell and generates a high priority ' ' interrupt to the target processor on the associated card. The use of a non-maskable interrupt allows the RDS system in the command mode to reliably interrupt the target processor so that other interrupt handlers on the card can even be debugged using the RDS.
Since both RDS command and RDS event cells conform to standard ATM
cell format in: ' with the present invention, these cells can be hansmitted 3 o across an ATM net vork so that an RDS host processor can remotely debug a target processor by operating in a remote mode. The ingress interface circuitry (Figure 6) of the system containing the target processor causes the cell type (NCI~
, to be set to RDS Command for RDS comrnand cells arriving on the VP/VC
(Figure 6).
Turning now to Figure 9, a functional block diagram is provided of the 5 interface ASIC which performs ATM backplane functions required for any card tointerface with the switchirlg fabric. As such, the circuit of Figure 9 is intended for any interface, hub or switchirlg card that transmits and receives ATM cells through the system, such as the UCS interface card 21 discussed above with reference to Figure 6.

In order to send cells into the switching fabric, the circuit of Figure 9 provides a receive link interface 100 irl the fomn of an extemally timed irlterface for formatted ATM cells to be i ' on the add bus 25. This receive link irlterface 100 operates at a maximum of 400 Mbps, although the maximum add bus 15 late is 200 Mbps, as discussed above.
The completely formatted ATM cells received from a UCS (or other) card via receive link 100, are applied to the add bus 25 via add bus interface/headerprotector 101 along with an inserted CRC-8 byte in the ATM EIEC fidd. As 2 o discussed above with reference to Figure 6, the UCS card assembla completelyformatted cells using the header fields shown in Figures 3 and 4, except for theCRC-8 byte. The CRC-8 byte covers the seven octet (ie. byte) overhead as wdl ~s the four remaining octets of the standaT~ ATM header.
2 5 Control cells and RDS cdls can be applied to the add bus 25 through FlFOs 102 and 104 which are accessible through a , interface 106.
The circuit of Figure 9 provides a separate interface for each of the redundant drop buses 27. For each drop bus 27, the circuit monitors for a loss of 3 o clock and for CRC errors on all cells, via drop bus fraTning/CRC check circuits 108. The signals output from circuits 108 are, ~ l ~ at 110 and applied to a receive cdl filter 112.

WO 95130318 2 ~ ~ 7 g ~ 6 PCT/CA9S/00248 . ~
The received cells from the active fabric are then filtered via receive cell filter 112 to determine which cells are addressed to the associated interface circuit 21. ControllRDS cells and user data cells are filtered using the predefined Card5 Address field (i.e. the fourth byte in the point-to-point cell format of Figure 3) to facilitate irlterface card ' - ' y, as discussed in greater detail below. Multi-cast cells are verified against entries in an external, 64K ~nnnP~ion, multi-cast look-up table 116, also discussed in greater detail below.
Turning to Figure 10, the weive cell filtering process executed by filter 112, is shown in detail. Upon weipt of a formatted ATM cell (step 124), empty cells are identified and discarded (step 126). T~l.on~ifir~inn of empty cells is, " ' ' by checking the MT bit in the first octet of the formatted ATM
header. Next, the Pt-Pt bit is queried to determine whether the ATM cell is formatted for point-to-point or point-to-multipoint addressing (step 128). Address filtering is then split into multi-cast and point-to-point portions of Figure 10.
For multi-cast cells, the Multi-cast Group Identifier field is used to look up an enable bit in a multi-cast look-up table (MCLT) stored within an external RAM116, discussed in greater detail below. If a match occurs (step 130), the cell is accepted. Otherwise, the cell is discarded (step 127). Accepted cells are then sorted according to the Newbridge Cell Type (NCT) field in the header (step 132).
Turning briefly to Figure 11 in ,~...;, .. I;n.l with Table E bdow, the multi-5 cast cell sorting step 132 is shown in greater detail.TABLE E
N~;l Cell Type 00 User data -01 Control RDS Command 11 RDS Event Upon receipt of a multi-cast cell (step 134), the NCT bits are analyzed to ~ 876 identify an RDS Command, User Data, and Control or RDS Event (step 136). In response, sorting is continued on the basis of the cell being identified as either an RDS Cell (step 138), a Control Cell (step 140) or a User Data Cell (step 142).
Retuming to Figure 10, the identified RDS Cells, Control Cells and User Data Cells are then accepted by the filter 112, as ~ t~l by steps 144, 146 and 148.
For point-to-point cells, the Card Address field of the expanded ATM
header is compared against the contents of two intemal filter registers, hereafter referred to as F1 and F2. An exact match is required against tlle filter register contents before a cell is deemed to have passed the filter function. Cells which do not match F1 or F2 are discarded (steps 150, 152 and 127).
Control cells can be required to match F1, F2, or either F1 or F2 before being accepted. User Data Cells pass through an identical stage. This allows theControl Cells to be filtered off of one address, for example, the physical card address, and the User Data Cells to be filtered off of other addresses, for exarnple, the physical card address of the redundant card. This also allows the User Data 2 0 Cells (andlor the Control Cells) to be filtered off of either F1 or F2. This permits cells addressed to either card of a redundant pair to be accepted by both. RDS
Cells are accepted only of the match F1.
Details of the sorting and filtering procedure for F1 and F2 matched point-to-point cells are shown in Figures 12 and 13, ~
Once a point-to-point cell has matched Fl (step 150) it is then sorted by the expanded ATM header ' (step 154). With reference to Figure 12, upon receipt of the point-to-point (PP) cell (step 156), the Newbridge Cell Type is identified using the criteria set forth in Table E, above (step 158). RDS
Command Cells are accepted (step 160). Control Cells and RDS Event Cells are accepted if the Control Filter Select field (CFS[1:0]) in an internal filter select _ _ ~ , ,,,,, , , , , _ , , ,,,, .,, .,,, , .. _, .,, . .. , . = . , _ .

register of filter 112 is ~.u~;-~.. ~ to accept Fl passed cells. The CPS bit field is shown in Table F, below. Control and RDS Events cells will therefore be accepted if the CFS bit field is "10" or "11" (steps 162 and 164).
~!CAB,ILE p 0) Cell Filter Selected 00 Undefined 01 Filter 2 Filter 1 o 11 Filter 1 or Filter 2 User Data Cells are accepted if the User Filter Select field (UFStl:O]) in the Filter Select Register is ~ ' to accept Fl passed cells (steps 166 and 168). The UFS bit field is shown below in Table G. User Data Cells will 15 therefore be accepted if the UFS bit field is "10" or "11~. If either a Control Cell or a User Data Cell fails to pass either Fl or Fl+F2, then the cell is discarded (step 170).
T~BLE G

UFS(1:0) Cell Filter Selected 00 Undefined 01 Filter 2 Filter 1 11 Filter 1 or Filter 2 Once a point-to-point (PP) cell has matched F2 (step 152), it is then sorted by the expanded ATM header r '- (step 171). With reference to Figure 13, upon receipt of the point-to-point (PP) cell (step 172), the Newbridge Cell Type is identified using the criteria set forth in Table E, above (step 174).
- RDS command cells are discarded (step 176). Control Cells and RDS Event Cells are accepted if the Control Filter Select f~eld (CFS[1:0]) in the intemal filter select register of filter 112 is ~ to accept F2 passed cells. The CFS bit field is shown in Table F, above. Control and RDS Events cells will therefore beaccepted if the CFS bit field is "01" or "11" (steps 178 and 180).
. _, . _, , . ,, . _ _ _ ,,,, ., ,, ,, , _ , WO 9~/30318 PCT/CA95100248 2~87876 User Data Cells are accepted if the User Filter Select field (UFS[l:0]) in ~he Filter Select Register is I " ' to accept F2 passed cells (steps 182 and 184). The UFS bit fidd is shown below in Tablë G, above. User Data Cells will therefore be accepted if the UFS bit field is "01" or "11". If eit-h-er a Control Cell or a User Data Cell fails to pass either F2 or Fl +F2, then the cell is discarded (step 176).
The interface ASIC of Figure 9 stores multicast lookup tables in the same e~ternal RAM 116 that is used for queue memory. The first 2Kx32 block of memory, from address 0 to 800 hex, is reserved for this purpose. The lookup tables are used when a multicast cell arrives, to determine if the multicast group is destined for the particular card. To ~rc~mrlich this, the 16-bit Multicast GroupIdentifier in the expanded ATM header of the cell is used to address a single bit of the multicast block of external memory. The 16-bit identifier is translated into an 11-bit address to access the 2K block of external memory, and a ~-bit identifier to select which bit of the 32-bit wide data word to choose. This bit, a yes/no indicator of the validiq of the multicast cell to this ASIC, is used when processing incoming cells. A -o" in the memory lo~ation indicates that the multicast cell is valid, and a "I" indicates that the multicast cell is inva',id. When no external RAM
116 is used (which may occur in bypass mode), the data pins of the external RAM
controller 118 may be tied to a logic high (eg. "1") level, so th-at all multicast cells outside the internal lookup range will be discarded. Alternatively, the data pins may be wired to present a logic low (ie. "0") value when a multicast "read" is ~ ' i, so that all cells are accepted.
An intemal lookup feature is supplied for the use of an interface ASIC without external RAM 116. The uppermost 32 bits of the external memory multicast block are ~ , mapped to an internal 32-bit memory. This enables a subsd of the mu'lticast ~p~l~i1i*Pe for cards t-h-at have no extemal RAM. User access of the 32-bit 3 o internal f~eld is ~ q~ , it is accessed through the ll~lU~llU~,~,it tVl as if it were in external RAM. The 32-bits of external RAM are ~t~ mapped over.

WO 95130318 218 7 g 7 6 PCTICA95/00248 Receive cells which have been filtered by Receive Cell Filter 112 are then sent to the designated receive queues via queue manager 114. User data cells arequeued in external memory 116, through a 1.5 Gbps memory interface 118. The queue manager 114 of the preferred ~ L- " supports up to 4096 cdls of 5 external storage. RDS command cells are sent to the RDS cell FlFOs 104 for access through the processor port 106. Control oells and RDS event cells are sent to the internal sixteen cdl FIFO 102 for access through the processor port 106.
The operation and flow of RDS command cells, control cells and RDS event cells discussed in greater detail below.

Receive queuing to transmit link interface 120 can be bypassed (i.e. queue manager 114 can be disabled for receive cells). This allows the circui~ of Figure 9 to function as a receive cell filter for an external cell queuing device. However, the RDS and control cells are ' -' sent to the internal FlFOs 102 and 104, if so enabled.
Finally, the receive cells are sent out the transmit link interface 120, under control from an external clock (IXLINKCLK).
The circuit of Figure 9 services the priority "3" queue via queue manager 114 if it contains a cdl, and then the priority "2" queue and so on down to priority "0". However, this feature may be over-ridden via the transmit link arbitration port 122. This port provides an indication of a cell arrival, with the cell priority, to the ~ exkrnal arbikr (not shown). In return, the external arbiter can force the circuit of Figure 9 to service a given priority queue for the next cell, regardless of whether a higher priority queue is currently non-empty.
The 800 Mbps Inter-Shelf Link (ISL 5) is the common mechanism for 3 0 connecting all component shelves together in the syskm of the present invention.
The ISL is a high-speed serial link which uses the lower layers of the Fiber Channel ~ ; - to transfer digital signals between access shelves 3A, 3B, .

2~8~876 38 etc., in a multi-shelf access A IAIIC,. ..1. ..1, and bet~ween switching core l and the access shelves 3A, 38, etc. As discuss~d above, each hub card 23 generates u~ ~.y "supercells" for i along the ISLs 5 and drop bus 27 using Fibre Channel technology. Specifically, the output formatter 98 (Figure 8) of the 5 switching ASIC cell queuing core 85 (Figure 7), generates supercells in accordance with the concept of an Ordered Set, as discussed in greater detail below. A ~ v~ ISL 5 is shown in Figure 14 comprising a high speed parallel to serial converter ~AIX 151), ~ ;-- circuitry 153, ~
155, physical transport media (eg. shielded pair copper wires or optical fiber), receiver coupling 156, i 157, and a high speed serial to parallel converter (RX 158). The 8BllûB code requires a 1 Gbaud line rate in order to support the 800 Mbps data rate on the link. The physical transport media for theFiber Channel interface can be either electrical or optical.
One of the features of the 8B/lOB encûding scheme is the ability to special command characters over the serial link. The K28.5 code is a ~ uly special command character in that it is used by the receiver 158 to establish byte and word ~ ' Additionally the K28.5 character is used within the system of the present invention for cell delineation and optionally for 20 the transport of the 8 Khz system ~~ signal, as discussed in greater detail below.
The Fiber Chanrlel ~ introduces the concept of an Ordered Set.
An Ordered Set (OS) is a four byte grouping, composed of the K28.5 character 25 and three additional data bytes. Ordered Sets can be sent over the ISL 5 by asserting a special signal on the Fiber Chalmel transmit device 151, and their presence is detected at the receiver 158 by the assertion of a OS indication signal.
An ordered set is defined as shown in Table H.

Bit 31 - I Bit 23 - I Bit 15 - I Bit 7 -Bit 24 ¦ Bit 16 ¦ Bit 8 ¦ Bit 0 WO 95130318 21 8 7 g 7 6: PCT/C~95100248 OS Type 11~8.5 I Drive & Scan I RFU
Bitfidd ¦ Special Character ¦Byte (SOS only) ¦ l The second byte is always the K28.5 special character. The first byte is a field of 8 bits for encoding the various OS types. Since an OS may be considered to signal an event or status condition, each condition is assigned one bit in the field (as shown in Table I) which is set to indicate the relevant event or status condition, allowing a single OS to encode numerous types of OS "events". These conditions are not necessarily mutually exclusive - for instance, an OS with a first byte equal to 05H
would indicate both an SOS and an STOS.
Bits 7-3 Bit 2 Bit 1 Bit 0 Reserved ForFuture Use ~ystem Bxtracted ~upercell Iiming ~iming O~
Q~ ~
The Drive & Scan fidd is only used if the OS Type Bitrleld's SOS bit is20 asserted. Otherwise, it is treated as a "don't care" field. Upon reception of an SOS, the switching ASIC of Figures 7 and 8 will latch the Drive & Scan byte in an internal register of the 800 Mbps input processors 91. For ~ - of an SOS, the output formatter 98 (Figure 8) derives the value of its Drive & Scan byte from an internal register. This provides out-of-band u, .i~ -l;.. from one switching ASIC through the Fiber Channel to the next ~IU.. I~LI~.I switching ASIC.
An Idle Ordered Set is defined by all bits in the OS Type Bitfield having the value 0. RFU bits are set to zero by default.

The Inter-Shdf Iink makes use of Fiber Channel technology and the notion of a "supercell" to aid in cell ~ As indicated above, a supercell consists of a Supercell Ordered Set (SOS) followed by 128 60-byte ~JlUpl;~,lal,y ATM cells.

WO 95/30318 ~ 8 7 6 PCTICA95/00248 The Supercell format is shown below in Table J.
Bit Number Word 15 8 7 0 0 OS Type Bitfield K28.5 Drive & Scan byte RFU
2 to 128 x 60 Byte Newbridge c 115 3,841 Supercells are used on the Fiber Channel ISLs S and the local drop busses 27, as well as internally in certain cards. The presence of any Ordered Set is always indicated by some sort of Ordered Set Indication (OSI) signal. The 8 Khz 5 timing signal is carried on these same Fiber Channel links and local drop busses via the supercells. The two Timing Ordered Sets, ETOS and STOS (Table 1), are used to distribute timing ;"r..." ~;..., through-out the system, as discussed ingreater detail below. They may therefore occur at any time, even in the middle of a supercell or ATM cell.
Each switching ASIC (Figure 7) is capable of generating and outputting a continuous stream of supercells. This data stream consists only of ordered sets and yluyli..Lu y formatted 60-byte cells. Cells that are received by a switchingASIC for ~ are inserted into a cell slot within this output stream of 25 supercells. When a 60-byte formatted ATM cell is not available for ~
either an empty cell or one or more Idle Ordered Sets are inserkd, since both represent unused bandwidth.
As discussed above, since some inkrface cards 21 require a standard 3 0 timing reference, the system of the present invention provides means for ;.,e syskm timing throughout the switching fabric. Any UCS in an peripheral shelf 3A, 3B, etc., can contain an inkrface card 21 which acts as a WO95/30318 2187876 41 PCT/CA95/aO248 reference clock source (eg. a TI interface). If a card is chosen to be a reference clock source, it will be enabled to transmit its clock signal to the local hub card 23 via a backplane line designated as ESYNC. All interface cards 21 share this lineto the hub card 23, and only drive the line if enabled, The ESYNC signal 5 received by hub card 23 is distributed to the rest of the system as an ETOS signal (Table 1) via the switching fabric. The ETOS signal is routed through the systemto a System S~ ,, Unit (SSU), which uses the received ETOS signal to generate STOS from the ETOS timing reference. The STOS signal is then re-~" ' ' '~ throughout the system, for receipt of STOS by any card in the 10 system. The SSU receives the ETOS reference clock signal via the switch fabric drop bus 27. In this way, the reference clock signal can reach the system s~,,.,luu.li~Lu.. unit (SSU) regardless of where the SSU is located.
S~ lllUIIUUa amd ~ interfaces can both be used to 15 provide reference clocks. SJ ~ interfaces inherently contain reference timing in the interface's data signal. A,~ ' interfaces can contain reference timing in the form of the PLCP frame rate, which has ûo ,.~ h;l. to the physical data rate of the interfaoe. An ~.~ , provided referenoe clock usually contains c~ jitter, typically at 8 Khz, but this can easily be 2û filtered ûut by the SSU. Examples of ~ ' interfaces would be El and Tl;
E3 and T3 carry reference timing either ~a~ lllulluual~ or ~Il~ ulluual~.
As discussed above, th~e system ~ll~ v~ iull unit (SSU) is rP~rnn~ih for generating the system clock STOS from the selected reference clock ETOS.
25 The SSU is essentially a very stable PLL, coupled with control logic to allowselection of different reference sources, and additional logic to minimize system clock pCI ~u.l,dLonJ that might occur during referenoe clock changes or failures.
The PLL comprises a DAC, VCXO, phase . in feedback in the usual manner.
3û
Distribution of the system clock is ~ h ~ l via the switching fabric, providing ~l;~l,;l.--:;.... to all interfaoe cards 21 without requiring a dedicated cloc~
............... ..... _ _ .. _ _ _ .. ~ . _ . . .

WO 95/30318 218 ~ 8 7 6 PCT/CA95100248 42 'f, --network. The ' by which this is done is the ~ff.)rf. m~ -' Ordered Set (OS). As discussed above, an Ordered Set (OS) comprises 32 bits of data which are transmittf d on the drop bus 27. The OS is uniquely identified by a ' _ Ordered Set Indicator (OSI) pulse. A singlf~ bit in the 32 bit data 5 pattern indicates if the OS is also a System Timing OS (STOS), a Spf cial case of OS which is the efluivalent of a rising edge of an 8 Khz clock pulse.
The same is usf d by hub cards 23 in order to transmit the reference clock from an interface card 21 to the SSU. In this case a single ~it in 10 the OS pattern is used to indicate if the OS is also an ESYNC Timing OS (EIOS), ~hich is a special case of an OS which is the efluivalent of a rising edge of an 8 ~:hz reference clock pulse.
In the event that the system and reference clock signals experience ' _ rising edges, the STOS and ETOS must occur ' 'y. This is possible within a single OS by asserting both the STOS and ETOS bits, therefore the switching fabric is capable of .~ multiple clock signals .. .~.
2 0 Due to the flexibility of the reference clock and system clock ~1; ~1, ;l . ~t;, .. .
method, the location of the SSU within the system is also very flexible. The SSUmust be located within an peripheral shelf 3A, 3B, etc., but there is no restriction as to which peripheral shelf within the system contains the SSU, unless the c-," l~ matrix is not a non-blocking one. The SSU can be lof ated on any hub card 23, or can be located on a dedicated card that is installed in a UCS slot.
Distribution of ETOS and/or STOS timing signals through a multi-stage switching core can be a~c~ l,~ in many ways. Figure 16 shows a possible f1i~trihuti~n scenario in the 32x32 switching core I (depicted here in stages IA, lB, etc.). Note that it is sufficient for only one of the ISLs to carry TOSs out of the first and second stages lA and lB of the switch.

WO 9S/30318 ~ 1 8 ~ 8 7 6 PCT/CA95/00Z48 ' r~ fi~ c and alferna~ive ~ o~ of fhe invenfion are ?ossible wifhin the sphere and scope of fhe invenfion as described herein.

Claims (8)

WE CLAIM:

1. A communication system comprising:
a) a hub slot for receiving any one of a plurality of hub cards for receiving and transmitting data cells;
b) a plurality of universal card slots;
c) a plurality of interface cards insertable into any one of said plurality of universal card slots for receiving incoming ones of said data cells containing data and transmitting outgoing ones of said data cells containing data;
d) an add bus having respective data links connected between individual ones of said universal card slots and said hub slot for receiving said outgoing ones of said data cells from said plurality of interface cards and transmitting said outgoing ones of said data cells to said one of said plurality of hub cards;
e) a drop bus having a single data link connected between all of said universal card slots and said hub slot for transmitting said incoming ones of said data cells from said one of said plurality of hub cards to said plurality of interface cards;
and f) means within each of said interface cards for filtering said incoming ones of said data cells from said drop bus and thereby routing said data cells to an appropriate one or more of said plurality of interface cards.

2. The communication system of claim 1, wherein at least one of said plurality of hub cards comprises an internal communication path between said add bus and saiddrop bus.

3. The communication system of claim 1. wherein at least one of said plurality of hub cards further comprises a plurality of first inputs connected to respective data links of said add bus, a second input connected to a switching means, a first output connected to said drop bus and a second output connected to said switching means, for receiving and concentrating said outgoing ones of said data cells into a high-speed output data stream for receipt by said switching means and for receiving a high-speed input data stream from said switching means and applying said high-speed input data stream to said drop bus for receipt by said appropriate one or more of said interface cards.

4. The communication system of claim 3, wherein said switching means comprises a high-speed data link between said second output and said second input of said one of said plurality of one of said plurality of hub cards.

5. The communication system of claim 3, wherein said switching means comprises a cell switching core having at least one input thereof connected to said second output of said one of said plurality of one of hub cards and at least one output thereof connected to said second input of said one of said plurality of hub cards.

6. A communication system comprising:
a) a plurality of interconnected universal card slots;
b) a plurality of interface cards and control cards insertable into said universal card slots for receiving incoming ATM cells containing routing information and either data or control and diagnostic information, respectively,and transmitting outgoing ones of said ATM cells containing routing information and either data or control and diagnostic information, respectively;
c) means within each of said interface cards and control cards for pre-pending to said outgoing ones of said ATM cells a plurality of additional headerbytes to provide multiple system functions in addition to ATM cell routing in accordance with said routing information; and d) means for receiving said outgoing ones of said ATM cells. filtering said additional header bytes and in response; implementing predetermined ones of said multiple system functions.

7. The communication system of claim 6, wherein one of said multiple system functions comprises selective point-to-point or point-to-multipoint routing of said outgoing ones of said ATM cells within said system.

8. The communication system of claim 6, wherein one of said multiple system functions comprises in-band control and diagnostics.