CA2152637A1 - Network for Transferring Consecutive Packets Between Processor and Memory with a Reduced Blocking Time - Google Patents

Network for Transferring Consecutive Packets Between Processor and Memory with a Reduced Blocking Time

Info

Publication number
CA2152637A1
CA2152637A1 CA2152637A CA2152637A CA2152637A1 CA 2152637 A1 CA2152637 A1 CA 2152637A1 CA 2152637 A CA2152637 A CA 2152637A CA 2152637 A CA2152637 A CA 2152637A CA 2152637 A1 CA2152637 A1 CA 2152637A1
Authority
CA
Canada
Prior art keywords
data
buffers
consecutive packets
stored
select
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2152637A
Other languages
French (fr)
Other versions
CA2152637C (en
Inventor
Yuuki Date
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Yuuki Date
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yuuki Date, Nec Corporation filed Critical Yuuki Date
Publication of CA2152637A1 publication Critical patent/CA2152637A1/en
Application granted granted Critical
Publication of CA2152637C publication Critical patent/CA2152637C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17375—One dimensional, e.g. linear array, ring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Abstract

For making in a parallel computer system an interconnection network transfer data sequences, each composed of consecutive packets, from input ports (17) to a destination port indicated among output ports (19) by a routing address specified by a leading packet of each data sequence, control registers (31) hold the routing address of a privileged sequence determined by arbiters (39) in response to such addresses held in the control registers and stored in control buffers (33), Data of the consecutive packets of the privileged sequence are simultaneously stored in and produced from data buffers (37). Controlled by the arbiters, input selectors (41, 43) select the data for delivery to the destination port through output buffers (55) and output selectors (57) controlled by a selector operating arrangement (59-63).
When the data of the consecutive packets are not yet wholly stored in the data buffers, the input selectors select only those already stored in the data buffers and then select the data of remaining ones of the consecutive packets as soon as they reach the data buffers.
CA002152637A 1994-06-27 1995-06-26 Network for transferring consecutive packets between processor and memory with a reduced blocking time Expired - Fee Related CA2152637C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6145100A JP2644185B2 (en) 1994-06-27 1994-06-27 Data processing device
JP145100/1994 1994-06-27

Publications (2)

Publication Number Publication Date
CA2152637A1 true CA2152637A1 (en) 1995-12-28
CA2152637C CA2152637C (en) 1999-08-17

Family

ID=15377378

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002152637A Expired - Fee Related CA2152637C (en) 1994-06-27 1995-06-26 Network for transferring consecutive packets between processor and memory with a reduced blocking time

Country Status (6)

Country Link
US (1) US5857078A (en)
EP (1) EP0690390B1 (en)
JP (1) JP2644185B2 (en)
BR (1) BR9502279A (en)
CA (1) CA2152637C (en)
DE (1) DE69519825T2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7274692B1 (en) 2001-10-01 2007-09-25 Advanced Micro Devices, Inc. Method and apparatus for routing packets that have multiple destinations
US7295563B2 (en) * 2001-10-01 2007-11-13 Advanced Micro Devices, Inc. Method and apparatus for routing packets that have ordering requirements
US7221678B1 (en) * 2001-10-01 2007-05-22 Advanced Micro Devices, Inc. Method and apparatus for routing packets
US7353317B2 (en) * 2004-12-28 2008-04-01 Intel Corporation Method and apparatus for implementing heterogeneous interconnects
JP5691555B2 (en) * 2011-01-25 2015-04-01 日本電気株式会社 Interconnected network control system and interconnected network control method
US9137173B2 (en) * 2012-06-19 2015-09-15 Advanced Micro Devices, Inc. Devices and methods for interconnecting server nodes
US11275632B2 (en) 2018-09-14 2022-03-15 Advanced Micro Devices, Inc. Broadcast command and response
CN113010173A (en) 2019-12-19 2021-06-22 超威半导体(上海)有限公司 Method for matrix data broadcasting in parallel processing
CN113094099A (en) 2019-12-23 2021-07-09 超威半导体(上海)有限公司 Matrix data broadcast architecture
US11403221B2 (en) 2020-09-24 2022-08-02 Advanced Micro Devices, Inc. Memory access response merging in a memory hierarchy

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4320502A (en) * 1978-02-22 1982-03-16 International Business Machines Corp. Distributed priority resolution system
US4480307A (en) * 1982-01-04 1984-10-30 Intel Corporation Interface for use between a memory and components of a module switching apparatus
US4560985B1 (en) * 1982-05-07 1994-04-12 Digital Equipment Corp Dual-count, round-robin ditributed arbitration technique for serial buses
US4724520A (en) * 1985-07-01 1988-02-09 United Technologies Corporation Modular multiport data hub
JPH01221042A (en) * 1988-02-29 1989-09-04 Toshiba Corp Congestion control method for packet exchange
US4862454A (en) * 1988-07-15 1989-08-29 International Business Machines Corporation Switching method for multistage interconnection networks with hot spot traffic
US5053942A (en) * 1988-11-01 1991-10-01 The Regents Of The University Of California Bit-sliced cross-connect chip having a tree topology of arbitration cells for connecting memory modules to processors in a multiprocessor system
DE69030640T2 (en) * 1989-11-03 1997-11-06 Compaq Computer Corp Multiprocessor arbitration in single processor arbitration schemes
JPH077975B2 (en) * 1990-08-20 1995-01-30 インターナショナル・ビジネス・マシーンズ・コーポレイション System and method for controlling data transmission
US5251209A (en) * 1991-03-28 1993-10-05 Sprint International Communications Corp. Prioritizing attributes in integrated services networks
US5313458A (en) * 1991-06-03 1994-05-17 Fujitsu Limited Traffic control system
US5339313A (en) * 1991-06-28 1994-08-16 Digital Equipment Corporation Method and apparatus for traffic congestion control in a communication network bridge device
US5467295A (en) * 1992-04-30 1995-11-14 Intel Corporation Bus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unit
MX9308193A (en) * 1993-01-29 1995-01-31 Ericsson Telefon Ab L M CONTROLLED ACCESS ATM SWITCH.

Also Published As

Publication number Publication date
DE69519825D1 (en) 2001-02-15
JP2644185B2 (en) 1997-08-25
DE69519825T2 (en) 2001-08-02
EP0690390A3 (en) 1996-01-17
US5857078A (en) 1999-01-05
EP0690390B1 (en) 2001-01-10
BR9502279A (en) 1996-02-27
CA2152637C (en) 1999-08-17
EP0690390A2 (en) 1996-01-03
JPH0818565A (en) 1996-01-19

Similar Documents

Publication Publication Date Title
US5418781A (en) Architecture for maintaining the sequence of packet cells transmitted over a multicast, cell-switched network
US5436893A (en) ATM cell switch suitable for multicast switching
US8320369B1 (en) Systems and methods for implementing virtual switch planes in a physical switch fabric
US6160811A (en) Data packet router
CA2124424C (en) Fast connection setup interfaces using pre-assigned virtual channel identifiers
KR100356447B1 (en) Memory interface unit, shared memory switch system and associated method
AU767085B2 (en) Optimizing the transfer of data packets between LANs
CA2297650C (en) Networking systems
US6813274B1 (en) Network switch and method for data switching using a crossbar switch fabric with output port groups operating concurrently and independently
US6795886B1 (en) Interconnect switch method and apparatus
US5724348A (en) Efficient hardware/software interface for a data switch
EP0195589B1 (en) Switching system for transmission of data
EP1045558B1 (en) Very wide memory TDM switching system
US5657314A (en) Network multiplexer
US5434855A (en) Method and apparatus for selective interleaving in a cell-switched network
US5224093A (en) High-speed multi-port fifo buffer circuit
US20050018609A1 (en) Fabric router with flit caching
JPH11346223A (en) Atm switchboard
US6570845B1 (en) Switching system including a mask mechanism for altering the internal routing process
CA2152637A1 (en) Network for Transferring Consecutive Packets Between Processor and Memory with a Reduced Blocking Time
US6310875B1 (en) Method and apparatus for port memory multicast common memory switches
US6643294B1 (en) Distributed control merged buffer ATM switch
Bianchini Jr et al. Design of a non‐blocking shared‐memory copy network for ATM
WO1996038792A1 (en) Monitoring and control of data flow in a computer network device
US7254139B2 (en) Data transmission system with multi-memory packet switch

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed