CA2142542A1

CA2142542A1 - Process for the production of structures

Info

Publication number: CA2142542A1
Application number: CA002142542A
Authority: CA
Inventors: Walter Schmidt; Marco Martinelli
Original assignee: Dyconex Patente AG
Current assignee: Dyconex Patente AG
Priority date: 1994-02-21
Filing date: 1995-02-15
Publication date: 1995-08-22
Also published as: US5639389A; JP3779745B2; EP0668712A1; CA2137861A1; EP0668712B1; DE59508829D1; ATE197525T1; JPH07273448A

Abstract

The invention relates to a process for the production of printed circuit boards and film circuit boards from inter-mediates (Z), in which starting products (A) are used, which comprise plasma-etchable insulating material (2), coated on one or both sides with plasma etching-resistant conductor material (1, 3) and in this process in a first process stage openings (8, 8') are plasma-etched in the insulating material (2) in accordance with prepared openings (7, 7') in the conductor material (1, 3), so that projecting edges (9, 9') of the prepared openings (7, 7') are plasma back etched, so that the prepared openings (7, 7') and the openings (8, 8') are structured in planned back etched manner and then in a second process stage the projecting edges (9, 9') are chemically etched away, so that the prepared openings (7, 7') and the openings (8, 8') are structured in planned etch-back free manner, so that intermediates (Z) are formed for further plating on.

Description

- 2142~2 -PROCESS FOR THE PRODUCTION OF STRUCTURES

The invention is in the field of the production of printed circui~ boards and film circuit boards and relates to a p~o~ess f ~ ~he production of structuresr patterns or shapes in plasma-etchable insulating material, which is clad with plasma etching-resistant conductor material in accordance with the present claims.

Plasma-etchable insulaeing material can be structured in the plasma etching process according to the DYCOstrate~ process.
Such structures can be openings, which pass through the insulating material as through holes, or blind holes, which merely extend into the insulating material. Through holes and blind holes can also be in the form of elongated holes such as grooves, which run in different and varying depths in the insulating material with straight or round edges. During plasma etching the structures are simultaneously produced with high precision in the insulating material. This process is economic, because it permits an inexpensive, rapid formation of very varied structures and patterns ln the insulating material. The plasma-etchable lnsulatlng materlal is consti-tuted by organic, dielectric films such as e.g. polyimide films, aramide fibre-reinforced laminates of epoxy, polyimides or cyanate-ester resin films, as well films of li~uid crystal polymers (LCP), etc.

In order to be able to etch such insulating material with a locally controlled plasma, it is coated with a plasma etching-resistant material. Such plasma etching-resistant materials can e.g. be metal layers of copper or aluminium, i.e. layers made from plasma etching-resistant conductor material. The applied, plasma etching-resistant material is provided with openings extending down to the insulating material, so that the plasma can interact through said openings with the insulating material and etch the same.

~1~2542 - i ;
Since for thermal reasons and for reasons of the plasma etching rate associated therewith, directional plasma etching (reactive ion etching) does not appear appropriate for the production of film circuit boards, use is made of isotropic plasma etching, i.e. insulating material is removed everywhere and in uniform manner where the plasma has access to it.
Thus, the insulating material can also be removed below the edges of the openings in the plasma etching-resistant material, i.e. below the plasma etching-resistant material.
This underetching or undercutting means that the edges of the openings project in quasi-insulated manner in the space from the solid or rigid plasma etching-resistant material following plasma etching and that the insulating material has etched-back cavities.

The use of plasma etching-resistant conductor material firmly connected to the plasma-etchable insulating material has proved advantageous in the manufacture of printed circuit boards and film circuit boards. Such conductor material can be applied to one or both sides of the insulating material in the form of clad copper layers. Following the plasma etching of openings in the insulating material, the conductor material can be structured in current paths in fùrther process stages and the openings in the insulating material can be plated on in order this way to form interfacial connections between the different planes of structured material.

However, etch-backs, i.e. the projecting edges or webs of plasma etching-resistant material around openings in the insulating material, prove disadvantageous for further, follo~ing pr~Ssiny sta~eS. Th~3, ~he followinc problems occur in the elec~roaeposition of copper.
The area below the webs around openings in the insulating material is electrically shielded during the electrodeposition of metal layers, so that there only small copper quantities 2142~42 _ are deposited, so that e.g. the reliability of interfacial connections is not ensured.

The etched-back cavities of the openings in the insulating material cannot be adequately cleaned, e.g. by degassing or washing out. In electrodeposition with the plurality of succeeding baths, this leads to inadequate results and to a carrying over of chemicals from one bath to the next.

The webs around the openings in the insulating material are thin and easy to deform mechanically. For example, they are bent up and deformed by ultrasonic baths as the cleaning medium. This leads to inadequate results during the following photochemical process stages.

One possibility for removing such etch-backs is to press the webs around the plasma-etched openings by pressure action into said openings in the insulating material, such as is e.g.
described in US patent 4 472 238. The latter patent uses two-sided, copper clad polyimide films, such as Pyralux~ Du Pont F9111 or copper foil-coated Kevlar~ as the plasma etching-resistant conductor material and plasma-etchable insulating material. Projecting copper edges of 76-254 ~m holes in the polyimide or Kevlar films are pressed into the said holes at 124 atm.

This process suffers from serious~disa~vantages. The finer the plasma-etched structures, which are underetched, the greater the overpressures which must be applied in order to press the webs into the openings. This leads to excessive mechanical stressing and undesired dimensional changes and is cor,sequently tecnnically im.pract~_Gble Another possibility for removing said underetchings is to press the webs around plasma-etched openings into the latter by material bombardment. In printed circuit board technology such a process is referred to as a jet scrubber process, in which e.g. an aqueous solution of pumice powder is sprayed - 2142 54~
_ - 4 -under hlgh pressure onto the pro~ectlng edges of openlngs and pressed lnto said openings.

However, thls process also suffers from serlous disadvantages. There ls a mechanical cold deformation of the pumice powder-bombarded surfaces whlch leads to undesired mechanical stresses and ~men~ional changes. The process is only usable with very thin layers of plasma etching-reslstant conductor material. There is a partlal incorporation of the pumice powder and knocked off particles of plasma etching-resistant material into other areas of the printed circuit board and film circuit board to be produced, which in turn leads to disturbing effects such as impurities, electrlcal short-circuit contacts, etc. Thus, this process is technically impracticable.

The problem of the inventlon ls to obvlate these problems. The inventlon permlts a productlon of structures ln insulatlng materials, etchable ln a first etching process, whlch is clad wlth conductor material, resistant to sald flrst etchlng process. In particular an operationally rellable production of structures in etching-resistant conductor material is to be possible. This is to take place in a relatively small number of working steps using established, proven processing steps.

This problem is solved by the inventlon, as deflned in the claims.

The idea of the invention was arrived at in the light of the disadvantageous effects of underetchlng and in an attempt to prevent the latter. Such underetchlng is generally undeslred and is pre~udicial to product quality. In the present invention such underetching is brought about in planned manner in order to produce structures, patterns or shapes in an insulating material and are removed again in equally planned manner ln order to produce structures in a conductor materlal.
According to the invention disadvantageous weak points of structures in one material produced by a flrst process are used as advantageous weak points ln the productlon of structures ln the other materlal by a second 21425~2 -process, so that the weak polnts are removed and the product quallty ls optlmlzed.

Accordlng to the inventlon, two dlfferent etchlng processes are successlvely used. There ls firstly an etching process for etchlng the lnsulatlng materlal, whllst the conductor materlal remalns unaffected.
Thls ls followed by a structurlng process for structurlng the conductor materlal, whllst the lnsulatlng materlal ls not attacked. Both processes, namely etchlng of insulator material and structuring of conductor material are lsotroplc processes. The actlon of the two processes is balanced out.
All etch-backs disadvantageous for further processing stages produced by the etching process of insulator material are preferably removed in the structurlng process of conductor materlal.

The inventlon relates to a process for the productlon of prlnted clrcult boards and fllm circult boards from starting materlals and via intermediates. The starting materials consist of plasma-etchable insulating material coated on one or both sides with plasma etching-reslstant conductor material. In a first process, stage openings are plasma-etched in the insulatlng materlal according to openings prepared in the conductor material, the edges of said prepared openings being plasma-back etched. The prepared openings in the conductor material and the openings in the insulating material are etched-back in planned manner. In a second process stage, the pro~ecting edges are chemically etched away.
The prepared openings in the conductor material and the openings in the insulating material are consequently structured in planned manner in back etch-free manner. Thus, intermediates are formed, which can be further processed e.g. by plating on ~o l~orm printec circuit boards and film clrcuit boards.

The process according to the invention for producing structures is explained in greater detail relative to Figs. 1 to 8, which diagrammatically show the inventive process for ~ 42~42 ~

removing etched-back, projecting edges of plasma etching-resistant material around openings in the plasma-etchable insulating material.

Fig. 1 shows a starting product A for the production of printed circuit boards and film circuit boards. The starting product A is a multilayer comprising a layer of plasma-etchable insulating material 2 coated on both sides with a plasma etching-resistant conductor material 1, 3. The plasma-etchable insulating material 2 is constituted by organic, di-electric films such as e.g. polyimide films, aramide fibre-reinforced laminates of epoxy, polyimide or cyanate-ester resin films and films of liquid crystal polymers (LCP). The plasma etching-resistant conductor material 1, 3 consists of electrically conductive-layers, e.g. metal layers such as of copper, aluminium or silver. The conductor material l, 3 is laminated onto the insulating material 2 or is applied thereto galvanically or by vapour deposition, sputtering or plasma-activated vapour phase deposition ~PECVD) and mechanically firmly connecte~ thereto. The starting product A is laminated onto a carrier substrate 4 and firmly mechanically connected thereto.

In advantageous embodiments of starting products A for the production of film circuit boards these layers of insulating material 2 and conductor material 1, 3 are formed from specific, advantageous materials and are particularly thin.
Thus, the starting product A advantageously comprises a polymer film copper clad on both sides, in which the polymer film is 25 to 50 ~m thick and the copper layers 8 to 12 ~m thick. Naturally the starting products A for the production of printed circuit boards can be formed from much thicker layers of insulating material and conductor material and the starting products A may only have one layer of conductor material 1 on insulating material 2.

Fig. 2 shows a starting product A according to Fig. l follow-ing the application of a photoresist layer 5 on the conductor material layer 1, so that the latter is completely covered with the photoresist. It is possible to use a solid or liquid photoresist. The photoresist 5 can be exposed by a known, photochemical process. An opening design is transferred by means of photomasks into the photoresist 5. The opening design contains the position and structure of the openings to be produced or structures in the insulating material 2.

Fig. 3 shows the photochemically performed structuring of the photoresist layer 5 complying with the opening design. In the structured photoresist layers 5 are formed opening structures 6, 6', which extend down to the conductor material layer 1.
The other areas of the conductor material layer 1 covered with the photoresist are protected against wet chemical etching in the following, photochemical processing stages. The area of the opening structures is 10 to 100 ~m. The shapes of the surfaces are freely selectable and can be circular cylindrical, round, cval, as weil as square, rec~angular and polygonal.

Fig. 4 shows the conductor material layer 1 covered with a photochemically structured photoresist layer 5 following the wet chemical etching of the conductor material 1 not covered by the photoresist 5. According to the opening design this etching only takes place in the vicinity of the opening structures 6, 6' and leads to the planned formation of pre-pared openings 7, 7' in the conductor material 1 extending down to the insulating material 2. Such masks are not attacked by the etching medium and the latter can only pass to the conductor material 1 to be etched in the vicinity of openings in said masks.

Fig. 5 shows the starting product A in the production stage according to Fig. 4 following the removal of the photoresist 5 using known, proven chemical processes. This stage is optional, because as a function of the nature and duration of - 2142~42 the following plasma etching of the insulating material 2, the photoresist 5 is more or less completely removed.

Fig. 6 shows the starting product A from which the photoresist has been removed following the plasma etching of openings or structures 8, 8' though the insulating material 2 and extending down to the conductor material layer 3. In this first process stage plasma-etchable insulating material 2 is isotropically plasma-etched in accordance with the prepared openings 6, 6' of the clad layer of plasma etching-resistant conductor material 1. Where the plasma comes into contact with the insulating material 2 openings are formed, the con-ductor material 1 is back-etched and has at these openings projecting edges or webs 9, 9'. These projecting edges 9, 9 border the structures 8, 8' in the insulating material 2 and are quasi-insulated in the space.

Fig. 7 shows the starting product A with etched-back openings or structures 8, 8' in the insulating material 2 resulting from the through-etching of the webs 9, 9' of the upper, structured conductor material layer 1. In this second pro-duction stage the plasma etching-resistant conductor material 1, 3 is isotropically chemically etched, i.e. it is etched away where the chemicals come into contact with the conductor material 1, 3.

Chemical etching takes place uniformly in all surface areas accessible to the chemicals. The edges 9, 9' of the plasma etching-resistant conductor material layer 1 projecting in quasi-insulated manner in the space have a large surface to volume ratio and are particularly readily accessible to chemicals and are chemically etched away, whereas the o~her, not etched-back surface areas 12, 12' of the conductor material layer 1, 3 are only chemically thinned. Thus, the exposed surface areas of the lower conductor material layer 3, which form the bottoms 10, 10' of the openings 8, 8' in the insulating material 2, are uniformly etched thinner, but ` _` 2~42~42 g I

instead of being etched away they merely undergo a thickness reduction.

The chemical etching parameters are chosen in such a way that the conductor material 1, 3 is etched away, that the conductor material 1, 3 fulfils a mechanically stabilizing and an electrically conducting function for the starting product A
and that the projecting edges 9, 9' of the conductor material 1, 3 are etched away or through. The etch-backs from the first process stage are consequently removed in planned manner, so that an intermediate Z is produced. The openings 8, 8' according to Fig. 7 can e.g. be in the form of blind holes or grooves. When using e.g. approximately 10 ~m thick conductor material layers 1, 3 made from copper the projecting edges 9, 9' are simultaneously etched from all sides and are consequently completely etched away when on the other, covered and consequently not etched-back surface areas only about 5 ~m of the conductor mate~ial 1, 3 is etched away. Thus, there are varyingly thick conductor material areas 1, 3. It is easy for the expert with the knowledge of the present invention to choose the chemical etching parameters for the particular materials used and for their material thicknesses, so that said second process stage is ended when the disadvantageous projecting edges around the plasma-etched openings of the con-ductor material have been etched away or through. Such chemical etching processes are prov~n, known procedures in the circuit board industry. For example, copper layers 1, 3 can be etched by sodium persulphate, copper chloride and hydrogen peroxide. The removal rate is very precisely controlled by the expoSure ~ime a~ the temperat~e ~f the etzhing medium.
Fig. 8 shows the intermediate Z according to Fig. 7 following the plating on of a layer of plasma etching-resistant, electrically conductive material 11. This process stage is optional and serves either to mechanically reinforce or electrically connect the layers of chemically more thinly etched conductor material 1, 3. For example, thin metal 2142~42 layers of copper or palladium can be plated on as plasma etching-resistant, electrically conductive material 11.

The intermediate Z is suitable for the production of printed circuit boards and film boards. With the thus reinforced con-ductor material layers 1, 3, 11 it can undergo structuring in current paths and interfacial connections e.g. using the DYCOstrate~ process. Such structures can be current paths in conductor material layers, but can also be interfacial con-nections in openings of insulating material layers, so that different layers of structured conductor material can be electrically interconnected. Numerous implementation possi-bilities are available to the expert with the knowledge of the present invention.

The openings 8, 8' according to Fig. 8 are blind holes with sloping walls 14, 14' relative to the flat extension of the intermediate Z which, after plating on, electrically inter-connect the conductor material layers 1, 3 as interfacial connections 13, 13' and have corresponding sloping walls 14, 14' relative to the flat extension of the intermediate Z.
Such sloping walls 14, 14' can be better photochemically structured in further production stages. Such sloping walls 14, 14' can also be more easily cleaned. In addition, such sloping walls 14, 14' are more reliable against disturbing external influences. On extending the insulating material layer 2 in the Z-direction, e.g. due to a temperature rise during soldering, sloping walls do not fracture as easily at the corners and edges as vertical walls.

During pho~ochemica~ str~c~_i.g slop_ng walls 14, 14~ are better accessible through the prepared op~nings 7, 7' in the conductor material 1 plated with electrically cond~ctive material 11. It is also possible to use negative operating photoresists, which can be exposed in the interfacial connec-tions 13, 13' and which are cheaper and less sensitive to positive operating photoresists. The higher sensitivity has ~2~2 the important advantage that lower exposure intensities are required and faster exposure can take place.

The formation of openings 7, 7' in the conductor material layer 1 according to Figs. 1 to 5 can simultaneously and in completely identical manner be performed in the second conductor material layer 3. For this purpose, the intermediate Z is not laminated onto the carrier substrate 4, at least in the surface areas intended for this, so that at these points the conductor material layer 3 can be photoresist-coated. This photoresist layer is now structured in opening structures and in the chemical etching process prepared openings are etched in the conductor material layer in accordance with these opening structures. In the plasma etching process openings or structures are plasma-etched in the insulating material corresponding to these prepared openings in the conductor material layer. Such structures can then have straight or sloping walls relative to the surface extension of the intermediate Z. In the process stage according to Fig. 8, plating on is possible to interfacial connections and then have straight or sloping walls relative to the surface extension of the intermediate Z.

The first etching process for etching the insulating material 2 is preferentially a plasma etching process. Said first etching process can be also a chemical etching process. Plasma etching and chemical etching produce the identical effect of ~1~2~42 underetching. The chemically etchable insulator material 2 is constituted by organic, dielectric films such as eg. polyimide, epoxy and acrylate films, fibre-reinforced laminates of epoxy, polyimide resin films, which can be etched chemically using etching mediums such as e.g. KMnO4, NaOH, KOH - alcohol, H2S04, H3P04. Such chemical etching processes are proven, known procedures in the circuit board industry. It is easy for the expert with the knowledge of the present invention to choose the chemical etching parameters for the particular insulating material 2 and conductor material 1,3 used.

The structuring process for structuring the conductor material 1,3 is a chemical etching process or said structuring process is an electrodeplating process ~galvanic deplating). Chemical etching and electrodeplating of conductor material 1,3 produce the same effect of removing projecting edges around openings in insulator material 2 by removing material 1,3. The conductor material 1,3 consists of electrically conductive layers, e.g.
metal layers such as of copper, aluminium or siiver. Such electrodeplating processes are proven, known procedures in the circuit board industry, the removal rate is uniform and can be very precisely controlled. It is easy for the expert with the knowledge of the present invention to electrodeplate, for example, thin copper layers 1,3 and to remove entirely projecting edges around openings in insulator material 2 by removing partially copper layers 1,3.

~142~42 -The structuring process stage for structuring the insulator material 2 can be a plasma etching process or a chemical etching process. The structuring process stage for structuring the conductor material 1,3 can be a chemical etching process or an electrodeplating process. For example, four different realisations of the inventive process are possible.

According to a first realisation of the invention, the first structuring process stage consists in plasma etching of openings 8,8' in the insulating material 2 in accordance with prepared openings 7,7' in the conductor material 1,3, in such a way that projecting edges 9, 9' of the prepared openings 7,7' are formed by back etching. In a second structuring process stage, the conductor material 1,3 gets chemically etched and the projecting edges 9,9' are removed, so that the prepared openings 7,7' and the openings 8,8' are structured in planned etch-back-free manner.

In a further realisation of the invention, the first structuring process stage consists in plasma etching of openings 8,8' in the insulating material 2 in accordance with prepared openings 7,7' in the conductor material 1,3 in such a way that projecting edges 9,9' of the prepared openings 7,7' are formed by back etching. In a second structuring process stage, the conductor material l,3 gets electrodeplated and t projecting edges 9,9' are removed, so that the prepared openings 7,7' and the openings ~142542 8,8' are structured in planned etch-back-free manner.

In a further realisation of the invention, the first structuring process stage consists in chemical etching of openings 8,8' in the insulating material 2 in accordance with prepared openings 7,7' in the conductor material 1,3 in such a way that projecting edges 9,9' of the prepared openings 7,7' are formed by back etching. In a second structuring process stage, the conductor material 1,3 gets chemically etched and the projecting edges 9,9' are removed, so that the prepared openings 7,7' and the openings 8,8' are structured in planned etch-back-free manner.

In a further realisation of the invention, the first structuring process stage consists in chemical etching of openings 8,8' in the insulating material 2 in accordance with prepared openings 7,7' in the conductor material 1,3 in such a way that projecting edges 9,9' of the prepared openings 7,7' are formed by back etching. In a second structuring process stage, the conductor material 1,3 gets electrodeplated and the projecting edges 9,9' are removed, so that the prepared openings 7,7' and the openings 8,8' are structured in planned etch-back-free manner.

Claims

1. Process for the production of printed circuit boards and film circuit boards from starting products (A) of insulating material (2), which is coated on one or both sides with conductor material (1,3), characterized in that in a first process stage openings (8,8') are etched in the insulating material (2) in accordance with prepared openings (7,7') in the conductor material (1,3) in such a way that projecting edges (9,9') of the prepared openings (7,7') are formed by back etching, so that the prepared openings (7,7') and the openings (8,8') are etched back in planned structured manner and that in a second process stage the projecting edges (9,9') are removed, so that the prepared openings (7,7') and the openings (8,8') are structured in planned etch-back-free manner, so that intermediates (Z) for further plating on are formed.

2. Process according to claim 1, characterized in that in the second process stage, the conductor material (1,3) is uniformly chemically etched or electrodeplated in all accessible surface areas that the conductor material (1,3) is chemically etched or electrodeplated in accordance with the local surface/volume ratios, that projecting edges (9,9') are chemically etched or electrodeplated away and that non-etched-back surface (12,12') are in part made thinner.

3. Process according to claim 2, characterized in that in the second process stage the conductor material (1,3) is chemically etched or electrodeplated in all accessible surface areas until the projecting edges (9,9') are chemically etched or electrodeplated through and consequently, the etch-backs are removed.

4. Process according to either of the claims 2 and 3, characterized in that the etchable insulating material (2) is plasma-etchable or chemically etchable, that the first process stage is a plasma etching process stage or a chemically etching stage, that in further process stages etching-resistant, electrically conductive material (11) is plated on the intermediate (Z), so that the accessible surface areas of more thinly etched or electrodeplated conductor material (1,3) and the accessible surface areas of insulating material (2) are mechanically reinforced with electrically conductive material (11).

5. Process according to claim 4, characterized in that the openings (8,8') in the insulating material (2) in said further process stages are completely covered with electrically conductive material (11) and form interfacial connections (13,13'), so that different conducting material layers (1) and (3) are electrically inter-connected.

6. Process according to either of the claims 4 and 5, characterized in that the surface areas of more thinly etched or electrodeplated conductor material (1,3) plated with electrically conductive material (11) and the surface areas of insulating material (2) plated with electrically conductive material (11) during further production stages can be structured according to a circuit design on one and/or two sides in current paths with interfacial connections.

7. Process according to claim 1, characterized in that as insulating material (2), an organic dielectric film is plasma-etched or chemically etched, that as the conductor material (1,3) copper layer clad on both sides on the organic, dielectric film are chemically etched or electrodeplated on one or both sides, that the organic dielectric film is 25 to 50 µm thick and that the copper layers are 8 to 12 µm thick.

8. Process according to claim 7, characterized in that as organic, dielectric films use is made of polyimide films or liquid crystal polymer films.

9. Process according to claim 7, characterized in that the organic, dielectric films are constituted by aramide fibre-reinforced laminates of epoxy or polyimide resin films.

10. Process according to claim 7, characterized in that as organic, dielectric films use is made of aramide fibre-reinforced laminates of cyanate-ester resin films.

11. Process according to claim 4, characterized in that as electrically conductive material (11) thin metal layers of copper or palladium are plated on.

12. Intermediate (Z) produced in the process according to either of the claims 1 and 4, characterized in that the conductor material layers (1,3) structured by plasma etching and chemical etching have areas of different thickness.

13. Intermediate (Z) according to claim 12, characterized in that the etched openings (8,8') in the insulating material (2) do not have etch-backs in the form of projecting edges (9,9') of the prepared openings (7,7') in the conductor material (1,3).

14. Intermediate (Z) according to either of the claims 12 and 13, characterized in that the interfacial connections (13,13') have sloping walls relative to the surface extension of the intermediate (Z), that via these different conductor material layers (1,3) are electrically interconnected and that a conductor material layer (3) undergoes a thickness reduction in the vicinity of the bottoms (10,10') of the openings (8,8').

15. Printed circuit boards and film circuit boards produced in the process according to either of the claims 1 and 4, characterized in that the conductor material layers (1,3) structured by plasma etching and chemical etching have areas of different thicknesses.

16. Printed circuit boards and film circuit boards according to claim 15, characterized in that the etched openings (8,8') in the insulating material (2) do not have any etch-backs in the form of projecting edges (9,9') of the prepared openings (7,7') in the conductor material (1,3).

17. Printed circuit boards and film circuit boards according to either of the claims 15 and 16, characterized in that the interfacial connections (13,13') have sloping walls relative to the surface extension of the intermediate (Z), that via the latter, the different conductor material layers (1,3) are electrically interconnected and that a conductor material layer (3) has a reduced thickness in the vicinity of the bottoms (10,10') of the openings (8,8').