CA2141613A1 - Network link controller - Google Patents

Abstract

A link controller for use in a node of a network includes a digital controller (102) that employs a knowledge-based control program (103).
The device and method provide flexible master node designation, automatic installation, configuration and reconfiguration, and recognition and correction of network communication problems resulting from interference and other adverse conditions. The knowledge-based control program (103) employs an inference engine and a set of rules to dynamically optimize network configuration. Multipath is managed by locking on to reflected signals when a direct signal is unavailable. Operation is transparent to network users .

Description

- 21~1613 NF.T~VOI~K l ~ K CONTRO~.I.Fl~.

BACKGROUND OF 1~; INVENTION

1. Field of thP Inve~Qn This invention relates to CoullJut.,l n~,lwo-~ and, more partieularly, to a linkS controller deviee and method pçnnitting iulpro-~d impl~m~nt~tion, control, and regulation of a couuput~r net~,vork.

2~ Descri~tion of Related Art Couuput~,r hC~wOIl~S are known in the art. However, cou~ ional n.,lwu suffer from several disadvantages.
One disadvant~ge is that sueh n~,l.. u ll~ typieally require pe~mqn~!nt desigTlqtion of a partieular node to aet as a master eontrol unit. This node typieally must be eentrally loeated, and eontrols the entire ncl-..,lL The lc~lui~ ul of a pennqnrnt1y-decig~qted master node limits the fle~ibility of the network.
Another disadvantage is that con~,utional nct~. ulki~g systems are CA~ , to 15 install and m~in-qin They typieally use analog eontrol of transmit and Iccei~r frequeneies, and require e-Apert p,,.~.,..,l to initially tune and install, as well as to subsc.lu- ~lly mqintqin, the trancmitt~r.c and recei~ . If the n~lwolk's band ofoperation bccouucs noisy or eontqinC m~.L.~,nce from other sourees, manual reeonfiguration by trained p~ o~ rl is required. Sueh plobl~,uls are partieularly evident 20 in whcless n~,~wol~illg systems, although they may eAist in wired and other hard-co~ r~l~d systems as well.
.A-lditi~ nqlly, any mo~c uent, a~liti~n or removal of a node may require req~ mrnt andtor .eeo~l~ ion of the network to take into aeeount new power and wo 94/29986 2141613 PCT/USg4/06373 frequency requirements caused by the changes to the network. Such realignment and reconfiguration is typically performed by specialized personnel, and may be expensive.
Many conventional networks, particularly those using infrared or RF wireless technology. require a line of sight between the master node and the other nodes. Finally, convc~Lional nct~ol~ are relatively slow.

SUMMARY OF THE I~V~ "ON
In aeco-d~ee with the present invention, there is provided a link controller foruse in a node of a network. The device addresses the above-described problems, pennits design~ion of a new master when appropriate, pe~nits peer-to-peer 10 cornm~lnira~ion~ is easy to install, is self-configuring, and yields very high data Ll~ c;on rates aeross the n~lwolL
The linl~ eontroller deviee is used in each node of the networlc The deviee ~ eS a radio transcc;~r (101), a digital eontroller (102) for the ll~scei~," and a knowledge-based eontrol plO~sl~ (103) that uses a set of rules to m~int~in the link to 15 the network. The rules have been speeially d~ lopcd to handle eomple~c cit~7~inn.c sueh as iniri~li7~tion, ~cessi~c noise at certain L~ -cs, and loss of a network node. In acco.da~ce with application of these rules to the current state of the network, the control plo6l~ sends insL u.,lions to the digital eontroller s~ccir~ing ehanges to the transmit and reeeive r~ u~ s, ~ ".ic~ - power, and the like. For e~ample, if the system 20 deteets e~ceessive noise, or a nearby neLwo.k eausing i~t~,.r.,nc..ce, at the base band of the nctwu-L the control p-ug-~ may move the base band away from the problematie frequeney. The.cfo.~i, manual reeonfiguration is seldom, if ever, required.
The lcnowledge-based eontrol pro6.~ f7~ s self-inct~ inn The rules allow the eontrol program to reeQgni7~- and take into aeeount various op.~ g 25 ~nom~ during or after inst~ tinn eonfiguration, or reloeation of nodes. In additinn the deviee mnnitor~c and eontrols its power level. under the ~1iun of the eontml program. so as to reduce or eliminate multipath problems automatically, without manual reconfiguration. When necess~ry, under the direction of the control program. thenetwork may use a packet relay to reach distant nodes. In packet relay operation, a packet is sent to a first node. but includes information in the header inl1irating that its in-5 tended destinqtion is a second node; the first node strips part of the header, adds its ownheader, and sends the packet to the second node.
A network employing the link controller device described herein may operate without pcrmanent designq-tion of a master node. A master node may be decign~tedeither perrnq-n~-n~ly, if desired, or dynqmirqlly, so that sehPction of a new master node 10 occurs under certain cirCumc~qnres~ By removing the need for a perrnqn~ntly designq-~Pd master node, the system facilitates improved flexibility and adaptability.
The link controller of the present invention uses mi~,rowa~, tr-ncmic~ion (r~ ucn~ 1 gc and higher), and ~hc.cfol~ does not require a line of sight to commlmicqt~ among nodes. Where possible, the system uses mllltipath to further 15 h~ ro~.~ co~-.;ç~qtion among nodes through walls, floors, and other obstq-rlet All of the above may be accomplished ~qutomqticqlly, without tPçhnirql inc~qllqtion staff. ~d~ nnqlly~ with the inclllcion of robust monitoring surlwal~ and an ~ ,h~ rule-based control plUgl~ll, 51;.t;cl;r5 and configuration i~f,~ ;on may be obtained from various nodes of the system in order to provide the user with q~l~ition 20 instructions or sl)gg~ctionc that may be err~,~h~, in opt;.~ ing the G.,twull~
configuration. These ~shu-,~,ons and suggcsl;ol-~ may be relatively simple operations that can be pc.rullllcd by any user, such as moving a radiator to a wall mount, or qtts~rhing a passive coupler to the ceilillg.
Finally, the present invention is faster than cull~n~ional nclwGl~ nodes. The 25 present invention allows data ~.~sL.:, of at least 50 megabits per second. ~d~it-ion the n~,lwol~ as a whole has at least 28 separate çhqrtn~lc each capable of a transfer rate WO 94129986 21~1613 PCT/US94/06373 of at least 50 megabits per second. Therefore, the network has an effective bandwidth of at least 1400 megabits per second, if groups are formed.
The p,ef~ ,d embodiment of the present invention operates in a wireless network, although it may be used in any other type of co~ r network, including 5 wired and hard-connected networks.

BRIEF DEscR~rloN OF THE DR~WINGS
Figure 1 is a block diagram of a network link controller accoldiug to the present invention.
Figure 2 is a block diagram of a radio transceiver according to the present 10 invention.
Figure 3 is a block diagram of a digital controller acco,ding to the present invention.
Figures 4, 5, 6a, and 6b are directed graph-process diagrams showing the operation of a control pro~,~ acco~ g to the present in~_~iùn.
Figure 7 is a flowchart sLvwing a first method of desi~ing a master node.
Figure 8 is a flowchart showing ,a second method of designating a master node.
Figure 9 shows an e~ample of a data packet format accol~g to the present invention.
Figure 10 is a flow chart showing a F~c~ lc~ ~ccignm~nt Tcch.~i4Lc accoldi-lg 20 to the present ~,~,nlion.
Figure 11 is a flow chart showing a method of m.lltip^~h mq~l~emrnt accoldulg to the present ill~_~ion.

DET~LED DES~ 11O~ OF T~ ~ ~k~ EMsoD~ Nrs A plcfe-lGd embo~ -rnl of the il.._~on uses the lUi~.lU~.a~C portion of the 25 electromq~tir s~ ,~. Mic~u~.a~_s have been found to have certain advantages wo 94/29986 2141613 PCT/US94/06373 over other portions of the spectrum. One major advantage is power efficiency.
Microwaves have relatively low path qtt~nuation~ p~ itlihlg operation with trncmin~r power of less than 10 mW. The use of such low power trqncmitters reduces manufacturing costs.
Another major advantage of microwaves is their Grfc~ ,ness and versatility for data tr~ncmiccion: microwa~cs may be reflected off various structures, and they do not suffer from the same degree of intGlrG~Ilce as do other portions of the electromagnetic ~pc~ ULU.

Transmlc~ S-~h~m~
Refernng now to Figure 1, there is shown a block diagram of a network linl;
- controller 100 according to the present invention. Link controUer 100 provides link level support for a net.. o,L Link level support is defined as the first three layers of the seven-layer ISO network standard. Lin~ level support consists generaUy of the physical layer (layer 1), data link (layer 2), and network layer (layer 3). These layers col.Gs,vond 15 to the bit, frame, and packet protocols, IG;~ 1Y.
Link controller 100 contqinc three major coulponcnls. a radio l,~ce;~c- 101, a digital controller 102, and a l~uu..ledge-basGd control program 103. A radiator 253 (or antenna) is co~ r~t~ d to link controller 100.
In general, transeG;-~,I 101 upC.dt~,S at a LG~IU~n~;Y greater than 1 Gigahertz. In the plGf~ ,d embodim~nt t.~sce;~w 101 operates in the X Band (8.4 to 12.6 Gigahertz). Other LG I~c;es may also be used.
~rf~rrinp now to Figure 2, there is shown a block diagra2n of radio ll~sce;~,r 101 accoldmg to the present ~- .l~on. Radio ll~scc.~,r 101 ;~ ~ludGs a ~l~r.c"~ r section (blocks 201 through 211) and a receiver section (blocks 212 through 216).
The ~ - section OpC~at~,S as follows. Two carrier g~,nc.. lol~ 201 and 204 are used. Chqnn~l carrier gC~C.dlOf 201 ,gcnc.dt~s channel carrier 2S5, and sub-band 21~1613 wo 94l29986 PCT/US94/06373 carrier generator 204 generatcs sub-band carrier 259. Channel carrier 255 provides multiple subchannels within the trqncmicsion band. Sub-band carrier 259 providesmultiple channels within a given subchqnn~l Each of the carrier generators 201 and 204 contains a frequency-agile oscillatorS and is controlled by digital controller 102 using digital control lines 258 and channel selee~ line 268. The three control lines 258 permit eight dir~cleL l eommq-n~lc to be provided to the earrier genc.~tor. Si~c ehannel select lines permit 26 = 64 separate eharmels, although in the plcÇcllcd embodiment, only 28 are used. Seven of thesecomm-q-n~C speeify changes to the frequeney output of the oscillator in the gcnc~ator, and 10 one cnmmq-nd causes the osçillq~or to s~ut do vn.
Channel carrier 255 generated by ch. nnel earrier gc n~ or 201 is fed to data earrier generator 202. Data earrier g~ l~r~AIor 202 uses ehannel earrier 255 along with a data syneh eloek 267 and data signal 2S1 co..li-;..;..g raw data from a digital souree (not shown) to ~U~,~oLU~ the data to the earrier. As deseribed below, a phase loeked loop 15 is employed, wherein a VCO is divided by a variable modulus divider and fed to a phase cGuul,&ator. The phase eoLu~ or CO1UP~GS this signal with a lefçl~--re osç~ or. If the divider modulus is ehq~d. the loop eauses the VCO to ehange L~u~,n.;y uDtil phase loek is established with the .Gfc.enee osçillqtor. By applupliatG seleetion of the divider and .cfG.cncc os~ or~ many dirrc.cnt ch~nnrlc and sub-band sources may be 20 gcll~,.at~,d. The sources thus gcncl~t~,d are then cur .~,lt~d up to the ~ r., frequeney, by any of a number of ~rrhl-;~luGs known in the art, sueh as Lc~ucn~i~
multiplieation or h ~mnnir phase loeking. The result is data earrier 256 eo I~ g earrier-s~ucl~ol~.zcd data Data earrier 256 is fed to data/bi~phase tran~lqtor 203, whieh cull~.b the mono-25 polar signal to a bipolar signal. The result is bipolar data earrier 261.
Me~.. l~ile, sub-band ea~rier 259 gcncl~t~ d by sub-band eamer gcuclalor 204 is fed to h~rnonic phase deteetor 205. Hannonie phase deteetor 20S uses the sub-band wo 94/29986 21416 13 PCT/USg~l06373 carrier 259 to excite a comb gcllc-ator (not shown) that produces multiple harmonic frequencies. Halmonic phase detector 205 also accepts a signal from sub-band carner voltage controlled oscillator (VCO) 206. VCO 206 operates at the fundamental output frequency of the tr~ncmitter~
The operation of the phase locked loop will now be describcd. Hannonic phase detector 205 compares the phase relationship between the signals from sub-band carrier gcnc,ator 204 and VCO 206, and gc~ t~s control signal 260 crJntqining a DC voltage rc;~yonsivG to this comparison. If the relative phasc is zero, then the DC voltage is null.
lf the relative phase is non-zero, then the DC voltage of control signal 260 is given a unique polarity corresponding to the phase rela~,o~sLp. Conol signal 260 is then low-pass-filtered and fed to the voltage control input of VCO 206. Thus, a feedback loop bc~ ,cn harmonic phase deteGctor 205 and VCO 206 is establishcd. This feedbar~ loop forccs VCO 206 to lock to a hq~nonic of the L~u~,n.,~ of sub-band camcr 259. Anydcviation from this phasc lock rcsults in a DC voltagc on control signal 260 that causcs VCO 206 to re-establish phase lock.
The output of VCO 206 is fcd to phasc modulator 208, along with bipolar data carrier 261. Phasc mod~ ,or 208 phasc mod~ s thc two signals. Thc systcm may operate with any number of phascs, employing multi-phasc modu~ on ~chni~lues that arc well known in thc ar~
The output of phasc modulqt~ r 208 is fed to output ~ p!;r.. r 210, which is a gain-controllablc widc band linear ~mrlifi~r. The gain of amplificr 210 is controlled by a control signal from RF power modulator 209. Power modulator 209 ~ c..,t,s thiscontrol signal in lbi~pOn~e tO digital comm~n~lC on ~ power control line 262 from digitàl controller 102. In thc plefe.,~;d cmbo-l-"-c~, digital c~ n~C- 262 are 25 supplied along two lines. onc for "power up" and one for 'powcr down". In accor~ncc with thesc commands, power modulator 209 dctl ....;"- c an app,up,i~ powcr level and WO 94t29986 2141613 PCTtUS94/06373 sends a signal to amplifier 210. Amplifier 210 amplifies the signal from modulator 208 by the gain specified by power modulator 209, to produce amplified signal 263.
Amplified signal 263 is fed to forward directional coupler 211, which samples.
rectifies, and low-pass filters the signal. The output of coupler 211 is an analog DC of 5 the relative power output of amplifier 210. This output is made available to digital controller 102 as a filtered DC signal, shown as antenna power level 266. The output is also fed to circulator 252. Circulator 252 feeds the output of coupler 211 to radiator 253. The purpose of circulator 252 is to isolate the ~l~..c...;~ d signal (going from coupler 211 to radiator 253) from the received signal (going from radiator 253 to filters 212), and also to match radiator 253 to the receiver and trqnsmitte- sections oftransceiver 101.
Thc ,~,cc;~,. section operates as follows. A received signal from radiator 253 passes through circulator 252 and is scnt to bqn~lpqo-s filters 212. Received power level may be i-,ulcascd or de~eqo~d in ,~,sl,onse to signals from controller 102. Filters 212 15 pass all frequencies within the subcq~rier fic.lu.,~ .y range, and e~clude all out-of-band signals.
The signal is then sent to mi~er 216, which employs a direct con~ ion technique to e~tract data from the signal. In direct COu~ iOIl, the received signal has the same frequency as a local oscillqtor; combining the two signals produces a zero 20 Tn~er~ne~iqte F,cqu~,h,_~ (IF). Direct co.,~ ion is a general t rh~ G that is known in the art for a~pli~ n to single oi~lcb~d phase modlllqtinn, or qmrlitvde mo~lllq-tir~n However, for ,~cption of Phase Shift Keyed (FSK) signals only, the system can besubst~nti~lly c;l..r~ d by using limiting ~mplifiers and a digital logic ~ )r.
Such simplifir~tic n limits thc typc of modlll~tirn that the recciver may acccpt, but it 25 results in a relatively ;~e-pc~ dcvicc.
A dircct coll~_.;,;on FSK rcccivcr has a numbcr of advantagcs ovcr a co~ L,onal sur~- h. b,. od~..c ~cc-,;~_..

wo 94/29986 21 11613 PCTrUS94/063~3 o Most of the gain is at a relatively low frequency. resulting in power savings.o A direct conversion receiver has the following cost advantages: it does not require any crystal filters or ceramic filters; the number of coils required is limited; no need for IF tuning; only one frequency source (LO) needs to be set up and controlled, compared to three for a double-conversion sul)clllct (2 LOs and a discriminq-tor).
o A direct conversion receiver produces a much simpler and less troublesome frequency response spectrum than a con~ lional sup~ dyne receiver, due to the fact that a ~upclLct may gc~ atc uuw~t~d sum and difference Lc.lu~ rs for any number of inputs of the mi~cer. In addition, the output of the su~,c.llct may contain higher-order detection products that may introduce u~l~.an~d spurious ~c~ponceC The most signifirqnt such response is image fi~ u~,nc~, which can produce a dirre-Gnce fic~lcncy component. Direct con~cl~ion avoids these problems, because the IF is at such a low Lc~lu~,n~,~ that irnage rejection is ecc~ntiqlly infinite and general IF leakage is çssentiq-lly zero.
In direct conversion FSK, a fun~l^mrntq-l relationship e~ists between the phase deviation and the maximum possible output data ratc. Larger deviations permit wider channel spacing and filter bandwidth, and co~lc~,ondingly higher data ratcs. By providing a digital ~ic., i~ o" thc input data may be ~qmrl~d at tvice the deviation frcquency.
In thc p.cfc.-~,d embodiment, direct col.~ ion FSK is achieved as follows. Thc in~()ming signal, after being filtered, is directed into two chqnn~lc, where it is mi~ed in quadrature with thc carrier frequcncy g.,nclat~,d by VCO 206. The mi~cer output signals are se~ tcd in phase by 90 dcgrccs, ~d arc at a f~c~ c~ cqual to the deviation of the incoming signal. Th~.efolc, when they are combined, they cancel each other out, lcaving thc modulated data carrier 264. The iu~lion could also be p.~iccd with phase sGpa,aL~nc of less than or greater than 90 degrees. Mod~lst~d data carrier 264 is fed to IF variable gain q~mrlifi~r and band pass filters 213, which amplify and filter the 21~1613 wo 94/29986 PCT/US94l06373 signal. Band pass filters 213 provide channel selectivity, while ~F variable gain amplifier provides limiting so that the output can be regarded as digital waveforms. The variable gain of the amplifier may be changed in response to reeeive gain control signal 272 that is genc.~ted by digital eontroller 102. To achieve desired selectivity, band pass S filters 213 must pass the FSK frequeney deviation while attenuating adjacent cha~nel signals by appro~ quly 60 dB.
The amplified and filtered signal is fed to data phase deteetor 214 for digital demodulqtion Data phase deteetor 214 deteets the lag or lead relqtionchir among the ehannels, by eomparing the phase of the signal with the phase of lcfc,cnce signal 254 10 from ehannel earrier genc.~lor 201, whieh does not eontain any intenhonql phase modul~tinn Data phase deteetor 214 is able to seleet among various f~ eneies in cfc,cnce signal 254 in order to demodulate any of a number of ehqnn~lc of data for a given sub-band earrier. The reeeived signal from 213 is phase mod~ d by the ,ecei~d data. Thus, when these two signals are eo~p&~ed, the result is the ,ceo~cled 15 data base band. Phase deteetor 214 outputs this data base band in NRZ format, in the form of DC signal 265, the ~ ..r1;L.~clc of whieh is direedy related to dle phase re1q~ionchip between the rceeived signal and the ,c~ ce signal.
DC signal 265 is fed to data shaper and output driver 215, whieh, COnSL~u-.;l the shape of the ..~ foll,l aeeo~ g to urhni~lues that are known in t_e art Recovered 20 data is sent along data out linc 269. Data shaper and output driver 215 also may dcc.~idse the rise time and fall time of the ~ ,Çol~ edges, and adjust output levels ae-cording to the l~ r.,~l~ of the digital logie that output driver 215 feeds. Data eloek r~o~ blûek 270 rC~u~_.S a eloek signal from the data, and L~lnilS it on line 271.
The base band of ~ c. 101 is ndj~t~d by i lcleasi~g or dee,casin& the DC
25 bias voltage to a varaetor. A greaur voltage lowers the fic.lu~ y, and a Iesser voltage raises the fic.lucn~

wo 94/29986 2 1 4 1 6 1 3 PC~IUS94/06373 Transceiver 101 is able to provide several data channels. Each data channel is separated by approximately tWO times the bandwidth of the data. The tr~ncmitPr section of transceiver 101 selects a data channel by switching active elem~nLs in the resonating portion of the transmitter to move t_e center of the base band by the5 appropriate bandwidth offset. Since the IF is produced by combining t_e incoming signal with the transmitter frequency in mixer 216 (see above in connection with Figure 2), t_e receiver is able to track the received signal.
Radiator 253 may be of any type known in the art, includiog an omnidirectional lensing radiator or a slotted waveguide radiator.

10 MUII~h MPr~m~
~ tip?th occurs when radio fl~u.,ù~;y waves reflect from the surfaces of physical objects. These reflected waves may be ~,dutut~,d in a path that may differ from the path of the incident wave. Repe~d refl~ctionc often result in a comple~c pattern of il~Lc~fG~h~g ellc~,~d waves.
A receiving antenna e~posed to such a couuplc~c pattern may receive multiple inct~nceS of the same signal. The multiple ;ncl;~nrcs of the signal are typically phase shifted with respect to each other, and ~t~.... t' d to varying ~egrees, depen~ling on the reflecting surface and the distance traveled.
In con~Gnlional systems, mllltip^~h may present an iutclrclence problem in that 20 it may be difficult to Ji~- t;~;n ~- the primary signal from reflected signals. This p-utle~u is particularly evident in systems employing ~...pl;~.,d~ mod~ tion The p~erG.-.,d emboAim~nt of the present invention operates in a wireless n~,twoll. that employs phase modlll~ti- n, whereio average f.cqu~,n-, ~ over 360 degrees of c~ ~uction does not change. Only the instantaneous r~ucn~;y is c~n~g~d Thus. the25 system is able to dic ~ tc between t vo signals that are eALIeu-ely close in frequency and ~nplinl~lc Generally, primary and .eflcet~d signals are very close in fl c.lu.,uC)/, so wo 94/29986 PCT/US94/06373 that the difference frequency (the "beats" caused by i~lte,r~.cilce between the signals) is low.
Referring now to Figure 11, there is shown a flow chart of a method of multipathmanagement according to the present invention. After packets are prepared 1102 for 5 tr~ncmiccion by the tPncmitting node, the first packet is tr~ncmi~tPd 1103. An oscillator in the receiver is phase-locked to the strongest of the primary or reflected signal 1104 with a slew rate or loop band pass filter that will not permit locking to the inte.r~ g signal. Thus, the primary and reflected signals may be readily distinguished from one another. The oscillator locks onto either the primary or the reflected signal, as either is a 10 valid signal as long as they are not both p~u~_essed at the same time. In fact, two (or more) signals may be processed ~lt~rn~t~,ly with no d~ lcn~l effect on signal quality.
In general, the system of the present invention uses primary signals where possible, but is capable of ~wi~hing to reflected signals when the primary signal is blocked or unavailable. Once the receiver has alb~up~ ~ 1105 to receive the packet, it checks 1106 15 to see if reception was su.icec~rul. If not, it ~wi~hcs 1107 either from a direct to a reflected signal path, or vice versa if it was already using a reflected path. The tr~ncmittmg node then re-t-~s~b 1108 the packet, and the receiver again altu~lJb1105 to receive it. Once the packet is ~ucccs~rully received, the ll ;~n~ ;U~ proceeds to transmit 1110 the ne~t packet, and the process is repeated until there are no more pack-20 ets.
In order to ensure that the reflected signal is not proccssed when a direct signalis available, the device of the present invention sel~;~ ,ly reduces l,~--c-";~, d sig~
powcr using software control, as follows. When a direct signal e~ists, the phase locked loop will never lock on the ,eflc~d signal, since it always locks on the sllullgesl first-25 received signal. The reflected signal will never arrive before the direct signal, sincerçflec~ionc travel a greater distance. It is lcnown that the signal power of a reflection is always less than 50% of the signal power of the direct signal. Thus, the system can WO 94/29986 21 g 1613 PCT/I~S94/06373 ensure that only the direct signal is received and processed by reducing the transmit power level until the reflected signal is below the minimum detection level of the system. Thus, the phase locked loop will lock only on the direct signal. If there is no direct signal, and only reflected signals exist, then the phase locked loop will lock on the 5 strongest reflected signal.
The tr~ncmit*ng node is responsible for adjus*ng power levels. Power levels are controlled and adjusted by digital controller 102 of the tr~ncmitting node, using digital feedba~l~ information found in the Sender State Records of the packet header, as described below.
Each data packet is short enough to be tr~ncmitt~d faster than the radio frequency eî~vhu~ ent can impose changes that would cause the phase detector to lose its lock. The factors that generally cause loss of lock are physical mo~,cl,.ent of nodes, or a change in pl~çm~n- of solid objects. Such physical l.lo~,~l,.cnt may be considered rapid in human terms, but is still slow enough for the system to avoid loss of lock.
For example, suppose 100 blocks of data are to be tr~ncmitt~d Initially, the phase detector of the rccei~,~,. Iocks onto the primary signal. After data block 20 has been received, the primary signal is obscured, so that only a reflected signal is of suffici~nt signal strength to be received and understood. The phase detector locks onto the reflected signal to the e~clu~;o~ of the prirnary signal, so that even if the primary 20 signal became available during trancmic~i~n of data block 21 (or any ~ubs,~u~ -t data block), the rece;~cr will m~int~in its lock on the Ienc~t~d signal for the r~m~in~ r of that block. As described above, if the reflected signal is int~l.u~ during a data block, the t.~ c..,;ll;.,p node will re~ the bloc~
As flc.lucnc~ Se~v&aliOn of the two signals incleascs, diC~ n beco~cs 25 more difficult. A band pass filter with sharp cutoff is employed to al r~ ~m ~r. the out-of-band signals ~..rr..~ lly~ so that they do not cO...~! with the primary signal. This technique is successful only if the pass band is relatively narrow for the relationship between the primary signal and the reflected signal.

D~t~l Corltrol~
Referring now to Figure 3, there is shown a block diagrarn of digital controllerS 102 according to the present invention. Digital controller 102 includes digital-to-analog and analog-to-digital c~ , as well as digital I/O lines, all in block 501, to measure inCQming signal strength, to provide voltagcs necded by the t~ section of tla~ei~cr 101 to vary the power output of the t~ scction, and to sclect thechanncl. Con~el tel~ 501 accept power level data along line 266, and provide comm~n-ls 10 along ~rancmittrr power control line 262, rcccive gain control line 272 and channel select line 268.
An 80286 Illicropl~1ccssor 502 performs ylu~cS~ g o~,~;. nc, using ~danl random-acccss memory (RA~ 503 and standard read-only memory (ROM) 504.
Clocks 505 gcncla~ clock signals for usc by various parts of controller 102. Bus15interf~ce 506 handles address dccodes, comm~n~1c, and timings betwecn controller 102 and the computer to which it is atr~hed (not shown). AT glue chip 507 handles memory timings, iLuplcmc~b DMA, PIC, timers, and the like, that make up an ~BM AT.
Bus latch 508 latches data betwecn local bus 509 and PC VO bus 510. Local bus 509 ties together and allows co~ u~ir~ti(nn among other coll-poncn~, while PC I/O bus 20 510 lc~ ;se~ a standard bus for an IBM PC AT.
Rec FIFO block 511 reccives inr,oming ~.cembled bytc/word data from I/O
Dccodc block 51~, and buffers high speed inromi~ data until CPU 502 checks for packct validity. Once the check has been pc.r~JI..~cd, block 511 empties the data into RAM 503.
25Receive control logic S12 detects the start of ~-~ '~rs performs parity checks, detects packet errors and packet length, assembles byte/word data for Rec FIFO S l l .

wo 94l29986 PCT/uss4/06373 Block 512 also contains FIFO strobe logic. Receiver shift register 513 accepts data on line 269 and clock on line 271, both from transceiver lOl, and gates the bits.
Xmit FIFO 514 contains a packet to be transmitted. Xmit control logic 515 generates the synch header. parity check, transmit enable, data synch clock out, and S strobes for the FIFO and xmit shift register 516. Xmit shift register 516 provides the serial data to transceiver 101 along line 257, synchronized with data synch clock out on line 267.
VO decode block 517 provides the VO address decoding for various output/input ports. Memory decode block 518 is used for FIFO-to-memory and memory-to-FIFO
10 operations.
Shift register 513 receives an incoming data signal from the Data Out line 269 of the receiver, also in~ic~ted as Serial In line 269 in Figure 3. Shift register 513 also receives a data synch clock from IGco~_rGd data clock line 271. Data is ~,co~G..,d from the data signal on line 269 by clocking the signal into shift register 513, and pC.Çol.l.illg 15 a pattern match to ~llc~oniLG the ;.~o...;ng serial stream into discretc bytcs. The bytes are then gated to Rec FIFO block 511 when the end of the synch header is reached, as is known in the ar~

Fi,.. ,.~ie 0~ . c.
Digital controller 102 also cont~inc firmware, which inrludes a small multi-20 tasking p.cc...~ti~, kernel. The kernel providcs a single-thrcadcd proccss e--vir~,~ent that allows inter-process co.. ~ ;on and s~hl~d~lling The rl~w~c uses thc proccss e-lviro~c.-L to facilitate a ~u~;lwcd hicrarchy of interrelated coopc.~ p.uccsses to ,,,;nh,,;~. int~..u~" latency. Ploccsses may wait for an event, pass m~Ccagr.c t_rough a monitor, share code, and delay themsclves in process 25 qucues awaiting s~h~d~ ng and/or resources. This methodQlogy is well known in the wo 94/29986 PCT/US94/06373 l 6 art. and is described in Per Brinch Hansen. Concurrent Pascal Re~ort, Information Science Department of the California Institute of Technology (1975) The monitor is a shared process resource that allows only one process at a time to access the code and data. Processes that invoke a monitor are blocked, and must wait 5 in an entry queue for the current process in that monitor to leave or delay itself in a local monitor-controlled process queue.
Code is shared among processes by making all process, monitor, and class code re-entrant. Class code consists of shared process routines that have their data instance in the declaring process. Monitor inc'~nrçs are part of the Initial Process (see below) and 10 are outside the scope of all other processes.

Kernel The following primitives are used to implement the various el....- UL~ of the kernel: Initial Process, Init Process, Init Monitor, Init Class, Enter Monitor, Leave Monitor, Resume Process, Delay Process, I/O Interrupt Process, Ready Queue, and 15 Execute Process. Each of these will be described in turn.
Initial Process: This process contains three main parts: power up and self diagnostic test (POST), creation of multi-process data ~LIu-,lulcS (monitors andprocesses), and creation and assumption of the identity of the cu--c~ly running process.
The POST tests the in~6lily of the CPU, memory, controller circuits, il,t~,.,ul~l 20 controller, and setup for the download of the operating c.-vilu~Luenl from either the host processor or the ROM file. The creation of multi-process data SlIUCIUIGS consists of a series of calls to inhi~lir~ class, monitor, and process data ~I-u~ ucs. It also places the defined child processes in the ready queue and sl~h~d~ s these p.ocesscs for eS~CUtinn The Initial Process ~csnm~s the identity of each child for e~uti-~n ~ ,oscs.

wo 94/29986 2191613 PCT~ss4/063~3 Init Process: Allocates a stack and data area for a process stack. Passes the address of any and all monitors shared by that address. Sets the entry point for the process, and queues the process for execution.
Init Monitor: Allocates the private data area for the monitor and calls the 5 initialization code of the monitor.
Init Class: Allocates the private data area for the class, and calls the ini-tialization code of the class.
Enter Monitor: Serializes entry to the monitor. If a process is already ir~ the monitor, then the invoking process is queued in the monitor gate queue. Otherwise, the 10 gate is closed.
Lea~e Monitor. Enters a process from the monitor gate qucue in the ready - queue. If no process is present in the monitor gate queue, then the monitor gate is opened.
Resume Process: The process in thc specifi~d process queue variable is placed 15 at the end of the monitor gatc queue. This run.,L,on is only allowed in a monitor.
Delay Process: The process delays itself in the process queue variable specified.
If the monitor gate queue is not empty, then the first process in the monitor gate queue is placed in the ready qucue.
1/0 Interrupt Process: A formless process that preempts the ;u~c~ly executin~
20 process eithcr partially or fully.
Ready Queue: A threaded list of plVCCSSCS that are to bc ç~cut~d in first-in first-out (FIFO) sequence.
Execute Process: ~int~inc the cullc~llly e~ecu'ing process. Sets some global variables when invoked. When no child plOCCSSCS are running, the Initial Process is 25 running.

wo 94/29986 PCT/US94/06373 The above-described primitives are used to implement the kemel. Referring now to Figure 4, there is shown a block diagram showing the structure of kernel 600, and its various elements. Each of the elements will be described in turn.
Class P_FIFO 601 is a FIFO queue to hold background processes awaiting 5 execution.
Class T_FIFO 602 is a FIFO queue to hold processes awaiting expiration of a timer to resume execution.
Class IO_FIFO 603 is a FIFO queue to hold p-ucesses awaiting certain inputloutput evcnts.
Monitor WAll_Q 604 sllspen~lc and resumes processes held in class P_FIFO
601, according to comm~n~C from process TIMER TASK 611. WAIT_Q 604 is used for primary time slice ~rh~dllling of bac~g.uund pluces~cs.
Monitor READY_Q 605 is a FIFO queuc of processcs sçh~d~ d for execution.
Monitor EXEC 606 is thc uu~cn~y esecutirlg proccss.
Monitor TIMER 607 coordinates timer events and timer sch~dnlinE among interrupt process ALARM 610, inlC~l UIJt process TICK 612, process TIMER_TASK
611, and process IO_TASKS 613. Monitor TIMER 607 sllcpcn~c prûccsses TIMER_TASK 611 and IO_TASKS 613 that use illtc,lu~ll pnucesscs TICK 612 and ALARM 610 to rcsume eSc~lltion for timings, fault d~,t~ ;on, sçh~dlllin~, and the 20 like.
Monitor IO 608 schedules process IO_TASKS 613 from intcrrupt process INT
614.
BACKGROUNDS 609 includc5 a numbcr of proccsscs that run pcriodically to monitor and/or control thc systcm, including a simplc.~ proccss, di~n- stiC process, and 25 an awareness proccss. BACKGROUNDS 609 also includcs thc following plvcessos:

wo 94/29986 2141613 PCT/US94/06373 SPATIAL_WATCH: Gauges vectors between nodes (ranging in effect) This process uses a linear algorithm. similar to simplex, to compare all internode signal strength pairs to generate a rough estimate of direction and dic~n~e XMIT_LEVEL_WATCH: Prepares data for the simplex algorithm.
S This process monitors ch~nging signal strengths as found in received packet headers.
NODE_WATCH: Prepares data for the simplex algorithm. This process monitors packets and notes when nodes have disappeared from the network.
DIAGNOSTIC_WATCH: Monitors errors in packets and provides some inforrnation to the simplex algorithm.
STATISTIC_GATHER: Organizes node and system statistics for pres~ A~;on to the PC in various formats.
Interrupt process ALARM 610 is a timeout Lut~-lupl generally used for long-term sch~!duling or for fault d~t~ctis~n Process TIMER_TASK 611 implements the coarsc sçhçduling control of the systcm, and also handles the packet timeouL/,el,~ controls.
Interrupt process TICK 612 is a periodic timer inputloutput process.
IO_TASKS 613 inrlvdcs a number of p,uccsses that handle input/output operations. These processcs use monitor IO 608 and monitor TIMER 607 to await "watchdog" iL~t~ll upt events.
Interrupt process INT 614 is a generic formless LU~ Upt process of the hardware.
L

Timer Inte~ace The firmware relies upon interrupts to perform operations. A key in~upt 25 colllpûn~,n~ is a set of timers that perform mess~e re-s~n-ling, status ch~r~ing, and some process sçh~!dvling-wo 94/29986 PCT/US94/06373 Referring now also to Figure 5, there is shown a tirner interface 640 according tothe preferred embodiment of the present invention. It includes the following elements.
Interrupt processes IOTICK 641 and IOALARM 642 are equivalent to hltcllu~t processes TICK 612 and ALARM 610, respectively. These hlkll~llJt processes are S activated by intel~t~ and pl.,cmpt the cul~cntly ex~cuting process. Once activated, they enter monitor TrME 643 and schedule process TIMER 644.
Monitor TIME 643 is equivalent to monitor TIMER 607.
Process TIMER 644 is equivalent to one of the processes in IO_TASKS 613. It provides timed watchdog operation for various other pl vcesses through monitor WATCH 650.
Process WATCHER 645 is equivalent to one of the processes in IO_TASKS
613. It coordinates data transfer to and from the PC, as well as transmit and receive data mo~ t. It activates intu.lulJl process ALARM 610 (for long-term events sueh as packet retr~n.cmi.csion) and handles the short-term free-running timer ticks (for short-term events such as proeess RECEIVE_DATA 647 and other VO l,llleoub).
Process REC_TO_PC 646 is equivalent to one of the pl vcesses in IO_TASKS
613. It handles received packets to the PC.
Process RECEIVE_DATA 647 is equivalent to one of the plvcesses in IO_TASKS 613. It handles in~oming data from Rec FIEO 511, filters the data~ queues it for process REC_TO_PC 646, abstracts control information, and creates tables for use by some of the processcs in BACKGROUNDS 609.
Process XMIT_DATA 648 is equivalent to one of the pn)cesses in IO_TASKS
613. It forms the data paekets, loads Xmit FIFO 514, and enables the channel andL.~lllit cloc~
Process XMIT_FROM_PC 649 is equivalent to one of the ploccsses in IO_TASKS 613. It controls data coming from the PC.
Monitor WATCH 650 cool.linat~s DMA, PC bus, and FIFO usages.

wo 94/29986 2141613 PCT~S94/06373 Transmit Processing Referring now to Figure 6a, there is shown a transmit processing block 660 according to the present invention. It includes the following elements.
Process XMIT_FROM_PC 649 is equivalent to one of the processes in 5 IO_TASKS 613. It controls data coming from the PC.
Monitor WATCH 650 coordinates DMA, PC bus, and FLFO usages.
Monitor PC_BUS 661 controls the access of PC I/O bus 510.
Input/output process BUS_ACT 662 handles PC ...tc,, ul,ls.
Monitor DMA 663 controls access to the DMA channel.
Input/output process DMA_INT 664 handles DMA terminal count ihl~,lupt.
Process DMA_XFER 665 handles all DMA setups and tennin~tions.
Interrupt process XMlT_INT 667 is the transmit FIFo empty in~~ process.
Monitor XMIT_Q 668 delays process XMIT_DATA 648 pending an interrupt.

Receive P~ .g Referring now to Figure 6b, there is shown a receive pn,cess~g block 680 according to the present invention. It includes the following elem~ntc Process REC_TO_PC 646 is equivalent to one of the p,ucesses in IO_TASKS
613. It handles received packets to the PC.
Process RECEIVE_DATA 647 is equivalent to one of the p-ucesscs in IO_TASKS 613. It handles in-~oming data from Rec FIFO 511, filters the data, queues it for process REC_TO_PC 646, abstracts control information, and creates tables for use by some of the processes in BACKGROUNDS 609.
Monitor WATCH 650 coordinates DMA, PC bus, and FIFO usages.
F.l~.mrnts 661 through 665 are equivalent to the co.,~,on~ing elements in Figure 6a Input/output l~ Jt process CARRIER 681 in(li~ætrs receive data incoming.

214161~
wo 94/29986 2 2 PcT/uss4/06373 Monitor REC_QUE 682 controls the queuing of received data in FIFO and status results.

PC inter~ace The PC interface (not shown) includes processes sharing the DMA and register 5 interface to the PC bus. The status and control register is updated by a process, in order to ensure consistency (i~ltcllu~L~ are off). The cnmm~n~l register is handled by a single process whieh activates the appropriate process to handle processes REC_TO_PC 646, XMIT_TO_PC (not shown), DIAGNOSTIC_WATCH (part of BACKGROUNDS 609), and STATISTIC_GATHER (part of BACKGROUNDS 609).
The data is transferred to and from the PC via D,MA from the local memory of link controller 100. Blocking occurs on these processes to allow serial access to the DMA rh~nnrl The register interface consists of the following:

I~i~r Tv~e Off.c~t Use Status and Read/write 0 Error inr~ic2tinn~ interrupt con-liti~mc pr.nrling, Control byte int~.race busy, int~ u~Jt status Command Write byte 1 Command to perform Data Readlwrite 2 Data in and data out (configuration, received word paekets, ~ d paekets, and the like) The PC status/eontrol ;l~br!~ ri ~e is m~ d by proeess DMA_X~:ER 665. This proeess is &clivat.,d by any of the following:
o an illt~llupl that is gcnclat.,d wL,u~ ,r the PC writes a bit in the ;~t - r.~ ~c;
o eompletion of a L~ pael~et culu~ l~r~ or a reeeive pac~t SC~v~ `G; or o de~eti~n of a fatal error.

wo 94/29986 2 3 PCT/US94/06373 The process then sets the appropriate bits in the interface to generate an interrupt on the PC side. The PC status/control interface consists of the following:

Bit # Use 0 Reserved, reads 0 Read l; reset controller (hard reset, enters boot se~lu~nce, all local controller memory lost, all status bits cleared); clear to 0 when finished with reset 2 Read 1; perform comm~nd: clear to 0 when CQmm~nrl finishcd 3 Reserved, reads 0 4 Write 1 when fatal (irrecoverable) error occurs; error code is placed in data port Write 1 when transmit packet operation complete; write 0 when all transmit packets status read ("~et local status" comrnand complete) 6 Write 1 when receive packet pending; write 0 when all receive packets read and/or flushed ("~et local status" comm~n~ complete) 7 Write 1 to enable i[~lCllU~ to PC; clear to 0 to disable int.,llu~J~

S The PC ope.~tcs on the intcrfacc by writing to the comm~n~ register and setting bit 2 to alert the controller. After the controller has completed the comm~ , it clears bit 2.

The comm~n~ register accepts a single byte as a comm~nd and ad~lition~l data 10 for the comm~n~ through the data port. Return inform~tion is gene-ated to the data port.
The following table describes the available Comm~n~15 wo 94/29986 PCTIUS94/06373 Command Value Description No Operation 0 Do nothing; no return value ResetAII I Reset entire controller Reset RX 2 Reset receiver hardware and processes Reset TX 3 Reset tr~ncmitt~r hardware and processes Get Local Status 4 Get local controller status Get Net Status S Get network status tables Transmit Packet(s) 0~N6 Transmit N packets (N ranges from 1 to 15) Receive Packet(s) 0xN7 Receive N packets (N ranges from 1 to 15) Load Program 8 Load program to process Write Memory 9 Write data to specified memory area Read Memory 10 Read specified memory to ;.. t~ . ~ee A description of each comm~n~ follows:
No Operation: Causes no operation to the controller e~ccept to write a 'YD"
pattem in ASCII to the data port ResetAII: Causes a reset of the operating environ.
Reset RX: Flushes all receive buffers. Activates any and all network resyneh filnction~ Once c~ -pkted, clears bit 5 in the status register.
Reset TX Flushes all pending transmit buffers. Any pending buffers are considered lost, even if reeeived at the other end. Forces a resynch with the network.
Once completed, clears bit 6 in the status register.

wo 94/29986 2 5 PCT/USg~/06373 Get Local Status: Returns inforrnation about transmit and receive buffers in thecontro Ier. Data forrn t at the data ports is:
# of Bvtes Descri~tion 2 Length in bytes of rem~ining fields Number of transmit packet records (N) 3*N Transmit packet records. The first nvo bytes in each record is the ID as set in the transmit packet; the third - byte is the status Number of receive packet records (M) 2*M Receive packet records.

Get Ne~ Stah~s: Returns the status table for the network. Data format at the data 5 portsi~:
# of Bvtes Dcscl;~Jl;~n 6 This Node ID (EEE 802.3 style) In resl,onse to the ~fo....~l;on provided by the GetLocalStatus and GetNet Status comm~nAc~ the local drivers in the PC at the node may instruct the user to perform some action in order to ilJly~o~., network co.. U~.;ra~;on These instructions 10 may be relatively simple upc~lions that can be pclr.lmcd by any user, such as moving a radiator to a wall mount, or a~^^hing a passive coupler to the ceiling.

wo 94/29986 2141613 PCT/US94/06373 Transmit Packet(s): Packet data is transferred to local memory from the PC.
Data format of the pac cet from the PC is:
# of Bvtes DescriDtion 2 Length in bytes of remaining fields 2 Transmit packet ID (used for return status) 2 Transmit control word 6 Destination node ~D (EEE 802.3 standard) 6 Source node ID (IEEE 802.3 standard; filled in by controller) 2 Length of packet in bytes (N) Type of packet N 0 to 1590 bytes of user data Receive Packet(s): Packet data is queued in local memory. The PC driver S ~ct~ çs the number and size of the queued packets from the Gct Local Status fields.
The PC issues the comm~n~ including number of packets, to get one or more packets.
The PC gets the high part of the c~ mmP~ byte, then awaits comm~nd complete status.
Then, -he PC reads th~ packets from the data port. Packet data format is:
# of B~s DescriD~inn 6 DC~ ;on node ID (EEE 802.3 standard) 6 Source node ID (EEE 802.3 ~ndald; filled in by controller) 2 LenBth of packet in bytes (N) Type of packet N 0 to 1590 bytes of user data wo 94/29986 21 4 1 61 3 PCT/USg1/06373 Load Program: Invokes the controller's loader. Optionally passes execution to the loaded pro~ram. Data format is:
# of Bvtes DescriDtion 2 Len~th in bytes of rem~inin~ ficlds 4 Load address (offsct: se~ment form) 4 Startin~ address (0x~F: load only option) 2 Number of relocation offsets (N) 2*N Relocation offsets M Loaded pro~ram Wnte Memor~: Allows the PC to write to any por~on of the controller's 5 memoy. Dataformatis:
# of Bvtes DescriDtion 2 Length in bytes of rçm~inin~ fields 4 Write memory start (offset: sc Illcnl form) 2 Number of bytes of data to be written Read Memory: Allows thc PC to read any portion of the controllcr's memory.
When the command has been acc~ . the PC reads the data from the data port. Data format is:
of B~,rtes Dcs.";.~ n 2 Len~th in bytes of rem~inin~ fields 4 Rcad memory start (offset: se~mcnt form) 2 Number of bytes of data to bc read Returned Status Codes: Data fonnat for status codes returned in data port is as follow:
Value DescriDtion 0 Operation OK
CommAnd not recognized 2 Insufficient memory for operation 3 Data format error 4 POST - ROM ch~L ~ " error POST - RAM integrity error 6 POST - FIFO error 7 POST - Control ~h.,.~ error 8 POST - Radio self test error Packet sent and (optionally) ,~,cci~cd 81 Packet queued for sending 82 Packet being sent 83 Packet send time out 84 Packet dcs~ ;on not responding Transmit nucess~s The l.A~,~ proccss,s form packets to be tlAIIC''';u d over the radio. Packets S are obtained from the PC commAnti process, fonn~ d for s~n~ling, and are sent one packet at a time. Each packet is then queued in a hold queue, until one of the following occurs:
o Acknowled~n~nt is received: packet is released. Required acknowle-lgJnl-.nt is specifi~d in the packet control inform~tion from the PC.

wo 94l29986 21~1 61 3 PCTIUS94l06373 o Timeout occurs: packet is retransmitted, unless the retransmit retry count is exhausted. When exhausted, the packet is released. The retransmit retry count isspecified in the packet control information from the PC.

S The transmit processes operate as follows:

Packet Data to Serial Out: Process TRANSMIT waits in the XMIT_DATA_IN
monitor for activation. It takes the pasced packet, registers it, adds the header for the radio and adds it to the end of the ~l~O stack in the XMIT_MON monitor. It then 10 registers the packet as being queued in the LOCAL_STATUS monitor and re-enters the XMIT_DATA_IN monitor for morc packcts.
Process SERLAL_OUT waits in thc XMIT_MON monitor for activation.
Activation occurs when a packet is placed in thc transmit FIFO stack by the TRANSMIT process, by the CARRIER_INT_IO, or by the SERLAL_OUT_F~:O_INT
15 activation. These p~ucesses activate SERIAL_OUT and, dcpcnJ~g on thc type of activation, SERIAL_OUT perforrns the following functionc cQntinl]ously:
o If transmit scrial FIFO stack is empty and a packet is queued, load the packetinto the FIFO stack and mark it as being scnt in the LOCAL_STATUS.
o If t,~cs~l scrial FIFO stack is loaded but data is not bcing ~ .c...;l~. d and20 CARRIER is not prescnt, set band and channel and enable ~ ;on o If transmit scrial FIFO just emptied (data has bcen ~l~..c...;lt.,d), then thepacket is queued in thc XMIT_WAIT monitor, and the packet is marked in the LOCAL_STATUS as having been sent and awaiting ackno~vledgJn~lt Packet Send Hold~Acknowledgment/Retry: Process XMIT_HOLD handles the ~.... .....iccion.c. It is activated from the XMIT_WAIT monitor by either anacknowll~dgJn~nt or by a TIMER_ALERT signal from the timer subsystem. If timeout wo 94/29986 2141613 PCT/US94/06373 retry is requested for a packet in the holding queue, then the packet is resubmitted to the XMIT_MON monitor. If retries are exhausted, then the packet is released and LOCAL_STATUSis posted for error. If acknowledgment is requested and received, then LOCAL_STATUS is updated with the proper completion code. If no 5 acknowlrdgmt~nt is requested. then the packet is released and LOCAL_STATUSis updated appn,~iately.

Receive Prucesscs Serial-In to Packet Data: The process checks the length of the packet and other error indications to verify packet integrity. If the packet is found to be valid, systcm 10 inforrnation is registered and if the packet is for this node, it is passcd to process REC_TO_PC 646.
Tnroming data is rcccived from the FIFO stack via DMA channcl to local memory. When thc packct has bccn fully reccivcd, or when rcceive overrun, receive underrun, parity error or ECC error occurs, an interrupt is gcnclat~d.

15 Control Pro~
Control program 103 is a statc mP~hin~ that lllOni~Ul~ the statc of digital controller 102 to which it is conn~ When the state of digital controllcr 102 ch~e~, control program may issuc comm^n~ls regarding reconfiguration of the nctwor~

20 Kr: ~ledg~ Bascd Expcrt Sys~4m In order to gencratc and issuc such comm- ds control program 103 consists of a knowledge-bascd c~cpcrt systcm, inrl~ an i''rc.~incc engine and a set of rules. As is known in the art of e~pcrt systems (sce Balr and Fçi~ m Th~ n~lh~ ok of WO 94129986 2141613 PCT/lJS94/06373 Artificial Intelli~ence), the inference engine accepts a set of input data representing a state description. In the present invention, such input data may include, for example:
o Object descriptions: node i~entifiers, network identifiers, ranges of DACs.
packet formats for node communication, sub-network definitions;
S o Event descriptions: comrnunication attempts between one node and another, responses to queries, adjustment of operating pdla,llc~.~;
o Performance data: data throughput measurements, signal strength, unacknowledged packets in~lirqting loss of communirq-tion o Meta-knowledge: measured information on average signal strength as related to distance, mul~p~q~th characterizations, obstacle insertion and removal, types of signal loss, likelihood of noise band avoidance by moving base band.
Many of the rules are heuristic and dynamic in nature. Data and rules are ,ep-1sentcd in a variant record approacl~, as is known in the art of language compiler met objects. For each rule, the variant record appruacll describes the type of rule, its use (such as timed, absolute, observational, or creational), its dcp~ 1c~- ;e on other rules, probabilistic p,ul c.lics (to define "fuzzy" rules), and child rules.
Additionally, one set of rules may be decigr qted for appliration to certain configurations (such as a factory inctqllqtion where t_ere is a great deal of steel near the network), while another set of rules may be deci~q~rd for other cûnfigurations (such as a conventional office installatiûn).
Rule pruning may also occur, acco.dillg to ~ ucs known in the art, to simplify or limit the number of rules.
F~mrlr~ of rules are as follows:
o Event: packet to node X is sent at power level 0.9 of full power and received o Event: packet to node X is sent at power level 0.2 of full power and received wo 94/29986 2141613 PcTluss4lo6373 o Fact: if two or more power levels are found to node X, then an inte~ lGnt obstacle exists o Performance: packetpowershouldbeminimi7~d o Meta-rule: first try low power, then high power; also, deterrnine hit frequency on low power; if hit frequency is greater than a certain peruentage, then reverse the rule, to first try high power, then low power The il~Çe~ence engine applies the rule set to the state dcsc,i~tion col,G~ponding to the current state of the network, and gcnel~bcs a set of outputs co"~,sl.onding to reconfiguration commqn~C for the network. The control program may permit addition, 10 deletion, or mo~lifira~ir,n of the rules. The engine typically uses goal-oriented baektracking reeursive descent algorithms, as are known in the art. The rules typically consist of a series of "if then" s~t~ r~ , and are inbc~ ctl~d using forward chqining mrthrJdology. State dcsc-ipLions may be defined in terms of probabilities assoelated with the defined goals of the iufc.~nce engine. Thus, a teehnique known as "fu77y"
15 logie may be impl~ t~
The knowledge-based system is used to reduee the input data set to a set of relatively few outputs. Eaeh output forms a series of eommqnflC to be applied to the network. In some si~ua~ nC, where more than one output set is generated, indieating more than one possible eonfiguration for the network, the system may try eaeh of the 20 outputs, apply a pc rw~anee metrie to measure the relative sueeess of the eonfiguration, and feed baek the results of the performq~lr~ metrie to the kuo..ledge-based system's rule set in order to refine the eonfiguration proeess. Thus, the eontrol p~Ug~LUI 103, inrlUAing the knowledge-based system, provides the link level support for the n.,lwo~L
The eontrol pro~ requires that one node's digital controller 102 be 25 decignqtrd as the master. The master dietates the fic~lucnc~ used in the network to the other eontrollers 102. Other eontrollers 102 adjust their ~c.l"v~ s to mateh that of the master. r~e.lucn~;~ a~ ,C~ is aceo...pli~l-rd in a eo"~c.llional manner by ch^-~n,~ a wo 94/29986 2141613 PcTn~ss4lo6373 DC bias on the "cavity" resonator using a digital-to-analog converter (DAC) under the control of the software. By performing such adillstmçllt-c~ the network compensates for frequency drift.
Thus, the present invention employs an inexpensive method of frequency control 5 wherein a common communication &equency is established by a master and followed by all other controllers 102. This method provides the ability to easily move the frequency to another band in order to avoid noise and in~lre~ ce with other networks or comm~lnir~tion bands. The method also f~Gili-~t~s establi.chmrnt of a secondary comm~lnic~tion frequency for a deci~nqted portion of the network. This secondary10 commnnic~tion r.e~ ,ncy is accomplished using a second tuned "cavity" that is switch-able under soflw~e control.

In~ r~
The initi~li7~ion process for each digital controller 102 consists of two parts:power-on self test, and node insertion into the networ~
The power-on seLf test performs standard controller i"~ checks (including ROM, RAM, control section ve ifir~tion and radio chccLoul). The node insertion step consists of lirte.nin~ to the controller's own traffic to establish that the radio section is operating prope~ly.
After initi~li7~tion, each controller 102 must d~ t~" ~..;..~. whether it will become 20 the master.

Method of Designat~g a Mastcr The system may use one of two methods to dr ~ ";l~r a master. Referring now to Figure 7, first method is shown. The network d~cigrqt~s 702 a specific li~
controller as an initial ma_ter, usually based on a selrction that is made by a system 25 ~d~ .lor upon inct~ n A status bit in the packet header is set 703 to indicate wo 94/29986 21416 13 PCTIUS94/06373 the status of the master. and the packet header is transmitted 704. All the other controllers 102 scan their frequency range 705 and lock onto the master. The frequency range of each controller 102 is defined by the allowable variance in the DC bias to the DAC that controls the base band. The controllers recognize the master by checking the 5 relevant status bit in the received packet. Once the other controllers 102 have locked onto the master 706, they track the master as described above, and set their frequency range 707 to match the master.
Referring now to Figure 8, a second method of de~ ;n;~e a master is shown.
This method involves a controller selection process to be pc.Ço-~ucd across all of the 10 controllers in the nc~olL In this method, every time a controller is initiqli7l~d the controller must deterrnine whether it will become the master. To make this dct,c....;n~ n, the controller ~ ÇOl~S the following steps.
First, the controller scans its Lcqu~,ue~ range 802 looking for a master_syne paeket. A master_sync packet is a paeket wherein the master bit within the Sender State 15 Status Byte is set, intljc^~ine that the sender has deci~nqted itself as the master (see Data Protoeols, below). All other data in the paeket is the same as for a typieal eontroller data paeket, inrlu~1ing, opti~nqlly, a user-de&ed portion.
If the eontroller &ds a master_syne packet, that means that one of the controllers in the system has already been decien ~ed as the master. The sc- mine 20 controller mq~rh~5 804 to the master's rlc~lu~,nc~ and sends the master a "link controller ready" paeket. If no master_sync packet is found, the controller seleets 806 themidpoint of its fic~lu~,n~;y range and begins ~ c~ g a master_sync paeket 807 atthat rlc.lu~lley. Thus, the controller deci~--~s itself as the master.
If a master r~ s a master_syne paeket from another eontroller, it waits for a 25 period of time (the time period may depend on past history info~-~ Ieg~dmg the network) and performs the ini~iqli7qtirn proeess again. This pl~edu e takes plaee under the d;~ ~ l;on of the eontrol program, whieh ;.~slu~es rules gO~ g master wo 94/29986 PcT/US94/06373 selection. Such rules include: minimi~qtion of signal power while mqin~qining contact with all nodes; maximization of uptime (the amount of real time that the node isoperational): minimi7qtion of multipath to nodes; preference for stability based on past history information regarding previous desi&nqtionc of master nodes; and maximization 5 of node uptime as a percentage of network uptime. Sincc all nodes share the same information and rules, all nodes are capable of arriving at the same decision as to which will be the master. Thus, simultaneous deci~nq~ion of more than one master is avoided.

FrequencyAssignmentTechni7 e Once a master is desi~nqted the master can change the network ~lG~Iucnc~ as 10 required. Typically, the frequency may need to be changed due to iutelr.,lGnce. noise, or other factors. To change the n~lwGlk flG~IU~,nCy, the master employs a r.Gquc~, ;y ,~.c.cignm~.nt Technique (FAT).
Referring now to Figure 10, there is shown a flow chart of FAT acco,dillg to thepresent invention. In step 1001, the process begins. In step 1002, the master dct~ u~s 15 a new f~.lu~,n~;y for the ncl-. o,~ based on availability"llt~,.rc,~ince, levels, and other factors. In step 1003, the master ~ a new_r,~ucnc~ packet a~ouuculg the new frequency to all the link controllers in the network. The packet header for this packet also includes a byte i~ g the power level at which the packet was sent. Once the link controllers receive the packet, they change to the new r,G~Iucnc~ in step 1004. All 20 fl~u~,n.;~ changcs are ~Co...rlich~d either by chqrl,~ing the DC bias value in the DAC
to the "cavity" reson~-or, or by selccting another "caviq".
~ n steps 1005 through 1012, the master performs adj~ to the network by sel~cting optimal power levels for each link controller.
This is done one node at a time. In step 1005, the master selects a link 25 controller. Then, in step 1006, the master transmits a change_power packet to that link controller. In step 1007, the link controller changes its power level in lcsl,onsG to the wo 94/29986 PCT/US94/06373 change_power packet, and in step 1008 it sends a new_power_ack packet back to the master. in-licating acknowledgment of the change_power packet. In step 1009, themaster measures the signal strength of the received new_power_ack packet. In step 1010, the master determines whether the signal strength is optimal. This determination 5 is made according to the simple~ algorithm, a well-known linear programming technique that dcs~,libcs the ma~itude and sign of the changes to be made in order to optimize the received signal strength. In ~d~lition, the Simple~c algoritbm specifies the -threshold for cou~ G~gcllce at the optimal value of signal strength, and ~e~;rlrs methods for d~,~g whether the con~ d value is the true optimal valuc or an ar~fact of 10 errors in the data. The simple~ algorithm is desc~ibed in S.I. Gass, T .in~qr Pro~ ",~
M~th~lC ~n~ qti- nc 2d ed., New York: McGraw-Hill, 1964; G. Hadley, Linear Plo~ Reading, Mass.: Addison-Wesley, 1962; and A F. Carley and T.H.
Morgan, '~co~ ul~l;o~ Methods in the Ch~micql Scirnrçs~ 'hi~h~st~r, Ellis Hor-wood T .imite.l 1989.
The simple~c op imi7~tion is pc.rul~cd using variables lcplcs~ g the following:
o Previous and current signal strengths among nodes;
o Channcls used;
o Previous channel inte~r.,..,nces found;
o Previous rnaster history;
o Plc~ious node traffic history;
o Error rate; and o Previous and current spatial rela~ nr5 Other v~iablcs may also be used. In general, the v ~ s are clesc~ibed by a 25 value, range, and statistical range. Variables may lc~ signal level ~ni~,C~ vectorvalues (for spa~al data), .~ aec counts, and Boolean values. To perform the simple~c algorithm, a matri~c is consl,u~t~,d using known values for the variables, selected wo 94/29986 3 7 21~1613 PCT~US94/06373 variables are relaxed, and the matrix is solved to obtain the optimal signal strengths for the various nodes.
Each node selects its power levels as follows. Included in each node's Sender State Records is the lowest power level, plus a reasonable margin, that the tr~ncmit ing 5 node saw. Since background traffic (such as heartbeats, acknowl~gmentc, and the like) is often continually present, and since the control program is instructed, at first, to va~y the power Ievel for the node to establish these optimal power levels, the system quickly establishes its internode transmit power levels. If co~n~.;r~t;o.. is lost bet veen two nodes (for exarnple, when obstacles appear, in~lic?ting a need for multipath), then fur-10 ther communication auc~l~p~s are made using the highest available power settings. Ifcommunication cannot be established at these high levels, and other nodes also indicate that the node has dis~pc&~,d, it is p-~su.,lcd to be powered off. Otherwise, a relay is set up to allow access to the node.
If the signal strength is not optimal, steps 1006 through 1010 are repeated until 15 the linl; controller is t.;~C~ ;ng at an optimal power level. Then, in step 1011, the master checks to see if there are any more link controllers to be adjusted. The master repeats steps 1006 through 1011 for each link controller. Then, in step 1012, the master selects a minim~l optimal signal strength for itself.
Once the steps of Figure 10 have been p~,,ru~ued, the power level of each node 20 of the nctwolk is at a 1--; -;--.----. optimal level.
FAT allows the master to change the ncl~u,k L~,4u~n -~ to avoid noise and intG.rc.~nce, and to automatically adjust power Ievels for the new fi~ u~,n~. Thus, FAT provides the following advantages:
o r.~ u~ and power level ~Cci&rlm~m and reconfiguration that is transl,~cn 2~ to the user.
o Forrn^~ion of work groups within the network. Work groups are known in the art. Conventional wire adapters i~..pl~...rn~ work groups by logically tying lûgctLcr two wo s4n9986 2141613 PCT/US94/06373 separate Ethemet cabling systems, each with a separate adapter. By contrast, the present invention provides for a single adapter dynamically h~n~lling a number of distinct net-works. Any adapter may participate in any of the separate networks. This provides im-proved flexibiIity and increased system perfommance. Each node can periodically 5 monitor each of the separate networks under user and/or node control. Each such work group operates at a dirrclent frequency and with its own master. The work groups can be reconn~ct~d to the overall network or to other work groups under soflw~c control.
Formation of work groups in this manner enables operation of four n.,lwu~ks, each operating at a 50 megabits/second data ratc.
o Increased network security by p-c~,n i~g llnqllthon7~d nodes from co~c~ i~g to the Ii~lwGlL User-specifi~d eml~yLlon keys for de and system access can be monitored to prevent co~n~;on of dllp! ~ or foreign nodes. The system may use power level information to ascel~ill by triangulation t_e position of each node. By ç~hqnging this information among nodes, by way of a special "user" packet, the system 15 is made aware of spatial relqti~nchir among nodes. Appc~ce of a node whose po-sition does not accord with this spatial re~ nchir may indicate the plesence of an intruding node, so that a supervisor or ~ I...;..;cl."l(,l may be notified.
Alternatively, the system may encrypt packets and employ the rlc.lucllc~-agilityof the n~,lwolk to im, l-ln.~nt pseudo-random channel hopping in order to make it more 20 difficult for ~ u~ d users to connect to the network.

12at~ 1 lU' ~nlc Figu~e 9 shûws an e~^mpl~ ûf a data packet format accoldi~g to the present h~ ion, in.~ controller header 900. As will be ~ nl to those skilled in the art, other protocols and for nats may also be used in co.-ne~!;on with the present 25 in~ lion.

wo 94/29986 PCT/USg4l06373 Refernng now to Figure 9, link controller header 900 includes the following items: synch header 901, digital frequency 902, sender state 903, and synch header CRC 904. The information in link controller header 900 describes the node sending the packet, and the view of the network seen by the sending node.
Synch header 901 is used to indicate the start of a packet. In the prefc,lcd embodiment, synch header 901 consists of seven bytes of the binary value 10101010 followedby 10101011.
Digital frequency 902 is a two-byte field that ~ ;r.~S the number of bytes in the packet. It also SpCC;r.~S the frequency of the node that is t~ g the packet.Thus, digital control of frequency is accomplished by counting the number of bytes received in the packet and COulpali..g this count against the value of digital rr~(luc~,.;y 902. If the counted number is less than the value of digital frequency 902, then the base band (controlled by the DAC as descnbed above) must be adjusted dG..II-.a.d~, if the counted number is more, then the rl~.lu.,nc~ must be . djus~ed u~,~.~.ls. The adjustment is pclrullllcd by the tl~nscel~r 101 as described previously.
For esample, if the DAC value is 1000, and the number of bytes received in the packet is more than 1000, the DAC value is iu-,.cased, for esqmp'~ tO 1100. If the number of bytes rccel~,~d is less than 1000, the DAC value is dc~ ased, for çrqmrle to 920.
Sender state 903 con~ C inform~*on describing the node that is ~ g the packet, and its view of the network. This informq~inn is used by the receiver of the packet in order to update packet counts and traffic information. Sender state 903 consists of a Sender State Status Byte (inrlirqti~ such iu~ol~ ;on as whether the t~r c-- -;l ~ r is a Master, or alb.,~ t~g tO find a master, its unit type. and whether it is a relay point), a Sender State Count Byte jn~lil'9tiTU~ the number of sender state records that are to follow (from 0 to 10), and the sender state records themselves. In some wo 94/29986 4 0 21 11613 PCTIUSg4/06373 cases, there will be no sender state records. Each sender state record contains the following:
o Four bytes in~icating a unique identification code;
o One byte inAic,q,ting power control information;
o One byte inAir~ ting a fi~,qu~n~;y drift factor;
o One byte inAirqting frequency control information; and o One byte intlirqting packet receive and transmit status.
Sender state 903 further containc informq~iQn about current packet number received from that node and the current send packet number. Each directed packet has a sequence number (modulo 256) included in it. Synch header CRC 904 is a 16-bit field cn.~ t.;..g a value that is derived, according to ~ch~ucs known in the art, from the values of the other fields in header 900. It senes as a valitlqtit n check to ensure that the infotTnqtiQn co~ rd in all the fields is correct.
Data packet 905 in the p.Gfcll~d embod;.... ~1 inr,ludes the following items: link controller header 900, packet header 906, packet type 907, data 908, packet error detection 909, and epilogue 910.
Link controller header 900 dcs-,-ibes the node sending the packet, and is identical to that described above.
Packet header 906 co~ ;..c informa.*on dcs~"ibing the packet, its des*nA inn node, and its source node. It col~lAi-~c si~c bytes ~.,il~i~g the des*n ~jon node address, si~c bytes ~ccifjillg the source node address, and two bytes ~if~ g the paclcet length.
Packet type 907 describes the type of data in the packet. It is user-defined, and is one byte in length.
Data 908 is the actual data being tran~ A Its length may range from zero bytes to lS94 bytes.

wo 94/29986 2141613 PCTIUS94/063~3 Packet error detection 909 is a four-byte field employing standard ECC multiple bit error detection methodology to verify the validity of the preceding fields.
Epilogue 910 cont~inC packet termination information. It consists of two bytes con~ining the binary pattern 00110011.

WO 94ngg86 4 2 2 1 41613 PCT/US94/06373 Thus, the data packet as a whole contains the following f~elds:

Field Name Size (bvtes) DescriDtion Synch header 901 8 Synchronization bit stream for packet start (seven bytes of 10101010 followed by one byte of 10101011).
Digital frequency 2 Lcngth of the data packct e~clu~iing Synch 902 Header. Uscd to adjust LG.Iu~,n~;y of transceiver 101.
Sender state status 1 Bit 0: Tn~ tes whether sender is mastcr byte Bit 1: Tn~ q~tes whether trying to establish a mastcr Bit 2: Indicatcs whclhcr network has lost mastcr Bit 3: ~n~irat~s whether sender is bcing used as a rclay Bits ~7: Reserved for futurc usc Sender state count 1 Numbcr of sender state records following.
byte Sender state rccords 8~n Four bytes in~ir~ting unique idr nl;l ;r~-;oll code;
one bytc of power control info~nq~ion; one byte of LG~ Cn~;Y drift factor; one bytc of r~qu~ y control inforrnqtion; one bytc of packet receive and tl~...i~ status. n is uscr-selcctable, from 0 to 10.
Synch header CRC 1 CRC for lin~ controller header WO 94/29986 21~1613 PCT/US94/06373 Packet header 906 14 Six bytes of destination node address; six bytes of source node address; two bytes of length.
Packet type 907 1 User-defined.
Data 908 m User-defined. m may range from zero to 1594.
Packet error detec- 4 Standard ECC error detection.
tion 909 Epilogue 910 2 Packet t~rrnin~tion. Two bytes of 00110011.

From the above description, it will be app~nL that the invention disclosed herein provides a novel and advantageous network system and method. The fo.cgoil,g discussion discloses and describes merely e~mpl~ry method~c and embodiment-c of the S present invention. As will be und~ ood by t_ose familiar with the art, the invention may be embodied in ot_er specific forms without departing from the spirit or eccen*~l ch~ra~tericticc thereof. For e~mple. ot_er data packet formats or modula-tion/demodul~tion sçh~ s could be employed. Accordingly, thc liicclosure of the pre-sent invention is int~nded to be illu~ ." but not limiting, of the scope of the 10 invention, which is set forth in the following claims.

Claims (32)

Claims What is claimed is:

1. A network link controller for configuring, regulating, and controlling a node in a computer network, wherein the network includes a dynamically designated master node, comprising:
a radiator for transmitting and receiving modulated signals;
a radio transceiver coupled to the radiator for processing received and transmitted modulated signals; and a digital controller coupled to the radio transceiver for providing a control signal to control a selected parameter of the radio transceiver .

2. The network link controller of claim 1, wherein the modulated signals comprise phase modulated signals.

3. The network link controller of claim 1, further comprising a control program coupled to the digital controller for controlling the digital controller.

4. The network link controller of claim 1, wherein the signals are transmitted using multiple carriers.

5. The network link controller of claim 4, wherein each carrier operates at a different frequency.

6. The network link controller of claim 4, wherein:
the modulated signals comprise phase modulated signals; and each carrier operates at a different phase.

7. The network link controller of claim 4, wherein the modulated signals are transmitted using multiple polarization modes.

8. The network link controller of claim 1, wherein the radio transceiver modulates the transmitted signals and demodulates the received signals using direct conversion.

9. The network link controller of claim 1, wherein the received signals are modulated by a phase shift keyed modulation technique.

10. The network link controller of claim 1, wherein:
the radio transceiver operates at a selectable power level; and the radio transceiver adjusts the selectable power level according to control signals from the digital controller.

11. The network link controller of claim 10, wherein the digital controller sends the control signals to the radio transceiver specifying adjustments to the selectable power level in response to network conditions.

12. The network link controller of claim 1, further comprising a control program coupled to the digital controller for monitoring network conditions and selectively specifying control signals to the digital controller in responseto the network conditions.

13. The network link controller of claim 12, wherein the control program comprises:
computer-implemented means for providing a set of rules defining particular actions corresponding to particular network conditions;
means for accepting input describing network conditions; and a computer-implemented inference engine for applying the set of rules to the monitored network conditions and for generating commands corresponding to the particular actions corresponding to the monitored network conditions.

14. The network link controller of claim 13, wherein the control program further comprises means for learning new rules and adding the new rules to the set of rules.

15. The network link controller of claim 13, wherein the input describing network conditions comprises:
object descriptions;
event descriptions;
performance data; and meta-knowledge.

16. The network link controller of claim 1, wherein the radio transceiver sends and receives the phase modulated signals using microwave transmission.

17. The network link controller of claim 1, wherein the radio transceiver selectively employs multipath to avoid obstacles in data transmission .

18. The network link controller of claim 1, wherein the radio transceiver comprises a phase locked loop to maintain a frequency lock with the received phase modulated signals.

19. The network link controller of claim 1, wherein the control signals comprise:
a first signal for commanding the radio transceiver to increase transmitted power; and a second signal for commanding the radio transceiver to decrease transmitted power.

20. The network link controller of claim 1, wherein the control signals comprise:
a first signal for commanding the radio transceiver to increase received power;
and a second signal for commanding the radio transceiver to decrease received power.

21. The network link controller of claim 20, wherein the control signals further comprise:
a third signal for commanding the radio transceiver to increase transmitted power; and a fourth signal for commanding the radio transceiver to decrease transmitted power.

22. The network link controller of claim 1, wherein the control signals include a signal for commanding the radio transceiver to change frequency.

23. A method of designating a master node in a network containing a plurality of nodes, each node having a frequency range and a transmission frequency, comprising the steps of:
designating one of the nodes as an initial master node;
transmitting a packet header to other nodes in the network at a first frequency, the packet header including a status indicator indicating master node status;
scanning the frequency range of each other node to lock onto the first frequency;
and setting the frequency range of each other node to match the first frequency.

24. A method of designating a master node in a network containing a plurality of nodes, each node having a frequency range and a transmission frequency, comprising the steps of, for each node:
scanning the frequency range of the node to determine whether a master packet has been transmitted by another node;
responsive to a determination that a master packet has been transmitted by another node, matching the frequency of the other node; and responsive to a determination that no master packet has been transmitted by another node:
selecting a frequency; and transmitting a master packet at the selected frequency.

25. A method of changing network frequency in a network containing a plurality of nodes, each node having a transmission frequency, comprising the steps of:
determining a new frequency;
transmitting a packet announcing the new frequency; and for each node, changing the transmission frequency of the node to match the announced new frequency in response to the packet being received at the node.

26. The method of claim 25, further comprising the step of, before the determining step, monitoring conditions of the network, and wherein the determining step comprises the step of determining a new frequency based on the monitored conditions.

27. A method of selecting an optimal transmit power level for a first node in a network containing a plurality of nodes, comprising the steps of:
a) transmitting a first packet from a second node to the first node to indicate a change in power;
b) changing the transmit power level of the first node in response to the first packet being received at the first node;
(c) transmitting a second packet from the first node to the second node to indicate acknowledgment of the first packet;
(d) measuring the strength of the received second packet at the second node;
(e) determining whether the strength of the received second packet at the second node is optimal; and (f) responsive to a determination that the strenght is not optimal, repeating steps (a) through (e)

28. A method of selecting an optimal transmit power level for a first node in a network containing a plurality of nodes, comprising the steps of:
(a) transmitting a first packet from a second node to the first node to indicate a change in power;
(b) changing the transmit power level of the first node in response to the first packet being received at the first node;
(c) transmitting a second packet from the first node to the second node to indicate acknowledgment of the first packet;
(d) measuring the strength of the received second packet at the second node;
(e) adjusting the received signal strength;
(f) determining whether the adjusted received signal strength at the second node is optimal; and (g) responsive to a determination that the adjusted received signal strength is not optimal, repeating steps (a) through (f).

29. The method of claim 28, wherein step (e) comprises the substeps of:
(e.1) determining values of a plurality of variables describing characteristics of the network; and (e.2) applying a simplex optimization algorithm to the determined values.

30. The method of claim 29, wherein the plurality of variables comprises:
previous signal strength among nodes;
current signal strength among nodes;
channels being used;
previous channel interferences found;
previous master history;
previous node traffic history;
error rate;
previous spatial relationships among nodes; and current spatial relationships among nodes.

31. A method of transmitting a plurality of data packets from a transmitting node to a receiving node in a wireless network, comprising the steps of, for each data packet:
(a) the transmitting node transmitting the data packet;
(b) the receiving node attempting to lock onto a received signal containing the data packet;
(c) responsive to the receiving node being unable in step (b) to lock onto the received signal:
(c.1) the transmitting node re-transmitting the data packet; and (c.2) the receiving node attempting to lock onto a received reflected signal containing the data packet; and (d) responsive to the receiving node being unable in step (c) to lock onto the received signal:
(d.1) the transmitting node re-transmitting the data packet; and (d.2) the receiving node attempting to lock onto a received direct signal containing the data packet.

32. The method of claim 31, further comprising the step of repeatedly performing steps (c) and (d) until the receiving node successfully receives the data packet.