CA2140686A1 - Bus Master Arbitration Circuitry Having Improved Prioritization - Google Patents

Bus Master Arbitration Circuitry Having Improved Prioritization

Info

Publication number
CA2140686A1
CA2140686A1 CA2140686A CA2140686A CA2140686A1 CA 2140686 A1 CA2140686 A1 CA 2140686A1 CA 2140686 A CA2140686 A CA 2140686A CA 2140686 A CA2140686 A CA 2140686A CA 2140686 A1 CA2140686 A1 CA 2140686A1
Authority
CA
Canada
Prior art keywords
bus
priority
retried
arbiter
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2140686A
Other languages
French (fr)
Other versions
CA2140686C (en
Inventor
Maria L. Melo
Randy M. Bonella
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2140686A1 publication Critical patent/CA2140686A1/en
Application granted granted Critical
Publication of CA2140686C publication Critical patent/CA2140686C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Abstract

An arbiter which allows retried requests to have high priority in subsequent arbitrations by not changing priority on a granted, but aborted, access to the bus and yet prevents the aborted requestor from thrashing the bus by masking its bus request signal until the data is available. Further, should an access to main memory be retried, all bus requests except the one from the memory system are masked to provide the memory system the highest effective priority to allow any flushing operations to occur. The masking of the various bus requests allows the arbiter to control access to a PCI
standard bus without requiring that specific signals be added. The arbiter further includes modified priority LRU techniques and provides a locking requestor with an additional, highest priority position if retried.
CA002140686A 1994-01-28 1995-01-20 Bus master arbitration circuitry having improved prioritization Expired - Fee Related CA2140686C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/188,456 US5471590A (en) 1994-01-28 1994-01-28 Bus master arbitration circuitry having improved prioritization
US188,456 1994-01-28

Publications (2)

Publication Number Publication Date
CA2140686A1 true CA2140686A1 (en) 1995-07-29
CA2140686C CA2140686C (en) 1999-02-02

Family

ID=22693236

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002140686A Expired - Fee Related CA2140686C (en) 1994-01-28 1995-01-20 Bus master arbitration circuitry having improved prioritization

Country Status (6)

Country Link
US (1) US5471590A (en)
EP (1) EP0665500B1 (en)
JP (1) JP2596895B2 (en)
AT (1) ATE207218T1 (en)
CA (1) CA2140686C (en)
DE (1) DE69523189T2 (en)

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Also Published As

Publication number Publication date
US5471590A (en) 1995-11-28
DE69523189T2 (en) 2002-05-16
JP2596895B2 (en) 1997-04-02
EP0665500A1 (en) 1995-08-02
EP0665500B1 (en) 2001-10-17
JPH07219892A (en) 1995-08-18
DE69523189D1 (en) 2001-11-22
ATE207218T1 (en) 2001-11-15
CA2140686C (en) 1999-02-02

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