CA2122118A1 - Method for low temperature growth of epitaxial silicon and devices produced thereby - Google Patents

Method for low temperature growth of epitaxial silicon and devices produced thereby

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Publication number
CA2122118A1
CA2122118A1 CA002122118A CA2122118A CA2122118A1 CA 2122118 A1 CA2122118 A1 CA 2122118A1 CA 002122118 A CA002122118 A CA 002122118A CA 2122118 A CA2122118 A CA 2122118A CA 2122118 A1 CA2122118 A1 CA 2122118A1
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CA
Canada
Prior art keywords
layer
substrate
silicon
buffer layer
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002122118A
Other languages
French (fr)
Inventor
Jueinai R. Kwo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of CA2122118A1 publication Critical patent/CA2122118A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02516—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/967—Semiconductor on specified insulator

Abstract

METHOD FOR LOW TEMPERATURE GROWTH OF EPITAXIAL SILICON
AND DEVICES PRODUCED THEREBY
Abstract A thin layer of epitaxial silicon is grown at low temperatures at or below 300°C by the steps of providing a substrate, forming an oriented dielectric buffer layer on the substrate and growing epitaxial silicon on the buffer layer. Preferably the substrate has a glass surface and the oriented buffer layer is cubic ZrO2. The buffer layer is preferably oriented by bombarding it with a directed ion beam while the buffer layer is being deposited on the substrate. For example, a buffer layer of (100) cubic ZrO2 can be grown at a temperature as low as 300°C. The oriented cubic ZrO2 is an excellent buffer for epitaxial silicon on glass due to a good match of lattice parameters with silicon and a good match of thermal expansion coefficients with glass. An oriented (100) silicon epitaxial film can then be grown on the epitaxial template provided by the buffer layer at a temperature as low as 250°C.
This low temperature process for producing epitaxial films offers multiple advantages: (1) reduced silicon interfacial defect densities and enlarged grain size permitting improved thin film transistor performance due to a lowered "off" current;
(2) higher electron mobility permitting the fabrication of integrated displays; (3) lower temperature processing permitting the use of inexpensive glass substrates such as borosilicates; (4) sufficiently low temperature processing to permit the use of new lightweight substrates such as glass-coated polymeric materials (glass-coated plastics) which can substantially reduce the weight of displays and thus enhance the portability of portable computers, video telephones, and personal communicators;and (5) the use of new buffer layers such as ZrO2 which can block the diffusion of Na ions from the substrate.

Description

.
-METHOD FOR LOW TEMPER~TURE GROWTH OF EPITAXIAL SILICON
ANI) DEVICES PRODUCED THEREBY

Field of the Invention The present invention relates to methods for growing at low temperature S layers of epitaxial silicon. Such layers are particularly useful for making thin film transistors and lightweight flat-panel display devices.

Background of the Invenffon With the rapid expansion of capacity to transmit and process information, devices for visually displaying information have become increasingly 10 important. Lightweight, flat visual display devices are particularly needed for portable computers and wireless communications instruments.
One promising approach to providing flat-panel displays is the active matrix liquid crystal device (AMLCD). In essence the AMLCD comprises an array of thin film transistors, capacitors and electrodes formed on a transparent substrate 15 and incorporated in an LCD display. Each thin film transistor controls an electrode which, in turn, polarizes a pixel-size region of liquid crystal. Typically the transistors are comprised of thin films of amorphous silicon. One difficulty with these devices, however, is that amorphous silicon lacks sufficient electron mobility to be used for drivers and registers in the display. Hence a hybrid structure 20 combining amorphous silicon on glass and a crystalline silicon chip is required.
Polysilicon has higher electron mobility than amorphous silicon, and if polysilicon can be substituted for amorphous silicon in AMLCD devices, the entire display --complete with drivers-- can be integrated on the substrate. However, few trarisparent-materials can withstand the high temperatures, typically in excess of 25 600C, required to grow polysilicon. Consequently efforts to make polysilicon based displays have required substrates of high temperature glass, such as fused quartz which are expensive, heavy, and fragile. Moreover typical thin films of polysilicon have randomly oriented grains producing random distribution of defect densities and non-uniform etching and oxidation characteristics. Accordingly, there is a need for a 30 method for low temperature growth of silicon of enhanced electron mobility and reduced grain structure (hereafter "epitaxial silicon") which can utilize a wider variety of substrate materials.

21221 l 8 Summary of the Invention A thin layer of epitaxial silicon is grown at low temperatures at or below 300C by the steps of providing a substrate, forming an oriented dielectric buffer layer on the substrate and growing epitaxial silicon on the buffer layer. Preferably S the substrate has a glass surface and the oriented buffer layer is cubic ZrO2. The buffer layer is preferably oriented by bombarding it with a directed ion beam while the buffer layer is being deposited on the substrate. For example, a buffer layer of (100) cubic ZrO2 can be grown at a temperature as low as 300C. The oriented cubic ZrO2 is an excellent buffer for epitaxial silicon on glass due to a good match of 10 lattice pararneters with silicon and a good match of thermal expansion coefficients with glass. An oriented (100) silicon epitaxial film can then be grown on the epitaxial template provided by the buffer layer at a temperature as low as 250C.
This low temperature process for producing epitaxial films offers multiple advantages: (1) reduced silicon interfacial defect densities and enlarged grain size 15 permitting improved thin film transistor performance due to a lowered "off' current;
(2) higher electron mobility permitting the fabrication of integrated displays; (3) lower temperature processing permitting the use of inexpensive glass substrates such as borosilicates; (4) sufficiently low temperature processing to permit the use of new lightweight substrates such as glass-coated polymeric materials (glass-coated 20 plastics) which can substantially reduce the weight of displays and thus enhance the portability of portable computers, video telephones, and personal communicators;and (S) the use of new buffer layers such as ZrO2 which can block the diffusion of Na ions from the substrate.

Brief Descripffon of Ule Drawin~
In the drawings: ~ ~
FIG. 1 is a flow diagram showing the steps of a preferred process for ~ `
low temperature growth of epitaxial silicon;
FIG. 2 shows apparatus for low temperature growth of epitaxial silicon;
FIG. 3 is a schematic cross section of a typical workpiece prepared in 30 accordance with the process of FIG. l;
FIG. 4 is a schematic cross section of a thin film transistor made in accordance with the process of FIG. l; and FIG. S shows the use of an array of thin film transistors used as pixel switches in a lightweight AMLCD device.

2122~ 18 Detailed Description Referring to the drawings, FIG. 1 illustrates the steps for low temperature growth of polysilicon. As shown in block A of FIG. 1, the first step is to provide a suitable substrate such as a transparent body of glass or plastic. Preferred 5 glasses include borosilicates such as Corning 7059. Preferred plastics includepolyimides and polyethersulfone (PES). Advantageously plastic substrates are provided with a micron thick glass seed layer as by RF sputtering at low temperature.
The next step shown in block B is to provide the substrate with a 10 suitable buffer layer for the epitaxial growth of silicon. The layer should be dielectric, have lattice parameters closely matching those of silicon (preferably matching within about 5%), and have a coefficient of thermal expansion which closely matches the substrate. Preferred buffer layer materials include cubic ZrO2 stabilized by 8% yttrium, CeO2 ,PrO2, and Y2 03. The buffer layer is applied as an 15 oriented layer by subjecting the substrate to a low energy ion bombardment at the same time the buffer layer is being applied. The beam is directed to maintain a velocity component in a predetermined direction parallel to the growth surface.
Such a directed ion beam will preferentially remove misoriented grains and thereby promote the growth of an oriented buffer layer. For a given set of materials, the ion 20 energy can be chosen below the energy level producing significant ablation of the buffer layer crystal structure. ZrO2 buffer layers can be grown by e-beam evaporation while bombarding a glass-surfaced substrate with a beam of argon ions preferably having energy in the range 50-200 volts. This process can achieve a buffer layer with a (100) orientation in the predetermined direction, and a mosaic spread in 25 the plane better than 2.
The third step shown in block C of FIG. 1 is to grow epitaxial silicon on the buffer layer using standard processes such as sputtering or low pressure chemical vapor deposition (CVD). This step can be better understood by reference to FIG. 2 which schematically shows preferred apparatus for both applying a buffer layer and growing the silicon layer. Specifically, the substrate 20is mounted within the low pressure growth chamber 21 having a buffer source container 23 (e.g. zro2) usinge-beam evaporation and a silicon source container 24 using sputter deposition. The chamber is provided with means, such as an ion gun 25, for directing a beam of ions 26 such as argon onto substrate 20.

-In operation, chamber 21 is evacuated to a low pressure of about 10~6Torr or lower. The substrate 20 is heated to a temperature of about 300C by a heating element (not shown), and an electron beam is applied to source 23 to apply a thin buffer layer (about 500A-SOOOA thick) to the substrate and, at the same time, 5 ion gun 25 is activated to direct a stream of argon ions at an angle of about 30 onto the growing surface. The buffer layer is grown with its (100) plane parallel to the major surface of the workpiece. Next the silicon source 24 will apply silicon atoms to the workpiece by sputtering vith argon ions (or by low pressure CVD process).After silicon growth deposition, vacuum is broken and the epitaxial silicon coated 10 workpiece is removed from the chamber for further processing as desired.
Fig. 3 is a schematic cross section of a resulting device showing the substrate 20 comprising a plastic body 20A having a seed layer of glass 20B.
Preferably the substrate is transparent to visible light. The glass seed layer 20B can be produced on the body by RF sputter deposition from a glass target. Buffer 15 layer 30 is grown on the glass surface, and silicon layer 31 is epitaxially grown on the buffer. In particular the silicon is grown with its (100) plane parallel to the major surface of the workpiece.
FIG. 4 illustrates a preferred device comprising a self-aligned thin film transistor 40 formed on the workpiece of FIG. 3. Transistor 40 uses portions of an ~ ~
20 epitaxial silicon layer 31 grown in accordance with the method of FIG. 1 to form a ;
transistor source 31A, a channel 31B and the drain 31C. Specifically, after the growth of the polysilicon layer 31, a gate oxide 41 is thermally grown or deposited, followed by a gate 42 of metal or polysilicon. After the gate is patterned, the source and drain 31A and 31C are formed on layer 31 by ion implantation. A thick 25 insulator 43 such as SiO2 is then deposited, and metal source and drain contacts 44 and 45 are applied through vias in the insulator 43.
FIG. 5, which is a schematic rendering of a portion of an active matrix liquid-crystal device, shows how the device of FIG. 4 can be used to make an improved dat display. In essence the AMLCD comprises a liquid crystal medium 30 (not shown) disposed between a transparent common electrode 50 and an array of transistors 40 and local electrodes 51 (preferably pixel-size) all disposed on acommon substrate 20. Each local electrode is switched by an associated transistor 40 interconnected to an associated storage capacitor 53. The transistors 40 therebycontrol the state of the voltage on each local electrode and, in accordance with well 35 known principles, control the optica1 state of a pixel size liquid crystal region.

In accordance with conventional structure, the AMLCD includes a back light (not shown), a diffuser 54, polariærs 55 and, if color is desired, a grid of color filter layers 56 disposed on a transparent substrate 59. Rows of transistor gates can be interconnected via conductive gate lines 57 and columns of transistor sources can S be interconnected via conductive data lines 58 for switchable control of individual pixels.
The AMLCD of FIG. S is of conventional construction except that the transistors 40 are epitaxial silicon thin film transistors formed of a layer of (100) oriented epitaxial silicon (not shown in FIG. 5) grown at low temperature in 10 accordance with the method of FIG. 1. Preferably the transistors are self-aligned coplanar transistors 40 formed on a glass-coated plastic substrate 20 such as are shown in FIG. 4.
The advantages of using the process of FIG. 1 and the device of FIG. 4 in this AMLCD include enhanced transistor performance and the availability of a 15 wider variety of substrate materials such as borosilicate glasses and even glass-coated plastics. A substantial reduction in weight is obtainable when the low temperature process of the invention perrnits the fabrication of epitaxial silicon devices on plastic substrates rather than glass. In addition to lighter weight, the AMLCD devices with plastic substrates are more shock resistant, more flexible, and 20 less expensive. `
The new low temperature process for producing epitaxial silicon films offer mu1tiple advantages in the fabrication of thin film silicon devices. (1) Thin film transistor performance is enhanced due to a lowered "off" current by reducing the interfacial defect densities and enlarging the grain size. (2) Electron mobility is 25 increased. (3) Inexpensive glass substrates such as borosilicates can be used. (4) New lightweight substrates such as glass-coated plastics can be used, substantially reducing the weight and increasing the portability of displays for portable computers, television sets, video telephones, and personal communicators. (5) The conventional SiO2 diffusion barrier can be replaced by a Zr2 buffer layer which blocks 30 effectively the diffusion of Na ions from the substrate.

Claims (20)

1. A method for growing a layer of silicon comprising the steps of:
providing a substrate;
depositing on the substrate a buffer layer of dielectric material and, at the same time, bombarding the substrate with a directed beam of ions in order topromote oriented growth of said buffer layer; and depositing a layer of silicon on said buffer layer at substrate temperature of 300°C or less.
2. The method of claim 1 wherein said substrate comprises a glass layer.
3. The method of claim 1 wherein said substrate comprises a body of borosilicate glass.
4. The method of claim 1 wherein said substrate comprises a body of polymeric material.
5. The method of claim 1 wherein said buffer layer is deposited by electron beam evaporation.
6. The method of claim 1 wherein said silicon is deposited by sputter deposition.
7. The method of claim 1 wherein said silicon is deposited by chemical vapor deposition.
8. The method of claim 1 wherein said substrate comprises a glass layer and said buffer layer comprises ZrO2, CeO2, PrO2 or Y2O3.
9. A silicon device comprising:
a substrate comprising a body of material having a planar major surface and a layer of glass overlying said major surface;
overlying said glass layer a (100) oriented buffer layer of dielectric material; and overlying said buffer layer a (100) oriented layer of silicon.
10. A device according to claim 9 wherein said substrate is transparent to visible light.
11. A device according to claim 9 wherein said body comprises a body of polymeric material.
12. A device according to claim 11 wherein said polymeric material is a polyimide or a polyethersulfone.
13. A device according to claim 9 wherein said buffer layer comprises ZrO2, CeO2, PrO2 or Y2O3.
14. A thin film transistor comprising a source, a gate-controlled channel and a drain disposed upon a substrate having a planar major surface wherein saidsource, channel and drain comprise a layer of (100) oriented silicon overlying said planar major surface and said substrate comprises a body of polymeric material.
15. The transistor of claim 14 wherein said substrate further comprises a layer of glass overlying said body of polymeric material.
16. The transistor of claim 15 further comprising a buffer layer of (100) oriented dielectric material disposed between said layer of glass and said layer of silicon.
17. A liquid crystal display comprising a common electrode, a liquid crystal medium, and a plurality of transistor-controlled local electrodes for controlling local regions of the liquid crystal medium wherein one or more of the transistors for controlling said local electrodes comprises a transistor in accordance with claim 14 or 15 or 16.
18. A liquid crystal display comprising a common electrode, a liquid crystal medium, and a plurality of transistors and local electrodes disposed on a common substrate wherein a plurality of said transistors are thin film transistors having sources, channels and drains comprised of a (100) oriented layer of silicon and said common substrate comprises a body of polymeric material.
19. A display device according to claim 15 wherein said common substrate comprises a body of polymeric material having a planar major surface and a layer of glass overlying said major surface.
20. A display device according to claim 16 further comprising a buffer layer of (100) oriented dielectric material disposed between said layer of glass and said oriented layer of silicon.
CA002122118A 1993-06-24 1994-04-25 Method for low temperature growth of epitaxial silicon and devices produced thereby Abandoned CA2122118A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US082,194 1993-06-24
US08/082,194 US5523587A (en) 1993-06-24 1993-06-24 Method for low temperature growth of epitaxial silicon and devices produced thereby

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EP (1) EP0631297A3 (en)
JP (1) JP3096573B2 (en)
CA (1) CA2122118A1 (en)

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EP0631297A2 (en) 1994-12-28
US5523587A (en) 1996-06-04
JP3096573B2 (en) 2000-10-10
EP0631297A3 (en) 1997-07-09
JPH07149508A (en) 1995-06-13

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