CA2117341A1 - Electronic component and process for making it - Google Patents
Electronic component and process for making itInfo
- Publication number
- CA2117341A1 CA2117341A1 CA002117341A CA2117341A CA2117341A1 CA 2117341 A1 CA2117341 A1 CA 2117341A1 CA 002117341 A CA002117341 A CA 002117341A CA 2117341 A CA2117341 A CA 2117341A CA 2117341 A1 CA2117341 A1 CA 2117341A1
- Authority
- CA
- Canada
- Prior art keywords
- layer
- base
- laterally
- electronic component
- structured
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 40
- 230000008569 process Effects 0.000 title claims abstract description 38
- 230000003071 parasitic effect Effects 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 48
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 230000007704 transition Effects 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 5
- 239000002131 composite material Substances 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 5
- 229910052782 aluminium Inorganic materials 0.000 claims 5
- 150000001875 compounds Chemical class 0.000 claims 4
- 230000000737 periodic effect Effects 0.000 claims 4
- 229910020751 SixGe1-x Inorganic materials 0.000 claims 1
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- 238000005530 etching Methods 0.000 description 9
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- 238000001020 plasma etching Methods 0.000 description 6
- 239000002800 charge carrier Substances 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000001741 metal-organic molecular beam epitaxy Methods 0.000 description 3
- 230000007480 spreading Effects 0.000 description 3
- 238000003892 spreading Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910017401 Au—Ge Inorganic materials 0.000 description 2
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- 230000008021 deposition Effects 0.000 description 2
- 239000004922 lacquer Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000007723 transport mechanism Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
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- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
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- 238000012546 transfer Methods 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66454—Static induction transistors [SIT], e.g. permeable base transistors [PBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/7722—Field effect transistors using static field induced regions, e.g. SIT, PBT
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/011—Bipolar transistors
Abstract
The invention relates to an electronic component with a plurality of layers produced in the combination and with at least one laterally structured layer designed to control a space charge region. In addition, the invention relates to a process for producing such a component. The aim of the invention is such an electronic component having an enhanced switching speed. To this end, the component of the invention has a pn junction as a space charge region with a p and an n conducting layer. One of the two layers is the laterally structured base. Finally, in order to reduce parasitic space charge capacitance in the region of the lateral boundary surfaces, particularly not designed to control the space charge region at the base, the component has an additional layer having the same lateral structure at one of the two lateral boundary surfaces of the base.
Description
flLE~ rlN ~ s t't~ E~
19288 ~ TR~h~5~p~T i TRANSLATION
DESCRIPTION
ELECTRONIC COMPONENT AND PROCESS FOR MAKING IT
The invention relates to an electronic component, especially a p-channel or n-channel permeable base transistor [PBT] with a plurality of layers, fabricated in a laminated composite, and with at least one laterally structured layer provided for controlling a space charge zone, especially a base.
The invention further relates to a process for manufacturing such a component.
For use in super computers and fast data networks in the context of information technology, there are under development integrated circuits as fast microwave components. Of greater significance are integrated circuits on GaAs chips.
Components which have been used hitherto in this context are the MESFET and the HEMT. They both are so-called field effect transistors (FET), in which the current transport is parallel to the surface of the chip. An important speed determining r-A~ 1 1 7 34 1 parameter, the so-called "transit time under the gate" is here limited by the smallest lateral structuring of the gate achievable lithographically.
The permeable base transistor (PBT) proposed already in 1979, also deals with the principle of a field effect transistor was, although with a current flow direction perpendicular to the chip surface, in which the "transit time under the gate" was significantly reduced. ~Translator's note: end of page 1]
This had its basis in that the gate length in the vertical structuring was given by the thickness of the epitactically deposited base layer. With the methods of modern epitaxy, like modular beam epitaxy [MBE], metal organic gas phase epitaxy [MOCVD] or metal organic molecular beam epitaxy (MOMBE, CBE, GSMBE) for production of the metallic structured base, layer thicknesses in the range of several atom layers can be produced in a controlled manner.
From German Patent Application DE 40 25 269.8, a permeable base transistor is known, especially from GaAs. Thus several layers are bonded with one another which form the active elements of the components, namely, emitter, base and collector.
~A21 1 7341 The lateral finger-like structured base forms at its boundary surface a pn transition with the material surrounding it. These components as a result of thie characteristic have also been designated as permeable junction base transistors (PJBT). The thus formed space charge zone is controllable via the highly doped conductive base. As the basic material for the region surrounding the base and to which the current channels between the fingers of the base belong, is GaAs with an n-doping in the range of 1017 to lol~ cm~3 has been proposed. The p-doping of the base in the range of lo20 to 1021 cm~3 is achieved with the aid of a carbon doping.
The space charge zones formed on the boundary surface of the base are used for control of the electric current in the region of the current channels with the aid of a suitable voltage bias on the base. In this case ~Translators note: end of page 2]
it is a disadvantage that in the remaining space charge zone in the region of the lateral boundary surface of the base layer and spreading out therefrom, there is a parasitic space charge capacitance which limits the switchlng speed of the component disadvantageously.
It is an object of the invention to provide an electronic component of the type described at the outset in which this effect is reduced and which enables an increased switching speed. It is also an object to provide a corresponding method of making such a component.
These objects are achieved with an electronic component with the characterizing features of claim 1.
Thus the laterally structured base is provided with one of the two pn transitions as the controllable space charge zone forming layer. The base contains on at least one of its two lateral boundary surfaces, at least one additional layer which is equally laterally structured and serves to reduce parasitic space charge capacitance in the region of the lateral boundary surface of the base.
An advantageous further reduction of this parasitic space charge capacitance is then achieved when on both lateral boundary surface of the base, such a layer is provided. It is therefore advantageous to provide a semiconductive material with a doping reduced by at least a factor of 10 with respect to the C A~ ~ ~ 7~
charge carrier doping of the base as the material for this additional layer. [Translators note: end of page 3]
It can be advantageous, moreover, that within the layer a variation of the doping is provided whereby during epitaxial growth, for example, a targeted change of the doping substance can be achieved. An especially advantageous embodiment of the component of the invention resides in that as the material for filling the respective region in the openings of the laterally structured base, which provides a single current channel, semiconductive material is provided which from the viewpoint of charge carrier doping, but also through the partial replacement of an element of the semiconductor e.g. Al in GaAs AlxGalxAs) so that the deposition of a semiconductive heterostructure provides an additional possibility to improve the current transport mechanism.
A further, especially advantageous, embodiment of the electronic component resides in that the base is structured laterally with a sieve shaped.
Advantageously, the base can have lateral circular-shaped and/or oval and/or square openings. This is possible because the PJBT is homogeneously constructed, i.e. only fromsemiconductor material (e.g. GaAs). In this case, the space charge zone extends substantially uniformly from all sides into the current channel. As a result the latter can be constricted in two lateral directions, i.e. two dimensionally upon spreading of the space charge zone. In addition, this sieve structure, by contrast with a finger-like structure of the base, achieves a higher rate of rise [slope] of the component for the same voltage change in the form of a greater current change in the channel.
[Translators note: end of page 4] Moreover a stronger spread of the space charge zone toward the hole center of the respective channel is generated by comparison to the spread of the space charge zone on the lateral boundary surface. This simplifies the lithographic requirements because already have a given current control, by comparison 1.4 times larger dimensions are obtained.
With respect to the reduction of the RC time constant, this results in an increase in the switching speed of the component.
Anyway, it can be advantageous to select the appropriate lateral dimensions of the openings contained in the sieve shape or their lateral cross sections from opening to opening or optionally to make them different. Thus, one obtains current channels with individually selectable lateral dimensions. It is conceivable to select the qeometric dimensioning of the openings of the sieve shape in a mathematic relationship to respective other openings so that by such a definition of the sieve shape, a given sub-linear or super-linear or nonlinear current-voltage characteristic is obtained for the component. For example, one can conceive of a sieve shape of circular openings in which the diameter of the first to the neighboring opening differ by a factor of 2.
Further advantageous embodiments of the component of the invention will be found in the remaining claims and with respect to the process of the invention in the following claims.
The process of the invention advantageously provides for the selection as the material for the base [Translators note: end of page 5] of AlGaAs. Where GaAs is selected as the basic material for the remaining active component layers within the layer sequence, a base composed of AlGaAs forms an etching stop tetching resist] upon appropriate selection of the etching agent.
As a consequence, also by the relatively reduced layer thickness CA21 173~1 -of the base, for example, the contacting of the base layer can provide a targeted stopping of the etching of the layers applied over the base until the surface of the base chemically different from GaAs has been penetrated to the correct depth. It will be self understood that the choice of this material is not limited only to the base. In addition, there is a possible location of such an etch stop where the overgrown channel should begin and directly over the highly doped layers which must be formed with contacts.
The objects are also achieved when an electronic component with the characterizing features of claim 18.
It is advantageous that the base has lateral circularly shaped and/or oval and/or s~uare openings. This is possible because the PJBT is homogeneously constructed, i.e. only from semiconductor material (e.g. GaAs). In this case, the space charge zone extends substantially uniformly from all sides into the current channel. As a result the latter can be constricted in two lateral directions, i.e. two dimensionally upon spreading of the space charge zone. In addition, this sieve structure, by contrast with a finger-like structure of the base, achieves a higher rate of rise [slope] of the component for the same voltage change in the form of a qreater current change in the channel.
Moreover a stronger spread of the space charge zone toward the hole center of the respective channel is generatèd by comparison tTranslators note: end of page 6] to the spread of the space charge zone on the lateral boundary surface. This simplifies the lithographic requirements because already have a given current control, by comparison 1.4 times larger dimensions are obtained.
With respect to the reduction of the RC time constant, this results in an increase in the switching speed of the component.
Anyway, it can be advantageous to select the appropriate lateral dimensions of the openings contained in the sieve shape or their lateral cross sections from opening to opening or optionally to make them different. Thus, one obtains current channels with individually selectable lateral dimensions.
Thus the laterally structured base is provided with one of the two pn transitions as the controllable space charge zone forming layer. The base contains on at least one of its two lateral boundary surfaces, at least one additional layer which is equally laterally structured and serves to reduce parasitic space charge capacitance ln the region of the lateral boundary surface of the base.
An advantageous further reduction of this parasitic space charge capacitance is then achieved when on both lateral boundary surface of the base, such a layer is provided. It is therefore advantageous to provide a semiconductive material with a doping reduced by at least a factor of 10 with respect to the charge carrier doping of the base as the material for this additional layer. [Translators note: end of page 7]
It can be advantageous, moreover, that within the layer a variation of the doping is provided whereby during epitaxial growth, for example, a targeted change of the doping substance can be achieved.
An especially advantageous embodiment of the component of the invention resides in that as the material for filling the respective region in the openings of the laterally structured base, which provides a single current channel, semiconductive material is provided which from the viewpoint of charge carrier doping, but also through the partial replacement of an element of the semiconductor e.g. Al in GaAs to AlxGAlxAS) so that the ~A21 1 7341 deposition of a semiconductive heterostructure provides an additional possibility to improve the current transport mechanism.
Further advantageous embodiments of the component according to the invention are found in the remaining claims and with respect to the process of the invention in the thereafter following claims.
In FIG. 1, a component according to the invention is shown, comprised of a p-channel and an n-channel PJBT on a single chip and is described in the following.
From the point of view of the process, the component in FIG. 1 is fabricated as follows:
In a first epitaxial process, a layer sequence is produced in which, upon a substrate of n-doped GaAs, a n+-i-p+-i-n+-i-layer sequence [Translators note: end of page 8] is grown epitactically in GaAs. (n+/p+ signifies n or p doped GaAs, i signifies intrinsic GaAs). In a subsequent step, an sio2 layer is vapor deposited upon this layer sequence. Thereafter, with the aid of an appropriate mask, the Sio2 cover layer is opened to form an etching mask for the production of the current channels ~A 2 1 1 734 1 of the p-PJBT. Next, with the aid of a reactive ion etching process and the etching mask structured as defined from the sio2 cover layer, the region provided for growth of the current channels is etched free to the p+ layer. In a further epitaxy step, this etched region is filled with p-doped GaAs.
Finally, even these field channels are covered with an sio2 layer.
To form the n-permeable base transistor shown in the right-hand part of the FIGURE, the there initially provided SiO2 cover layer as well as the upper i-layer and n+ layer are removed with the aid of an appropriate etching process. On the now highest lyinq plane/layer sio2 is newly vapor deposited and in known manner opened with the aid of a suitable etching mask for forming the regions provided for the current channels of the n-PJBT. Thereafter these are filled up to the n+ layer etchedregion in a third epitaxial step with n-doped GaAs and closed with an sio2 cover layer. For contacting, the highly doped n+ or p~ layers are exposed by etching and simultaneously for separating the regions provided as p channel PJBT or n channel PJBT, an insulating trough is etched on the n-doped substrate and the contacts are produced. [Translators note: end of page 9]
The component shown in FIGURE l represents an example for integration of multiple components on the same chip. It will be self-understood that further components, as, for example lasers constructed from PJBT's, photodetectors, can be additionally provided upon the chip.
By corresponding wiring, which advantageously also can be effected through the p+-, n+ layers, or via additional, deeper lying layers, optional circuits can be fabricated, e.g. an inverter comparable to a C-MOS-inverter or a Darlington-circuit.
For this purpose, it is of special significance that the individual transistors upon fabrication of the -especially-epitactic layer sequence, are provided with an sio2 layer.
Advantageously these layer sequences are thus preserved so that at other locations on the same chip further individual components can be fabricated.
Such a cover layer can indeed be made from SiO2, but also from Si3N4 or another suitable material. The material should thus be suitable as an etching mask, especially for CA 2 1 i 734 1 -reactive ion etching (RIE). For this the layer sequence in the semiconductor material (e.g. GaAs) should have as much as possible no diffusion and finally should enable selective epitaxy with sufficiently good characteristics.
Through the relatively small space-saving PJ~T's of the invention and such an advantageous effective integration method, tTranslator's note: end of page 10] very high integration densities can be achieved. The above indicated cover layers can thus be used as "substrates" for further epitactically grown layer sequences so that therewith a three dimensional networking on a single chip can be realized.
In FIG. 2 the schematic section of a PJBT according to the invention is illustrated, with a p-doped, laterally rectangular, sieve-shaped base.
Upon a silicon doped GaAs wafer (n = 3x 10l8 cm~3) a layer sequence: nip++i is deposited by means of MOMBE to a thickness of 900 nm.
After the epitaxy, a 60 nm thin SiO2 layer is vapor deposited and to improve the oxide, is tempered for several minutes at 550~C. Thereafter fine structuring up to 0.5~m is generated photolithographically (W) with a reverse lacquer (AZ 5206 IR).
Using CHF3, the oxide is opened by reactive ion etching (RIE), the lacquer is removed with ~2 plasma and finally troughs are etched in the oxide transfer mask through all layers to the n GaAs. The Sio2 is a satisfactory mask for HJCH4-RIE since it enables the generation of substantially perpendicular flanks.
With such a process a polymide is formed that again with ~2-plasma can be removed.
Prior to the renewed insertion in the epitaxial growth apparatus, the structured wafer must be cleaned by a wet chemical etching whereby in comparison with the structuring only thin surface layers are removed [Translator's note: end of page 11 and sio2 layer is not attacked. The parameters for the second etpitaxy are so selected that the channels are filled with GaAs of the desired doping and simultaneously the sio2 surface remains free. By means of this selectively filling epitaxy, only the previously etched troughs are filled and the distance between source and gate can be predetermined in the first epitaxy by the there-selected layer thickness of the intrinsic cover layer.
Thereafter, with several masking steps utilizing a liftoff process, metallization is vapor deposited for the contacts. For the source contact Au-Ge/SiO2 or Ni/Au-Ge/Ni can be utilized and can form by alloying it about 400 C in ohmic contacts.
Thereafter the SiO2 and, with H3PO~:H2O2, the i-GaAs over the gate are removed. Ti/Au is vapor deposited to yield an ohmic contact to the p~-GaAs and can also serve as contact reinforcement for the source contact. The drain contact is made above the backside of the wafer or simultaneously with the source contact. (NOTE: The drain, source and gate correspond to the concepts of collector, emitter and base). [Translator's note:
end of page 12]
19288 ~ TR~h~5~p~T i TRANSLATION
DESCRIPTION
ELECTRONIC COMPONENT AND PROCESS FOR MAKING IT
The invention relates to an electronic component, especially a p-channel or n-channel permeable base transistor [PBT] with a plurality of layers, fabricated in a laminated composite, and with at least one laterally structured layer provided for controlling a space charge zone, especially a base.
The invention further relates to a process for manufacturing such a component.
For use in super computers and fast data networks in the context of information technology, there are under development integrated circuits as fast microwave components. Of greater significance are integrated circuits on GaAs chips.
Components which have been used hitherto in this context are the MESFET and the HEMT. They both are so-called field effect transistors (FET), in which the current transport is parallel to the surface of the chip. An important speed determining r-A~ 1 1 7 34 1 parameter, the so-called "transit time under the gate" is here limited by the smallest lateral structuring of the gate achievable lithographically.
The permeable base transistor (PBT) proposed already in 1979, also deals with the principle of a field effect transistor was, although with a current flow direction perpendicular to the chip surface, in which the "transit time under the gate" was significantly reduced. ~Translator's note: end of page 1]
This had its basis in that the gate length in the vertical structuring was given by the thickness of the epitactically deposited base layer. With the methods of modern epitaxy, like modular beam epitaxy [MBE], metal organic gas phase epitaxy [MOCVD] or metal organic molecular beam epitaxy (MOMBE, CBE, GSMBE) for production of the metallic structured base, layer thicknesses in the range of several atom layers can be produced in a controlled manner.
From German Patent Application DE 40 25 269.8, a permeable base transistor is known, especially from GaAs. Thus several layers are bonded with one another which form the active elements of the components, namely, emitter, base and collector.
~A21 1 7341 The lateral finger-like structured base forms at its boundary surface a pn transition with the material surrounding it. These components as a result of thie characteristic have also been designated as permeable junction base transistors (PJBT). The thus formed space charge zone is controllable via the highly doped conductive base. As the basic material for the region surrounding the base and to which the current channels between the fingers of the base belong, is GaAs with an n-doping in the range of 1017 to lol~ cm~3 has been proposed. The p-doping of the base in the range of lo20 to 1021 cm~3 is achieved with the aid of a carbon doping.
The space charge zones formed on the boundary surface of the base are used for control of the electric current in the region of the current channels with the aid of a suitable voltage bias on the base. In this case ~Translators note: end of page 2]
it is a disadvantage that in the remaining space charge zone in the region of the lateral boundary surface of the base layer and spreading out therefrom, there is a parasitic space charge capacitance which limits the switchlng speed of the component disadvantageously.
It is an object of the invention to provide an electronic component of the type described at the outset in which this effect is reduced and which enables an increased switching speed. It is also an object to provide a corresponding method of making such a component.
These objects are achieved with an electronic component with the characterizing features of claim 1.
Thus the laterally structured base is provided with one of the two pn transitions as the controllable space charge zone forming layer. The base contains on at least one of its two lateral boundary surfaces, at least one additional layer which is equally laterally structured and serves to reduce parasitic space charge capacitance in the region of the lateral boundary surface of the base.
An advantageous further reduction of this parasitic space charge capacitance is then achieved when on both lateral boundary surface of the base, such a layer is provided. It is therefore advantageous to provide a semiconductive material with a doping reduced by at least a factor of 10 with respect to the C A~ ~ ~ 7~
charge carrier doping of the base as the material for this additional layer. [Translators note: end of page 3]
It can be advantageous, moreover, that within the layer a variation of the doping is provided whereby during epitaxial growth, for example, a targeted change of the doping substance can be achieved. An especially advantageous embodiment of the component of the invention resides in that as the material for filling the respective region in the openings of the laterally structured base, which provides a single current channel, semiconductive material is provided which from the viewpoint of charge carrier doping, but also through the partial replacement of an element of the semiconductor e.g. Al in GaAs AlxGalxAs) so that the deposition of a semiconductive heterostructure provides an additional possibility to improve the current transport mechanism.
A further, especially advantageous, embodiment of the electronic component resides in that the base is structured laterally with a sieve shaped.
Advantageously, the base can have lateral circular-shaped and/or oval and/or square openings. This is possible because the PJBT is homogeneously constructed, i.e. only fromsemiconductor material (e.g. GaAs). In this case, the space charge zone extends substantially uniformly from all sides into the current channel. As a result the latter can be constricted in two lateral directions, i.e. two dimensionally upon spreading of the space charge zone. In addition, this sieve structure, by contrast with a finger-like structure of the base, achieves a higher rate of rise [slope] of the component for the same voltage change in the form of a greater current change in the channel.
[Translators note: end of page 4] Moreover a stronger spread of the space charge zone toward the hole center of the respective channel is generated by comparison to the spread of the space charge zone on the lateral boundary surface. This simplifies the lithographic requirements because already have a given current control, by comparison 1.4 times larger dimensions are obtained.
With respect to the reduction of the RC time constant, this results in an increase in the switching speed of the component.
Anyway, it can be advantageous to select the appropriate lateral dimensions of the openings contained in the sieve shape or their lateral cross sections from opening to opening or optionally to make them different. Thus, one obtains current channels with individually selectable lateral dimensions. It is conceivable to select the qeometric dimensioning of the openings of the sieve shape in a mathematic relationship to respective other openings so that by such a definition of the sieve shape, a given sub-linear or super-linear or nonlinear current-voltage characteristic is obtained for the component. For example, one can conceive of a sieve shape of circular openings in which the diameter of the first to the neighboring opening differ by a factor of 2.
Further advantageous embodiments of the component of the invention will be found in the remaining claims and with respect to the process of the invention in the following claims.
The process of the invention advantageously provides for the selection as the material for the base [Translators note: end of page 5] of AlGaAs. Where GaAs is selected as the basic material for the remaining active component layers within the layer sequence, a base composed of AlGaAs forms an etching stop tetching resist] upon appropriate selection of the etching agent.
As a consequence, also by the relatively reduced layer thickness CA21 173~1 -of the base, for example, the contacting of the base layer can provide a targeted stopping of the etching of the layers applied over the base until the surface of the base chemically different from GaAs has been penetrated to the correct depth. It will be self understood that the choice of this material is not limited only to the base. In addition, there is a possible location of such an etch stop where the overgrown channel should begin and directly over the highly doped layers which must be formed with contacts.
The objects are also achieved when an electronic component with the characterizing features of claim 18.
It is advantageous that the base has lateral circularly shaped and/or oval and/or s~uare openings. This is possible because the PJBT is homogeneously constructed, i.e. only from semiconductor material (e.g. GaAs). In this case, the space charge zone extends substantially uniformly from all sides into the current channel. As a result the latter can be constricted in two lateral directions, i.e. two dimensionally upon spreading of the space charge zone. In addition, this sieve structure, by contrast with a finger-like structure of the base, achieves a higher rate of rise [slope] of the component for the same voltage change in the form of a qreater current change in the channel.
Moreover a stronger spread of the space charge zone toward the hole center of the respective channel is generatèd by comparison tTranslators note: end of page 6] to the spread of the space charge zone on the lateral boundary surface. This simplifies the lithographic requirements because already have a given current control, by comparison 1.4 times larger dimensions are obtained.
With respect to the reduction of the RC time constant, this results in an increase in the switching speed of the component.
Anyway, it can be advantageous to select the appropriate lateral dimensions of the openings contained in the sieve shape or their lateral cross sections from opening to opening or optionally to make them different. Thus, one obtains current channels with individually selectable lateral dimensions.
Thus the laterally structured base is provided with one of the two pn transitions as the controllable space charge zone forming layer. The base contains on at least one of its two lateral boundary surfaces, at least one additional layer which is equally laterally structured and serves to reduce parasitic space charge capacitance ln the region of the lateral boundary surface of the base.
An advantageous further reduction of this parasitic space charge capacitance is then achieved when on both lateral boundary surface of the base, such a layer is provided. It is therefore advantageous to provide a semiconductive material with a doping reduced by at least a factor of 10 with respect to the charge carrier doping of the base as the material for this additional layer. [Translators note: end of page 7]
It can be advantageous, moreover, that within the layer a variation of the doping is provided whereby during epitaxial growth, for example, a targeted change of the doping substance can be achieved.
An especially advantageous embodiment of the component of the invention resides in that as the material for filling the respective region in the openings of the laterally structured base, which provides a single current channel, semiconductive material is provided which from the viewpoint of charge carrier doping, but also through the partial replacement of an element of the semiconductor e.g. Al in GaAs to AlxGAlxAS) so that the ~A21 1 7341 deposition of a semiconductive heterostructure provides an additional possibility to improve the current transport mechanism.
Further advantageous embodiments of the component according to the invention are found in the remaining claims and with respect to the process of the invention in the thereafter following claims.
In FIG. 1, a component according to the invention is shown, comprised of a p-channel and an n-channel PJBT on a single chip and is described in the following.
From the point of view of the process, the component in FIG. 1 is fabricated as follows:
In a first epitaxial process, a layer sequence is produced in which, upon a substrate of n-doped GaAs, a n+-i-p+-i-n+-i-layer sequence [Translators note: end of page 8] is grown epitactically in GaAs. (n+/p+ signifies n or p doped GaAs, i signifies intrinsic GaAs). In a subsequent step, an sio2 layer is vapor deposited upon this layer sequence. Thereafter, with the aid of an appropriate mask, the Sio2 cover layer is opened to form an etching mask for the production of the current channels ~A 2 1 1 734 1 of the p-PJBT. Next, with the aid of a reactive ion etching process and the etching mask structured as defined from the sio2 cover layer, the region provided for growth of the current channels is etched free to the p+ layer. In a further epitaxy step, this etched region is filled with p-doped GaAs.
Finally, even these field channels are covered with an sio2 layer.
To form the n-permeable base transistor shown in the right-hand part of the FIGURE, the there initially provided SiO2 cover layer as well as the upper i-layer and n+ layer are removed with the aid of an appropriate etching process. On the now highest lyinq plane/layer sio2 is newly vapor deposited and in known manner opened with the aid of a suitable etching mask for forming the regions provided for the current channels of the n-PJBT. Thereafter these are filled up to the n+ layer etchedregion in a third epitaxial step with n-doped GaAs and closed with an sio2 cover layer. For contacting, the highly doped n+ or p~ layers are exposed by etching and simultaneously for separating the regions provided as p channel PJBT or n channel PJBT, an insulating trough is etched on the n-doped substrate and the contacts are produced. [Translators note: end of page 9]
The component shown in FIGURE l represents an example for integration of multiple components on the same chip. It will be self-understood that further components, as, for example lasers constructed from PJBT's, photodetectors, can be additionally provided upon the chip.
By corresponding wiring, which advantageously also can be effected through the p+-, n+ layers, or via additional, deeper lying layers, optional circuits can be fabricated, e.g. an inverter comparable to a C-MOS-inverter or a Darlington-circuit.
For this purpose, it is of special significance that the individual transistors upon fabrication of the -especially-epitactic layer sequence, are provided with an sio2 layer.
Advantageously these layer sequences are thus preserved so that at other locations on the same chip further individual components can be fabricated.
Such a cover layer can indeed be made from SiO2, but also from Si3N4 or another suitable material. The material should thus be suitable as an etching mask, especially for CA 2 1 i 734 1 -reactive ion etching (RIE). For this the layer sequence in the semiconductor material (e.g. GaAs) should have as much as possible no diffusion and finally should enable selective epitaxy with sufficiently good characteristics.
Through the relatively small space-saving PJ~T's of the invention and such an advantageous effective integration method, tTranslator's note: end of page 10] very high integration densities can be achieved. The above indicated cover layers can thus be used as "substrates" for further epitactically grown layer sequences so that therewith a three dimensional networking on a single chip can be realized.
In FIG. 2 the schematic section of a PJBT according to the invention is illustrated, with a p-doped, laterally rectangular, sieve-shaped base.
Upon a silicon doped GaAs wafer (n = 3x 10l8 cm~3) a layer sequence: nip++i is deposited by means of MOMBE to a thickness of 900 nm.
After the epitaxy, a 60 nm thin SiO2 layer is vapor deposited and to improve the oxide, is tempered for several minutes at 550~C. Thereafter fine structuring up to 0.5~m is generated photolithographically (W) with a reverse lacquer (AZ 5206 IR).
Using CHF3, the oxide is opened by reactive ion etching (RIE), the lacquer is removed with ~2 plasma and finally troughs are etched in the oxide transfer mask through all layers to the n GaAs. The Sio2 is a satisfactory mask for HJCH4-RIE since it enables the generation of substantially perpendicular flanks.
With such a process a polymide is formed that again with ~2-plasma can be removed.
Prior to the renewed insertion in the epitaxial growth apparatus, the structured wafer must be cleaned by a wet chemical etching whereby in comparison with the structuring only thin surface layers are removed [Translator's note: end of page 11 and sio2 layer is not attacked. The parameters for the second etpitaxy are so selected that the channels are filled with GaAs of the desired doping and simultaneously the sio2 surface remains free. By means of this selectively filling epitaxy, only the previously etched troughs are filled and the distance between source and gate can be predetermined in the first epitaxy by the there-selected layer thickness of the intrinsic cover layer.
Thereafter, with several masking steps utilizing a liftoff process, metallization is vapor deposited for the contacts. For the source contact Au-Ge/SiO2 or Ni/Au-Ge/Ni can be utilized and can form by alloying it about 400 C in ohmic contacts.
Thereafter the SiO2 and, with H3PO~:H2O2, the i-GaAs over the gate are removed. Ti/Au is vapor deposited to yield an ohmic contact to the p~-GaAs and can also serve as contact reinforcement for the source contact. The drain contact is made above the backside of the wafer or simultaneously with the source contact. (NOTE: The drain, source and gate correspond to the concepts of collector, emitter and base). [Translator's note:
end of page 12]
Claims (43)
1. An electronic component with a plurality of layers fabricated in a composite laminate and at least one laterally structured base to provide for control of a space charge zone.
characterized in that - a pn- transition is provided as the space charge zone with a p- conducting and a n- conducting layer, - the laterally structured base is provided as one of the two layers forming the pn transition and - at least on one, especially on both of the two lateral boundary surfaces of the base, an additional layer is provided showing the same lateral structuring for the purposes of reducing parasitic space charge capacitance in the region of the lateral boundary surface provided on the base and especially which are not for control of the space charge zone.
characterized in that - a pn- transition is provided as the space charge zone with a p- conducting and a n- conducting layer, - the laterally structured base is provided as one of the two layers forming the pn transition and - at least on one, especially on both of the two lateral boundary surfaces of the base, an additional layer is provided showing the same lateral structuring for the purposes of reducing parasitic space charge capacitance in the region of the lateral boundary surface provided on the base and especially which are not for control of the space charge zone.
2. The electronic component according to claim 1, characterized in that as the material for the additional layer on one of the two boundary surfaces of the base and bonded to the base, a material is provided which has a doping reduced by at least a factor of 10 by comparison to the base doping and is especially an intrinsically semiconductive material.
3. The electronic component according to claim 1 or claim 2 characterized in that the doping of a such further layer having the same lateral structuring as the first has a doping profile.
4. The electronic component according to claim 1, claim 2 or claim 3 characterized in that as the material for the respective semiconductor in the openings for the laterally structured base for the purpose of forming individual current channels with the respective channel having individually stepped doping and/or material profile, GaAs to which especially aluminum has been added is provided.
5. The electronic component according to one of the previous claims characterized in that the base is structured laterally in the form of a sieve.
6. The electronic component according to one of the preceding claims characterized in that the lateral sieve-shaped structured base has lateral circular and/or oval and/or square openings.
7. The electronic component according to one of the preceding claims characterized in that as the component a p-channel -or n-channel - permeable base transistor or a combination of one or more of these transistors is provided.
8. The electronic component according to one of the preceding claims characterized in that if the material for at least one of the active component layers, especially for the base, AlGaAs is provided with especially within the layer a varying aluminum proportion.
9. A process for producing an electronic component having a plurality of layers fabricated in a laminated composite in at least one laterally structured, space charge zone controlling base, characterized in that - for forming the space charge zone a p-conducting layer is bonded together with an n-conducting layer to a pn transition, - at this pn transition the laterally structured base forms one of the two layers and - at least on one of the two layers, especially on both laterally boundary layers of the base, an additional layer is provided with the same lateral structuring as the base for the purpose of reducing parasitic space charge capacitance in the region of the lateral boundary layer which is provided on the base and is bonded to the base but does not control the space charge zone.
10. The process according to claim 9 characterized in that as the material for the additional layer on one of the two boundary layers of the base and bonded to the base, an especially intrinsic semiconductor material is selected with a doping reduced by at least a factor of 10 by comparison to the base doping.
11. The process according to claim 10 characterized in that a layer with the laterally equivalent structuring as the first layer, is so fabricated that it has a gradually falling doping profile.
12. The process according to one of claims 9 through 11 characterized that as the material for the respective regions provided in the openings of the laterally structured base for the purpose of forming individual current channels, semiconductive material with individually stepped doping and/or material profile for the respective channel is selected.
13. The process according to one of claims 9 through 12 characterized in that the base is structured laterally with a sieve shape.
14. The process according to claim 13 characterized in that the laterally sieve shaped is formed laterally by circular and/or oval and/or square openings in the base.
15. The process according to one of claims 9 through 14 characterized in that the layer sequence with a laterally structured base, at least one additional layer and enabling layers bonded together with these both via current channels is fabricated by the use of an epitaxial process.
16. The process according to one of claims 9 through 15 characterized in that as the material is at least one of the active component layers, especially for the base, AlGaAs is selected, especially with an aluminum proportion varying within the layer.
17. The process according to one of claims 9 through 16 characterized in that after fabrication of an epitaxial layer sequence an individual transistor of this layer sequence is provided with an SiO2- or Si3N4 layer.
18. An electronic component with a plurality of layers fabricated in a laminated composite and with at least one laterally structured layer provided to control a space charge zone, characterized in that as the lateral structuring of this layer a sieve shape is provided.
19. An electronic component according to claim 18 characterized in that the sieve shaped lateral structuring oval and/or circular and/or square openings.
20. An electronic component according to claim 18 or claim 19 characterized in that as the laterally structured layer, a base is provided.
21. An electronic component according to one of the previous claims characterized in that as controllable shape charge zone, a pn transition with a p-conducting and an n-conducting layer is provided.
22. An electronic component according to claim 21 or one of the other preceding claims, characterized in that the laterally structured layer is comprised of highly p doped or n doped semiconductor material of a III-V compound [Group III
- Group V of the Periodic Table], especially of p- or n- doped GaAs.
- Group V of the Periodic Table], especially of p- or n- doped GaAs.
23. An electronic component according to claim 21 or one of the other preceding claims characterized in that the laterally structured layer is comprised of highly p-doped or n-doped semiconductor material of a II-VI compound [Group II- Group VI of the Periodic Table].
24. An electronic component according to one of the preceding claims characterized in that the laterally structured layer is comprised of highly p-doped or n-doped semiconductive material of Si or SixGe1-x.
25. An electronic component according to one of the claims 21 through 24, characterized in that the laterally structured layer at least on one side, especially on both sides, is provided with a further layer laterally equially structured therewith of a materal, especially an intrinsic semiconductive materal, having a doping which is less by at least a factor of 10 relative to the material of the first layer, on one of the two lateral boundary surfaces of the first laterally structured layer and bonded therewith.
26. An electronic component according to claim 25 characterized in that the doping of such further layer with the first laterally structured layer has a doping profile within the [further] layer.
27. An electronic component according to one of the preceding claims characterized in that as the material of at least one of the active layers, especially for the first laterally structured layer, AlGAaS is provided, especially with a varying aluminum proportion within the layer.
28. An electronic component according to one of the preceding claims characterized in that as the electronic component a permeable base transistor or a field effect transistor or a combination of these transistors is provided.
29. An electronic component according to one of the preceding claims characterized in one that as the material provided for the respective regions in the openings of the first laterally structured layer for the purpose of forming individual current channels, semiconductive material is provided with an individually stepped doping and/or material profile individual to the channel.
30. Process for producing an electronic component with a plurality of layers fabricated in a laminated composite and having at least one laterally structured layer for controlling a space charge zone, characterized in that this layer is laterally structured in a sieve shape.
31. A process according to claim 30 characterized in that the layer has laterally circular and/or oval and/or square openings structured in a sieve shape.
32. A process according to claim 30 characterized in that the layers are produced by the use of an epitaxial process and that the layer provided for controlling a space charge zone is laterally structured in a sieve shape.
33. A process according to claim 32 characterized in that the layer is structured with lateral circular and/or oval and/or square openings.
34. A process according to one of claims 30 to 33 characterized in that, for forming the space charge zone, a p-conducting layer is bonded together with an n- conducting layer to a pn transition.
35. A process according to claim 34 characterized that as the materal for the laterally structured layer p-doped or n-doped semiconductive material a III-V compound [Group III- Group V of the Periodic Table], especially p- or n- doped GaAs is selected.
36. A process according to claim 34 characterized in that as the material for the laterally structured layer, p-doped or n-doped semiconductive material of a II-VI compound [Group II- Group VI of the Periodic Table] is selected.
37. A process according to claim 34 characterized in that as the material for the laterally structured layer p-doped or n-doped semiconductive material of Si or SixG1-x is selected.
38. A process according to claims 34 to 37 characterized in that the laterally structured layer at least on one side, especially on both sides has a further layer laterally equivalently structured with it of especially intrinsic semiconductive material on one of the two lateral boundary surfaces of the first laterally structured layer and bonded thereto, which has, relative to the material of the first layer, a doping smalled by at least a factor of 10.
39. A process according to claim 38 characterized in that such a layer which is laterally identically structured with the first which is so fabricated that it has a gradually falling doping profile.
40. A process according to one of claims 30 to 39, characterized in that as the material for at least one of the active component layers, especially for the first laterally structured, AlGaAs is selected, especially with a varying aluminum proportion within the layer.
41. A process according to claims 38 to 40 characterized in that the base material for at least one of the further layers, the base material of the first layer is selected.
42. A process according to one of the claims 30 to 41 characterized in that as the electronic component a vertical field effect transistor or a permeable base transistor or a combination plurality of these transistors is selected.
43. A process according to one of the claims 30 to 42 characterized in that fabricated an epitactic layer sequence of a transistor, this layer sequence is provided with an SiO2 or an Si3N4 layer.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19914142654 DE4142654A1 (en) | 1991-12-23 | 1991-12-23 | P-channel or N-channel permeable base transistor - has screen-type laterally structured layer for controlling space charge zone |
| DEP4142595.2 | 1991-12-23 | ||
| DE19914142595 DE4142595C2 (en) | 1991-12-23 | 1991-12-23 | Electronic component and manufacturing method |
| DEP4142654.1 | 1991-12-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2117341A1 true CA2117341A1 (en) | 1993-07-08 |
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ID=25910448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002117341A Abandoned CA2117341A1 (en) | 1991-12-23 | 1992-12-19 | Electronic component and process for making it |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US5541424A (en) |
| EP (1) | EP0619921A1 (en) |
| JP (1) | JPH07502379A (en) |
| CA (1) | CA2117341A1 (en) |
| WO (1) | WO1993013560A1 (en) |
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| CA2117341A1 (en) * | 1991-12-23 | 1993-07-08 | Jurgen Graber | Electronic component and process for making it |
| US6011279A (en) * | 1997-04-30 | 2000-01-04 | Cree Research, Inc. | Silicon carbide field controlled bipolar switch |
| US6106454A (en) * | 1997-06-17 | 2000-08-22 | Medtronic, Inc. | Medical device for delivering localized radiation |
| US8017085B2 (en) | 2007-08-31 | 2011-09-13 | Unifrax I Llc | Substrate mounting system |
| CN102575542B (en) * | 2009-08-14 | 2014-09-10 | 尤尼弗瑞克斯I有限责任公司 | Mounting mat for exhaust gas treatment device |
| EP2464838A1 (en) * | 2009-08-14 | 2012-06-20 | Unifrax I LLC | Multiple layer substrate support and exhaust gas treatment device |
| US9385224B2 (en) * | 2014-08-13 | 2016-07-05 | Northrop Grumman Systems Corporation | Method of forming an integrated multichannel device and single channel device structure |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3381189A (en) * | 1964-08-18 | 1968-04-30 | Hughes Aircraft Co | Mesa multi-channel field-effect triode |
| FR2147883B1 (en) * | 1971-08-05 | 1977-01-28 | Teszner Stanislas | |
| US4171995A (en) * | 1975-10-20 | 1979-10-23 | Semiconductor Research Foundation | Epitaxial deposition process for producing an electrostatic induction type thyristor |
| US4719496A (en) * | 1982-11-24 | 1988-01-12 | Federico Capasso | Repeated velocity overshoot semiconductor device |
| US4901121A (en) * | 1985-03-29 | 1990-02-13 | American Telephone & Telegraph Co., At&T Bell Labs. | Semiconductor device comprising a perforated metal silicide layer |
| US4758534A (en) * | 1985-11-13 | 1988-07-19 | Bell Communications Research, Inc. | Process for producing porous refractory metal layers embedded in semiconductor devices |
| JPS6384066A (en) * | 1986-09-26 | 1988-04-14 | Semiconductor Res Found | Integrated optical trigger-optical quenching electrostatic induction thyristor and manufacture thereof |
| US5016074A (en) * | 1987-10-20 | 1991-05-14 | Bell Communications Research, Inc. | Epitaxial intermetallic contact for compound semiconductors |
| US4903089A (en) * | 1988-02-02 | 1990-02-20 | Massachusetts Institute Of Technology | Vertical transistor device fabricated with semiconductor regrowth |
| DE4025269A1 (en) * | 1990-02-07 | 1991-08-08 | Forschungszentrum Juelich Gmbh | ELECTRONIC COMPONENT AND METHOD FOR THE PRODUCTION THEREOF |
| FR2663466A1 (en) * | 1990-06-15 | 1991-12-20 | Thomson Csf | SEMICONDUCTOR COMPONENT WITH SCHOTTKY JUNCTION FOR HYPERFREQUENCY AMPLIFICATION AND FAST LOGIC CIRCUITS, AND METHOD FOR MAKING SAME. |
| CA2117341A1 (en) * | 1991-12-23 | 1993-07-08 | Jurgen Graber | Electronic component and process for making it |
-
1992
- 1992-12-19 CA CA002117341A patent/CA2117341A1/en not_active Abandoned
- 1992-12-19 US US08/256,600 patent/US5541424A/en not_active Expired - Fee Related
- 1992-12-19 WO PCT/DE1992/001080 patent/WO1993013560A1/en not_active Application Discontinuation
- 1992-12-19 EP EP93901646A patent/EP0619921A1/en not_active Withdrawn
- 1992-12-19 JP JP5511352A patent/JPH07502379A/en active Pending
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1997
- 1997-08-19 US US08/914,496 patent/US5814548A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| WO1993013560A1 (en) | 1993-07-08 |
| US5541424A (en) | 1996-07-30 |
| JPH07502379A (en) | 1995-03-09 |
| EP0619921A1 (en) | 1994-10-19 |
| US5814548A (en) | 1998-09-29 |
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