CA2114857A1 - Data Queueing Apparatus and ATM Cell Switch Based on Shifting and Searching - Google Patents

Data Queueing Apparatus and ATM Cell Switch Based on Shifting and Searching

Info

Publication number
CA2114857A1
CA2114857A1 CA2114857A CA2114857A CA2114857A1 CA 2114857 A1 CA2114857 A1 CA 2114857A1 CA 2114857 A CA2114857 A CA 2114857A CA 2114857 A CA2114857 A CA 2114857A CA 2114857 A1 CA2114857 A1 CA 2114857A1
Authority
CA
Canada
Prior art keywords
data
shift
destination
memory
searching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2114857A
Other languages
French (fr)
Other versions
CA2114857C (en
Inventor
Hideaki Yamanaka
Hirotaka Saito
Munenori Tsuzuki
Hirotoshi Yamada
Harufusa Kondoh
Kazuyoshi Oshima
Hiromi Notani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to CA002306286A priority Critical patent/CA2306286C/en
Publication of CA2114857A1 publication Critical patent/CA2114857A1/en
Application granted granted Critical
Publication of CA2114857C publication Critical patent/CA2114857C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478Provisions for broadband connections
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems 
    • H04L12/56Packet switching systems
    • H04L12/5601Transfer mode dependent, e.g. ATM
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/10Packet switching elements characterised by the switching fabric construction
    • H04L49/104Asynchronous transfer mode [ATM] switching fabrics
    • H04L49/105ATM switching elements
    • H04L49/108ATM switching elements using shared central buffer
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems 
    • H04L12/56Packet switching systems
    • H04L12/5601Transfer mode dependent, e.g. ATM
    • H04L2012/5638Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5651Priority, marking, classes
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems 
    • H04L12/56Packet switching systems
    • H04L12/5601Transfer mode dependent, e.g. ATM
    • H04L2012/5678Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681Buffer or queue management
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems 
    • H04L12/56Packet switching systems
    • H04L12/5601Transfer mode dependent, e.g. ATM
    • H04L2012/5685Addressing issues

Abstract

A data queueing apparatus processes data switching and queueing using a smaller capacity memory, while reducing data discard and loss possibility. Received limited-length data at the input line is written in shift memories, which can shift the data to the next stage regardless of the destination of the data. Destination indicating bits, which indicate the destination of the data, are associated with each of shift memories. A search circuit detects an asserted bit among the destination indicating bits corresponding to the output lines.
The data is extracted by a selector. Then the selector transmits the data to the desired output line, and the data stored in the previous stage of the shift memory is shifted.
The memory is used in common with a plurality of output lines, so that a lower possibility of data discard and loss can be attained in a smaller capacity memory.
CA002114857A 1993-02-15 1994-02-03 Data queueing apparatus and atm cell switch based on shifting and searching Expired - Fee Related CA2114857C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA002306286A CA2306286C (en) 1993-02-15 1994-02-03 Data queueing apparatus and atm cell switch based on shifting and searching

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2528093 1993-02-15
JPHEI5-025280 1993-02-15

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CA002306286A Division CA2306286C (en) 1993-02-15 1994-02-03 Data queueing apparatus and atm cell switch based on shifting and searching

Publications (2)

Publication Number Publication Date
CA2114857A1 true CA2114857A1 (en) 1994-08-16
CA2114857C CA2114857C (en) 2000-08-01

Family

ID=12161615

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002114857A Expired - Fee Related CA2114857C (en) 1993-02-15 1994-02-03 Data queueing apparatus and atm cell switch based on shifting and searching

Country Status (4)

Country Link
US (1) US5504741A (en)
EP (2) EP1030483B1 (en)
CA (1) CA2114857C (en)
DE (2) DE69429200T2 (en)

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JP3220599B2 (en) * 1993-12-28 2001-10-22 三菱電機株式会社 Data queuing device
SE506955C2 (en) * 1995-07-06 1998-03-09 Ericsson Telefon Ab L M ATM flow control
AU6648796A (en) * 1995-07-19 1997-02-18 Ascom Nexion Inc. Method and apparatus for queuing data in a communications device
US5956342A (en) 1995-07-19 1999-09-21 Fujitsu Network Communications, Inc. Priority arbitration for point-to-point and multipoint transmission
US5898671A (en) 1995-09-14 1999-04-27 Fujitsu Network Communications, Inc. Transmitter controlled flow control for buffer allocation in wide area ATM networks
US5991298A (en) 1996-01-16 1999-11-23 Fujitsu Network Communications, Inc. Reliable and flexible multicast mechanism for ATM networks
US5748905A (en) 1996-08-30 1998-05-05 Fujitsu Network Communications, Inc. Frame classification using classification keys
US6487212B1 (en) * 1997-02-14 2002-11-26 Advanced Micro Devices, Inc. Queuing structure and method for prioritization of frames in a network switch
JP3604282B2 (en) * 1998-06-15 2004-12-22 富士通株式会社 Address release method and common buffer device of ATM switching system using the same
US6584517B1 (en) 1999-07-02 2003-06-24 Cypress Semiconductor Corp. Circuit and method for supporting multicast/broadcast operations in multi-queue storage devices
US6603771B1 (en) 1999-07-02 2003-08-05 Cypress Semiconductor Corp. Highly scalable architecture for implementing switch fabrics with quality of services
US6628656B1 (en) 1999-08-09 2003-09-30 Cypress Semiconductor Corp. Circuit, method and/or architecture for improving the performance of a serial communication link
US6625177B1 (en) 1999-08-09 2003-09-23 Cypress Semiconductor Corp. Circuit, method and/or architecture for improving the performance of a serial communication link
DE10217856B4 (en) * 2002-04-22 2006-11-02 Infineon Technologies Ag Telecommunications network and method for transmitting data in a telecommunication network
US20040037558A1 (en) * 2002-08-20 2004-02-26 Nortel Networks Limited Modular high-capacity switch
AU2002951013A0 (en) * 2002-08-27 2002-09-12 Sunbay Software Ag System for improved network data access
US8861515B2 (en) 2003-04-22 2014-10-14 Agere Systems Llc Method and apparatus for shared multi-bank memory in a packet switching system
KR101595090B1 (en) * 2015-04-30 2016-02-17 주식회사 아마다스 Information searching method and apparatus using voice recognition
EP3681107B1 (en) * 2017-09-05 2022-10-26 Mitsubishi Electric Corporation Expanding the address range of on-board instruments to be mounted in a train

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FR2538976A1 (en) * 1982-12-29 1984-07-06 Servel Michel SYSTEM FOR SWITCHING SYNCHRONOUS PACKETS OF FIXED LENGTH
US4623996A (en) * 1984-10-18 1986-11-18 Mcmillen Robert J Packet switched multiple queue NXM switch node and processing method
US4692894A (en) * 1984-12-18 1987-09-08 Advanced Micro Devices, Inc. Overflow/Underflow detection for elastic buffer
US4734907A (en) * 1985-09-06 1988-03-29 Washington University Broadcast packet switching network
US4920534A (en) * 1986-02-28 1990-04-24 At&T Bell Laboratories System for controllably eliminating bits from packet information field based on indicator in header and amount of data in packet buffer
US4949301A (en) * 1986-03-06 1990-08-14 Advanced Micro Devices, Inc. Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs
US4730305A (en) * 1986-04-11 1988-03-08 American Telephone And Telegraph Company, At&T Bell Laboratories Fast assignment technique for use in a switching arrangement
US4821259A (en) * 1986-09-05 1989-04-11 American Telephone And Telegraph Company, At&T Bell Laboratories Control information communication arrangement for a distributed control switching system
CA1297567C (en) * 1987-02-06 1992-03-17 Kazuo Hajikano Self routing-switching system
JPH0714164B2 (en) * 1987-02-19 1995-02-15 富士通株式会社 Header driven packet switch
US4851991A (en) * 1987-02-24 1989-07-25 Digital Equipment Corporation Central processor unit for digital data processing system including write buffer management mechanism
BE1000396A7 (en) * 1987-03-18 1988-11-22 Electronique Et Telecomm Bell Switching system.
US4910731A (en) * 1987-07-15 1990-03-20 Hitachi, Ltd. Switching system and method of construction thereof
JPH0683261B2 (en) * 1987-05-26 1994-10-19 富士通株式会社 Header-driven packet switch
FR2618624B1 (en) * 1987-07-24 1992-04-30 Michel Servel HYBRID TIME MULTIPLEX SWITCHING SYSTEM WITH OPTIMIZED BUFFER MEMORY
SE462361B (en) * 1988-03-30 1990-06-11 Ellemtel Utvecklings Ab PAKETDATAVAELJARE
JP2667868B2 (en) * 1988-04-06 1997-10-27 株式会社日立製作所 Cell switching system
DE68929523T2 (en) * 1988-07-22 2005-12-15 Hitachi, Ltd. ATM switching system
JPH02117241A (en) * 1988-10-27 1990-05-01 Mitsubishi Electric Corp Data switching device
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JP2910770B2 (en) * 1989-03-20 1999-06-23 富士通株式会社 Self-routing switching system and current / standby switching method for self-routing switching system
JP2677418B2 (en) * 1989-06-22 1997-11-17 富士通株式会社 ATM switch system switching method
US5210744A (en) * 1989-06-28 1993-05-11 Mitsubishi Denki Kabushiki Kaisha Cell exchange apparatus
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US5291482A (en) * 1992-07-24 1994-03-01 At&T Bell Laboratories High bandwidth packet switch

Also Published As

Publication number Publication date
DE69433229D1 (en) 2003-11-13
DE69429200D1 (en) 2002-01-10
EP0612171A2 (en) 1994-08-24
CA2114857C (en) 2000-08-01
DE69433229T2 (en) 2004-08-12
EP1030483A1 (en) 2000-08-23
EP0612171A3 (en) 1995-09-27
EP0612171B1 (en) 2001-11-28
EP1030483B1 (en) 2003-10-08
DE69429200T2 (en) 2002-07-18
US5504741A (en) 1996-04-02

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