CA2114792A1 - Process for producing subsequently conditionable contact points on circuit substrates and circuit substrates with such contact points - Google Patents
Process for producing subsequently conditionable contact points on circuit substrates and circuit substrates with such contact pointsInfo
- Publication number
- CA2114792A1 CA2114792A1 CA002114792A CA2114792A CA2114792A1 CA 2114792 A1 CA2114792 A1 CA 2114792A1 CA 002114792 A CA002114792 A CA 002114792A CA 2114792 A CA2114792 A CA 2114792A CA 2114792 A1 CA2114792 A1 CA 2114792A1
- Authority
- CA
- Canada
- Prior art keywords
- conducting path
- conducting
- planes
- circuit carrier
- parts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4084—Through-connections; Vertical interconnect access [VIA] connections by deforming at least one of the conductive layers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
- H05K1/0289—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
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- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/0388—Other aspects of conductors
- H05K2201/0397—Tab
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/066—Heatsink mounted on the surface of the PCB
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/0909—Preformed cutting or breaking line
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
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- H05K2201/09327—Special sequence of power, ground and signal layers in multilayer PCB
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09554—Via connected to metal substrate
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09609—Via grid, i.e. two-dimensional array of vias or holes in a single plane
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09627—Special connections between adjacent vias, not for grounding vias
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09836—Oblique hole, via or bump
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09945—Universal aspects, e.g. universal inner layers or via grid, or anisotropic interposer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10666—Plated through-hole for surface mounting on PCB
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0548—Masks
- H05K2203/0554—Metal used as mask for etching vias, e.g. by laser ablation
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0736—Methods for applying liquids, e.g. spraying
- H05K2203/0746—Local treatment using a fluid jet, e.g. for removing or cleaning material; Providing mechanical pressure using a fluid jet
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1184—Underetching, e.g. etching of substrate under conductors or etching of conductor under dielectrics; Means for allowing or controlling underetching
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1545—Continuous processing, i.e. involving rolls moving a band-like or solid carrier along a continuous production path
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
- H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
- H05K3/0064—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a polymeric substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Liquid Crystal (AREA)
- Press Drives And Press Lines (AREA)
Abstract
ABSTRACT
The method for producing subsequently contactable contact points or pads between two conducting path planes of a circuit carrier separated from one another by an electrically insulating layer offers the possibility of e.g.
producing a basic conductor diagram, which can be quickly subsequently easily adapted to the corresponding needs. By making windows in the conducting path planes in such a way that during the following through-etching of the elect-rically insulating layer by undercutting land-like parts connected to the opening periphery are exposed between or in the openings and said exposed, land-like parts can be contacted with electrically conductive parts of the other conducting path plane by mechanically bending together said conductive paths in order to bring about an electrical connection.
(Fig. 6b)
The method for producing subsequently contactable contact points or pads between two conducting path planes of a circuit carrier separated from one another by an electrically insulating layer offers the possibility of e.g.
producing a basic conductor diagram, which can be quickly subsequently easily adapted to the corresponding needs. By making windows in the conducting path planes in such a way that during the following through-etching of the elect-rically insulating layer by undercutting land-like parts connected to the opening periphery are exposed between or in the openings and said exposed, land-like parts can be contacted with electrically conductive parts of the other conducting path plane by mechanically bending together said conductive paths in order to bring about an electrical connection.
(Fig. 6b)
Description
P~s~ ~a ` ' 211~732 METHOD F~R PROWCrNG SUBSEÇUENTLY CCNDITIONABLE CONTACT PADS ON CIRCUIT
CARRIERS AND CIRCUIT CARRIERS WITH SUCH CONTACT PADS
The invention is in the field of circuit carrier production and relates to a method according to the preamble of the first, independent claim for the pro-duction of subsequently conditionable contact points or pads on circuit carr-iers, as well as circuit carriers with such contac~ points or pads according to the preamble of the corresponding, independent claim. Subseguently condi-tionable contact points or pads are locations in a random layout of conducting paths on which two paths are, if required, contacted following the production of the circuit carrier, i.e. are electrically conductively interconnectable.
The problem of the invention is to produce subseguently conditionable contact pads on circuit carriers in such a way that given layouts can be conditioned by subsequently formable, electrical connections between conducting paths.
This is intended to make it possible to provide in circuit diagrams and on circuit boards locations, which can be subseguently contacted, which increases the flexibility of prefabricated circuits. Such "tactically distributed"
reequipping points in a circuit board cannot be produced using conventional layout and etching technology, because the latter involve hybrid processes.
However, it is important that the subseguent contacting can be adequately per-foLmed and the possibility of providing this remarkable extension of the pro-duct having these disadvantages does not lead to any significant cost increase.
This extension would e.g. make it possible in a production line to produce basic CilCUits with a plurality of variants over which a decision can be made at short notice. Thus, the invention allows a cost-optimizing, flexible, computer-assisted manufacture.
For the production of the conditionable contact points or pads according to the invention use is made of the phencmenon of undesired undercutting or under-etching. The undercutting phenomenon is known and every effort is made to avoi~ it. As a rule undercutting is undesired and prejudices the product quality. In order to produce the contact pads according to the in~ention it is carried out and utilized in planned manner. In the present invention a plasma etching process on a thin plastic foil metal-clad on both sides is used and to which beforehand windows have been made in the metal cladding by photo-chemical and wet etching process steps. For the conditioning of the condition-211~7~2
CARRIERS AND CIRCUIT CARRIERS WITH SUCH CONTACT PADS
The invention is in the field of circuit carrier production and relates to a method according to the preamble of the first, independent claim for the pro-duction of subsequently conditionable contact points or pads on circuit carr-iers, as well as circuit carriers with such contac~ points or pads according to the preamble of the corresponding, independent claim. Subseguently condi-tionable contact points or pads are locations in a random layout of conducting paths on which two paths are, if required, contacted following the production of the circuit carrier, i.e. are electrically conductively interconnectable.
The problem of the invention is to produce subseguently conditionable contact pads on circuit carriers in such a way that given layouts can be conditioned by subsequently formable, electrical connections between conducting paths.
This is intended to make it possible to provide in circuit diagrams and on circuit boards locations, which can be subseguently contacted, which increases the flexibility of prefabricated circuits. Such "tactically distributed"
reequipping points in a circuit board cannot be produced using conventional layout and etching technology, because the latter involve hybrid processes.
However, it is important that the subseguent contacting can be adequately per-foLmed and the possibility of providing this remarkable extension of the pro-duct having these disadvantages does not lead to any significant cost increase.
This extension would e.g. make it possible in a production line to produce basic CilCUits with a plurality of variants over which a decision can be made at short notice. Thus, the invention allows a cost-optimizing, flexible, computer-assisted manufacture.
For the production of the conditionable contact points or pads according to the invention use is made of the phencmenon of undesired undercutting or under-etching. The undercutting phenomenon is known and every effort is made to avoi~ it. As a rule undercutting is undesired and prejudices the product quality. In order to produce the contact pads according to the in~ention it is carried out and utilized in planned manner. In the present invention a plasma etching process on a thin plastic foil metal-clad on both sides is used and to which beforehand windows have been made in the metal cladding by photo-chemical and wet etching process steps. For the conditioning of the condition-211~7~2
- 2 -able contact pads, i.e. for the effective production of a contact, use is made of the jet scrubber method known in connection with circuit board technology in one of two planned, exemplified embo~iments.
Two embodiments of the invention are discussed hereinafter relative to the drawings. The foil etching process is preferably constituted by a plasma etching process, but it is fundamentally also possible to use wet methods.
The etching process for the metal cladding,, e.g. copper mask, can be a conven-tional circuit board production process.
Figs. ~ and b show in exemplified manner two windows etched in the metal cladding, which are aligned on in each case one side of a sub-strate, e.g. a plastic film (but other forms with functionally correlated contact points are possible). ;
',, Fig. 2 shows in section and diagrammatically the conditionable contact point, which is obtained through the through-etching of the sub~
strate and the undercutting of the two windaws according to fig. 1. -Fig. 3 shaws the contact point according to fig. 2, as is subsequently contacted by pressure on the lower and/or upper conducting paths. - ;
Fig. 4 shows another example for an etching window for producing a -~
subsequently conditionable contact point or pad.
Fig. 5 diagrammatically shows the conditionable contact pad, which results from the undercutting of an etching window according to fig. 4 and through-etching of the substrate.
igs. 6a and b show the contact pad according to figs. 4 and 5 contacted subsequently by means of jet scrubbing (fig. 6a) and subsequently fixed by means of a conductive fixing means (fig. 6b).
ig. 7 diagrammatically shows an exemplified embodiment of a circuit carrier with two conducting path planes and inventive contact ~ 3 - 211~7~2 pads b~tween them, the conducting path patterns and contact pads being designed in such a way that the circuit carrier is suit-able for the selective pin conversion of electronic components.
Fig. 8 shows the circuit carrier according to fig. 7 in section for making visible contact pads contacted and not contacted during the subsequent conversion. ~
.: ~ ':..
Fig. 9 shows a diagram of the nested standard grid of the circuit ~; -carrier according to figs. 7 and 8 with pin locations and conditionable contact pads.
Whereas windows for conventional plated-through holes in the substrate are noDmally round or square, the corresponding windcws for contact pads condition-able according to the invention and as shown in figs. la and b, e.g. have a land or bridge spanning the window, the two lands not being in the same direc-tion on facing windows. On through-etching the substrate these lands are left behind and undercut, so that following the etching stage they fonm crossing conducting paths passing over the openings and which bridge the resulting hole, as can be gathered from fig. 2. As a result of the fact that the substrate, if it is a plastic film, is only e.g. 12 to 25 ~m thick, this means that two copper conductors without interposed, solid dielectric cross or face one ~-another with a spacing of 10 to 20 ~m.
By local pressure, as is shown in fig. 3, optionally connected with thethrough-flow of a weak electric current, the two conductors of such a condi-tionable contact point or pad can selectively be welded together. In the case of thin foils or films such contact pads can be rapidly and securely pressed together, combined and therefore contacted using a fine, elastic punch/counter-punch. If necessary, the contact pad can subsequently be fixed with a dab of adhesive. In the case of thicker foils (over 100 um), the diameter-increased conducting paths (for space reasons here oval or elongated, rectangular shapes -of one of the two windows are recommended) are pressed in with one or two oppositely acting, fine pins S (as indicated by force arrows in fig. 3 and as a pin in fig. 5).
: . -: .
The second~ exemplified embodiment of the contact pads according to the inven- ~-"''; ~` '`' - 4 - 21~732 - ~
tion is less circuit board thickness-sensitive and is in particular recomm~
ended for thicker substrates.
Fig. 4 shows the etching window to be applied on one side for producing the second embodiment of the subsequently conditionable contact pad according to the invention. This window is a recess into which projects a tongue, whereas on the other side the cladding is left (in the form of a conducting path).
Follawing through-etching, which leads to a type of blind hole through the substrate and undercutting of the tongue, without any interposed solid dielectric the tongue projects freely at a distance of 10 to 200 ~m over the exposed d adding of the other side, as shown in fig. 5. The tongue is made correspondingly longer with greater thicknesses.
The two sides can be contacted with the aid of a pin S (fig. 5) or with the aid of planned jet scrubbing (indicated by many small force a~rows in fig. 6a), the tongue being bent towards the opposite cladding (fig. 6a). The contact is additionally fixed by introducing an electrically conductive adhesive or an uncured plastic (fig. 6b). The electrical through-connection can also be obtained exclusively by filling electrically conductive adhesive. The latter presses the tongue against the other side, links the two copper foils and pro-duces the electrical contact. The intrcduction of such an electrically con-ductive adhesive can take place by means of a printing process, such as screen process printing. Another possibility is to use an electrostatic printing process with an electrically conductive toner system. The toner is pressed by a conventional electrostatic printing procedure into the etched-out holes and is melted in by heat action.
In place of jet scrubbing electrical contact can also be carried out by means ~-of screen process printing, in that at the contact points, which are to be closed or through-contacted, solder paste is pressed into the contact points -and the sides to be connected are then soldered together by melting on the paste using hot air, IR, laser, gas-phase soldering or combinations of these methods.
It is readily apparent that for the second variant according to figs. 4 to 6 the substrate thickness is less i~portant than in the first case (figs. 1 to 3).The first variant is more particularly suitable for the conditioning of ~ ~ 5 ~ 2 ~ 1 4 7 3 2 contact points or pads accessible on both sides, i.e. on circuit carriers with substantially two conducting path planes on either side of the substrate. ~ -The second variant is more particularly suitable for conditionable contact pads between an accessible, outer conducting path layer and an inaccessible, inner conducting path layer.
As has been stated hereinbefore, the subsequently conditionable contact points produced according to the described method can be provided in random circuits~
Figs. 7, 8 and 9 show a special use, namely on a substrate, which is used for the selective conversion of the standard pin ccverage or occupancy of inte-grated circuits.
Commercially available, active components of a more ccmplex construction gen-erally have a larger number of connecting contacts or pins, which are arranged in accordance with a standard diagram and the layout of the circuit board to be provided with the component is based thereon. This leads to compulsions by the object in question, if only one such component is used on a circuit board, e.g. a microprocessor and this becomes even re serious when there are sev~
e-al such components.
On optimizing a layout without taking account of all the necessary pins of such components, whilst only taking account of the part to be placed in the layout, then the pin occupancy of the component must be converted in such a ;
way that it fits into the layout. Conversely this dictates the pin occupancy of the circuit boarl on the chip. Such conductor interfaces can be housed in the case of customized components either in the chip casing or in the base pin. Foil technology and the contact pads conditionable according to the invention are suitable for producing such interfaces.
Foil cimuit board technology makes it possible to produce circuit carriers with two conducting path planes with an extremely dense application of conduc- -tors and conditionable contact points between the conductor planes, so that it is possible within the standard grid arrangement of the pins of a chip to ~ -provide several conducting paths and contact points, so that in the base area there is an infrastructure with a large number of potential rerGuting points -~
through which the contacts of a random number of pins can be "displaced".
- ~: :. - :, - 6 - 2 1 ~ 4 7 ~ 2 Fig. 7 diagrammatically shows this infrastructure. A substrate S, generally a foil circuit board having approximately the size of the base, is provided on one side (top) with a plurality of parallel conducting paths. On the other side (bottom) is prcvided an equal number of parallel conducting paths, but which cross the upper ones. At each projected intersection of the conductors there is a conditionable contact point, as described in conjunction with figs.
1 to 6. Contacts can be selectively obtained at these contact points in a subsequent conditioning stage.
Fig. 8 shows the substrate S in section. To clarify the representation the contact points or pads with active contacts (closed, cf. figs. 3a and 6a/b) and passive contacts (open, cf. figs. 2 and S) are only symbolically shcwn.
It is possible to see the conductor arrangement at the top and bottom with active and passive contact point.s or pads between the same. Fig. 8 shows how a conducting path L is bridged, namely in that the upper conductox Lo is passed via an active contact to the lower conductor Lu and from there via another active contact to another upper conductor Lo. Between them it is possible to see open, passive contacts. If necessary, if the circuit density is to be increased, conductors, e.g. conductors Lu can be interrupted between two contacts, e.g. cut through with a laser. ~-.. . :
Fig. 9 shows the nested grid system. Circles indicate the pin grid of stan-dard components with the standard spacing N and with a mesh system the partial grid with the spacing T. There are sufficient degrees of freedom for the par-tial grid in order to adapt it to the technology used and also to the set requirements. On the left-hand side are diagrammatically shown square conn-ection points for the conversion substrate to the surrounding area.
It is advantagecus that it is possible to prefabricate substrates with the nested grids, in which the conducting paths are located and which are provided with conditionable contact pads at the projected intersections. By means of plasma etching it is possible to simultaneously produce all the contact points and by means of planned jet scrubbing a plurality of contact points can be conditioned in a single operation. In a layout router the calversion substrate is mathematically "carried alongn. The router checks whether intersections can be avoided by pin occupancy changes. It is to be assumed that with this tech-nology the number of "non-connectable" contacts would decrease by a factor of 10.
Two embodiments of the invention are discussed hereinafter relative to the drawings. The foil etching process is preferably constituted by a plasma etching process, but it is fundamentally also possible to use wet methods.
The etching process for the metal cladding,, e.g. copper mask, can be a conven-tional circuit board production process.
Figs. ~ and b show in exemplified manner two windows etched in the metal cladding, which are aligned on in each case one side of a sub-strate, e.g. a plastic film (but other forms with functionally correlated contact points are possible). ;
',, Fig. 2 shows in section and diagrammatically the conditionable contact point, which is obtained through the through-etching of the sub~
strate and the undercutting of the two windaws according to fig. 1. -Fig. 3 shaws the contact point according to fig. 2, as is subsequently contacted by pressure on the lower and/or upper conducting paths. - ;
Fig. 4 shows another example for an etching window for producing a -~
subsequently conditionable contact point or pad.
Fig. 5 diagrammatically shows the conditionable contact pad, which results from the undercutting of an etching window according to fig. 4 and through-etching of the substrate.
igs. 6a and b show the contact pad according to figs. 4 and 5 contacted subsequently by means of jet scrubbing (fig. 6a) and subsequently fixed by means of a conductive fixing means (fig. 6b).
ig. 7 diagrammatically shows an exemplified embodiment of a circuit carrier with two conducting path planes and inventive contact ~ 3 - 211~7~2 pads b~tween them, the conducting path patterns and contact pads being designed in such a way that the circuit carrier is suit-able for the selective pin conversion of electronic components.
Fig. 8 shows the circuit carrier according to fig. 7 in section for making visible contact pads contacted and not contacted during the subsequent conversion. ~
.: ~ ':..
Fig. 9 shows a diagram of the nested standard grid of the circuit ~; -carrier according to figs. 7 and 8 with pin locations and conditionable contact pads.
Whereas windows for conventional plated-through holes in the substrate are noDmally round or square, the corresponding windcws for contact pads condition-able according to the invention and as shown in figs. la and b, e.g. have a land or bridge spanning the window, the two lands not being in the same direc-tion on facing windows. On through-etching the substrate these lands are left behind and undercut, so that following the etching stage they fonm crossing conducting paths passing over the openings and which bridge the resulting hole, as can be gathered from fig. 2. As a result of the fact that the substrate, if it is a plastic film, is only e.g. 12 to 25 ~m thick, this means that two copper conductors without interposed, solid dielectric cross or face one ~-another with a spacing of 10 to 20 ~m.
By local pressure, as is shown in fig. 3, optionally connected with thethrough-flow of a weak electric current, the two conductors of such a condi-tionable contact point or pad can selectively be welded together. In the case of thin foils or films such contact pads can be rapidly and securely pressed together, combined and therefore contacted using a fine, elastic punch/counter-punch. If necessary, the contact pad can subsequently be fixed with a dab of adhesive. In the case of thicker foils (over 100 um), the diameter-increased conducting paths (for space reasons here oval or elongated, rectangular shapes -of one of the two windows are recommended) are pressed in with one or two oppositely acting, fine pins S (as indicated by force arrows in fig. 3 and as a pin in fig. 5).
: . -: .
The second~ exemplified embodiment of the contact pads according to the inven- ~-"''; ~` '`' - 4 - 21~732 - ~
tion is less circuit board thickness-sensitive and is in particular recomm~
ended for thicker substrates.
Fig. 4 shows the etching window to be applied on one side for producing the second embodiment of the subsequently conditionable contact pad according to the invention. This window is a recess into which projects a tongue, whereas on the other side the cladding is left (in the form of a conducting path).
Follawing through-etching, which leads to a type of blind hole through the substrate and undercutting of the tongue, without any interposed solid dielectric the tongue projects freely at a distance of 10 to 200 ~m over the exposed d adding of the other side, as shown in fig. 5. The tongue is made correspondingly longer with greater thicknesses.
The two sides can be contacted with the aid of a pin S (fig. 5) or with the aid of planned jet scrubbing (indicated by many small force a~rows in fig. 6a), the tongue being bent towards the opposite cladding (fig. 6a). The contact is additionally fixed by introducing an electrically conductive adhesive or an uncured plastic (fig. 6b). The electrical through-connection can also be obtained exclusively by filling electrically conductive adhesive. The latter presses the tongue against the other side, links the two copper foils and pro-duces the electrical contact. The intrcduction of such an electrically con-ductive adhesive can take place by means of a printing process, such as screen process printing. Another possibility is to use an electrostatic printing process with an electrically conductive toner system. The toner is pressed by a conventional electrostatic printing procedure into the etched-out holes and is melted in by heat action.
In place of jet scrubbing electrical contact can also be carried out by means ~-of screen process printing, in that at the contact points, which are to be closed or through-contacted, solder paste is pressed into the contact points -and the sides to be connected are then soldered together by melting on the paste using hot air, IR, laser, gas-phase soldering or combinations of these methods.
It is readily apparent that for the second variant according to figs. 4 to 6 the substrate thickness is less i~portant than in the first case (figs. 1 to 3).The first variant is more particularly suitable for the conditioning of ~ ~ 5 ~ 2 ~ 1 4 7 3 2 contact points or pads accessible on both sides, i.e. on circuit carriers with substantially two conducting path planes on either side of the substrate. ~ -The second variant is more particularly suitable for conditionable contact pads between an accessible, outer conducting path layer and an inaccessible, inner conducting path layer.
As has been stated hereinbefore, the subsequently conditionable contact points produced according to the described method can be provided in random circuits~
Figs. 7, 8 and 9 show a special use, namely on a substrate, which is used for the selective conversion of the standard pin ccverage or occupancy of inte-grated circuits.
Commercially available, active components of a more ccmplex construction gen-erally have a larger number of connecting contacts or pins, which are arranged in accordance with a standard diagram and the layout of the circuit board to be provided with the component is based thereon. This leads to compulsions by the object in question, if only one such component is used on a circuit board, e.g. a microprocessor and this becomes even re serious when there are sev~
e-al such components.
On optimizing a layout without taking account of all the necessary pins of such components, whilst only taking account of the part to be placed in the layout, then the pin occupancy of the component must be converted in such a ;
way that it fits into the layout. Conversely this dictates the pin occupancy of the circuit boarl on the chip. Such conductor interfaces can be housed in the case of customized components either in the chip casing or in the base pin. Foil technology and the contact pads conditionable according to the invention are suitable for producing such interfaces.
Foil cimuit board technology makes it possible to produce circuit carriers with two conducting path planes with an extremely dense application of conduc- -tors and conditionable contact points between the conductor planes, so that it is possible within the standard grid arrangement of the pins of a chip to ~ -provide several conducting paths and contact points, so that in the base area there is an infrastructure with a large number of potential rerGuting points -~
through which the contacts of a random number of pins can be "displaced".
- ~: :. - :, - 6 - 2 1 ~ 4 7 ~ 2 Fig. 7 diagrammatically shows this infrastructure. A substrate S, generally a foil circuit board having approximately the size of the base, is provided on one side (top) with a plurality of parallel conducting paths. On the other side (bottom) is prcvided an equal number of parallel conducting paths, but which cross the upper ones. At each projected intersection of the conductors there is a conditionable contact point, as described in conjunction with figs.
1 to 6. Contacts can be selectively obtained at these contact points in a subsequent conditioning stage.
Fig. 8 shows the substrate S in section. To clarify the representation the contact points or pads with active contacts (closed, cf. figs. 3a and 6a/b) and passive contacts (open, cf. figs. 2 and S) are only symbolically shcwn.
It is possible to see the conductor arrangement at the top and bottom with active and passive contact point.s or pads between the same. Fig. 8 shows how a conducting path L is bridged, namely in that the upper conductox Lo is passed via an active contact to the lower conductor Lu and from there via another active contact to another upper conductor Lo. Between them it is possible to see open, passive contacts. If necessary, if the circuit density is to be increased, conductors, e.g. conductors Lu can be interrupted between two contacts, e.g. cut through with a laser. ~-.. . :
Fig. 9 shows the nested grid system. Circles indicate the pin grid of stan-dard components with the standard spacing N and with a mesh system the partial grid with the spacing T. There are sufficient degrees of freedom for the par-tial grid in order to adapt it to the technology used and also to the set requirements. On the left-hand side are diagrammatically shown square conn-ection points for the conversion substrate to the surrounding area.
It is advantagecus that it is possible to prefabricate substrates with the nested grids, in which the conducting paths are located and which are provided with conditionable contact pads at the projected intersections. By means of plasma etching it is possible to simultaneously produce all the contact points and by means of planned jet scrubbing a plurality of contact points can be conditioned in a single operation. In a layout router the calversion substrate is mathematically "carried alongn. The router checks whether intersections can be avoided by pin occupancy changes. It is to be assumed that with this tech-nology the number of "non-connectable" contacts would decrease by a factor of 10.
Claims (16)
1. Method for producing subsequently contactable contact pads between two conducting path planes of a circuit carrier separated by an electrically insulating layer, particularly a plastic film, characterized by the placing of openings in at least one of the conducting path planes in such a way that during the subsequent through-etching of the substrate as a result of under-cutting land-like conducting path parts, connected to the opening periphery, are exposed between or in the openings, said exposed, land-like conducting path parts being combinable with electrically conductive parts of the other conducting path plane.
2. Method according to claim 1, characterized in that in both conducting path planes are made corresponding openings with the diameters of passing-through lands, the lands being directed in such a way that they intersect in the pro-jection and in that in a further stage the electrically insulating layer is etched away between two corresponding lands, so that the lands are freely superimposed and can, if required, be contacted by engaging with one another.
3. Method according to claim 1, characterized in that in one conducting path plane are made openings corresponding to the conductor pattern of the other conducting path plane with a conducting path part projecting into the opening and connected to the opening periphery, said conducting path part being directed in such a way that in projection it covers a conductor point of the other conducting path plane and in that in a further stage the insulating layer between the two conducting path planes is etched through the opening, so that the conducting path part is freely located over the corresponding contact pad and, if required, can be contacted by bending with the other contact pad.
4. Method according to claim 2, characterized in that for contacting at the contact pads the facing conducting path parts are moved together by means of a pin (S) and electrically conductively connected.
5. Method according to claim 2, characterized in that for contacting at the contact pads the exposed space between the lands is filled with an electric-ally conductive material.
6. Method according to claim 3, characterized in that for contacting at the contact pads the conducting path part connected to the opening periphery and projecting into the opening is bent by means of jet scrubbing (small force arrows) into the passage in the circuit board substrate in order to be cont-acted with the other side of the conductor pattern.
7. Method according to claim 6, characterized in that the conducting path part bent into the passage is fixed with a conductive material.
8. Method according to one of the claims 5 or 7, characterized in that the electrically conductive material is an adhesive or toner.
9. Method according to claim 8, characterized in that the electrically conduc-tive material is introduced into the contact pads by a screen printing process.
10. Circuit carrier with conditionable or conditioned contact points or pads between two conducting path planes separated from one another an electrically insulating layer and produced according to the method according to any one of the claims 1 to 9, characterized in that it has conducting path parts through passages through the electrically insulating layer, which are mechanically deformable and/or deformed and contacted with a conductor of the facing cond-ucting path plane.
11. Circuit carrier according to claim 10, characterized in that the mechan-ically deformable and/or deformed conducting path parts are crossing conduc-ting path portions extending over the passage on either side.
12. Circuit carrier according to claim 10, characterized in that the mechan-ically deformable and/or deformed conducting path parts emanate from the per-iphery of a passage and are bendable or bent into said passage.
13. Circuit carrier according to any one of the claims 9 to 12, characterized in that the deformed conducting path parts are fixed with electrically cond-uctive material in the contact position.
14. Circuit carrier according to claim 13, characterized in that the contact pads have electrically conductive materials introduced by screen process printing.
15. Circuit carrier according to any one of the claims 9 to 14, characterized in that the two conducting path planes in each case have an arrangement of parallel directed conducting paths, the conducting paths of one plane not being parallel to the conducting paths of the other plane and on at least part of the intersections of the conducting paths of the two planes are provided conditionable or conditioned contact pads.
16. Circuit carrier according to claim 15, characterized in that the conduc-ting path arrangement of the two conducting path planes are at an angle of 90° to one another.
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9212648.1 | 1992-06-15 | ||
CH187592 | 1992-06-15 | ||
CH1875/92-1 | 1992-06-15 | ||
CH1876/92-3 | 1992-06-15 | ||
GB929212648A GB9212648D0 (en) | 1992-06-15 | 1992-06-15 | Etched foil pcb |
CH187692 | 1992-06-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
CA2114792A1 true CA2114792A1 (en) | 1993-12-16 |
Family
ID=27173312
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002114792A Abandoned CA2114792A1 (en) | 1992-06-15 | 1993-06-10 | Process for producing subsequently conditionable contact points on circuit substrates and circuit substrates with such contact points |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP0600052B1 (en) |
JP (1) | JPH07505015A (en) |
AT (1) | ATE137079T1 (en) |
AU (1) | AU4058693A (en) |
CA (1) | CA2114792A1 (en) |
DE (1) | DE59302260D1 (en) |
WO (1) | WO1993026144A1 (en) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19633449A1 (en) * | 1996-08-20 | 1998-02-26 | Univ Dresden Tech | Spatial grid structure of functional elements for communications MHz and GHz range signals |
JP3799468B2 (en) * | 2000-01-19 | 2006-07-19 | 住友電装株式会社 | Circuit board manufacturing method, circuit board manufactured by the method, and electrical junction box including the circuit board |
US6449839B1 (en) * | 2000-09-06 | 2002-09-17 | Visteon Global Tech., Inc. | Electrical circuit board and a method for making the same |
JP4003556B2 (en) * | 2002-06-27 | 2007-11-07 | 株式会社デンソー | Printed circuit board manufacturing method |
WO2004027866A2 (en) * | 2002-09-23 | 2004-04-01 | Johnson Controls Technology Company | Method for creating a link in an integrated metal substrate |
US7745733B2 (en) | 2005-05-02 | 2010-06-29 | 3M Innovative Properties Company | Generic patterned conductor for customizable electronic devices |
US7352058B2 (en) | 2005-11-01 | 2008-04-01 | Sandisk Corporation | Methods for a multiple die integrated circuit package |
US7511371B2 (en) | 2005-11-01 | 2009-03-31 | Sandisk Corporation | Multiple die integrated circuit package |
EP1949440A2 (en) * | 2005-11-01 | 2008-07-30 | SanDisk Corporation | Multiple die integrated circuit package |
TWI451817B (en) * | 2011-05-26 | 2014-09-01 | 豐田自動織機股份有限公司 | Wiring board and method of manufacturing the wiring board |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3098951A (en) * | 1959-10-29 | 1963-07-23 | Sippican Corp | Weldable circuit cards |
GB1134632A (en) * | 1965-02-13 | 1968-11-27 | Elliott Brothers London Ltd | Improvements in or relating to the production of printed circuits |
US3346950A (en) * | 1965-06-16 | 1967-10-17 | Ibm | Method of making through-connections by controlled punctures |
US4064357A (en) * | 1975-12-02 | 1977-12-20 | Teledyne Electro-Mechanisms | Interconnected printed circuits and method of connecting them |
US4319708A (en) * | 1977-02-15 | 1982-03-16 | Lomerson Robert B | Mechanical bonding of surface conductive layers |
FR2480554A1 (en) * | 1980-04-15 | 1981-10-16 | Eaton Manford | Solderless printed circuit and through hole connections - comprising plastics board with punched holes, with circuits on metal foil adhered and metal filled plastic connections |
US4517050A (en) * | 1983-12-05 | 1985-05-14 | E. I. Du Pont De Nemours And Company | Process for forming conductive through-holes through a dielectric layer |
-
1993
- 1993-06-10 CA CA002114792A patent/CA2114792A1/en not_active Abandoned
- 1993-06-10 EP EP93909756A patent/EP0600052B1/en not_active Expired - Lifetime
- 1993-06-10 AU AU40586/93A patent/AU4058693A/en not_active Abandoned
- 1993-06-10 JP JP6500997A patent/JPH07505015A/en active Pending
- 1993-06-10 AT AT93909756T patent/ATE137079T1/en active
- 1993-06-10 WO PCT/CH1993/000147 patent/WO1993026144A1/en active IP Right Grant
- 1993-06-10 DE DE59302260T patent/DE59302260D1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH07505015A (en) | 1995-06-01 |
WO1993026144A1 (en) | 1993-12-23 |
DE59302260D1 (en) | 1996-05-23 |
ATE137079T1 (en) | 1996-05-15 |
EP0600052A1 (en) | 1994-06-08 |
AU4058693A (en) | 1994-01-04 |
EP0600052B1 (en) | 1996-04-17 |
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Legal Events
Date | Code | Title | Description |
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FZDE | Discontinued |