CA2104754C - Multirate, sonet-ready, switching arrangement - Google Patents

Abstract

A time-division multiplex switch (100) switches a hierarchy of data rates. It sets up higher-rate connections not as a plurality of individual lowest-rate connections but as one or more time slots in each one of a plurality of sequential frames (40, 50) that correspond to that higher rate in each superframe (30). A time-slot-interchange switching element (131, 141) of the switch utilizes a plurality of physically orlogically distinct double-buffered data memories (301,302,303) each corresponding to a different one of the superframe and different-size ones of the frames. Reading and writing of each of the data memories' buffers alternates with the corresponding one of the superframe and different-size frames; reading of a data memory's buffer immediately follows writing of that buffer. Information from all incoming time slots is written into each one of the data memories, but only information corresponding to the data rate of an individual data memory's corresponding frame size is read from that data memory into outgoing time slots. A control memory (305) maps memory locations of the data memories to output time slots. A corresponding control architecture in a switching element (1700) of a time-multiplexed switch (120) uses a control memory (1701) that maps input ports to time slots of an output port.

Description

- - 21047~

MULTIRATE, SONET-READY, SWITCHING ARRANGEMENT
Technical Field This invention relates to telecomml-nications switching.
Background of the Invention Time-division multiplex (TDM) circuit-switching techniques have been in widespread comllle~ial use for quite some time. Central to typical prior-art TDM
arrangements is the notion of a "frame" divided into a predetermined number of time slots. The frame has a fixed, predetermined duration, and individual duplicate frames follow each other in sequential succession. Thus each time slot recurs at a 10 fixed frequency, or rate, referred to herein as the "frame rate". For example, if the frame has a duration of 125 ~lsec, each time slot recurs at a rate of lt(l25xlO-6) sec=8 KHz. Each con~mullicating frame is assigned to one or more time slots and,when the time slot(s) occur, the channel is enabled to place data on andtor remove data from the TDM medium (e.g. a collln~ullications link or a switching fabric). The 15 traffic of the different colllmunicating channels is thereby interleaved on the TDM
medium. If a plurality of non-adjacent time slots within a single frame is assigned to a channel, that channel's traffic is also interleaved inside each frame with the traffic of other channels.
In recent years, standards have been developed for the transport of 20 broadband comlllul-ications. Among these are the Synchronous Optical Network (SONET) and the similar Synchronous Digital Hierarchy (SDH). The expected growth in synchronous transport facilities based on SONET and SDH ~UppOl ls a need for more efficient synchronous switch fabric architectures. The modular byte-interleaved structure of SONET is based on Synchronous Transport Signal level 1, or 25 STS- 1, format, in which overhead plus payload results in a rate of 51.840 Mb/s. The STS-l frame consists of 90 columns by 9 rows of bytes, or 810 bytes, with a frame rate of 125 lls. The first three columns in the frame are devoted to transport overhead (TOH), while the r~ Ai~ g 87 columns carry the payload, including one - 21047Sl column devoted to path ovcrhcad (POH). 87 columns of payload constitute a Synchronous Payload Envelopc (SPE). Howcvcr, an SPE can cross frarnc boundaries, and is allowed to float anywherc within the payload-carrying portion of one or more contiguous frames to accommodate thc semi-synchronous nature of the 5 transport facilities. For switching of rates below the STS- I ratc, a switch assumes that the path overhead has been aligned with the f~rst column following transport overhead.
Super STS-l signals (STS-N) are forrne~ by byte-multiplexing the N
constituent STS-l signals, with the resultant bandwidth being N times that of the 10 STS-l rate. Conversely, sub STS-l signals are transported in Virtual Tributaries (VTs), of which four sizes are de~ned at present, namely VTl.5 (1.728 Mb/s), VT2(2.304 Mb/s), VT3 (3.456 Mb/s) and VT6 (6.912 M/b/s). To accornmodate mixes of VTs, the VT-structured STS-l SPE is divided into 7 VT groups, with each group occupying 12 columns of the 9-row frame structure; 2 columns remain unused and 15 are referred to as Sl UFF columns. A VT group may contain 4 VT1.5s, 3 VT2s, 2VT3s, or 1 VT 6. Both the super STS and sub STS signals retain the frame rate of125 ~s.
FIG. 2 shows a 3~imensional representation of an STS-12 frarne as an illustrative example. There are 12 vertical planes which represent the 12 STS-ls, 20 each composed of 90 columns and 9 rows, for a total of 9720 bytes. Vertical columns may be grouped to forrn Virtual Tributaries (VTs), as shown by the four regularly-spaced columns ie~resenting a VT2 in position #3. While a VT2 requires4 regularly-spaced columns, as shown, a VTI.5 requires 3 regularly-spaced columns, a VT3 requires 6 regularly-spaced colurnns, and a VT6 requires 12 regularly-spaced 25 colurnns. Finally, a DS-0, corresponding to a 64 kilobits-per-second rate, appears as a single byte within one row and column. There are a maximum of 774 DS-Os per STS- 1, some of which may be used for additional overhead functions; 7S6 DS-Os are available for traffic transport.
The three component sub-rates of an STS-N frame -- STS-l, VT, and 30 DS~ -- may be switched independently by three separate switching fabrics, each dedicated to switching one of the sub-rates. But this is inefficient in the amount of equipment used: it requires demultiplexers at the inputs to the switching fabrics to separate the sub-rates, a separate switching fabric for each sub-rate, and multiplexers at the outputs from the switching fabrics to combine the switched su~rates back into 35 STS-N frames. The use of a single switching fabric for all sub-rates is therefore preferable.

- 210~75~

Given a switching fabrie capable of switching multiple rates within an STS-N format, one is faced with the problem of efficiently setting up multirate calls through such a fabrie. One approach is to treat a call of any given bandwidth asmulliple DS-0 calls. Although this is a flexible approach, the disadvantage is that a 5 path-hunt and a path-setup must be performed individually for each DS-0 call. For example, a single STS-l call would require as many as 810 individual path hunts and control-memory-setups. This is inefficient both in terms of the amount of time required for the path hunting and the number of control comrnunications required to set up the individual paths. There is an associated need for switching elements that 10 are adapted for efficient multirate application.
Summary of the Invention This need is met and a technical advance is achieved in accordance with the principles of the invention in a switching element and associated control method where the switching element switches a hierarchy of data rates including a lowest 15 rate corresponding to one time slot of a time-division &ame of time slots, and at least one higher rate corresponding to a plurality of time slots -- preferably of predefined spacing, for ease of implementation -- within the time~ivision frame. Generally,according to one aspect of the invention, rather than setting up a higher rate connection as a plurality of individual lowest-rate connections, a set of time slots for 20 the connection is determined from a single time slot that is specified by a cornmand that requests the connection to be made. Locations are determined in a control memory that correspond to the set of time slots, and those locations are used to store information defining the connection. The switching element is then operated in response to reading of the stored connection information from the control memory to 25 establish the higher-rate connection. Illustratively, the switching element serves either as a tirne-slot interchange switching element or as a time-multiplexed space-switching element. In the former case, the specified single time slot is illustratively speciSed in terms of an output time slot and a corresponding input time slot that maps thereinto. In the latter case, the specified single tirne slot is illustratively 30 specified in terms of an output time slot and a corresponding port.
Furthermore, a connection is established through the switching element at the lowest rate by using a single time slot within the frame that is specified by the cornmand requesting the lowest-rate connection. The corresponding control memorylocation is used to store the necessary connection inforrnation, which is read to 35 operate the switching element to establish the lowest-rate connection. Illustratively, the switching element is a time-slot interchanger, the control memory locations correspond to output time-slots of the time-slot interchanger, and the inforcnation - 21047~4 - defining the connection idcntifies input timc slots of thc time-slot interchanger.
Alternatively, the switching element is a time-multiplcxed space switch having firs~
(e.g., input) ports and a second (e.g., output) port, the control memory locations correspond to output time slots of the switch, and the information defining the 5 connection identifies one of the first ports.
Illustratively, the connection command specifies a data-rate corresponding to a plurality of time slots of predefined spacing within the time-division multiplex frame, and output time slots -- and corresponding input time slots in the case of the time-slot interchanger -- are determined in accordance with the 10 predefined spacing. In the illustrative embodiment herein, the time-division multiplex frarne is an STS-12 frame and the hierarchy of data rates comprises anSTS- I rate, any of a plurality of VT rates, and a DS-0 rate.
According to another aspect of the invention, a switching element --illustratively functioning as a time-slot interchanger -- for switching the hierarchy of 15 the data rates comprises first double-buffered data memory locations corresponding to each time slot of the superframe, second double-buffered data memory locations corresponding to each time slot of the predefined frame, and a control memory for defining switched connections at the lowest and the higher rate. Reading and writing of the first double-buffered data mernory locations alternates with the superframes.
20 That is, one buffer of the data memory locations is written during a first superframe and another buffer of those locations is read during the first su~.rlame, but the onc buffer is read during a next superframe and the other buffer is wrinen during the next superframe. Most significantly, reading and writing of the second double-buffered data memory locations alternates with the frames. In accordance with the switched-25 connecdon definitions stored in the controt memory, information is read from thcfirst double-buffered data memory locadons to effect switched connectdons at the lowest rate, and info~nation is read from the second double-buffered data memorylocations to effect switched connections at the higher rate. Illustradvely, informadon is likewise written into the first locations to effect the lowest-rate connections and is 30 written into the second locations to effect the higher-rate connections; in one implementation, all information is written into both the first and the second locations.
In one disclosed embodiment, the first and second double-buffered data memory locations are physically located in separate double-buffered data memories.
35 In another disclosed embodiment, the first and second locations are physically located in one double-buffered data memory, and the second locations are a subset of the first locations. In one disclosed variant of the second embodiment, the second -- locations arc N-buffered wherc N is an integer greatcr than two, and a sequcnce of N buffers of the second locations and buffers of the first locations occupy samcphysical locations of the data memory. The N buffers of the sequence are writtensequentially, and reading of an individual buffer of the sequence occurs while 5 writing occurs in an immediately-succeeding buffer of the sequence.
According to a further aspect of the invention, the switching element comprises a plurality of physical or logical data memories each one of which corresponds to a different one of (a) the superframe and (b) different-size ones of the frames within the superframe. Significantly, each data memory has information 10 written thereinto during an individual frame period of the corresponding one of the superframe and the different-size frarnes, and has information read therefrom during a frarne period of the corresponding one of the superframe and the different-size frames which immediately follows the individual frame period. Received infomlation, contained by an incoming superframe and its included frames, is 15 written into corresponding ones of the data memories. A control arrangement, such as a control memory shared by the plurality of data memories, maps time slots of the incoming superframe into time slots of an outgoing superframe. This mapping is followed in reading, into an outgoing superframe and its included frames, the stored information from corresponding ones of the data memories. ~eading of data 20 memory locations alternates between different ones of the data memories with changes in a corresponding one of the data rates of successive switching elementoutput time slots. Illustratively, writing of data memory locations likewise altemates between different ones of the data memories with changes in a corresponding one of the data rates of successive switching element input time slots.
Illustratively, the control arrangement indicates, for individual switching-element output dme slots, a corresponding data rate of the hierarchy, and in response thereto information is read from the data memory that corresponds to the superframe during output tirne slots for which the control arrangenxnt indicates the lower rate, while inforrnation is read from the data memory that corresponds to the 30 frames that correspond to the higher rate during output time slots for which thc control arrangement indicates the higher rates. Further illustratively, the control arrangement gives the l~ce rate indication for input time slots, and in responscthereto information is correspondingly written into one or another of the memories during those input time slots.
According to yet a further aspect of the invention, the control memory of the switching element includes a different control memory location for each timc slot of an outgoing SUpC,Iîî~nC. In the case of a tirnc-slot interchange switching 211)~7~4 elcment, con~ents of each control memory location indica~c which input time slot is to be connected to the corresponding output time slot during every occurrence of that corr~sponding output time slot. In the case of time-multiplexed spacc-switching element, contents of each control memory location indicate which first (e.g., input) 5 port is to be connected to the corresponding output time slot of the switchingelement during every occurrence of that corresponding output time slot. The contents of different ones of the control memory locations are then used during different time-slot intervals to effect connections at the lowest and the higher rates.
The switching element further includes an arrangement for programming the control 10 memory to define an individual switched connection corresponding to a selected rate of the hierarchy. The programming arrangement detects occurrence of an output time slot corresponding to the individual switched connection within each frame (including superframe) that corresponds to the selected rate in an output superframe, and writes into the control memory location that corresponds to the detected time 15 slot the infonnation that specifies either one of the input time slots or one of the first ports that is to be connected to the output time slot during each occurrence of that output time slot that corresponds to the written control memory location.
In a switching system constructed and operated according to one or more aspects of the invention, a hierarchy of data rates may be switched in a singlc 20 shared switching fabric. Yet each data rate undergoes a swi~ching delay that is proportional only to its corresponding frame rate. This means that the higher the data rate, the less switching delay it encounters. Any desired connection requires the specification of only a single time slot. Other tirne slots which are required for higher-rate connections are then determined automatically, and control memories are 25 automatically programrned accordingly. Programming of connections is thereby simplified. The data memories of a switching element share a control memory, thereby simplifying the architecture and the programming of desired connections.The same control architecture may be used for switching elements of different types, resulting in yet further architectural simplicity. And because of the commonality of 30 the control architecture, different switching elements can share portions of the control circuitry, resulting in further simplification, reduced circuit-pack size, and cost savings.
These and other advantages and features of the invention will ~ecome apparent from the following description of an illustrative embodiment of the 35 invention taken together with the drawing.

21047S~

-- Brief Description of the Dra~in~
FlG. I is a block diagrarn of a time-division multiplex circuit-switching system that incorporates an illustrativc cmbodiment of the invendon;
FIG. 2 is a block diagram of thc in~ernal configuration of a SONET
5 STS-12 frarne;
FIG. 3 is a block diagram of a first illustrative embodiment of a time-slot interchanger CTSI) of the system of FIG. l;
FIG S. 4-6 are a circuit diagram of a first illustrative implementation of the TSI of FIG.3;
FlG. 7 is a table of the ranges of address values that define frames of different types in the TSI implementation of FIG S. 4-6;
FIG S. 8-9, aIong with FIG. 4, are a circuit diagram of a second illustrative implementation of the TSI of FIG. 3;
FIG. 10 is a block diagram of a second illustrative embodiment of a TSI
15 of the system of FIG. 1;
FIG. l l- l 3 are a circuit diagram of an illustrative implementation of the TSI of FIG. 10;
nG. 14 is a block diagram of a third illustrative embodiment of a TSI of the system of FIG. l;
FIG S. 15-17 are a circuit diagrarn of a first illustrative implementation of the TSI of FIG. 14;
FIG. 18 is a table of the address-compensation values of the 4-word shift register of the TSI implementation of E;IG S. 15-17;
FIG S. 19-21 are a circuit diagrarn of a second illustrative implementation of the TSI of FIG.14;
FIG. 22 is a block diagram of the time-multiplexed switch (TMS) of the system of FIG. l;
FIG. 23 iS a circuit diagram of a first illustrative implementation of an output control of the TMS of FIG. 22;
FIG. 24 iS a circuit diagram of a second illustrative implen-~ontation of an output control of the TMS of FIG. 23;
FIG. 25 is a circuit diagram of a third illustrative implementation of an output control of the TMS of l;IG. 22;
FIG. 26 is a circuit diagram of a fourth illustrative implementation of an 35 output control of the TMS of FIG. 22;

21047~4 , FIG. 27 is a block diagram of timeslot-status table-hierarchies for thc TSls of thc swi(ching system of FIG. 1, which hierarchics are implemented by matriccs shown in FIGS. 28-31;
FIG. 28 is a block diagram of TSI STS-I ~imeslot block status matrices 5 for the TSIs of the switching system of FIG. I;
FIG. 29 is a block diagram of VT timeslot block status matrices for the TSIs of the switching system of FIG. I;
FIG. 30 is a block diagram of VT group status matrices for the TSIs of the switching system of FIG. 1;
FIG. 31 is a block diagrarn of DS-0 timeslot block status matrices for the TSIs of the switching system of FIG. l;
FIGS. 32-33 are a flow diagram of a broadband path-hunt procedure performcd by the control processor of the switching system of FIG. 1;
FIG. 34 is a flow diagram of multiple STS- 1 path-hunt pr~cedure of the 15 broadband path-hunt procedure of FIGS. 32-33;
FIG. 35 is a flow diagram of one STS-I paLh-hunt procedure of the multiple STS-1 path-hunt procedure of FIG. 34;
FIG 36 is a flow diagram of multiple VT6 path-hunt procedure of the broadband path-hunt procedure of FIGS. 32-33;
FIGS. 37-43 are a flow diagram of one VT6 paLh-hunt procedure of the multiple VT6 path-hunt procedure of FIG. 36;
FIG. 44 is a flow diagram of multiple V~3 paLh-hunt procedure of the broadband path-hunt procedure of FIGS. 32-33;
FIGS. 45-51 are a flow diagram of one VT3 path-hunt procedure of the 25 multiple VT3 path-hunt procedure of FIG. 44;
FIG. 52 is a flow diagram of multiple VT2 path-hunt procedure of Lhe broadband path-hunt procedure of FIGS. 32-33;
FIGS. 53-59 are a flow diagram of one VT2 path-hunt procedure of the multiple VT2 path-hunt procedure of FIG. 52;
FIG. 60 is a flow diagram of multiple VTl.S path-hun~ procedure of the broadband path-hunt procedure of FIGS. 32-33;
FIGS. 61-67 are a flow diagram of one VTl.5 path-hunt procedure of the multiple VTl.5 path-hunt procedure of FIG. 60, FIG. 68 is a flow diagram of multiple DS-0 path-hunt procedure of the 35 broadband path-hunt procedure of FIGS. 32-33; and 210~7S4 g `- FIGS. 69-95 are a flow diagrarn of onc DS-0 path-hunt procedure of thc multiple DS-0 palh-hunt procedure of FIG. 68.
Detailed Dcscription FIG. I is a block diagram of an exemplary SONET switching system S 100 in accordance with Ihe invention. System 100 is of the time-space-timc (T-S-T) type with 64 input time-slot interchangers (TSls) 131 connected to system input links 111 through elastic stores 121 and their output links 161, a central 64x64 timc-multiplexed switch (TMS) 120 connected to output links 171 of TSIs 131, and 64 output time-slot interchangers 141 connected to TMS output links 181 and to system 10 output links 151. Input TS~s 131 each receive the 9720 bytes of SONET STS-12 frames (FIG. 2) incoming on their respective input links 161 after they are aligned by elastic stores 121 A central control processor l l0 controls system l00 and, in particular, perforrns path hunts through the system and controls the various switching elenxnts (TSIs, TMS) in accordance with the path-hunt results.
It is well-known in the art that, in an NxN switching fabric, 2N paths are needed through the switch in order to obtain strictly-non-blocking performance. It is also well-known to obtain the 2N paths through a T-S-T switch by duplicating theT-S-T stages and operating the two duplicate fabrics in parallel. This duplication is assumed but not shown in FIG. 1 in order to avoid undue complexity of the 20 illustration.
As was mentioned previously, FIG. 2 is a SONET STS-12 frarne map.
Note that the 90 columns of each of the twelve included STS- 1 frames include four overhead columns (colurnns 0-3) as well as two stuffcolumns (columns 32 and 61).FIG. 2 illustrates the four columns used for a single VT2 virtual tlibutary. The four 25 columns are evenly spaced apan by 21 columns (excluding stuflf columns). Other virtual tributary rates VTl.5, VT3, VT6 may also be accommodated within the forrnat. A single DS-0 (64 kilobits-per-second) channel represents a single byte of the STS- 12 frame.
Note that the layout of the 9720 bytes of a single 1 25-microsecond 30 frame is depicted in three dimensions, with the order of trancmission (1-2-3) as shown on the right-hand side of FIG. 2. Ille twelve STS- 1 frames are thus transmitted in a byte-interleaved manner. One byte of the same row and column ofeach STS-1 frame is transmitted in succession, followed by one byte of the same row and next colurnn of each STS- 1. When one byte of each column of a row of each 35 STS- 1 frarne has been transmitted, trAnsmission proceeds to the first column of the next row of each STS- 1 frarne, and the process repeats.

21047~4 ._ --10--- Rcturning to FIG. 1, cach input TSI 131 is capablc of swi~ching any of the 9720 bytes, or timc slots, of an STS-12 framc receivcd from an ctastic store 121 to any other byte position, or time slot, on a dmc-multiplexed link 171 to TMS 120;
all time-slot interchanging occurs within the boundaries of individual STS-12 S frames; each output TSI 141 has a like capability. The SONET STS-12 format is maintained internally within system 100, with the exception that a parity bit is added to each eight-bit byte for internal transmission.
A first illustrative embodiment of a TSI 131 or 141 is shown in FIG. 3.
As indicated, TSI 131 or 141 comprises three data buffer memories 301-303. Each 10 memory 301-303 is double-buffered: it comprises two buffers 311 and 312, one of which is written while the other is read and the two of which alternate in timc between being read and written. I~ach memory 301-303 has its data input connected to its TSI's input link 161 or 181 and receives all bytes of each incoming STS-12 frame. The data outputs of the three memories 301-303 of an individual TSI are lS connected to inputs of a selector 304 whose output is connected to the TSI's output link 171 or 151. Atanyonetime, thedataoutputofonlyoneofthememories 301-303 of a TSI is selected by selector 304 as the output of that TSI. Memories301-303 and selector 304 of each TSI 131 or 141 operate under control of a control memory 305.
Each memory 301-303 of a TSI 131 or 141 serves a different type of tr~nsmission rate. Memory 301 serves the DS-0 rate, memory 302 serves the VT
rate, and memory 303 serves the STS- I rate. The different ra~es require different amounts of buffering, resulting in memories 301-303 being of different depths. Aparticular DS-0 channel appears in the data stream of an STS-12 frame only once,every 9720 bytes. Hence, memory 301 must buffer a filll STS-12 frarne, and so each buffer 311 and 312 of memory 301 is 9720 bytes deep. A particular VT channel appears in the data stream of an STS- 12 frame at least once in every row of one of the t~,velve STS-ls, i.c., at least once in each horizontal plane of rows that make up the STS-12 frame. Hence, memoIy 302 must buffel one such horizontal p]ane.
30 Every such horizontal plane comprises 12 (one for cach STS-l)-by-86 (one for each column excluding overhead and stuff columns), or 1008, bytes. Therefore, each buffer 311 and 312 of memory 302 is 1008 bytes deep. Finally, a par~cular STS-l channel appears in the data stream of an STS-12 frame every 12th byte. Hence, memory 303 must buffer 12 bytes of an STS- 12, and so each buffer 311 and 312 of35 memory 303 is 12 bytes deep.

210~751 - For casc of understanding, memory 301, opcrating under control ofcontrol mcmory 305, may be thought of as implementing aTSI 131 or 141 for 9720-byte frarnes (shown as STS-12 or DS-0 frame 30 in FIG. 2); memory 302 may be thought of as implementing a TSI for 1008-byte frames (shown as VT frame 40 in S FIG. 2), and memory 303 may be thought of as implementing a TSI for 12-bytc frames (shown as STS frarne 50 in FlG. 2). Since the rate of a full STS-12 superframe is 125 ~s, memory 301 causes a buffering delay of 125 ~ls for DS-0 rate traf~ic, memory 302 causes a buffering delay of only 1/9-125 lls for VT rate traffic, and memory 303 causes a buffering delay of only 1/810 125 ~s for STS-l ratc 10 traffic. This is a significant improvement over the conventional buffering delay of at least the full-frame rate of 125 ~s for all traffic rates.
While the 9720 time-slot STS-12 has been referred to above as a superframe that comprises STS- I, VT, and DS-0 frames, an alternative and equivalent terminology is to refer to the STS-12 as a frame and to refer to the STS-15 I s, VTs, and DS-0s as su~frames. For ease of discussion, the STS-12s, STS- ls, VTs, and DS-0s will all be referred to below merely as frames.
FIGS. 4-6 collectively make up a first illustrative implementation of TSI 131 or 141 of FIG. 3. FIG. 4 depicts various frarne-byte, or time-slot, counters that serve as control memory 305 address generators. Although the bytes received20 by input TSI 131 comprise eight bits, the internal time slots comprise an additional ninth parity bit; accordingly, a 9-bit byte clock CLK/9 s;gnal line 520 is used to drive each of four time-slot counters: a modulo-12 counter 501, a modulo-90 counter 502, a modulo- 1008 counter 506, and a modulo-9720 counter 511. The counters are reset by a FRM signal line 521 at the end of each STS-12 or DS-0 25 fiame 30. Modulo-12 counter 501 generates a four-bit STS ADDRESS, and when itreaches its tenninal count, at the end of an STS frame 50, it generates a terminal count ~TC) signal to toggle a flip-flop 504 that generates an STS FRM signal in response, and to enable modulo-90 counter S02. Accordingly, modul~90 counter 502 counts the 90 columns of the STS-l frame forrnat (FIG.2) and generates 30 a corresponding COL signal. When it r~aches its terminal count, modulo-90 counter 502 also generates a TC signal. The TC signal outputs of both counters 501 and 502 are connected to inputs of an AND gate 503. I~us, when both modulo-12 counter 501 and modulo-90 counter 502 reach their terrninal count, AND gate 503 generates a VT FRM END signal to indicate the end of a VT frarne 40, and also 35 toggles a flip-flop 505 to generate a VT FR~ signal. The VT FRM END signal isused to reset modulo-1008 counter 506. The COL signal is transmitted to inputs of each of three comparators 507, 508, 509, whose outputs effectively disable modulo-21047~

1008 countcr via NOR gatc S10 for columns <=3, =32, or =61, whcrcby thc ovcrhcadand stuff columns are not countcd as part of VT framc 40. Modulo- 1008 counler 506 gcnerates a 10-bit VT ADDRESS signal. Modulo-9720 counter 511 generates a 14-bit DS-O address signal, and when it reaches its terrninal count, at the 5 end of a DS-O frame 30, it generates a TC signal to toggle a flip-flop 512 that generates a DSO ~RM signal in response.
FIG. S is a diagram of the circuitry that generates control dat~ for storage in control memory 305 of a TSI 131 or 141 from inforrnation supplied as a result of a path-hunt perforrned by control processor 110. This control information 10 specifies which incoming time-slot of an incoming STS-12 frame is to be switched to which outgoing time-slot of the corresponding outgoing STS-12 frame. Since system 100 is adapted to establish connections of three types of rates (that is, STS-l, VT, and DS-O connections), and treats each type as having its own frame size (that is, respectively, STS frame 50, VT frame 40, and DS-O frame 30), the control I S circuitry must be able to distinguish which time slots belong to which of these three types of frames 30, 40, and 50.
At least two possible ways of accomplishing this distinction offer themselves. One is to use the same sequential numbers to designate the same sequential time slots of all three types of frarnes, but associate with each number an 20 indication (e.g., a separate number) that indicates which type of frame is being referred to. The other is to use numbers from different number ranges to designate time slots of the different frarne types, whereby the range used serves as the indication of which frame type is being referred to. The illustrative implementation shown in FIGS. 5-7 adopts the latter approach.
The time-slot coding table that is used to identify both the type of connection (type of frame) as well as the initial time slot of that connection is shown in FIG. 7. As shown, a VT frame 40 add;ress is encoded with the four most-significant bits having a binary value of 1110 (or a hexadecimal value of OxE~), and an STS frarne 50 address is encoded with the four most significant bits having a30 binary value of 1111 (or a hexadecimal value of OxF). lbe rem~ining bits for a VT
or an STS frarne define the first time slot of that connection. DS-O connections, which represent a single time slot, are encoded by decirnal numbers from O through 9719.
Retun~ing to FIG. 5, the path-hunt information that defines a par~cular 35 single connecdon selected by control processor 110 is received from processor 110 in three registers: an input time-slot register 601, an output time-slot register 602, and an offset register 603. Contents of output time-slot register 602 identify a - 21~754 - par~icular timc-slot at thc output of a TSI 131 or 141 according to the convcntion of FIG. 7. Contents of input timc-slot register 601 identify, also according to thcconvention of FIG. 7, the input timc-slot that is to bc switched to thc output timc-slot identified by register 602. Circuitry associated with input time-slo~ register 601 in 5 FIG. 5 generates the control data that are to bc stored in control memory 305.Circuitry associated with output timc-slot register 602 in FIG. 5 determines at which address of memory 305 the just-mentioned control data arc to bc stored. Thc addresses of control rnemory 305 have a one-to-one correspondence to the 9720 output time slots of an STS-12 frame output by a TSI 131 or 141.
Offset register 603 receives the constant offset, or spacing betwecn data-bearing columns of an STS-12 frame, that is necessary for the type of VT
connection being set up. For example, for a VT2 connection, an offset of 21 12=2S2 (decimal) would be stored in offset register 603. The stored offsets are 336, 168, or 84 for the other VTI.5, VT3, and VT6 connections, respectively. Contents of 15 offset register 603 are null for a non-VT connection. Preferably, an additional register (not shown) further receives information that selects one of the duplicate switching fabrics that were discussed in conjunction with FIG. 1.
Control memory 305 is updated on-the-fly. Norrnally, control memory 305 is only read, in a cyclical manner. When it is necessary to change a 20 word of control memory 305, the circuitry of FIG. S waits until occurrence of the cycle during which that word of control memory 305 is normally read. It then changes the cycle to a write cycle, writes the new data word into control memory 305, and at the same time supplies that data word to the other circuitry of TSI 131 or 141 in place of the now-overwritten data word that would haYe normally 25 been read from control memory 305.
Comparators 609 and 610 respectively determine whether the four most-significant bits in register 602 define a YT or an STS connection. The respective VT and STS outputs of comparators 609 and 610 control a selector 617.If the contents of register 602 define an STS connection, a control memory 305 30 write-enable (CM WE) signal is generated by selector 617 each time the four least-significant bits of register 602 are equal to the STS ADDR generated by modulo-12 counter 501, as indicated by the output of a comparator 614. If the contents of register 602 define a DS-0 connection (signified by no match being detected at comparators 609 and 610), a CM ~NE signal is generated by selector 617 during the 35 tirne slot when the 14 bits of register 602 are equal to the DS-0 ADDR generated by modulo-9720 counter 511, as indicated by the output of a comparator 61S.

21047.S~

Whereas each STS connection occurs once during each STS frarne S0 and ~ach DS-0 connection occurs once during each DS-0 frame 30, each VT
connection occurs one or more times during each VT frame 40. Hence, the matter is ~more complicated when lhe contents of register 602 define a VT connection. For the 5 case of a VT connection, ~here is provided an S-R flip-flop 618 that is set by the VT FRM END output of gate 503 of FIG. 4 and that is reset by the CM_WE output of setector 617. When it becomes set at the end of an STS-I, flip-flop 618 generates a VT_STRT signal that contTols a selector 611 and causes selector 611 to select a first one of its two inputs for connection to its output. The first input of selector 611 10 is connected to the nine least-significant bits of output time-slot register 14, whereas the second input of selector 611 is connected to the output of a register 612.
When the contents of register 602 define a VT connection, either the contents of register 612 or the nine least-significant bits of output time-slot register 602 are transmitted by a selector 611 to comparator 616, depending upon15 whether the first or a subsequent occurrence of the VT connection in a VT frame 40 is being searched for. When those bits are the same as the VT ADDR generated by modulo-100~ counter 506, as indicated by comparator 616, selector 617 generates a CM WE signal. The output of selector 611 is also added by an adder 613 to the contents of offset register 603, and the sum is stored in register 612. The contents of 20 register 612 are transrnitted via selector 611 to comparator 616, and a CM WE is generated by selector 617 during the next occurrence of the VT connection in this VT frame 40. This process repeats throughout each VT frarne 40.
Preferably, comparator 616 is disabled, by VT DISABLE signal generated by gate 510 of nG. 5, during the occurrence of output time slots that 25 correspond to the overhead and stuff columns of an STS-I. This disabling of comparator 616 lessens the possibility of a spurious, erroneous, output from comparator 616 while modulo-1008 counter 506 is disabled.
As was mentioned previously, the information that is written in control memory 305 (E~IG. 6) comes from input tirne-slot register 601. The four most-30 significant bits are always written directly to control memory 305. In the case of anSTS or DS-0 connection, the 10 least-significant bits are also written directly to control memory 305. However, for VT connections, an arrangement compris;ng a selector 605, an adder 607, and a register 606 generates the input tirne-slot identifiers for the VT connection, and transrnits those via a selector 608 to control rnemory 305.
35 The arrangement comprising elements 605-607 duplicates the arrangement comprising elements 611-613, with the exception that the fi~st input of selector 605 is connected to the 10 least-significant bits of input time-slot register 601.

21047~

Selector 608 is controllcd by thc VT output of comparator 609, analogously to selector 617.
FlG. 6 is a diagrarn of the circuitry that implemcnts control by memory 305 over a TSI 131 or 141. llle conlents of mernory 30S represent thc 5 input-time-slot to output-time-slot assignment that is to be effected by a TSI 131 or 141 for each STS-12 frarne. Because an STS-12 or DS-0 frame 30 has 9720 time slots, memory 305 is 9720 words deep. Addresses of memory 305 words arc sequenced-through by the DS~ ADDR generated by modulo-9720 counter 511 of FlG. 4. Normally, CM WE signal line is not asserted and the words of memory 305 10 are cyclically read out, one word per time-slot interval, to provide on an ADDR
bus 701 the address of a word of the appropriate one of data memories 301-303 that is to be written out as the output of the TSI during that instant time-slot. A word of control data is written into memory 305 in response to the CM_~E signal line being asserted. In response to this assertion, the fourteen-bit address CM DATA that is generated in FIG. S is output by a gate 701 onto ADDR bus 701, from where it is both written into memory 305 and made available to the other circuitry of FIG. 6 in place of the address that would otherwise normally have been read out of memory 305.
As was mentioned previously, each memory 301-303 serves a different one of the STS, VT, and DS-0 connection types. Memories 301-303 are double-buffered: each of the two buffers 311 and 312 is alternatively wntten during onecorresponding fra ne period and is read during the next corresponding frame period.
The data input DATA ~N, which corresponds to link 161 or 181, is connected to all three of data memories 301-303, and each incoming STS-12 frame is written into each one of these memories 301-303. At each memory 301-303, DATA ~ is connected through a respective one of selectors 731-733 to the data inputs of both buffers 311 and 312. Which buffer 311 or 312 is written at any given time is controlled at each memory 301-303 respectively by the STS FRM, VT FRM, and DS0 FRM signals, ~4hich control the outputs of selectors 731-733, respecdvely.
Addresses are conveyed to data rnemories 301-303 in the following manner. At each memory 301-303, ADDR bus 701 is connected to a first input of one, and the second input of another, of a pair of selectors. 704-705, 711-712, and 721-722, respectively. The second input of the one, and the first input of the other, of the pair of selectors 704-705 is connected lO the STS ADDRESS signal line from rnodulo-12 counter 501 of FIG. 4 and both selectors are con~olled by the STS FRMsignal line from flip-flop 504 of FIG. 4. The second input of the one, and the first input of the other, of the pair of selectors 711-712 is connected to the VT ADDRESS

210475~

signal line from modulo- 1008 counter 506 of FIG. 4 and both selectors arc controlled by thc VT FRM signal linc from flip-flop 50S of FIG. 4. And the sccond input of the one, and the first input of the other, of thc pair of sclectors 721-722 is connected to thc DS-0 ADDRESS signal line from modulo-9720 counter 511 of S FIG. 4 and both selectors are controlled by the DS0 FRM signal line from flip-flop S 12 of FIG. 4. The output of each selector of the three pairs of selectors 704-705, 711 -712, and 721 -722 is connected to the address input of a different one of the buffers 311 and 312 of the corresponding one of the data memories 301-303.
ADDR bus 701 supplies the address of a data buffer word that is to be 10 read while the STS ADDRESS, VT ADDRESS, and DS-0 ADDRESS lines supply the addresses of words of data buffers which are to be written with data incorning on DATA IN. And the STS FRM, VT F~M, and DS0 FRM signal lines select which address is supplied to which buffer 311 and 312 of a memory 301-303. The addresses are alternately supplied to the two buffers 311-312 of each memory 15 301-303 so that -- as was mentioned above -- one of the buffers 311-312 is read while the other is written during one corresponding frame period, and vice versaduring the next corresponding frame period.
The data outputs of both buffers 311 and 312 of each memory 301-303 are connected to the data inputs of a corresponding one of selectors 708,715, 20 and 725, respectively, whose outputs are in turn connected to the inputs of aselector 726. Selectors 708,715, and 725 are respectively controlled by the STS_~RM, VT FRM, and DS0_FRM signal lines, so as to always select for output the one of the buffers 311 and 312 of the corresponding memory to which addresses are being supplied from control memory 305 via ADDR bus 701. Selector 304 in 25 turn selects among the STS, VT, and DS-0 data memories under the control of VT_EN and STS EN signals which are generated by comparators 702 and 703, respectively. Comparators 702 and 703 respectively determine whether the most-significant bits of the address generated by control memory 305 on ADDR bus 701 . define a VT or an STS connection. Detection of nçither a VT or an STS connection 30 signifies a DS~ connection. Selector 304 selects for output from TSI 131 or 141 on link 171 or 151 the output of the one of the memories 301-303 that corresponds to the detected connection type.
FIGS. 4 and 8-9 collectively make up a second illustrative implementation of TSI 131 or 141 of FIG.3. As was mentioned previously, since 35 system 100 is adapted to establish connections, or channels, of three types of rates, the TSI control circuitry must be able to distinguish between time slots of the three types of frames 30,40, and 50 of FIG. 2. One way of accomplishing this distinction 210~7~4 is illustratcd in FIGS. S-6. Another way, which uscs thc same sequential numbcrs to designate the sarnc sequential timc slots of all thrcc typcs of frames but associatcs with each number an indication (c.g., a separa~e number) that indicates which typc of frame is being referred to, is illustrated in FIGS. 8-9. A comparison of FIG. S with S FIG. 8 and of FIG. 6 with FIG.9 readily shows that they are identical in many respects. The same numerical designations arc used for elements which they have in common. Only the differences are discussed below.
In nG. 8, a bandwidth-ty~c register 604 is substituted for comparators 609 and 610 of FIG. 5. Like registers 601-603, register 604 is loaded 10 by control processor 110 with inforrnation defining a particular connection selected as a result of a path hunt. The contents of register 604 are two bits whose valuc identifies the bandwidth of the desired connection. The rest of FIG. 8 duplicates FIG. 5.
In FIG. 9, a bandwidth-type memory 755 is substituted for comparators 15 702 and 703 of FIG. 6, and produces the same two-bit output, with one bit representing the VT EN signal and the other bit representing the STS EN signal.
Bandwidth-type memory 755 is of the same depth as control memory 305, and is addressed and cycled-through in tandem with control memory 305 by DS-0 ADDR
signals. Also lilce control memory 305, bandwidth-type mèmory 755 is enabled to 20 be written with a new word of data in response to the CM WE signaL Associatedwith bandwidth-typc memory 755 is a gate 751 which performs a function ecluivalent to that performed for control memory 305 by gate 701, and which allows bandwidth-type memory 755 to be updated on-the-fly and at the same time as control memory 305. Normally, CM WE signal line is not asserted and words of both 25 memories 305 and 755 are cyclically read out. A word of control data is written into each memory 30S and 755 in response to the CM WE signal line being asserted. In response to this assertion, the two-bit VT or STS signal that is generated by bandwidth-type register 604 of FIG. 8 is output by gate 751 onto the VT EN, ST~ EN signal line, from where it is both written into memory 755 and made 30 available to the other circuitry of FIG. 9 in place of the word of memory 755 that would otherwise normally have been read out of memory 755.
U~ile FIG. 3 shows an embodiment of a TSI having physically separate data memories for each connection type, FIG. 10 shows an altemative embodirnent of TSI 131 having logically separate data memories for each connection type 35 implemented in a single physical memory. The memory is sized to accommodate the largest possible frarne, i.e., a DS0 ~ame 30, and hence is the same physicalmemory as memory 301 of FIG.3. It is therefore designate~ by the samc 21047~

numcral 301. The first 12 bytcs of memory 301 scrvc as the c~uivalent of STS
memory 303 of FIG. 3, and are designated as STS ponion 303' in FIG. 10. The first 1080 byles of memory 301 servc as thc functional equivalent of VT memory 302 of FIG. 3, and are dcsignated as VT portion 302' in FIG. 10. And the full memory 301 S serves as the equivalent of DS0 memory 301 of FIG. 3, and is designated as DS0portion 301' in FIG. 10. Just like the memories 301-303 of FlG. 3, memory 301 ofFlG. 10 is double-buffered and comprises two buffers 311 and 312.
It will be noted that VT portion 302' consists of 1080 bytes of memory, as compared with 1008 bytes for VT 302 of FIG. 2. These extra 72 bytes are used to 10 store the STUFF and OVERHEAD bytes that accompany each VT frame 40.
These 72 bytes are discarded and ignored by memory 302 of FIG. 3, and could be handled in the same way in FIG. 10. HoweYer, for VT type calls, the appearance rate varies between 336, 252, 168, or 84 bytes, depending on the VT type. In order toallow TSI 131 or 141 to ignore these variances and make the hardware simpler, a 15 common appearance rate of 1080 bytes is used in FIG. 10. This rate guarantees that at least one byte from every VT channel is stored in a buffer 311 or 312 before switching over to the other buffer 312 or 311 takes place.
In operation, memory 301 of FIG. 10 is used in the identical manner as memories 301-303 of FIG. 3. The use of buffers 311 and 312 alternates for each 20 connection type at the rate cornmensurate with that connection's frame size, i.e., every 12 bytes for an STS connection, every 1080 bytes for a VT connecdon, and every 9720 bytes for a DS-0 connection. Due to the different frame rates of the different connections, it is possible that bytes may arrive, as part of one connection type, for storage in one of the buffers 311 or 312 while bytes are being read out of 25 that buffer as part of another connection type. Hence, buffers 311 and 312 either are dual-ported devices, so as to accommodate simultaneous reads and writes, or are high-speed devices that support two successive cycles -- both a read and a write --during successive halves of a single time - slot interval.
FIGS. 11-13 collectively make up a f~rst illustrative irnplementation of 30 TSI 131 of FIG. 10. A comparison of FIG. 4 with FIG. 11 shows that they are identical in many respects. The same numerical designations are used for elements which they have in common. Only the differences are discussed below.
In FIG. 11, a modulo-1080 counter 1506 replaces modulo-1008 counter 506 of FIG. 4, and the VT DISABLE circuit 507-510 is elimin~teA
35 Modulo-1080 counter 1506 counts the bytes that make up each horizontal plane of the STS-12 frame of FIG. 2. This planc may be referred to as an augmented VT
frame 40', as it is composed of VT frame 40 plus the 72 bytes of the STUFF and 210~7~4 OVERHEAD columns that lic in the same plane as the VT framc 40. And sincc thc STUFF bytes are no longer being ignored but are being counlcd, the circuit S0?-510 is no longcr needed.
A comparison of FIG. 8 with FIG. 12 likewise shows that these figures S are identical in many respecls. The same numerical designations are used for elements which they havc in common, and only their differences are discussed hereinbelow.
Since modulo-1080 counter 1506 of FIG. 11 includes the overhead and stuff columns (see FIG. 2) in its count, the spacing of addresses generated by 10 counter 1506 of columns of a particular VT-rate channel is not regular in theaugmented VT frame 40' -- contrary to the VT frame 40 - related output of modulo-1008 counter 506 of FIG. 4. This irregularity of spacing must be compensated for in FIG. 12 whenever the contents of offset register 603 are used to address a VT
channel's columns. Accordingly, adders 607 and 613 of FIG. 8 are replaced in 15 FIG. 12 by adders 1607 and 1613, respectively, and associated control comparators 1609 and 1610. Each control comparator 1609 and 1610 monitors the selector input to its corresponding adder, referred to as "old" address, and the adder output, referred to as "new" address. During any operational cycle when control comparator 1609 or 1610 deterrnines that (a) "old" address is less than decimal 384 20 and "new" address is greater than decimal 383, or (b) "old" address is less than 732 and "new" address is greater than decimal 731, the control comparator causes itscorresponding adder to increment new address by decimal 12.
Tuming briefly to FIG. 13, the implementation shown in FIG. 13 also uses a bandwidth-type memory like the implementation shown in FIG. 9. In FIG. 9, 25 each incoming byte is written into each data memory 301-303, and so bandwidth-type memory 75S need only indicate the bandwidth-type of each byte selected for output. But in FIG. 13, there is onIy one data mery 301 to wTite incoming data into, and therefore bandwidth-type memory 1755 of FIG. 13 must additionally indicate the bandwidth-type of each incoming byte. Bandwidth-type memory 1755 30 must therefore be provided with address control analogous to that which is provided to control memory 305. But because bandwidth-type memory 1755 relates to --indicates -- the bandwidt~ of incoming bytes, unlike control memory 305 it must have its address control derived from the contents of input time-slot register 601.
Returning to consideration of FIG. 12, there is accordingly provided circuitTy 1620, 35 1611, 1612, 1623, and 1614-1618 which duplicates the circuitry 611, 612, 613, 610, and 614-618 of FIG. 9, but with the following exceptions: a first input of selector 1611 is connected to the output of input dme slot register 601, selector 1611 210~703 is controlled by a signal VT-STRT which is thc output of flip-flop 1618, and thcoutput of selec~or 1617 is designated as BW_WE (bandwidth-type mcmory writc enable).
Tuming again to FIG. 13, bandwidth-type memory 175S must indicate S the bandwidth-type of each incoming byte. Accordingly, bandwidth-type memory 1755 is twicc as wide as memory 77S of FIG. 9, and has two two-bit outputs. The VT EN, STS_EN output corresponds to the output of memory 755 and indicates the bandwidth-type of the byte selected to be read out of data memory 301.
A VT_EN', STS EN' output indicates the bandwidth-type of ~he byte being wntten 10 into data memory 301.
As in the case of FIG. 9, control memory 305 and bandwidth-type memory 1755 are addressed and read out in a cyclical manner by DS-0 ADDRESS.
The VT EN, STS EN output of memory 1755 controls a selector 1202, while the VT EN, STS EN' output controls a selector 1201. Selector 1202 has the 15 STS FRM, VT FRM, and DSO_FRM signals connected to its inputs, while selector 1201 has the inverted values of these same signals connected to its inputs. It had been explained previously that each of these signals changes its value during successive occurrence of the corresponding frame type. Consequently, for any oneof the three frame types 30, 40, 50, selectors 1201 and 1202 each output a different 20 value during any one frame, and each changes the value of its output during successive frames.
The VT EN', STS EN' output of memory 1755 further controls the output of a selector 1200, which has STS ADDRESS, VT ADDRESS, and.
DS0 ADDRESS signal lines connected to its inputs. Consequently, selector 1200 25 outputs the address that corresponds to the frame type of the bit that is presently to be written into memory 301. The output of selector 1200 and the output of control memory 305 are connected to inputs of a selector 1203. The output of selector 1203 is connected to address inputs of buffers 311 and 312. Selector 1203 operates under control of a clock-generated read-wnte R/W signal. R/W signal changes value twice 30 during each time-slot interval. During the first half of the tirne-slot interval, the RIW
signal indicates a data rnemory-write cycle and causes selector 1203 to supply to memory 301 the address selected by selector 1200.
'lbe output of selector 1201 is connected to an input of an AND
gate 1204, and to an inverted input of an AND gate 1205. Second inverted inputs of 35 gates 1204 and 1205 are connected to RJW signal line. Output of gate 1204 is connected to a write-enable (WE) input of buffer 311, while output of gate 1205 is connected to a WE input of buffer 312. Gates 1204 and 1205 enable the one of the 21 ~7~4 two buffers 311 and 312 that is prcsently sclcctcd by thc output of selcctor 1201 to bc written with a byte of data incoming to buffers 311 snd 312 on DATA ~ linc during thc wri~e cyclc of cach time-slot interval.
During the second half of each time-slot interval, Ihe RIW signal 5 indicates a data-memory-read cycle and causes selector 1203 to supply to memory 301 the address that is output by control memory 305. Both buffers' WE
inputs are disabled during this cycle, and so both buffers are read. Outputs of buffers 311 and 312 are connected to inputs of a selector 1206, which operates under control of the output of selector 1202. Selector 1206 selects the output of the one of 10 the buffers 311 and 312 that is picked by the output of selector 1202 as the output of TSI 131 and transmits it on DATA OUT line.
New control inforrnation from CM DATA line (from FIG. 12) is written into control memory 305 under control of gate 701 and the CM_WE signal, as was the case in FIG. 9. Bandwidth-type memory 1755 is written in a 15 correspondingmanner. TheVT_EN,STS ENandVT EN,STS EN
inputs/outputs of memory 175S each have a respective gate 1751 and 1752 connected thereto. Gate 1751 operates under control of the CM_WE signal, while gate 1752 operates under control of the BW WE signal (from FIG. 12). These signals also control ~he writing of the respective parts of the bandwidth-type 20 mernory 1755. The inputs of gates 1751 and 1752 are connected to the VT, STS
output of bandwidth-type register 604 (from FIG. 12). When the CM WE line is asserted, a normal read cycle of the data-mernory-output-indicating portion (i.e., VT EN, STS EN) of bandwidth-type me~l~ 1755 is converted into a write cycle.
At the same time, gate 1751 supplies the VT, STS output of bandwidth-type 25 register 6(~4 to VT EN, STS EN signal line, from where the VT, STS output is written into bandwidth-type memory 1755. Similarly, when the BW WE line is asserted, a normal read cycle of the data-me~,oly-input-indicating portion (i.c., VT EN, STS_EN') of bandwidth-type memory 1755 is converted into a write cycle and, at the same time, gate 1752 supplies the VT, STS output of register 604 to 30 VT EN', STS_EN' signal line from where this output is wrinen into memory 1755.
FIG. 14 shows an alternative embodiment of the single-shared-memory TSI implementation. Unlike the implementa~on of FIG. 10, this implementation writes each incoming fuU STS-12 frame into data memory sequentially, and therebydispenses with the requirement of knowing to which one of the frame types 30, 40, 35 and 50 an incoming byte belongs. Like the irnplementation of FIG. 10, this implementation makes use of a single double-bufferul data rnemory, designated as 1301. UnlikeinFIG. 10,however,thetwobuffers311 and312OfFIG. 14are 2104~4 implcmented in scquence in a singlc physical memory devicc. To allow memory 1301 to bc simultaneously read and written, memory 1301 is implementcd as a dual-ported devicc. Each buffer 311 and 312 is sized to accornmoda~e a fullSTS-12 frame, which is also the DS-0 frame 30. Hence, each buffer 311 and 312 ofS FIG. 14 is of the same size as the corresponding buffers of FIG.10, and memory 1301 is 2-9720 = 19440 words deep.
Like the implementation of FIG. 10, the implementation of FIG. 14 has logically separate data memories for each connection type which share the sarnc physical memory locations. However, because an STS-12 frame is written into data10 memory 1301 sequentially, as if it were composed only of DS-0 type channels, each sequential 12 bytes of memory 1301 serve as the equivalent of STS memory 303 of FIG. 3 and STS portion 303 of FIG. 10. Hence, there are a plurality of logical STS
memories, with each sequential 12 bytes being designated as a separate STS
portion 303". Similarly, each 1080 bytes of memory 1301 serve as the functional 15 equivalent of VT memory 302 of FIG. 3 and VT portion 302' of FIG. 10, and so each sequential 1080 bytes of memory 1301 are designated as a separate VT
portion 303". And each full buffer 311 or 312 serves as the equivalent of DS-0 memory 301 of FIG. 10, and is designated as DS0 portion 301".
The addresses that are stored in control memory 305 for su~rate calls 20 are controlled so as to read from the preceding sub-frame (i.e., ~he preceding STS
portion 303" for an STS sub-rate, or the preceding VT portion 302" for a VT su~
rate) to the su~frarne that is being written, irrespective of whether the read and written sub^frarnes are in the sarne or in different buffers 311 or 312. The addresses are calculated algorithmically, as required when the frame that is being read is in one 25 buffer 311 while the frame that is being written has overlapped into the other buffer 312, and vice versa. The calculation views memory 1301 as a singlc continuous buffer of 19,440 bytes.
FIGS. 15-17 collectively make up an implementation of TSI 131 or 141 of FIG. 14. A comparison of FIG. 15 with FIG. 4 readily shows that they are 30 identical in many respects. The same numerical designations are used for elements which they have in common. Only the differences are discussed below.
Since reading and writing of su~frames in FIG. 14 occurs in adjacent portions 301"-303" irrespective of whether or not they lie in the same or in different buffers 311 and 312, the toggle flip-flops 504,505, and 512 of nG.4 are no longer 35 needed to indicate a changeover between buffers 311 and 312. Hence, these flip-flops are eUminated from FIG. 15. Also, since data mem~ry 1301 of FIG. 14 is twice as deep as data memory 301 of FIG.3, modulo-9720 counter 511 of FIG. 4 is - 2;047~

replaced in FIG. IS with a modulo-19440 counter 1511. Countcr ISI I is rcset only once every two STS-12 frame periods, i.e., at half thc STS-12 frame rate, and hence counter 1511 is provided with a FRM/2 lead 1522 which is connected to its reset (RST) input and which resets counter 1511 once every 19440 time slots.
Additionally, FIG. 15 includes circuitry IS50-1555 for generating an EN MATCH signal that directs the circuitry of FIG. 16 to commencc searching for the address of a control memory 305 location that is to be wrinen, only at the beginning of an even STS- 12 frame (the beginning of buffer 311 of FIG. 14), and for generating a STOP signal that directs the circuitry of FIG. 16 to end thc search at the end of an odd STS-12 frarne (the end of buffer 312 of FIG. 14). Circuitry 1550-1555 includes a D-type flip-flop 1550 whose D input is latched to a logical "I" level and whose CLK input is connected to a START signal line. Control processor 110 asserts START signal line after loading the registers of FIG. 16, to indicate that it has made available the information necessary for the search to cornmence. The output of flip-flop 1550 is connected to one input of an AND gate 1551, whose other input is connected to the TC output of modulo-19440 counter 1511. The output of gate 15S I is connected to the S input of an S-R flip-flop 1553 and to the R input of an S-R flip-flop 1554, The output of flip-flop 1553 is connected to the EN MATCHsignal line and to the D input of a D-type flip-flop 1555 whose output is connected to one input of an AN~ gate 1552. The CLK input of flip-flop 1555 is connected to CLK~ line 520, to delay the propagation of the EN MATCH signal to AND
gate 1552 by one time-slot period. The other input of gate 1552 is connected to the TC output of counter 1511, and the output of gate 1552 is connected to the S input of flip-flop 1554. The output of flip-flop 1554 forms the STOP signal, and is further connected to the R inputs of flip-flops 1553 and 1550. Assertion of START signalby control processor 110 enables the next assertion of the TC output by counter 1511 to cause flip-flop 1553 to generate the EN MATCH signal. The next assertion of the TC output by counter 1511 causes flip-flop 1554 to generate the STOP signal, which in turn causes flip-flop 1553 to cancel the EN MATCH signal.
Turning to FIG. 16, a comparison thereof with FIG. 8 shows their CM_WE and VT START signal-generation portions to be identical. The sarne numerical designations are used in both figures for elements which they have in cornmon, and only the differences are discussed below.
In the data memory implement~tion shown in FIG. 14, the input hme slot that corresponds to (that is to be output during) a particular output time slot is not always stored in the same data memory location. Rather, that input time slotmoves from portion 301"-303" to successive portion 301"-303" in memory 1301.

-24- 2 1 04 7 ~
Il is therefore no longer suffieient for an input dme slot register, such as register 601 of FIG. 8, to speeify the address of only a single data memory loeation. Rather, the register must now speeify the addresses of a whole sequenee of data memory locations. Consequently, the simple input time-slot register 601 of FIG. 8 is replaeed S in FIG. 16 with an input time-slot register/modulo-19440 eounter 1601. For eaeh change in switched eonneetions being effeeted, eontrol proeessor 110 loads register/eounter 1601 with an initial value. From that initial value, register/eounter 1601 inerements its eount during eaeh time-slot period, therebyprodueing the eorreet input time slot address during every oecurrence of the 10 eorresponding output tirne slot (e.g., during every assertion of CM WE signal line).
The initial value loaded by eontrol processor 110 into register/counter 1601 is equal to 19440 rninus the frarne size of the ehannel being switched (9720 for a DS-0 channel; 1080 for a VT channel; 12 for an STS-l channel) plus the sequence number, within the sequence of 19440 time slots of two STS-12 15 frames, of the first input time slot of the subject channel that is being switched. In other words, it specifies the data memory 1301 address in the very last portion 301"-303" that corresponds to the frame size of the channel that is to be switched, at which address is stored the input time slot that should be switched out during the first occurrence of the output time slot that corresponds to the switched channel.
20 Conceptually, one can view this as the drawing of FIG. 14 being overlayed onto a eylinder such that the bottom wraps around to join with the top to form a seamless eircular buffer.
The reason for this initial value is the following. An output time slot and the writing of memory 1301 occur during the same time slot. Hence, the output 2S time slot is properly thought of as occurring in the partition 301"-303" that is then being written. By action of the EN MATCH signal generated in FIG. 15, comparators 614-616 start looking for, and find, an output time slot match in (i.e., dunng the writing of) the first partition 301' -303" of data memory 1301. It will be recalled that reading from data memory 1301 is done in a partition 301"-303" that 30 immediately precedes the partition 301"-303" tha~ is being written. For the first partition 301"-303" of memory 1301, the immediately-preceding partition is the last partition 301"-303" (on account of memory 1301 being a circular buffer~. Hence, upon the detection by comparators 614-616 of the Srst matching output tirne slot, in the first partition 301"-303" of memory 1301, register/counter 1601 must indicate 35 the reading of an input time slot from the immediately-preceding partition, which is the last partition 301"-303" of memory 1301. And that is precisely what the initial value of register/counter 1601 does.

- 2 1 ~ 4 ~ e stuff and path overhcad colurnns neatly divide the payload envelopc of an STS-N frame into three partitions of equal size, as shown in FIG. 2. In turn, the 12 columns of a VT group neatly divide betwe~n the partidons, with four columns Iying in each partition. Hence, an e~ual number of columns of any one of5 the rates VTI.5, VT3, and VT6 lie in each of the partitions. Consequently, thedistance (in time slots) between the input time slots and output dme slots is constant, regardJess of the partidon.
Unfortunately, the sarne is not true for the VT2 rate. A VT2 rate occupies 4 columns of the 12 columns of a VT group, and these 4 colurnns cannot be 10 evenly divided between the three payload partitions created by the POH and stuff columns. Hence, the distance from the input time slots to the output time slots wiU
change if they happen to fall into different partitions, and this lack of regularity must be compensated for. This is the purpose of the circuits 1605-1609. The compensation is necessary when a column of input tirne slots of a VT2 rate lies to 15 one side of a stuff or POH column whi]e the column of corresponding output time slots lies to the other side of that stuff or POH column. In that case, the address generated by register/counter 1601 is high or low by 12 (the number of tirne slots in one row of the stuff or POH column). Control processor 110 knows when this will happen, based on the following consideration.
There are N 21 VT2 channels in an STS-N frame. For all N 21 VT2 channels, their first column lies in the first partition and their last--fourth--column lies in the last--third--partition. For the first se~ of N 7 of the N-21 VT2 channels, their second column lies in the first partidon and their third column lies in the second partition. For the next set of N-7 VT2 charmels, both their second and third columns 25 Lie in the second partition~ And for the last set of N~7 VT2 ch~n~ls, their second eolurnn lies i,n the second partition while their third column lies in the third partition.
Consequently, no compensation is ever required for the first and fourth columns of a V~I`2 channel irrespective of which other VT2 channel it is being switched to, but compensation may be required for the second and thir~ columns of a VT2 channd 30 and depends upon the relative positioning of the input VT2 and output VT2 within the three N~7 sets of VT2 channels in an STS-N frame. The requisite compensation, for each of the four columns of a VT2, is shown in the table of FIG~ 18.
Consequently, when loading registers 602-6~)4 and t601 of F~G. 16 with info~mation defining a switched connection for a VT2 channel, control processor 110 35 loads the corresponding one of the entries of the table of FIG~ 18 into a four-word shift register 1605~ For switched connections of channels other than VT2 channels, processor 110 loads register 1605 with all zeros. Further~ore, in the in~emational 210~L7~

SDH standard, s~uff columns arc positioncd directly ncxt lO thc overhcad colutnns.
Hence, abovc-dcscribed problem does not arise, i.e., thcre is no ne~d for any compensation. Consequently, when the system of FIG. 1 is switching SDH frarnes, processor 110 loads register 160S with all zeros for all switched connections S including VT2 connections.
The generation of input data to control rnemory 1301 of FIG. 17 by the circuitry of FlG. 16 occurs as follows. Following loading by control processor 110 of registers 602-604, 1601, and 1605 with the results of a path hunt and issuance of the START signal, circuits 611-617 generate the CM WE signal upon occurrence of 10 the desired output time slot. The CM_WE signal sets R-S slip-flop 1609, whoseoutput enables AND gate 1606 to start supplying CM_WE signals to the clock inputof register 1605 and also enables AND gate 1607 to start supplying time-slot interval signals from CLK/9 signal line 520 to the clock input of register/counter 1601. The output of flip-flop 1609 also enables register/counter 1601 and register 1605 to start 15 responding to their clock inputs.
Acting as a clock input to register 1605, the CM WE signals causes register 1605 to output the first of its four words. The output of register 1605 is connected to its input to forrn a recirculating register, and also to one end of a summing circuit 1608 whose other input is connected to the output of 20 register/counter 1608. Circuit 1608 compensates the input time-slot address generated by register/counter 1601 by the value supplied by register 1605 and outputs the compensated address as CM DATA to control memory 1305 of FIG. 17.
The output of register 1605 remains constant until the next occurrence of thc CM WE signal, which causes register 1605 to output the next one of its four words.
25 Generation of the STOP signal in FIG. 15 at the end of a read cycle through data memory 1301 of FIG. 14 resets flip-flop 1609, thereby disabling both AND
gates 1606 and 1607 and the outputs of register/counter 1601 and register 1605.
Since all input time slots are stored sequentially in data memory 1301 of FIG. 14, no bandwidth-type indication is required to supplement the output of 30 control ll~emo.~ 1305 in the irnplementation of FIGS. 15-17. Hence, turning to FIG. 17, a bandwidth-type memory is not used. Control memory 1305 has the sarne depth as data memory 1301 - 19440 words. Memory 130S is controlled in the same manner as explained for the illustrations discussed previously, e.g., F~G. 13. The output of control memory 1305 is connected to a first input of a selector 1703 whose 35 second input is connected to DS-0 ADDR. Selector 1703 operates under control of Rt~ signal line to supply both split-cycle read and write addresses to the address (A) input of data memory 1301, similarly to selector 1203 of FIG. 13.

The contents of memory 1305 are programmcd such that dunng cvcry data memory 1301 readlwrite cyclc, thc most-significant-bit output of memory 1305 has the opposite value of thc most-significanl bit of DS-0 ADDR. Thus, buffer 311 of memory 1301 is read while buffer 312 is written, and vice versa. The RIW signal 5 line is also connected to the write enable (WE) control input of memory 1301. Thc data (D) input of memory 1301 is connected to the DATA IN line and the output ofmemory 1301 is connected directly to the DATA OUT line which represents link 171 or 151~
Yet another implementation of TSI 131 or 141 of FIG. 4 is shown in 10 FIGS. 19-21. The departure of this implementation from that of FIGS.15-17 is that it uses a control memory 305 that is only half as deep. Because of this, only half of the count that was previously required is needed to cycle through the addresses of this reduced-size control memory 305. Modulo-19440 counter of FIG. 15 is therefore replaced in FIG. 19 with a modulo-9720 counter 511 which is reset by the 15 FRM signal line 521. But because the reduced-size control memory 305 has a capacity to address only one of the buffers 311 and 312 of data memory 1301, it must be used twice and its output must be modified during the second use in order for it to address all of data memory 1301. For this purpose, there is included in FIG. 19 a toggle flip-flop 512 which duplicates the flip-flop 512 of FIG. 4. In other 20 respects FIGS. 15 and 19 are identical.
Again, because control memory 305 can hold only half of the addresses of control memory 1305 of FIG. 17, input time-slot register/mo~ulo-19440 counter 1601 of l;IG. 16 is replaced in FIG. 20 with an input time-slot register/modulo-9720 counter 2601 and an S-R flip-flop 2602. Flip-flop 2602 is set by control processor 110 at the sarne time as it loads the registers of FIG. 20. It is reset by the terminal count of register/counter 2601. The output of flip-flop 2602 forms a FRM OFFSET signal which indicates whether the present count of register/counter 2601 is generating an address of buffer 311 or of buffer 312 of data memory 1301. In other respects, FIGS. 16 and 20 are identical.
FIG. 21 parallels FIG. 17 in many respects, and the same nurnerals arc used to designate elements common to both figures. Only the differences are discussed.
The F~M_OFFSET signal is written into control memory 305 along with the CM DATA signal. The writing thereof into memory 305 is controlled by a gate 2150 in the identical manner as gate 701 controls the writing of tbc C M_DATA
signal into memory 305.

21Q~7~

The FRM OFFSET signal output of gate 2150 and of control memory 305 forms an input to an cxclusivc-OR gate 2151, whose output is eonnected to the first input of selector 1703 in parallel with the CM WE signal output of gate 701 and of control memory 305. The DS0 FRM signal is connected 5 to the second input of selector 1703 in parallel with the DS0 ADDRESS signal, and also forrns the seeond input to exclusive-OR gate 2151. Therefore, the FRM-OFFSET signal acts as an indieator of which one of buffers 311 and 312 is being read, and the DS0 FRM signal acts as an indicator of which one of buffers 311 and 312 is being written.
It will be remembered, from the diseussion of FIG. 16, that the initial value of register/counter 1601 points into the last partition 301"-303" of memory 1301. To have the same be true of register/counter 2601, flip-flop 2602 is initialized by control processor 110 with a value of " 1". Thereafter, when register/counter 2601 begins to count and reaches its terminal count for the first time, lS its eount value in conjunction with the FRM_OFFSET value output by flip-flop 2602 points to the last location of memory 1301. Flip-flop 2602 is therefore reset at this time, so that the next count of register/counter 2601 in eonjunction with the FRM OFFSET value will point to the first loeation of memory 1301. Significantly,the value of FRM OFFSET will not change again until flip-flop 2602 is set by 20 eontrol proeessor 110 at the beginning of a new call setup. That means that only those locations in eontrol memory 305 that are read during the oecurrence -- the~vriting -- of the first partition 301"-303" of memory 1301 have stored an FRM_OFFSET value of N 1~. But the contents of eontrol memory 305 are used twiee: for the first time during the oceurrence -- the writing - of buffer 311 and a 25 seeond time during the oceurrenee -- the writing -- of buffer 312. Consequently, those same loeations in control memory 305 that have stored an FI~M OFFSET
value of ~ 1" will be read during the occurrence -- the writing - of the first partition 301 '-303" of the second buffer 312 of memory 1301. But during this oecurrence of the first partition 301"-303" of the seeond buffer 312, the last par~ition 301"-303"
of the first buffer 311 should be read. ~enee, the stored FRM OFFSET value of 1 is incorrect and must be ehanged to a 0. This is the function of exclusive-OR
gate 2151.
During the oecurrence of the second and all subsequent portions 301 '-303 of the second buffer 312, reading should be of the first and subsequent portions 301"-303" of the seeond buffer and not of the first buffer 311. But, as was explained above, the FRM OFFSET value stored by eontrol memory 305 loeations used at this tirne is 0. Hence, the stored FRM OFFSET value of 0 is ineorreet and 21~tl7~

must be changed to a 1. This is another funcdon of exclusive-OR gate 21S1.
Rctuming lo FIG. I, exercise of control over TMS 120 is implemented in much the same way as over a TSI 131 or 141. FIG. 22 shows an illustrative implcmentation of TMS 120. It comprises a plurality of output controls 1700, one5 for each TMS output link 181. Each output control 1700 comprises a selector 1702 and associated control memory 1701. Connected to the inputs of each selector 1702 are all of the TMS input links 171. Each selector 1702 operates under control of its own control memory 1701. During each time-slot interval, contTol memory 1701 of each selector 1702 selects one of the input links 171 of the corr~sponding 10 selector 1702 forconnection to its output link 181.
Just as there are numerous possible implementations of a TSI 131 or 141, there are correspondingly numerous implemen~ations of output controls 1700. The implementation of an output control 1700 that corresponds to the TSI 131 or 141 implementation of FIGS. 4-6 is shown in FIG. 23. The 15 implementation shares the circuitry of FIG. 4 with TSI 141 of its corresponding TMS output link 181. For the prograrnming of control memory 1701, this implementation uses circuitry that duplicates that of FlG. S in rn~ny respects. TMS
output time slot register 1802 duplicates the function of output time-slot register 602.
Input port register 1801 serves a similar function to input time-slot register 601, but 20 specifies which of the TMS input ports, or links 171, is to be connected by selector 1702 to the TMS output port, or link 181, du~ing the time slot specified by register 1802. Offset register 1803 duplicates offset register 603. Sirnilarly, elements 1809-1818 duplicate elements 609-618.
The output of input port registerl801 is coMected to the input of a 2S gate 1901, which serves the same function for control memory 1701 as gate 701 serves for control memory 30S of FIG. 6. Gate 1901 is controlled by the TMS-CM-WE output of selector 1817, as is the wnte enable input of control memory 1701.
Like memory 305, control memory 1701 is cycled through by DS-0 ADDR. Control memory 1701 is 9720 words deep, one for each byte/time slot of an STS-12 frame.
The irnplementation of an output control 1700 that corresponds to thc TSI 131 or 141 implementation of FIGS. 4 and 8-9 is shown in FIG. 24. Il~e implementation shares the circuitry of FIG. 4 with TSI 141 of its corresponding TMS output link 181. For the programming of control memory 1701, this implementation uses circuitry that duplicates that of FIG. 8 in rnany respects. Just as FIG. 8 is substantially identical to FIG. 5 but replaces comparators 609 and 610 with bandwidth-type register 604, the implementation of FIG. 20 is substantially identical to that of FIG. 23 but replaces comparators 1809 and 1810 with bandwidth-typc 210 175~

register 1804, which duplicates the function of rcgistcr 604 of FIG. 8. Thc sarne numerals arc uscd in FIGS. 23 and 24 to designatc elemcnts that are comrnon to both.
The implementation of an output control 1700 that corresponds to the TSI 131 or 141 implemen~ation of FIGS. 11-13 is shown in FIG. 2S. This implementation shares the circuitry of FIG. 11 with TS~ 141 of its correspondingTMS output link 181. For the prog~amming of control memory 1701, this implementation uses circuitry that duplicates portions of FIG. 12. Thc implementation of FIG. 25 is substantially identical to that of FIG. 24 but replaces adder 1813 with an adder 2813 and control comparator 2810, which respectively duplicate adder 1613 and control comparator 1610 of FIG. 12. Control memory 1701 of FIG. 25 is again 9720 words deep, one for each byte/time slot of an STS-12 frame.
The implementation of an output control 1700 that corresponds to the TSI 131 or 141 implementation of FIGS. 15-17 is shown in FIG. 26. This implementation shares the circuitry of FIG. 15 with TSI 141 of its correspondingTMS output link 181. For the pro~arnming of control memory 1701, this implementation uses circuitry that duplicates portions of FIG. 16. The implementation of FIG. 26 is substantially identical to that of FIG. 24. However, in this embodiment, control memory 1701 is 19440 words deep, spanning the two STS- 12 frames of storage of data memory 1301 of FIG. 14, and hence DS-0 ADDR
is 15 bits wide. The information stored in control memory 1701 is iden~ical for both STS-12 frames, i.ç., the contents of the two halves of memory 1701 are duplicates of each other.
An alternative equivalent implementation is to make memory 1701 of FIG. 26 only half as deep, i.c., 9720 words deep, and addressed by only the 14 least-significant bits of DS-0 ADDR, i.e., addressed by DS-0 ADDR modulo 9720. This alternative implementation corresponds to thc TSI 131 or 141 implementation of FIGS. 19-21.
As was mentioned previously, the switching fabric of FIG. 1 -- TSIs and TMS -- would normally be duplicated and the two duplicate fabrics would be operated in parallel in order to obtain strictly-non-blocking performance. The implementations of output controls 1700 shown in FIGS. 22-26 assume that each output control 1700 of both duplicate TMSs 120 has its own, dupUcate, circuitry for loading control memory 1701. An a1ternative irnplementation reduces the amount of required circuitry by sharing non~upUcated memory-loading circuitry among thc pair of control memories 1701 of the corresponding output controls 1700 of thc 2104~

duplicate TMSs 120. In such a shared implcmcntation, each FIG. 22-26 furthcr includes a register (not shown) that is written by control processor 110 at the timc of writing of the other registers to indicatc which onc of the pair of control memories 1701 is to be loaded.
As described above, the hardware of system 100 is configured to switch connections (also referred to herein as channels) at threc different types of rates:
STS- I, VT, and DS-0. However, system 100 is not limited to switching connections having these specific rates. Rather, a connection may have any rate up to and including the STS-12 rate, and system 100 allocates as much available bandwidth to 10 each connection as that connection requires. Bandwidth is allocated in different-size blocks whose sizes correspond to the specific rates which the hardware is configured to switch. A connection's full allocated bandwidth will therefore comprise one or more individually-allocated blocks of bandwidth preferably corresponding to one or more of the STS-I, VT, and DS-0 rates. BandwidLh allocation is accomplished 1 S hierarchically, such that as much of the required bandwidth is allocated in the largest available bandwidth blocks without wasting bandwidth, the remaining required bandwidth is allocated in the next-smaller available bandwidth blocks, and so on, until the connection's fu11 bandwidth requirement has been met.
A characteristic of this approach is that each rate will suffer a different 20 time delay through the switching system equal to the switch delay of that rate's corresponding frame Therefol~, for each call, the traffic switched at a higher rate will have to be delayed at the switch output to re-synchronize it with the call's traffic switched at the lowest rate used for that call. However, this is not expected to result in significant perforrnance degradation, because calls sp~nning a wide range of rates 2S are expected to be rarc.
In view of this need to delay a call's traffic being switched at higher rates, it is ne~ss~y to retain this traffic at the switch output for some time without immediately overwriting it with subsequent switched frames of traffic corresponding to those rates. One way of achieving this is to retain the call's traffic in the output 30 switching element's data ~ Oly. The implementation of data memory 1301 shown in FIG. 14 is particularly suited for this purpose, because it retains each rate's corresponding frames until the slowest rate's frarne, i.e., the entire DS~ frarne, has been received at the output.
It should be noted that a similar situation exists with calls that are 35 unrelated and of different rates arriving at the switch output with different delay characteristics. Because they are unrelated, these calls need not be delayed further but instead, the SONET/SDH pointer mechanism can be used to reconcile thc - 2104~i4 - diffcrcnt dclays.
One of thc rcquirernents of thc SONET/SDH standards is that section and line overhcad (i.c., ~he first 3 columns) of each constituent STS-l of an STS-N
signal must be aligned such that the N framing bytes are contiguous in their S transmission. The Synchronous Payload Envelope (SPE) is allowed to float relative to the STS- I overhead bytes. The SPE starting location is identified by a pointer located in the respective STS-I overhead and will be referred to as the STS-I level pointer. Virtual tributaries (VTs) are carried within the STS- l SPE. VTs have their own SPE which may float in a sirnilar fashion to the STS- 1 SPE or may be locked, 10 meaning that the VT SPE does not move relative to the STS-I SPE. Floating VTstherefore have a VT level pointer analogous to the STS-I level pointer. The VT
pointers always appear as the first seven to twenty-eight bytes (depending on the VT
size) of the STS-I SPE. Floating VTs are preferred for carrying asynchronous payloads, such as a DS- l, that is not locked to the same clock as the switch. This 15 allows these asynchronous signals to pass through the switch withou~ added delay.
Therefore, it is preferable to transport signals in the floating format. When the VT
payload is to be switched, as in the case of DS-Os carried in a VT, a slip buffer is used to convert the floating VT to a locked VT. Locked VTs carry payloads that are synchronized to the switch clock and therefore are ideal for locating individual bytes 20 (time slots) such as DS-Os for switching. The SONET/SDH standards however do not allow mLlcing locked VTs with floating VTs within a STS- I . For a multirateswitch, all traffic being switched below the STS- 1 level is done using the floating format. All traffic that is being switched below the VT level (i.e., DS-Os) is converted to a pseudo-floating forrnat. That is, the VT SPE passes through a slip 25 buffer so that the SPE appears locked, and the VT level pointer is set to 0. For VT
level switching, the VT pointer is incren-en~e~ by an amount corresponding to thc value of the STS-l level pointer. The STS-l level pointer is set to 0, rneaning that the STS- I SPE, and consequently the VT pointers, start in the first posidon of thc payload envelope. For switching at the STS-l and above levels, the STS-l pointer is 30 passed to the switch without change.
After switching in a TSI, the VTs will exit the TSI shifted down one row relative to the overhead due to the VT frarne length of one row of the 125 microsecond frarne. The STS-l level pointer is therefore incrernented by an equivalent amount showing the SPE as a whole being shifted. For DS-O level 35 switching, the delay is the full 125 rnicrosecond frarne tirne, which places the VT
pointer associated with the DS-Os one row above the VT pointers associated with the VTs being switched at that level. However, all VT pointers must be contiguous. The 21Q4~4 path hunting meehanism must therefore offset the output time-slot assignments for DS-0 level calls by one row, thereby allowing the VT pointers to be eontiguous once again Finally, if STS-1 or above calls are switched as an entity, their respective STS- I level pointers and VT level pointers pass through the switch unchanged. If, 5 however, these higher-rate call types must be split partially into lower-rate portions to avoid blocking, and the lower-rate portion is of type VT, then the STS- l level pointers must be incremented by an amount representing the added delay of one row required to be inserted in the high-rate portion of the call to resynchronize that portion with the lower rate portion, as deseribed above.
This hierarchical alloeation and corresponding path hunts are aceomplished as follows. Turning to FIG. 27, conceptually, eaeh TSI 131 and 141 has an assoeiated hierarchy 2700 of status tables 2701-2703 stored conventionally in the memory of eon~ol proeessor 110 to be used to perforrn path hunts through system 100. Each one of the plwality of layers 2721-2723 of each hierarchy 2700 15 corresponds to a different one of the STS-l, VT, and DS-0 data rates, respectively.
Each one of the layers 2721-2723 compnses one or more corresponding status tables2701-2703,respeetively. TheSTS-lratelayer2721eontainsoneSTS-1 timeslot block status table 2701 which has twelve entries 2711. Each entry 2711 eorresponds to one tirne slot equivalent to an STS-l frame 30 (see FIG. 2). Hence, 20 eaeh entry 2711 represents the bandwidth of one STS-l within an STS- 12. Eachentry 2711 is eneoded to indieate whether the eorresponding bandwidth is fully idle, partially idle, or busy.
For every entry 2711, the VT rate layer 2722 eontains a different eorresponding VT dmeslot bloek status table 2702. Henee, there are 12 status 25 tables 2702 for eaeh table 2701. Eaeh status table 2702 has up to 28 entries 2712, eaeti eorresponding to a different VT of an STS-l. How many entries 2712 a table 2702 has at any one time depends upon the mix of VT types that the eorresponding STS-l earries at that ~me. Eaeh entry 2712 of layer 2722 corresponds to a timeslot equivalent to of one VT within an STS- 1. Hence, eaeh entry 2712 30 replesents the bandwidth of one VT. Eaeh entry 2712 is also eneoded to indieate whether the co-lcsponding bandwidth is fully idle, partially idle, or busy.
For every entry 2712, the DS~ rate layer 2723 contains a corresponding DS0 timeslot block status table 2703. Henee, the number of tables 2703 in layer 2723 varies with the number of VT entries in tables 2702 in layer 2722. Each 35 status table 2703 has a plurality of entries 2713, eaeh co,l~sl)onding to a different DS-0 of the cc,lcsponding VT. How many entries 2713 a table 2703 has depends upon the eorresponding VT type. Each entry 2713 represents the bandwidth of one DS-0, i.e., of onc timc slot of an STS-12 framc. Hcncc, there is a total of 9720entries 2713 in onc laycr 2723. Each entry 2713 is cncoded to indicate whether thc corresponding bandwidth is idle or busy.
The hierarchy 2700 of tables may be cxpanded to contain additional 5 levels--for example, to include an STS-3 upper levcl and an H0 (i.e., 384 kbps) next-to-lowest level. However, there is a tradeoff between the number of levels and the width of each level. The three-level hierarchy 2700 shown in FIG. 27 represents a reasonable tradeof To establish a given connection between a given input TSI 131 and a 10 given output TSI 141, matching idle input-TSI output time-slots and output-TSI
input time-slots must be found. To perfo~n a path hunt between a TSI 131 and a TSI 141, control processor 110 searches their corresponding hierarchies 2700 of status tables in a predefined way. For an STS-1 rate or a higher-rate connection, the preferred choice is to find matching idle entries at the STS-I level 2721. For a sub-15 STS- 1 rate, e.g., a VT rate, connection, the preferred choice is to find matching idle entries at the VT level 2722 which are not a part of fully-idle STS-ls. This preserves the fully-idle STS-ls--to the extent possible--for other STS-l rate or higher-rate connections. Similarly, for a su~VT rate, e.g., a DS-0 rate, connection, it is preferable to find matching idle DS-0 entries which are not part of fully-idle STS-ls 20 or fully-idle VTs. This preserves the fully-idle STS-ls and VTs--to the extent possible--for other higher-rate, e.g., STS-1 rate and VT rate, connections. Hence, the allocation procedure is described in the following hierarchy of searching for bandwidth of a particular size:
1) partiaVpartial matching at the STS-l level and the VT level, 2) partiaVpartial m3tching at the STS-l level and partiaVIdle matching at the VT level, 3) partiaVpartial matching at the STS-1 level and idle/partial matching at the VT level, 4) partiaVpartial matching at the STS-l level and idlefildle m~tching at 30 the VT level, S) partiaVidle matching at the STS-l level and partialrldle matching at the VT level, 6) partialfildle matching at the STS- 1 level and idlerldle matching at the VT level, 7) idle/partial matching at the STS-l level and idle/partial matching at the VT level, _35- 2 1 047~4 8) idle/par~ial matching at thc STS-l levcl and idle/ldlc matching at thc VT levcl, and 9) idlefidle matching at the STS-I level and idlerldle matching at the VT
levcl.
S Of course, how deep into this hierarchy a search proceeds depends upon the size of bandwidth sought. Thus, a search for an STS-I bandwidth does not reach the levelof this hierarchy; a search for a VT bandwidth follows only steps 4, 6, 8, and 9 of this hierarchy, and only a search for a DS-0 bandwidth follows all steps 1-9 of this hierarchy. Non-blocking performance is maintained by always Jetaining the option10 to form a higher-rate connection from a collection of a greater-than-ideal number of smaller-than-ideal bandwidth components.
The actual physical structure of the hierarchies 2700 of status tables of FIG. 27 is depicted in FIGS. 28-31. Layers 2721 of hierarchies 2700 are implemented in two matrices 2800 and 2801 of FIG. 28. Input TSI STS- 1 timeslot 15 block status matrix 2800 implements layers 2721 of input TSls 131, and output TSI
STS-l timeslot block status matrix 2801 implements layers 2721 of output TSIs 141.
Matrix 2800 has 64 rows, each corresponding to a different one input link 171 ofTMS 120 of system 100 of FIG. 1. Similarly, matrix 2801 has 64 rows, each corresponding to a different one output link 181 of TMS 120 of system 100.
20 Matrix 2800 has 24 columns: two sets of twelve columns each corresponding to a ~ble 2701 of a different one of the pair of input TSIs 131 that serve each inputlink 111 in the duplicated architecture of system 100 that was descr bed above.
Similarly, matrix 2801 also has 24 columns: two sets of twelve columns each comesponding to a table 2701 of a different one of the pair of output TSIs 141 that 25 serve each output link 151 in the duplicated architecture of system 100. Hence, the entries of matrices 2800 and 2801 are the entries 2711 of all tables 2701 of allhierarchies 2700 of FIG. 27.
Layers 2722 of hierarchies 2700 are implemented in VT timeslot block status matrices 2900 of FIG. 29. Each matrix 2900 forrns one table 2702 and 30 corresponds to a different entry 2701 of matrices 2800 and 2801 of FIG. 28. Each VT timeslot block status matrix 2900 has seven rows, one for each VT group of an. STS- 1. Each VT type matrix 2900 also has four columns, one for each VTI .S of a VT group. If a VT group does not carry four VTl.Ss but instead carries three VT2s, only the first three colurnns of its corresponding row of VT type matrix 2900 are 35 used; if it carries two VT3s, only the first two colurnns of its co~.~s~onding row are us&d; and if it carries one VT6, only the f~rst column of its co,l~sponding row is us&d, as illustratively shown in FIG. 29. Hencc, each entry of a matrix 2900 is an 210 17~

entry 2712 of a table 2702.
To indicate which typc of VT rate any VT group is carrying, thcrc arc associatcd with VT timeslot block status matrices 2900 of FIG. 29 a plurality of VT
group status matrices 3000 of FIG. 30. There is one VT group status matrix 3000 for 5 each input link 111 and output link 151 of system 100. Each VT group status matrix 3000 has 24 rows: two sets of twelve rows, each set corresponding to a different one of the pair of input TSls 131 or output TSIs 141 that serve the corresponding input link 111 or output link 151 in the duplicated architecture of system 100. Each row of a set of twelve rows corresponds to a different one of the 10 twelve STS-ls carried by the STS-12 of its corresponding link. Each VT group status matrix 3000 also has seven colurnns, one for each of the seven VT groups carried by each STS-l. The intersecting rows and columns form a plurality of entlies 3001. The contents of each entry 3001 indicate the type of VT rate which the corresponding VT group is presently carrying. Hence, each entry 3001 correspondsto a different row of VT timeslot block status matrices 2900 of FIG. 29 and indicates how many columns, or entries 2712, of that corresponding row are to be used, i.e., which entries 2712 carry valid information.
Layers 2723 of hierarchies 2700 are irnplernented in DS-0 timeslot block status matrices 3100 of FIG. 31. There is a different matrix 3100 for every entry 2711 of each matrix 2800 and 2801 of FIG. 28. Hence, each matrix 3100 corresponds to a different STS-l. Each matrix 3100 has seven rows, each corresponding to a different one of the VT groups of the corresponding STS-l. Each matrix 3100 also has 108 colurnns, each corresponding to a different DS-0, i.e., a different one of the 108 time slots, of the corresponding VT group.
The path-hunt method used by contTol processor 110 is depicted in detail in FIGS. 32-95. Prograrns that implement this method are stored in the memory of processor 110 and are executed from the rnemory by processor 110, as is conventional. FIGS. 32-33 show a general procedure used for processing a request, received at step 3200, for a broa-ib~nd connection of bandwidth A between input 30 port X and output port Y of TMS 120. The bandwidth A is first trans1ated into STS-1, VT6, VT3, VT2, VTl.5, and DS-0 connections, at step 3201. The translation is done as follows: bandwidth A is divided into as many tB) ful~ STS-l connections as possible; any remaining bandwidth is divided into as many (C) full VT6 connections as possible; any rem~ining bandwidth is divided into as rnany (D) full VT3 35 connections as possible; any remaining bandwidth is divided into as many (E) full VT2 connections as possib1e; any rem~ining bandwidth is divided into as many (P)full VT1.5 connections as possible; and finally any remaining bandwidth is divided 21047~4 into a number (G) of DS-0 connections.
Path-hunts are thcn performcd to find thc requisitc numbcr B of STS-I
connections, at step 3202. This step is diagrarned in FIG. 34. Thc result of thepath-hunts indicates how many (H) of the requisite STS-1 connections could not be 5 found. This number H is used to increment the number of requisite VT connections, at step 3203, i.e., bandwidth represented by the failed STS- 1 connections is divided into additional requisite VT connections. Thus, for every one of the H failed STS-l connections, the number of VT6 connections to attempt is increased by 7, where new C = (H 7) +old C, or the number of VT3 connections to attempt is increased by 10 14, where new D = (H 14) + old D, or the number of VT2 connections to attempt is increased by 21, where new E = (H-21) + old E, or the number of VTI.5 connections to attempt is increased by 28, where new F = (H 28) + old F, or some other equivalent mix of VT connections is used.
Path-hunts are then performed to find the requisite number C of VT6 15 connections, at step 3204. This step is diagramed in FIG. 36. The result of the path-hunts indicates how many (n of the requisite VT6 connections could not be found. This number J is used to increment the number of requisite VT3, VT2, and/or VTl.5 connections, at step 3205. For every one of the J failed VT6 connections, the number of VT3 connections to attempt is increased by 2, where 20 new D = (J 2) + old D, or the number of VT2 connections to attempt is increased by 3, where new E = (J 3) + old E, or the number of VTl.5 connections to attempt isincreased by 4, where new F = (J 4) + old F, or some equivalent mLlc of VT3, VT2, and VTl.5 coMections is used.
Path-hunts are then performed to find the requisite number D of VT3 connections, at step 3206. This step is diagramed in FIG. 44. The result of the path-hunts in~icates how many (K) of the requisite VT3 connections could not bc found. For every one of the K failed VT3 connections, the number of VT1.5 connections to attempt is increased by 2, where new F = (K-2) + old F, at step 3207.
Path-hunts arc then performed to find the requisite number E of VT2 connections, at step 3208. This step is diagramed in FIG. 52. The result of thc path-hunts indicates how many (L) of the requisite VT2 connections could not be found. For every one of the L failed VT2 connections, the number of DS~
connections to attempt is increased by 32, where new G = (~ 32) + old G, at step 3209.
Path-hunts are then perforrned to find the requisite number F of VTl.S
connections, at step 3210. This step is diagramed in FIG. 60. The result of thc path-hunts infiicates how many (M) of the requisite VTI.S connections could not be 2~7~

found. For every one of the M failed VTI.5 eonneetions, the numbcr of DS-0 eonneetions to attempt is increased by 24, where new G = (M 24) + old G, at step 3211.
Path-hunts are then perforrned to find the requisite number G of DS-0 5 connections, at step 3212. This step is diagramed in FIG. 69. The result of the path-hunts indicates how many (N) of the requisite DS-0 eonnections eould not befound. if this number N is zero, as determined at step 3213, the broadband eonnection request for bandwidth A is now eompleted, as indicated at step 3214, and the eonnection has been programmed into eontrol memories of TSIs 131 and 141 and10 TMS 120. But if the number N is not zero, the broadband connection request for bandwidth A has failed, as indicated at step 3215, and the eonnection eannot be established. Any portions of the failed eonnection that have b~en set up at this point are torn down.
An alternative arrangement may not set up any portion of the eonnection 15 until the path-hunt returns with an indication, at step 3213, that the hunt for the requested bandwidth has been satisfactorily completed. The entire connection is then set up, at step 3214.
FIG. 34 shows the procedure for setting up B STS- I connecdons. The procedure is perforrned in response to a request received from step 3202 of FIG. 32, 20 at step 3400. The request specifies the input port X and the output port Y ofTMS 120 that are to be interconneeted. These ports eorrespond directly to the hierarchieal status tables of an input TSI 131 and an output TSI 141 required for a given eonnection. In response to the request, an STS- 1 eonnection counter and an STS-1 fail-check flag (both not shown) are initialized to zero, at step 3401. The 25 value of STS- 1 connection counter is then ehecked against the number B of requested eonnections, at step 3402. If the counter's value is less than the number B, an attempt is made to set up one STS-l connection from input port X to output port Y, at step 3403. This step is diagramed in FIG. 35. If this anempt fails, the STS-l fail~heck flag is set to 1. The value of this flag is checked at step 3404. If 30 the value is zero, indicating that the anempt to set up an STS- 1 connection sueceeded, the value of STS-1 eonnection eounter is incremented by one, at step 3405, and prograrn execution returns to step 3402. If the value of Lhe STS-l fail-check flag is found at step 3404 to be one, indicating that the attempt to set up an STS-l eonnection failed, or if the value of the STS-l connection counter is found at 35 step 3402 to not be less than the number B, indicating that all requisite STS-l connections have been set up, the attempt to set up STS-l connections between input port X and output pon Y comes to an end, as indicated at step 3406, and the proccdure rcturns to step 3202 of FlG. 32 with thc number 11 of failcd STS-l connections, at stcp 3407. Thc numbcr H is computed as the number ~ minus thc present count of the STS- 1 connection counter. If the hunt for all requested STS- 1 connections was successful, the value of H is zero.
S FIG. 35 shows the procedure for setting up one STS- 1 connection. A
check is made to determine whether there are corresponding idle STS-l bandwidth blocks for both port X and port Y. If there are, the corresponding STS-I, VT, and DS-0 entries are marked busy or full, and the inforrnation to set up thc STS-l connection is sent to the system hardware--the TSIs and TMS.
The procedure is performed in response to a request received from step 3403 of FIG. 34, at step 3500. The request specifies the input port X and the output port Y. In response to the request, the procedure identifies and accessesSTS-1 timeslot block status table 2701 in matrix 2~00 of input TSI 131 serving input port X and table 2701 in matrix 2801 of output TSI 141 serving output port Y (see FIG. 28), at step 3501. Also, an STS-1 time-slot block (TSB) counter (not shown) is initialized to zero, at step 3502. The value of STS-l TSB counter is then used as an address pointer to access and examine a corresponding entry 2711 of each one of the tables 2701 that were accessed at step 3501 to determine if their contents indicate fully-idle bandwidth, at step 3503. For example, if the count of the STS-l TSB
20 counter is 5, then the sixth table entry is accessed and examined. If so, all entries of VT tables 2702 and DS-0 tables 2703 (see FIG. 27) that correspond to the entries 2711 that were accessed at step 3503 are marked as busy, at step 3507. Also, those two entries 2711 themselves are marked as busy in tables 2701, at step 3508.
This STS-l connection can now be prograrnmed into control memories of TSIs 131 25 and 141 and TMS 120, and so the results of the path-hunt are loaded into the TSI and TMS programming registers (see FIGS. 5, 8, 12, 16, 20, and 23-26), at step 3509.The setup having been successfully completed, the procedure rehlrns to step 3403 of FIG. 34, at step 3510.
Retuming to consideration of step 3503, if it is there determined that 30 both examined entries 2711 of tables 2701 do not indicate fully-idle bandwidth, the STS-1 TSB counter is incremented by one, at step 3511, and the counter's value is checked to determine whether it is less than 24, at step 3512. If the c~unter's value is less than 24, there are more STS-ls to be checked for availability, and program execution returns to step 3503. If the counter's value is not less than 24, all STS-ls 35 of the requisite input and output TSIs have b~en checked without success, and the attempt to set up the STS-l fails. The STS-l fail-check flag is therefore set to one to indicate the failure, at step 3513, and the procedure returns with this lack~f-success _40_ 21Q1~ 7~I
indication to step 3403 of FIG. 34, at step 3514.
FIG. 36 shows the procedure for setting up C VT6 connections. This procedure parallels exactly the procedure of FIG. 34, but subs~itutes VT6 for any reference to STS- I, the number C for any reference to the number B, and the number S J for any reference to the number H.
FIGS. 37-43 show the procedure for setting up one VT6 connection. A
check is made to deterrnine whether there are matching STS- I bandwidth blocks both marked as partially-idle. If so, they are good candidates from which idSe VT
bandwidth blocks may be selected without affecting fully-idle STS-1 blocks. When10 matching partiaSSy-idle STS-1 blocks are found, execution proceeds to the VT group level to find a VT group marked undesignated. Sf such a group is found, the VT
group is marked as VT6 and the corresponding DS-0 time slots are marked busy forports X and Y, the corresponding STS- 1 time-slot blocks are marked as busy or partially-idle for ports X and Y, and info~nation to set up the VT6 connection is sent 15 to the system hardware--the TSIs and TMS.
If a VT6 connecdon is not found following the above steps, a check is made to detemline whether an STS- 1 block for port X is partially-idle and the STS- 1 block for port Y is fully-idle. lf so, execution proceeds to the VT group level.lf a VT6 connecdon is not found following the above steps, a check is 20 made to determine whether an STS- 1 block for port X is fully-idle and the STS- 1 block for port Y is partially-idle. lf so, execution proceeds to the VT group level.
If a VT6 connectdon is not found following the above steps, a check is made to determine whether an STS-l block for port X is fully-idle and the STS-1 block for port Y is also fully-idle. If so, execution proceeds to the VT group level.
The procedure is perforrned in response to a request received &om step 3603 of FIG. 36, at step 3700. The request specifies the input port X and the output port Y. In response to the request, the procedure idendfies and accesses table 2701 of input TSI 131 serving input port X and table 2701 of output TSI 141 serving output port Y, at step 3700. Also, the STS-l TSB counter is initi~l;7e~ to 30 zero, at step 3702. The count of STS-l TSB counter is then used to access andexamine a corresponding entry 2711 of each one of the tables 2701 that were accessed at step 3501 to determine if their contents indicate partially-idle bandwidth, at step 3703. If so, program execution proceeds to step 3720 of FIG.41; if not, the STS-l TSB counter is incremented by one, at step 3704, and the counler's value is 35 checked to determine whether it is less than 24, at step 3705. lf the counter's value is less than 24, there are more STS- 1 s to be checked for partially-idle bandwidth, and prograrn execution returns to step 3503.

-41- 210~7~
If the countcr's valuc is not lcss than 24, all STS-ls of thc requisitc input and output TSIs have been checked for partially-idlc bandwidth without success. Therefore, thc STS- I TSB counter is reset to a value of zero, at step 3706 of FIG. 38, and thc value of this counter is then used to access and examine a 5 corresponding cntry 2711 of each one of the tables 2701 that werc accessed at step 3703 to determinc if the contents of entry 2711 of input TSI 131 table 2701indicatc partially-idlc bandwidth while the contents of entry 2711 of output TSI 141 table 2701 indicate fully-idle bandwidth, at step 3707. If so, program executionagain proceeds to step 3720 of FIG. 41; if not, the STS-1 TSB counter is 10 incremented by one, at step 3708, and the counter's value is again checked todete~nine whether it is less than 24, at step 3709. If so, program execution returns to step 3707 If the value of STS-l TSB counter is not less than 24, all STS-ls of the requisite input and output TSIs have been checked for the partially-idle/fully-idle 15 bandwidth combination without success. Therefore, the STS-l TSB counter is reset to a value of zero, at step 3710 of FIG. 39, and the count of this counter is then used to access and examine a corresponding entry 2711 of each one of the tables 2701 that were accessed at step 3703 to determine if the contents of entry 2711 of input TSI 131 table 2701 indicate fully-idle bandwidth while the contents of entry 2711 of output TSI 141 table 2701 indicate partially-idle bandwidth, at step 3711. If so, progT~m execution again proceeds to step 3720 of FIG. 41; if not, the STS-l TSB
counter is incremenled by one, at step 3712, and the counter's value is again checked to deterrnine whether it is less than 24, at step 3713. If so, program execution returns to step 3711.
If the value of STS-l TSB counter is not less than 24, the STS-l TSB
counter is reset to a value of zero, at step 3714 of FIG.40, and the count of this counter is used to access and examine a corresponding entry 2711 of each one of thc tables 2701 that were accessed at step 3703 to determine if their contents indicate fully-idle bandwidth, at step 3715. If so, program execution again proceeds to step 3720 of nG. 41; if not, the STS-l TSB counter is incremented by one, at step 3716, and the counter's value is again checked to deterrnine whether it is less than 24, at step 3717. If so; program execution returns to step 3715. If not, all STS-ls of the requisite input and output TSIs have been checked for idle bandwidth without success, and the attempt to set up the VT6 fails. The VT6 fail-check flag is 35 therefore set to one to indicate the failure, at step 3718, and the procedure retums with this lack-of-success indication to step 3603 of FIG. 36, at step 3719.

210~

Stcp 3720 of the routine shown in FIG. 41 is r~ached from FIGS. 37-40 when idlc bandwidth has succcssfully becn found in corrcsponding STS-ls of both input and output TSIs 131 and 141. At step 3720, the row of the VT group status matrices 3000 (see FIG. 30) that correspond to these STS- I s of thesc input andS output TSIs are accessed. Also, a VT6 group counter (not shown) is initialized to zero, at step 3721. Thc counter's value is then used to access and examine a corresponding entry 3001 of each one of the two rows that were accessed at step 3720 to deterrnine if their contents indicate that the corresponding VT groups are not carrying any VT typc, at step 3722. If no VT type is indicated, prograrn10 execution proceeds to step 3725 of FIG. 42. lf a VT type is indicated, it means that the bandwidth of that VT group is at least partially occupied, and hence that VTgroup cannot carry a VT6. The VT group counter is therefore incremented by one, at step 3723, and the counter's value is checked to deterrnine whether it is less than 7, at step 3724. If so, there are other VT groups in this STS- I to be checked, and so 15 program execution returns to step 3722. But if the counter's value is not less than 7, there are no VT groups in this STS-I available to carly a VT6, and so program execution returns to the point in FIGS. 3740 from which execution of the routine of FIG. 41 had been invoked.
Step 3725 of FIG. 42 is reached when an idle VT group has been found 20 in the STS-l of interest in both input and output TSIs. At step 3725, the present count of the VT group counter is used to identify and access VT timeslot block status tables 2702 in matrices 2900 of FIG. 29 that correspond to the idle VT groups in the STS-ls of interest. Also, a VT6 TSB counter (not shown) is initialized to zero, at step 3726. The count of this counter is then used to access and examine a 2S corresponding entry 2712 of each one of the tables 2702 that were acresse~ atstep 3725 to determine if their contents indicate fully-idle bandwidth, at step 3727.
If not, an error condition exists, as indicated at step 3728, because a VT grouphaving no VT type designation in a VT group status matrix 3000 must be idle.
If the contents of both checked entries 2712 do indicate fully-idle 30 bandwidth at step 3727, both of those entries 2712 are marked as busy, at step 3729, and the corresponding entries 3001 of VT group status matrices 3000 that were accessed at step 3722 are marked to indicate a VT type of VT6, at step 3730. Then, all entries of DS-0 tables 2703 (see FIG. 27) that correspond to the entries 2712 that were marked at step 3729 are also marked as busy, at step 3731 of FIG. 43.
35 Furthermore, the entries 2711 of tables 2701 which correspond to the STS-l ofinterest (indicated by the present count of the STS- 1 TSB counter) are updated to indicate partially-idle or busy status, at step 3732. Illustratively, the update is 21~4~4 accomplished by checking the STS- I 's in VT timeslot block sta~us matrix 2900 to determine if any valid entIies 2712 arc idle or partially idle. If so, the STS-l's colTesponding entry 2711 is marked as panially-idle. If all valid entries 2712 of matrix 2900 are marked as busy, then the STS-l's corresponding entry 2711 is S nlarked as busy. The VT6 connection is now ready ~o be programrned into control memories of TSIs 131 and 141 and TMS 120, and so (he results of the path-hunt are loaded into the TSI and TMS programming registers, at s~ep 3733. The setup having been successfully completed, the procedure returns to step 3603 of FIG. 36, at step 3734 FIG. 44 shows the procedure for setting up D VT3 connections. This procedure also parallels exactly the procedure of FIG. 34, but substitutes VT3 for any reference to STS-I, the number D for any reference to the number B, and the number K for any reference to the number H.
FIGS. 4S-51 show the procedure for setting up one VT3 connection.
15 The procedure is the same as for a VT6 connection, except for the VT group level.
Initially at the VT group level, a check is made for matching idle VT blocks forports X and Y. When such idle blocks are found, the VT blocks are marked busy (or full). The VT group level then proceeds as described above for VT6, where VT3 issubstituted for any reference to VT6.
The procedure is performed in response to a request received from step 4403 of FIG. 44, at step 4500. FIGS. 45-48 duplicate FIGS. 37-40, except that the transfer of program execution from steps 4503, 4507, 4511, and 4515 is to FIG. 49; at step 4518 of FIG. 48, it is a VT3 fail-check flag that is set to one; and at step 4519, the procedure returns to step 4403 of FIG. 44.
Also, the routine of FIG. 49 duplicates the routine of FIG. 41, with some exceptions. Because only a VT3 band vidth is being sought and not a full VT6 bandwidth, at step 4522 the two entries 3001, co.lcsponding to the subjeet input and output STS-ls, of VT group matrices 3000 are ex~mined to determine if their contents indieate that the corresponding VT groups either do not calTy any VT type, 30 i.e., are und.-si n~te~, or carry a VT3 type. If the determination is affirmative, prograun exeeution proceeds to step 4525 of FIG. 50. Because a VT group found atstep 4522 to be carrying a VT3 type may be found in FIG. 50 to be busy, in such a case program execution will return &om FIG. 50 to step 4523 to continue the search for a suitably-idle VT group.
Step 4525 of FIG. 50 is reached when either an undesignated VT group or a VT group carrying the VT3 type has been found in the STS-I of interest in both input and output TSIs. At step 4525, the present count of the VT g~up counter is 21~4~

used to identify and access VT timeslot block status tables 2702 of matrices 2900 of FIG. 29 that correspond to these VT groups in the STS- 1 s of interest. Also, a VT3 TSB counter (not shown) is initialized to zero, at step 4526~ The count of this counter is then used to access and examine a corresponding entry 2712 of each one 5 of the two tables 2702 that were accessed at step 4525 to determine if their contents indicate fully-idle bandwidth for the corresponding VT3, at step 4527. lf not, sufficient bandwidth is not available in that corresponding VT3~ The VT3 TSB
counter is then incremented by one, at step 4530, and the counter's value is checked to determine if it is less than two. If the counter's value is less than two, prograrn 10 execution retums to step 4527 to check the status of the next VT3 in the VT groups of interest. But if the counter's value is not less than two, there are no more VT3s in these VT groups to be checked. In other words, the search for an idle VT3 in this input and output VT group has been unsuccessful, as indicated at step 4532, and program execution retums to step 4523 of FIG. 49 to select and check another input 15 and output VT group for an available VT3~
Returning to consideration of step 4527, if exarnined entries 2712 indicate fully-idle bandwidth for the corresponding VT3 in both the input and output VT groups, both of those entries 2712 are marked as busy, at step 452B, and the corresponding entries 3001 of VT group status matrices 3000 that were accessed at 20 step 4S22 are marked to indicate a VT type of VT3, at step 4529~ Prograrn execution then continues in FIG~ 51, which duplicates FIG~ 43 except that, at step 4536, the procedure of FIG. 51 returns to step 4403 of FIG~ 44~
FIG~ 52 shows the procedure for setting up E VT2 connections~ The procedure is the same as for a VT3 connection~ This procedure also parallels exactly 25 the procedure of FIG. 34, but subst;tutes VT2 for any reference to STS-I, thenumber E for any reference to the number B, and the number L for any ~fel~nce to the number H~
FIGS~ 53-59 show the procedure for seffing up one VT2 connection~
This procedure is the.sarne as for a VT3 connection~ This procedure is performed in response to a r~uest received from step S203 of FIG~ 52, at step S300~ Analogously to the procedure for a VT3 connection, FIGS. 53-S6 duplicate FIGS. 37-40, exceptthat the transfer of program execution from steps S303, 5307, 5311, and 5315 is to FIG. 57; at step 5318 of FIG. 56, it is a VT2 fail-check flag that is set to one; and at step 5319, the procedure returns to step 5203 of FIG. 52~
Also, the routine of FIG~ 57 duplicates the routine of FIG~ 41, with some exceptions~ Because only a VT2 bandwidth is being sought and not a fulI VT6 bandwidth, at step 5322 the two entries 3001 of VT group matrices 3000 ;~re 2~0~73~
--4s--examined to determinc if thcir contents indicate that the corrcsponding VT groups either do not carry any VT typc, i.e., are undesignated, or carry a VT2 typc. If the dctermination is affirma~ive, program execution proceeds to s~ep 5325 of FIG. 58.
Because a VT group found at s~ep 5322 rnay be found in FIG. 58 to have all 5 corresponding VT timeslot blocks busy, in such a case prograrn execution will return from FIG. 58 to step 5323 to continue the search for a suitably-idle VT group.
FIGS. 58 and 59 parallel almost exactly FIGS. S0 and 51 discussed above in conjunction with VT3 connections, but substitute VT2 for any reference to VT3. The only difference is that, in step 5329 of FIG. 58, the value of the VT2 10 counter is checked against three, on account of there being three VT2s in a VT group (whereas there are only two VT3s in a VT group).
FIG. 60 shows the procedure for setting up F VT1.5 connections. Thc procedure is the same as for a VT2 connection. This procedure also parallels exactly the procedure of FIG. 34, but substitutes VTl.5 for any reference to STS~ he 15 number F for any reference to the number B, and the number M for any reference to the number H.
FIGS. 61-67 show the procedure for setting up one VTl.5 connection.
This procedure is the same as for a VT2 connection. This procedure is performed in response to a request received from step 6003 of FIG. 60, at step 6100. Analogously 20 to the procedure for a VT2 connection, FIGS. 61-64 duplicate FIGS. 37-40, except that the transfer of program execution from steps 6103, 6107, 6111, and 6115 is to FIG. 66; at step 6118 of FIG. 64, it is a VTl.5 fail-check flag that is set to one; and at step 6119, the procedure returns to step 6003 of FIG. 60.
Also, the routine of FIG. 65 duplicates the routine of FIG. 41, with some 25 exceptions. Because only a VT1.5 bandwidth is being sought and not a full VT6bandwidth, at step 6122 the two entries 3001 of VT group matrices 3000 are exarnined to determine if their contents indicate that the corresponding VT groups either do not carry any VT type, i.e., are undesignated, or carry a VTl.5 type. If the determination is affirrnative, prograrn execution proceeds to step 6125 of FIG. 66.
30 Because a VT group found at step 6122 rnay be found in FIG. 66 to be busy, in such a case prograrn execution will return from FIG. 66 to step 6123 to continue to search for a suitably-idle VT group.
FIGS. 66 and 67 parallel almost exactly FIGS. 50 and 51 discussed above in conjunction with VT3 connections, but substitute VTl.5 for any reference 35 to VT3. The only difference is that, in step 6129 of FIG. 66, the value of the VTl.5 counter is checked against four, on account of there being four VTl.5s in a VT group (whereas there are only two VT3s in a VT group).

210~754 FIG.68 shows lhe procedure for setting up G DS-0 eonnecdons. This proeedure also parallels exaetly the procedure of FlG. 34, but substitutes DS-0 for any reference to STS-I, the number G for any referenee to the number 8, and the num~er N for any referenee to the number H.
FIGS. 69-95 show the proce~ure for setting up one DS-0 eonnection. A
eheck is made to determine whether there are matehing STS- 1 blocks for pons X and Y both marked panially-idle. If so, execution proceeds to the VT group level, and if a positive result is indieated, a cheek is made to determine whether there are matehing VTI.S or VT2 blocks for ports X and Y both marked partially-idle. If 10 there are, execution proceeds to the DS-0 level. If matching idle time slots are found, the DS-0 entries are marked busy, the VT g~up is marked either as VT2 or as VTI.5 as necessary, and the corresponding STS-I and VT blocks are marked busy orpartially-idle for ports X and Y. Infomlation to set up the DS-0 connection is then sent to the system hard~are--the TSls and TMS.
If a DS-0 connection is not found following the above steps, a check is made to deterrnine whether there are matching STS-1 blocks for ports X and Y both marked partially-idle. If so, execution proceeds to the VT group level, and if apositive result is indicated, a check is made to determine whether there is either a V 1`2 or VTl.5 block for port X marked partially-idle that has its matching VT block 20 for port Y marked fully-idle. If such blocks are found, execution proceeds to the DS-0 level. These are the 6rst two levels of the 9-level hierarehy listed above; the other levels are performed in a corresponding manner, as need demands.
. The procedure is performed in response to a request received from step 6803 of FIG. 68, at step 6900. FIGS. 69-72 each duplicate FIG.37, except that the transfer of prograrn execution from step 6903 of FIG. 69 is to FIG.78, from step 6907 of FIG. 70 is to FIG. 80, and from step 6915 of FIG.72 is to FIG. 81. Illis is because the search for a DS-0 follows a search hierarchy for a partial-partial, partial-idle, idle-partial, and idle-idle through the VTs, in FIGS.78-81, respectively, just as it does through STS-1s in FIGS, 37-40.
FIGS.73 and 75 each duplicate FIG. 38, except that the transfer of program execution from step 6919 of FIG. 73 is to FIG. 82, and from step 6927 ofFIG. 75 is to FIG. 86. Similarly FIGS. 74 and 76 eaeh duplieale FIG. 39, except that the transfer of program execution from step 6923 of FIG.74 is to FIG.84, and from step 6931 of FIG.76 is to FIG. 86.
FIG.77 duplicates FIG. 40, except that, at step 6935, transfer of execution is to FIG. 86; at step 6938, it is a DS-0 fail~heek flag that is set to one;
and at step 6939, the procedure returns to step 6803 of FIG. 68.

21~47~1 FIGS. 78-86 reflect the VT group-level search conducted for a DS-0 connecdon. Since a DS-0 occupies only a small portion of a VT group, both undesignated (fully-idle) and designated ~partially-idle) matching VT groups arcsuitable for carrying a DS-0. However, in the SONET and SDH standards, DS-0 S connections are mapped only into the lowest two VT rates--VTl.5 and VT2.
Furthermore, it is desirable, for blocking-avoidance pu poses, to ensure that a DS-0 connection is mapped into the same one VT rate end-to-end. Therefore, only matching VT groups that are either both undesignated, or both designated as VTl.S, or both designated as VT2, are acceptable to carry a DS-0 connection. The search 10 for a DS-0 follows a search hierarchy for designated/designated, designated/undesignated, undesignated/designated, and undesignated/undesignated matching VT groups. Hence, four sets of routines for searching through VT group status matrices are required. Then, within each suitable matching pair of VT groups, the search for a DS-0 follows a search hierarchy for a partial-partial, partial-idle, 15 idle-partial, and idle-idle through the VTs of that group. However, not all these searches need to be performed for each VT group -- a search for a partially-idle VT
in an undesignated VT group is meaningless, since undesignated VT groups are fully idle, by definition.
Accordingly, to reflect these various constraints, there are eight routines 20 -- FIGS. 78-86 -- each one of which parallels the routine of FIG. 41. Whereas the routine of FIG. 41 only searched for undesignated matching VT groups, FIGS. 78-81 search for matching VT groups either both designated as VT2 or both designated as VTl.S, FIGS. 82-83 search for matching VT groups wherein the input VT group is designated as VT2 or as VTI.5 and the output VT group is undesi~n~ted, FIGS. 84-25 85 search for matching VT groups wherein the input VT group is undesignated andthe output VT group is designated as VT2 or as VTl.5, and FIG. 86 searches for undesignated m~tshing VT groups.
Execution of FIG. 78 is entered from FIG. 69. If rnatching VT groups both designated either as VT2 or as VTl.5 are found at step 6942 of FIG. 78, 30 pro~am execution proceeds to FIG. 87 to search for partial-partial m~tçhing VTs within those VT groups; if the search of FIG. 87 should fail, pro~am execution will return to step 6943 to continue the search for suitably-designated matching VT
groups. If such VT groups cannot be found in FIG. 78, program execution proceedsto FIG. 79.
If suitably-designated matching V~ groups are found at step 6946 of FIG. 79, program execution proceeds to FIG. 88 to search for partial-idle m?tching VTs within those VT groups; if the search of FIG. 88 should fail, prograrn execution 210475~

will re~urn to step 6947 to continuc thc scarch for suilably-dcsignatcd matching VT
groups. If such VT groups cannot be found in FIG. 79, program exccution procccdsto FIG. 80.
If su;tably-designated matching V~ groups are found at step 6950 of 5 FIG. 80, program execution proceeds to FIG. 89 to search for idle-partial matching VTs ~vithin those groups; if the search of FIG. 89 should fail, program execution will return to step 6951 to continue the search for suitably-designated ma~ching VT
groups. If such VT groups cannot be found in FIG. 80, program execution proceedsto FIG. 81.
If suitably-designated rnatching VT groups are found at step 6954 of FIG. 81, program execution proceeds to FIG. 90 to search for idle-idle matching VTs within those groups; if the search of FIG. 90 should fail, prograrn execution will return to step 6955 to continue the search for suitably-designated matching VT
groups. If such VT groups cannot be found in FIG. 81, program execution retums to 15 FIG. 69.
Execution of FIG. 82 is entered from FIG. 70 or FIG. 73. If an input VT
group designated as VT2 or as VTI.5 and a matching undesignated output VT group are found at step 6959 of FIG. 82, prograrn execution proceeds to FIG. 88 to search for partial-idle matching VTs within those VT groups; if the search of FIG. 88 20 should fail, program execution will return to step 6960 to continue the search for a suitably designated-undesignated matching VT group combination. If such a VT
group combination cannot be found in FIG. 82, program execution proceeds to FIG. 83.
If a suitably designated-undesignated matching VT group combination 25 is found at step 6963 of FIG. 83, prograrn execution proceeds to FIG. 90 to search for idle-idle matching VTs within those VT groups; if the search of FIG. 90 should fail, program execution will return to step 6964 to continue the search for a suitably designated-undesignated matching VT group combination. If such a VT group combination cannot be found in FIG. 83, program execution returns to FIG. 70 or 30 FIG. 73 from whence it came.
Execution of FIG. 84 is entered from FIG. 71 or FIG. 74. If an undesignated input VT group and a matching output VT group designated as VT2 or as VTI.5 are found at step 6968 of FIG. 84, program execution proceeds to FIG. 89 to search for idle-partial m~tçhing VTs within those VT grol~ps; if the search of 35 FIG. 89 should fail, program execution will return to step 6969 to continue the search for an undesignated-suitably designated matching VT group combination. Ifsuch a VT group combinadon cannot be found in FIG. 84, program execudon 210~7~

-procccds to FlG.8S.
If an undesignated-suilably dcsignated matching VT group combination is found at step 6972 of FIG. 85, prograrn execution proceeds to FIG.90 to search for idle-idle matching VTs within those VT groups; if the search of FIG. 90 should 5 fail, prograrn execution will retum to step 6973 to continue the search for anundesignated-suitably designated matching VT group combination. lf such a VT
group combination cannot be found in FIG. 85, prograrn execution returns to FIG. 71 or FIG.74 from whence it came.
Execution of FIG. 86 is entered from FIG.72,75,76, or 77. If 10 undesignated matching VT groups are found at step 6977 of FIG.86, program execution proceeds to FIG.90 to search for idle-idle matching VTs within those VT
groups; if the search of FIG.90 should fail, program execution will return to step 6977 to continue the search for undesignated matching VT groups. If such VTgroups cannot be found in FIG. 86, program execution returns to FIG.72,75,76, or15 77 from whence it came.
The function of one of FIGS. 87-90 is reached when suitable matching VT groups have been found in FIGS.78-86, as described above. Turning first to FIG. 87, at step 6980, a VT# variable is set to the VT2 or VTl.5 designated status of the suitable matching VT groups that had been found in the one of the FIGS.78-86;
20 if the VT group's status is undesignated, then the VT# variable is set to either VTl.5 or VT2. The value of the VT# variable determines whether the DS-O connection is mapped to a VTl.S or a VT2 rate. Also, if the VT# variable is set to VT2, then a VT
count variable is set to 3 (the number of VT2s in a VT group) and a TS count variable is set to 36 (the nùmber of time slots, or DS-Os, in a VT2). If the VT#2S variable is not set to VT2, then the VT count variable is set to 4 (the number of VTl.5s in a VT group) and the TS count variable is set to 27 (the number of timeslots, or DS-Os, in a VTl.5).
The rem~ining steps of FIG. 87 closely parallel those of FIG. 50, which had been discussed above in conjunction with VT3 connections. At step 6981, the 30 present count of the VT group counter is used to identify and access VT timeslot block status tables 2702 that correspond to the subject matching VT groups of the input and output TSIs. Also, either a VT2 or a VTl.5 counter--depending upon thevalue of VT#--is initialiæd to zero, at step 6982. The count of this counter is then used to access and examine a corresponding entry 2712 of each one of thc 35 tables 2702 that were accessed at step 6960 to determine if their contents indicate partially-idle bandwidth for the col,esponding VT2 or VTI.S in both the input and output TSIs, at step 6983. If so, prograrn execution proceeds to FIG.91 to look for _50_ 210~7~4 an idle DS-O in that VT in both the input and output TSIs; if not, the VT2 or VTl.5 counter that was initialized at step 6982 is ineremented by one, at step 6984, and the eounter's value is checked against the value of the VT count variable to detennine if the counter's value is smaller. If so, program execution returns to step 6983 to check S the status of the next VT2 or VTl.5 in the subject matching VT groups. But if the counter's value is no~ less than the value of VT eount, there are no more VT2s or VTI.5s in these VT gToups to be checked. In other words, the search for a partially-idle VT2 or VTI.5 in this input and output VT group has been unsuccessful, as indieated at step 6986, and program execution returns to step 6943 of FIG.78 to 10 seleet and check another input and output VT group, The functions of FIGS. 88-90 essentially duplicate the funetion of FIG. 87. But whereas step 6983 of FIG. 87 checks for a partial-partial VT2 or VT1.5 combination, step 6990 of FIG. 88 checks for a par~ial-idle combination, step 6997 of FIG. 89 checks for an idle-partial combination, and s~ep 7004 of FIG. 90 checks 15 for an idle-idle combination.
The function of FIG. 91 is reached when a fully or a partially-idle VT2 or VTl.5 has been found in FIG. 87. At step 7008, the present count of the VT2 or VTl.5 TSB counter -- depending upon the value of VT# -- is used to identify and aecess DSO timeslot block status tables 2703 (see FIG. 27) in DS-O timeslot bloek 20 status matrices 3100 (see FIG. 31) that correspond to the suitably-idle VT2 or VT1.5 in the input and output TSIs. Also, a DSO TSB counter (not shown) is initialized to zero, at step 7009. The eount of this eounter is then used to aecess and exalrune a eorresponding entry 2713 of each one of the two tables 2703 that were accessed at step 7008 to determine if their contents indicate that the corresponding DSOs are idle 25 in both input and output TSIs, at step 7010. If so, the DS-O is available, and program exeeution proceeds to FIG.95; if not, the DS-O is not available, and the next DS~
must be eheeked. The DSO TSB eounter is therefore incremented by one, at step 7011, and the counter's value is eheeked against the value of the TS count variable, at step 7012. If the eounter's value is less than the TS eount's value, there 30 are more DSOs to be eheeked in this VT2 or VTl.5, and so pro~am exeeution returns to step 7010 to check the status of the next DS-O. But if the counter's value is not less than the TS eount's value, there are no more DS-Os in this VT2 or VTl.5 to be eheeked. In other words, the seareh for an idle DS~ in thlis input and output VT2 or VTl.5 has been unsuceessful, as indieated in step 7013, and program 35 exeeution returns to FIG. 87 from whenee it carne, to seleet another VT2 or VTI.5.

21Q~7~

FIGS. 92-94 substantially duplicatc FIG. 91. Thc function of FlG.92 is entered from FIG. 88, at step 7016 checks only the entry 2713 of table 2703 of thc input TSI 131 because the DS-0 of the output TSI is known to be idle from FIG. 88, and if the check is unsuccessful, it returns to FIG. 88. Similarly, the function of 5 FIG. 93 is entered from FIG. 89, at step 7022 checks only the entry 2713 of table 2703 of the output TSI 141 because the DS-0 of the input TSI is known to be idle from FIG. 89, and if the check is unsuccessful, it returns to FIG.89. In like vein, the function of FIG.94 is entered from FIG 90, at step 7028 performs a pro-forma check of the entries 2713 of table 2703 of the input and output TSls which10 should never fail because the DS-Os are known to be idle from FIG.90, and lhen proceeds to FIG.95 as do FIGS. 91-94.
Turning to FIG. 95, both of the entries 2713 that were just successfully examined in FIG. 91,92, 93, or 94 for matching idle DS-Os are marked as busy, atstep 7032. Also, if the entlies 3001 of VT group status matrices 3000 for the input 15 and output VT2 or VTl.5 which contain the subject DS0 do not indicate any VT
type, then they are marked to indicate VT2 or VT1.5--depending upon the present value of the VT# variable--at step 7033. Furthermore, the entries 2712 of - tables 2702 which correspond to the VT2 or VTl.5 that contains the subject DS0 (indicated by the present count of either the VT2 or the VT1.5 TSB counter--20 depending upon the present value of the VT# variable), and the entries 2711 of tables 2701 which correspond to the STS-1 which in turn contains that VT2 or VT1.5 (indicated by the present count of the STS-l TSB counter), are updated to indicate partially-idle or busy status, at step 7034, in the manner described previously for step 3732 of FIG.43. The DS-0 connection is now ready to be 25 prograrnmed into control memories of input TSI 131, output TSI 141, and TMS 120, and s~o the results of the path-hunt are loaded into the TSI and TMS prograrnrning registers, at step 703S. The setup having been successfully completed, the procedure retums to step 6803 of FIG. 68, at step 7036.
Of course, it should be understood that various changes and 30 modifications to the illustradve embodirnent described above will be apparent to those skilled in the art. For example, the invention can be applied to any three-stage switching network comprised of time and/or space switching stages. Specific examples include a space-space-space switching network or a space-time-space switchiing network These variations may be chosen depending upon the format of 35 the information being transported on the network. In addition, the invention can be applied to any network, in that any single stage in any network can be replaced by a three-stage network in accord~nce with this invendon. Also, mulds~age fabrics may -52- 210~7~
- bc subdivided into threc-stagc subsets, or the algorithm can be extendcd for paralle~
searches across all stages. For example, for a four-stage fabric, the search hierarchy would be extended to partial-partial-partial, partial-panial-idle, etc. Such changes and modifications can be made without departing from the spirit and the scope of the 5 invention and without diminishing its attendant advantages. It is therefore intended that all such changes and modifications be covered by the following claims.

Claims (29)

1. A switching element for switching connections having a hierarchy of data rates comprising a lowest rate corresponding to one time slot of a time-division multiplex (TDM) superframe of time slots and at least one higher rate corresponding to at least one time slot of a predetermined frame of time slots within said TDMsuperframe, said switching element comprising:
a first port;
a plurality of second ports;
control memory means for defining switched connections having said lowest rate and said at least one higher rate, said control memory means including a different control memory location for each time slot of said superframe wherein contents of each control memory location indicate which second port is to be connected to said first port during every occurrence of a switching element output time slot that corresponds to said control memory location;
means responsive to contents of said control memory locations for connecting said first port to ones of said second ports during first time-slot intervals to effect connections having said lowest rate and for connecting said first port to ones of said second ports during second time-slot intervals to effect connections having said at least one higher rate; and means for programming said control memory means to define an individual switched connection corresponding to a selected rate of the hierarchy and including means for detecting occurrence of a switching element output time slot corresponding to the individual switched connection within each frame that corresponds to the selected rate in a switching element output superframe, and means coupled to the detecting means and to the control memory means and responsive to each detection for writing, into the control memory location that corresponds to the detected output time slot, information specifying one of saidsecond ports that is to be connected to said first port during each occurrence of said output time slot that corresponds to said control memory location that corresponds to the detected output time slot.

2. The switching element of claim 1 wherein said switching element functions as a time-multiplexed space switch.

3. Apparatus for switching connections having a hierarchy of data rates comprising a lowest rate corresponding to one time slot of a time-division multiplex (TDM) frame of time slots and at least one higher rate corresponding to a plurality of time slots within said TDM frame, said apparatus comprising:
means, responsive to a command to establish a given connection having said higher rate, said command specifying only one time slot within said TDM frame and a data rate for said given connection, for determining from said specified time slot and data rate a set of a plurality of time slots within said TDM frame for said given connection;
control memory means having locations corresponding to said TDM
frame of time slots;
means coupled to the means for determining a set of a plurality of time slots for said given connection, for determining locations in said control memory means that correspond to determined said set of a plurality of time slots;
means coupled to the means for determining a set of a plurality of time slots for said given connection, for writing information defining said given connection into determined said locations of said control memory means; and switching means responsive to reading of connection information written into said determined locations of said control memory means for establishing said given connection having said higher rate.

4. The apparatus of claim 3 wherein:
the location-determining means are responsive to a command to establish a connection having said lowest rate, said command specifying a time slot within said frame and a data rate for said connection having said lowest rate, for determining a location in said control memory that corresponds to said specified time slot;
the writing means write information defining said connection having said lowest rate into said determined location of said control memory; and said switching element is responsive to reading of said stored lowest-rate connection information written into said determined location of said control memory for establishing said connection having said lowest rate.

5. The apparatus of claim 3 wherein said switching means is a time-slot interchanger and said determined set of time slots comprises output time slots of said time-slot interchanger.

6. The apparatus of claim 5 wherein said information defining said given connection identifies input time slots of said time-slot interchanger.

7. The apparatus of claim 6 wherein said command specifies only one output time slot and an input time slot corresponding to said one output time slot.

8. The apparatus of claim 3 wherein said switching means is a time-multiplexed space-switching element having a plurality of first ports and a second port and said determined set of time slots comprise output time slots of said time-multiplexed space-switching element.

9. The apparatus of claim 8 wherein said information defining said given connection identifies one of said first ports.

10. The apparatus of claim 9 wherein said command specifies only one output time slot and one of said first ports that corresponds to said one output time slot.

11. A time-slot interchanger comprising:
data memory means;
control memory means having a plurality of locations each corresponding to a different one of a plurality of time slots of a time-divisionmultiplex frame;
means responsive to a request for a connection comprising multiple time slots of the time-division multiplex frame, said request specifying only one input time slot and one output time slot and a data rate of said connection, for determining, from specified said time slots and specified said data rate, other input time slots and output time slots for use for said connection comprising multiple time slots;
means coupled to the determining means, for writing into locations of said control memory means which correspond to said one output time slot and determined said other output time slots, information identifying said one input time slot and determined said other input time slots; and said data memory means being responsive to said control memory means for transmitting information, stored from said one input time slot and said determined other input time slots, in said one output time slot and said determined other output time slots.

12. A time-slot interchanger in accordance with claim 11 wherein input time slots and output time slots of each higher rate within the hierarchy have a predefined spacing within said time-division multiplex frame; and said determining means determines said other input time slots and said other output time slots in accordance with said predefined spacing.

13. A time-multiplexed space switch comprising:
a plurality of first ports;
a second port;
control memory means having a plurality of locations each corresponding to a different one of a plurality of time slots of a time-divisionmultiplex frame;
means responsive to a request for a connection comprising multiple time slots of the time-division multiplex frame, said request specifying a first port and only one output time slot of said switch and a data rate for said connection, for determining, from specified said first port and one output time slot and data rate, other output time slots of said switch for use for said connection comprising multiple time slots;
means for writing into locations of said control memory means which correspond to said one output time slot and determined said other output time slots, information defining said first port; and means responsive to said control memory means for transmitting information from input time slots of one of defined said first port and said second port, in said one output time slot and said determined other output time slots of the other of said defined first port and said second port.

14. A time-multiplexed space switch in accordance with claim 13 wherein:
input time slots and output time slots of each higher rate within the hierarchy have a predefined spacing within said time-division multiplex frame; and said determining means determines said other output time slots in accordance with said predefined spacing.

15. Apparatus for switching connections having a hierarchy of data rates comprising a lowest rate corresponding to one time slot of a time-division frame of time slots, said hierarchy comprising at least one higher rate corresponding to a plurality of time slots of predefined spacing within said time-division frame, said apparatus comprising:
means responsive to a request to establish a given connection having said higher rate for determining a set of time slots of said predefined spacing within said time-division frame for said given connection;
control memory means for defining switched connections having said lowest rate and said at least one higher rate, said control memory means including a different control memory location for each time slot of said time-division frame of time slots wherein contents of each control memory location indicate which inputtime slot is to be connected to an output time slot corresponding to said memorylocation during every occurrence of said output time slot that corresponds to said control memory location;
means for determining locations in said control memory means that correspond to determined said set of time slots;
means for writing information defining said given connection into determined said locations of said control memory means, including means for detecting each occurrence of a switching element output time slot corresponding to said given connection within said time-division frame, andmeans coupled to the detecting means and to the control memory means and responsive to each detection for writing, into the control memory location that corresponds to the detected output time slot, information specifying one of said input time slots that is to be connected to said detected output time slot during eachoccurrence of said output time slot that corresponds to said control memory location that corresponds to the detected output time slot; and switching means responsive to reading of connection information written into said determined locations of said control memory means for establishing said connection having said higher rate.

16. A method of switching connections having a hierarchy of data rates comprising a lowest rate corresponding to one time slot of a time-division multiplex (TDM) superframe of time slots and at least one higher rate corresponding to at least one time slot of a predetermined frame of time slots within said TDM superframe,said switching method comprising the steps of:
during each time slot of said TDM superframe, reading a different control memory location of a control memory that defines switched connections having said lowest rate and said higher rate, said control memory means including a different said control memory location for each time slot of said TDM superframe, wherein contents of each control memory location indicate which one of a plurality of first ports is to be connected to a second port during every occurrence of a switching element output time slot that corresponds to said control memory location;
in response to contents of said control memory locations, connecting said second port to ones of said first ports during first time-slot intervals to effect connections having said lowest rate and for connecting said second port to ones of said first ports during second time-slot intervals to effect connections having said higher rate; and reprogramming said control memory means to define an individual switched connection corresponding to a selected rate of the hierarchy and including the steps of detecting occurrence of a switching element output time slot corresponding to the individual switched connection within each frame that corresponds to the selected rate in a switching element output TDM superframe, and in response to each detection, writing into the control memory location that corresponds to the detected output time slot, information specifying one of said first ports that is to be connected to said second port during each occurrence of said output time slot that corresponds to said control memory location that corresponds to the detected output time slot.

17. The switching method of claim 16 wherein said switching method performs a time-multiplexed space-switching function.

18. A method of controlling a switching element for switching connections having a hierarchy of data rates comprising a lowest rate corresponding to one time slot of a time-division multiplex (TDM) frame of time slots and at least one higher rate corresponding to a plurality of time slots within said TDM frame, said method comprising the steps of:
in response to a command to establish a given connection through said switching element having said higher rate, said command specifying only one timeslot within said TDM frame and a data rate for said given connection, determining from specified said one time slot and specified said data rate a set of a plurality of time slots within said TDM frame for said given connection;

determining locations in a control memory that correspond to determined said set of a plurality of time slots;
storing in determined said locations of said control memory information defining said given connection; and operating said switching element in response to reading of stored said connection information from said control memory to establish said given connection having said higher rate.

19. A method in accordance with claim 18 further comprising the steps of:
in response to a command to establish a connection through said switching element having said lowest rate, said command specifying a time slot within said TDM frame and a data rate for said connection having said lowest rate, determining a location in said control memory that corresponds to specified said time slot;
storing information defining said connection having said lowest rate in determined said location of said control memory; and operating said switching element in response to reading of stored said lowest-rate connection information to establish said connection having said lowest rate.

20. A method in accordance with claim 18 wherein said switching element is a time-slot interchanger and said determined set of time slots comprises output time slots of said time-slot interchanger.

21. A method in accordance with claim 20 wherein said information defining said given connection identifies input time slots of said time-slot interchanger.

22. A method in accordance with claim 21 wherein said command specifies only one output time slot and an input time slot corresponding to said one output time slot.

23. A method in accordance with claim 18 wherein said switching element is a time-multiplexed space-switching element having a plurality of first ports and a second port and said determined set of time slots comprise output time slots of said time-multiplexed space-switching element.

24. A method in accordance with claim 23 wherein said information defining said given connection identifies one of said first ports.

25. A method in accordance with claim 24 wherein said command specifies only one output time slot and one of said first ports that corresponds to said one output time slot.

26. A method of controlling a time-slot interchanger having a data memory and a control memory that includes a plurality of locations each corresponding to a different one of a plurality of time slots of a time-divisionmultiplex frame, the method comprising the steps of:
in response to a request for a connection comprising multiple time slots of the time-division multiplex frame, said request specifying only one input time slot and one output time slot and a data rate of said connection, determining, from specified said time slots and specified said data rate, other input time slots and output time slots for use for said connection comprising multiple time slots;
writing into locations of said control memory which correspond to said one output time slot and determined said other output time slots, information identifying said one input time slot and determined said other input time slots; and in response to contents of said control memory means, transmitting information stored from said one input time slot and said determined other inputtime slots, in said one output time slot and said determined other output time slots.

27. The method in accordance with claim 26 wherein input time slots and output time slots of each higher rate within the hierarchy have a predefined spacing within said time-division multiplex frame; and said step of determining determines said other input time slots and said other output time slots in accordance with said predefined spacing.

28. A method of controlling a time-multiplexed space switch having a plurality of first ports, a second port, and a control memory having a plurality of locations each corresponding to a different one of a plurality of time slots of a time-division multiplex frame, the method comprising the steps of:

in response to a request for a connection comprising multiple time slots of the time-division multiplex frame, said request specifying a first port and only one output time slot of said switch and a data rate for said connection, determining, from specified said first port and one output time slot and data rate, other output time slots of said switch for use for said connection comprising multiple time slots;
writing into locations of said control memory which correspond to said one output time slot and determined said other output time slots, information defining said first port; and in response to contents of said control memory transmitting information from input time slots of one of defined said first port and said second port, in said one output time slot and said determined other output time slots of the other of said defined first port and said second port.

29. The method in accordance with claim 28 wherein:
input time slots and output time slots of each higher rate within the hierarchy have a predefined spacing within said time-division multiplex frame; and said step of determining determines said other output time slots in accordance with said predefined spacing.