CA2097349C - Timing recovery for variable bit-rate video on asynchronous transfer mode (atm) networks - Google Patents
Timing recovery for variable bit-rate video on asynchronous transfer mode (atm) networksInfo
- Publication number
- CA2097349C CA2097349C CA002097349A CA2097349A CA2097349C CA 2097349 C CA2097349 C CA 2097349C CA 002097349 A CA002097349 A CA 002097349A CA 2097349 A CA2097349 A CA 2097349A CA 2097349 C CA2097349 C CA 2097349C
- Authority
- CA
- Canada
- Prior art keywords
- signal
- scr
- video
- stc
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
- H04N21/4305—Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
- H04N21/4307—Synchronising the rendering of multiple content streams or additional data on devices, e.g. synchronisation of audio on a mobile phone with the video output on the TV screen
- H04N21/43072—Synchronising the rendering of multiple content streams or additional data on devices, e.g. synchronisation of audio on a mobile phone with the video output on the TV screen of multiple content streams on the same device
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
- H04N21/44004—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving video buffer management, e.g. video decoder buffer or video display buffer
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client
- H04N21/63—Control signaling related to video distribution between client, server and network components; Network processes for video distribution between server and clients or between remote clients, e.g. transmitting basic layer and enhancement layers over different transmission paths, setting up a peer-to-peer communication via Internet between remote STB's; Communication protocols; Addressing
- H04N21/643—Communication protocols
- H04N21/64307—ATM
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5614—User Network Interface
- H04L2012/5616—Terminal equipment, e.g. codecs, synch.
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
Abstract
Complications of timing recovery in an ATM receiver are overcome by employing a first phase lock loop including a phase comparator, filter, voltage controlled oscillator (VCO) and output counter to lock to systems clock reference (SCR) values which are asynchronously received from a remote ATM transmitter. The SCR values represent the instantaneous values of a system timing clock (STC) at the instant of transmission of the asynchronous SCR values. In the receiver, the output counter is first set to the value of the initial received SCR value so that the derived STC is available for decoding data cells in the initial received packets. Then, so-called Presentation/Decode Time Stamps (PTS/DTS) included in the audio and video data are advantageously employed in conjunction with STC to display properly the received data. In one embodiment of the invention, underflow of the receiver data buffers is alleviated by the addition of a "jitter-delay (D j)" value which causes an extra accumulation of data in the data buffers prior to decoding. Dynamic tracking of the jitter-delay of the channel is obtained by monitoring the fullness of the data buffers and controllably adjusting the jitter-delay, accordingly. The stability of the decoder video timing is enhanced by employing an additional phase locked loop in a video display control which is supplied with a timing error signal. The additional phase locked loop includes a switch, filter, clipper and voltage controlled oscillator (VCO). The switch is enabled in response to output pulses from the VCO to supply the instantaneous error signal input to the filter for each so-called video presentation unit. The VCO has a very stable center frequency which variation is limited by clipping an input control voltage to some small voltage range.
Output pulses from the VCO are employed to enable decoding of the presentation units.
Faster synchronization is provided at start-up by increasing, via control of the clipper, the allowable voltage range of the VCO.
Output pulses from the VCO are employed to enable decoding of the presentation units.
Faster synchronization is provided at start-up by increasing, via control of the clipper, the allowable voltage range of the VCO.
Description
~ 2 0 9 7 3 ~
Timing Rcco~ For Variable Bit-Rate Video On A~ hr~..o~ Transfer Mode (ATM) N~h.~. h~
Technical Field This invention relates to digital tr~n~mi~ion of video info..llAIion and, 5 more particularly, to timing recovery for variable bit-rate video in an ATM digital receiver.
Back~round of the In~..li~l.
Netw~,Ls are known which support variable bit-rate tr~n~mi~ion by parhtioning user data into a sequence of so-called "cells" and inpul~ing them 10 asynchronously to the netvork. One such n.,lwc,l~ is the Bro~db~n~ Inte~alt;dServices Digital Network (B-ISDN) and is referred to as an Asynchronous TransferMode (ATM) nelwc.lL.
ATM networks allow video info- ...~;on to be tr~n~mitted with variable bit-rate (VBR). This, in turn, allows st~ti~t~ multiplexing of data from a relatively 15 large number of users for tr~n~mi~sion over a single data channel.
In the ISO Moving Picture Experts Group (MPEG) audio-video coding standard (ISO 11172 Committee Draft of ISO-lEC/rrCl/SC29/WGll), a system multiplexing capability is provided for combining bit streams from several audio, video and/or auxiliary data sources. At a receiver, a system demultiplexer supplies 20 audio packets, including one or more cells, to audio decoders, video packets,including one or more cells, to video decoders and/or auxiliary packets, including one or more cells, to auxiliary decoders. So-called Pl.,sen~ation/Decode Time Stamps (PTS/DTS) in the data packets enable synchroni7~h~n of the audio and video to be displayed at the receiver. The MPEG standard also provides for a Systems 25 Time Clock (STC) of a predelt;llllined nominal frequency that, in principle, could be locked to a constant rate channel clock. Audio and video clocks could, in principle, also be locked to the STC.
However, in many variable bit-rate or packetized ch~nnel.~ there is no continuous channel clock for the receiver to lock to. Moreover, there may be "jitter 30 delay" in the hr~nsmi~sion of the data packets. Then, a receive STC must be derived from timing information that is tr~n~mitted from a remote receiver. In such arrangelllellls, it is illlp(jllant subst~nti~lly to elimin~te the possibility of data overflow and/or underflow of data buffers in the receiver.
Timing Rcco~ For Variable Bit-Rate Video On A~ hr~..o~ Transfer Mode (ATM) N~h.~. h~
Technical Field This invention relates to digital tr~n~mi~ion of video info..llAIion and, 5 more particularly, to timing recovery for variable bit-rate video in an ATM digital receiver.
Back~round of the In~..li~l.
Netw~,Ls are known which support variable bit-rate tr~n~mi~ion by parhtioning user data into a sequence of so-called "cells" and inpul~ing them 10 asynchronously to the netvork. One such n.,lwc,l~ is the Bro~db~n~ Inte~alt;dServices Digital Network (B-ISDN) and is referred to as an Asynchronous TransferMode (ATM) nelwc.lL.
ATM networks allow video info- ...~;on to be tr~n~mitted with variable bit-rate (VBR). This, in turn, allows st~ti~t~ multiplexing of data from a relatively 15 large number of users for tr~n~mi~sion over a single data channel.
In the ISO Moving Picture Experts Group (MPEG) audio-video coding standard (ISO 11172 Committee Draft of ISO-lEC/rrCl/SC29/WGll), a system multiplexing capability is provided for combining bit streams from several audio, video and/or auxiliary data sources. At a receiver, a system demultiplexer supplies 20 audio packets, including one or more cells, to audio decoders, video packets,including one or more cells, to video decoders and/or auxiliary packets, including one or more cells, to auxiliary decoders. So-called Pl.,sen~ation/Decode Time Stamps (PTS/DTS) in the data packets enable synchroni7~h~n of the audio and video to be displayed at the receiver. The MPEG standard also provides for a Systems 25 Time Clock (STC) of a predelt;llllined nominal frequency that, in principle, could be locked to a constant rate channel clock. Audio and video clocks could, in principle, also be locked to the STC.
However, in many variable bit-rate or packetized ch~nnel.~ there is no continuous channel clock for the receiver to lock to. Moreover, there may be "jitter 30 delay" in the hr~nsmi~sion of the data packets. Then, a receive STC must be derived from timing information that is tr~n~mitted from a remote receiver. In such arrangelllellls, it is illlp(jllant subst~nti~lly to elimin~te the possibility of data overflow and/or underflow of data buffers in the receiver.
-2- ~Q~73~g Another complication arises in arrangements in which the receiver video and audio clocks must be more stable than the STC.
Summary of the Invention The complications of timing recovery in an ATM receiver are overcome by employing a first phase lock loop including a phase comparator, filter, voltage controlled oscillator (VCO) and output counter to lock to systems clock reference (SCR) values which are asynchronously received from a remote ATM transmitter. The SCR
values represent the instantaneous values of a system timing clock (STC) at the instant of transmission of the asynchronous SCR values. In the receiver, the output counter is first set to the value of the initial received SCR value so that the derived STC is available for decoding data cells in the initial received packets. Then, so-called Presentation/Decode Time Stamps (PTS/DTS) included in the audio and video data are advantageously employed in conjunction with STC to display properly the received data.
In one embodiment, underflow of the receiver data buffers is alleviated by the addition of a "jitter-delay (Dj)" value which causes an extra accumulation of data in the data buffers prior to decoding. In the embodiment, dynamic tracking of the jitter-delay of the channel is obtained by monitoring the fullness of the data buffers and controllably adjusting the jitter-delay, accordingly.
In another exemplary embodiment, the stability of the decoder video timing is enhanced by employing an additional phase locked loop in a video display control which is supplied with a timing error signal. The additional phase locked loop includes a switch, filter, clipper and voltage controlled oscillator (VCO). The switch is enabled in response to output pulses from the VCO to supply the instantaneous error signal input to the filter for each so-called video presentation unit. The VCO has a very stable center frequency which variation is limited by clipping an input control voltage to some small voltage range. Output pulses from the VCO are employed to enable decoding of the presentation units. In one embodiment, a faster synchronization is provided at start-up by increasing, via control of the clipper, the allowable voltage range of the VCO
signal .
In accordance with one aspect of the invention there is provided apparatus for recovering timing in a receiver comprising: means for receiving an asynchronous digital signal including system clock reference (SCR) values, an initially received SCR
value being a start-up SCR value; means for extracting said SCR values from said 7 ~ 4 ~
-2a-received asynchronous digital signal; phase locked loop means having an input and an output for locking to said extracted SCR values being supplied to said input to generate a system timing clock (STC) signal at said output; means within said phase locked loop 5 means in circuit with said output and being directly supplied with said start-up SCR value for setting said STC signal at said output to said start-up SCR value upon start-up; and means for supplying said start-up SCR value directly to said means for setting.
Brief Description of the Drawing In the drawings:
FIG. 1 shows, in simplified block diagram form, details of a multiplexer unit employed in an ATM network transmitter;
_ 20973~J
FIG. 2 shows, in simplified block diagram form, details of a deml~ltiplexer unit employed in an ATM network ~cei~e., FIG. 3 shows, in simplified block diagram from, details of the display controls employed in the dem~ltirlexer unit of ~IG. 2;
S FIG. 4 is a flow chart illu~llaling the process of generating jitter-delay values in the compute jitter-delay unit of FIG. 2; and FIG. S shows, in simplified block diagram form, details of a time base corrector employed in the display control to enh~nre the stability of video timing.
Detailed Description At the outset, it is noted that for brevity and clarity of exposition, only a single channel of video and its coll~,s~,onding audio are illustrated in the multiplexer unit 100 of FIG. 1 and the dem~lltirlexer unit 200 of FIG. 2. In practice, it will be app~llt that a plurality of channels of video and coll~;,ponding audio will be employed to be multiplexed for tr~nsmi~sion in multiplexer unit 100 and a similar 15 plurality of ch~nn~l~ of video and coll~spollding audio will be obtain~d via demllltiplexer 200.
Specifir~lly, multiplexer unit 100, shown in FIG. 1 in simplified form, includes in the video channel insert PTS, DTS unit 101, video encoder 102 and video data buffer 103. The audio channel inr,l~ldes insert PTS unit 104, audio 20 encoder 105 and audio data buffer 106. Data from video data buffer 103 and audio data buffer 106 are supplied to ~y~;lllS encoder and SCR inserter 110. Systems time clock g~nel~lor 112 incl~ldes oscillator 114 and output counter 115. The output of counter 115 is the STC value which is supplied to insert PTS, STS unit 101, insert PTS unit 104 and ~y~cllls encoder and SCR inserter 110. It is noted that according 25 to the MPEG specifir~tinns~ the frequency for oscill~tor 114 shall be 90 kHz + 50 ppm. Ad-lition~lly, the frequency drift of oscill~tc?r 114 shall not exceed 250 mic~h.,.~/second. In this embodiment, counter 115 supplies a 33-bit STC value asan output that is inclr~ n~e-l once for each pulse supplied from oscill~t< rll4.The video input data is first supplied to insert PTS, DTS unit 101 which 30 inserts ~,se.~al;on Time Stamps (PTS) on some or all of the image l~,pl~,sent~tions, i.e., picture frames. If a PTS is inserted on a non-Bidirectionally Predicted Image Represent~fiQn (nonB-picture), then a Decoding Time Stamp (DTS) must also be inserted. For these image ~ ,sentations, PTS exceeds DTS (in picture periods) byone plus the number of bidirectional image l~;pl~senta~ions to be encoded. The 35 resulting "time stamped" video data then passes to video encoder 102 where it is encoded in known fashion. In turn, the encoded video data is supplied to video data 20973~
buffer 103 to await tr~n~mi~sion via :iy~enlS en~oder and SCR inserter 110.
The input audio is in the form of so-called Audio Access Units (AAU), which are supplied to insert PTS unit 104 where PTS values are inserted on some or all of the AAUs. Th~leaf~r, the AAUs are supplied to audio encoder 105 where 5 they are digitally encoded in well-known fashion and, thereafter, supplied to audio data buffer 106 to await tr~n~mi~ion via s~lcms encoder and SCR inserter 110.
The PTS/DTSs are employed to control the decoding and displaying of the audio and video data, in accordance with an aspect of the invention, in dem--ltiplexer unit 200 (FIG. 2). The decoding and displaying in response to the10 PTS/DTSs are such as to n~Ai~lAin synchronism and to avoid overflow and underflow of data buffers in demllltiplexer unit 200. Typically, the PTS/DTS values inserted by units 101 and 104 are equal to some constant value plus the in~lA--I;1neous STC
values from systems clock gene~atol 112.
Systems encoder and SCR inserter 110 forms packs and packets of data 15 and supplies them asynch~ ously to a data co~ atiQn~ sh~nnel Packs include packets from a plurality of video and audio encoders (not shown). Pack headers also contain SCR values that are the in~t~nt~nçous values of STC from systems time clock generator 112. According to MPEG specifi~ation~, packs must be tr~n~mittedat least every 0.7 second~ Additionally, the MPEG specifi~ti- n~ assume that the20 channel data rate is constant for the duration of the pack.
The packets in a pack contain video or audio data with the PTS/DTS
values, if any, moved to the packet header. Hence, for situations of more than one PTS/DTS per packet, all except the first are discarded.
Ri is a re~ ;se..~tiQn of the number of bits being tr~n~mitted to the data 25 channel during the coding of image leplese-ltation (picture) i. For a current image lep~ ion being tr~n~mitted, systems encoder and SCR inserter 110 supplies to video cl-~ode~ 102 the actual number of bits being tr~n~mitted For future image sen~lions, video encoder 102 supplies to systems encoder and SCR inserter 110 sllgg~st~d values for the number of bits to be tr~n~mitte~l for each image 30 I~;present~l;on Systems encoder and SCR inserter 110 then chooses the actual values according to prescribed principles which are known (see, for example, ourarticle entitled "Constraints on Variable Bit-Rate Video for ATM Nelwol~s", Document #AVC-56, CCITT STUDY GROUP XV WP XV/l, Experts Group for ATM Video Coding, May 21, 1991).
_ 2~97~L9 FIG. 2 shows, in simplified block diagram form, details of dem-lltiplexer unit 200. Specifir~lly, shown are system decoder and SCR extractor 201, which supplies video il~fc....~tion to be decoded to video data buffer 202 where it is stored awaiting display. Video data from buffer 202 is supplied to video display control 5 203 and, eventually, to video ~ecoder 204. Similarly, audio data is supplied from systems decoder and SCR extractor 201 to audio data buffer 205 where it is stored awaiting display. Audio data from buffer 205 is supplied to audio display control 206 and, eventually, to audio decoder 207. Systems decoder and SCR extractor 201also detects the received system clock reference (SCR) values and passes them to10 systems time clock ge~ alo 208 along with an enable signal which in-liriq~s when there is a valid SCR value being received and a start up value.
Systems time clock genel~lol 208 is a phase locked loop inchlding phase colllp~tor 210, filter 211, voltage controlled oscill~tor (VcO) 212 and output counter 214. The enable signal from ~s decoder and SCR extractor 201 is 15 supplied to enable filter 211 when a valid SCR value is received. The start up value is supplied to set counter 214 to the value of the initial SCR value being received, so that the initial audio or video data in the packets of the initial received pack may pr~,lly be displayed. The STC output from counter 214 is cOIllpalc;d in phase colllpalator 210 to the received SCR value. Filter 211 smooths the dirr~ ces 20 SCR-STC and gell~lalt;s a control voltage which is used to control the frequency of VCO 212.
In the absence of tr~n~mi~sion jitter delay, and as~ullling that the center frequency of VCO 212 is close to that of the oscillator 114 in multiplexer unit 100 (FIG. 1), the control signal output of filter 212 will eventually stabili~ to a small, 25 nearly COIlSklllt value. If the frequency of oscill~tor 114 (E~IG. 1) drifts slightly upward, then the SCR values will increase slightly, pro~ucing a corresponding increase in the control voltage being supplied to VCO 212 which, in turn, increases its fi~u~ . This, in turn, causes the STC values being supplied as an output from ~y~t~,llls time clock generator 208 to increase slightly, thus tracking the values of the 30 received SCR. Similarly, for a decrease in frequency of oscil1~or 114, the SCR and STC values in demultiplexer unit 200 track each other by also decreasing.
The amount of smoothing provided by filter 211, i.e., the time duration over which averaging occurs of the SCR-STC diLr~lellce signal, d~t~ ines how fast VCO 212 can respond. A small amount of smoothing by filter 211 can cause a 35 rapid alignment of STC and SCR. However, if audio and video clocks were also derived from VCO 212, such a rapid ~lipnm~nt could be de~;lll~,nlal to the audio and _ 2~973 ~9 video quality. In such an in~t~nre~ ~ignifif~ntly more smrothing by filter 211 may be n~ces~ry.
The gain of filter 211, or equivalently the input sensitivity of VCO 212, also has an effect on the frequency stability of the output pulses being supplied to 5 counter 214. If the gain is large, then a small dirrcl~nce between SCR and STC will cause a large frequency shift in the output of VCO 212. If the gain is too large, then VCO 212 may never stabilize. If the gain is too small, stable operation could occur even if SCR and STC were not close to each other.
The audio and video decoder timing is controlled via 10 P~csen~lion/Decode Time Stamps (PTStDTS) that are, as in~ t~.~ above, includcd in the le.pc.-live audio or video data. ~ssumin~ PTSs occur on every image fep.~;~n~;on the DTS (PTS, if no DTS) of the oldest image l~,plese .~ ;on storedin video data buffer 202 passes to video display control 203. Video display control 203 waits until the STC-Dj value increases to the value of the oldest DTS. It then 15 extracts the coded video data for the co l~;,poading image l~,~.cse .l~;Qn from video data buffer 202 and passes it to video decoder 204 for deco~ For each video image ..,p.~se~ ;on, input to decoder 204, the image l~ipl~ise ~ ;on is supplied as the video output for display. The video output may be the same image ,senli~lion as the input (e.g., for B-pictures), or it may be a stored previously 20 decoded picture (e.g., for nonB-pictures).
If an image l~plesen~lion does not have a DTS, then video display control 203 com~u~s an extr~rol~ted DTS value by simply adding the nomin~l picture duration to the DTS of the previous image l~,~lcse,-t~tion It is ~sllmPd that video decoder 204 always completes ~lecorling each image l~.esenl~l;Qn before the 25 next image l~plesent~tion is due to be decode-l When the oldest received (or e~ ~l~d) audio PTS equals STC-Dj, then a next audio access unit in audio data buffer 205 is supplied via audio display control 206 to audio decoder 207. The audio is imme~i~tely passed as the audio output corresponding to the video output to be displayed.
Details of the video and audio display controls are shown in FIG. 3 and described below.
If there is substantial transmi~sion jitter delay, then dem~lltiplexer 200 may not operate correctly. This results because filter 211 of sy~tellls time clock generator 208 must average over a much longer time interval than in a jitter free 35 situation. However, even if this is the case, a more serious problem is that the data arrival times may be considerably different than was assumed in multiplexer 100 20g~3~ '~
(FIG. 1). When such an occullcince happens, there is a possibility of overflow or und~lllo. ~ of the video and/or audio data buffers in demultiplexer 200.
Overflow of the data buffers can be readily avoided by increasing the buffer si~s beyond what was ~sllmed by the encoder in multiplexer 100.
5 Underflow of the data buffers can be alleviated by the ~d~lition of a jitter delay Dj, which causes an extra u~cllmlll~tion of data in the data buffers prior to decoding.
The additional stored data provides insurance against nn-1erfll~w. In fact, if bounds on jitter delay can be guaranteed, the possibility of underfiow of the data buffers can be substantially elimin~te~ by choosing sufficiently large buffers and a sufficiently 10 large value for Dj. This value of jitter delay Dj is then algebraically combined in subtractor 216 with STC to form STC-Dj. The amount of the delay for MPEG is given by Dj/90000 seconds. Then, the STC-Dj value is supplied to be utili~d in video display control 203 and audio display control 206 as described below.
Dynamic tracking of jitter delay for the channel is realized by 15 employing co,~ule jitter delay unit 217 which dyn~mir~lly generates jitter delay value Dj. The resulting dyn~mir~lly obtained value of Dj is supplied to a negative input of subtractor 216 to obtain the value STC-Dj. To subst~nti~lly elimin~te data buffer underflow, it is only necess~ry to insure that Dj is sufficiently large. Data buffer underflow may occur if data is late in arriving, i.e., STC>SCR. Thus, a 20 conservative choice of Dj is the largest measured value of STC-SCR. In actualoperation, Dj is very slowly increased to the desired value without much effect on audio and video quality.
In this embo liment~ the in~t~nt~n~ous fullness of video data buffer 202 is used to mrdul~t~ the value of jitter delay Dj. To this end, the fullness value of 25 video data buffer 202 is supplied to com~u~ jitter delay unit 217 along with the SCR- STC value output from phase colllp~ator 210.
The colll~ute jitter delay process is illu~llated in the flow chart of FIG.
4. S~ lly, at start of the process step 401 initi~li7Ps the Dj value to a nomin~l eAl~cb!~d jitter delay value. Step 402 then reads the fullness of video data buffer 202.
30 Step 403 tests to dele,ll~ine if the fullness value of video data buffer 202 is too large, infli~ ting too much jitter delay. If the test result in step 403 is YES, step 404 causes the value of Dj to be de~l~...f nled Th~ idrt.,~, control is passed to step 405. If the test result in step 403 is NO, step 406 tests to determine if the fullness of video data buffer 202 is too small. If the test result in step 406 is YES, step 407 causes the 35 value of Dj to be inc~ enled. Thereafter, control is passed to step 405. If the test result in step 406 is NO, step 405 reads the value of SCR-STC from phase 2~97~
compa~o~ 210. Step 408 causes the sign of the value obtained in step 405 to be ch~nge~l to obtain STC-SCR. Then, step 409 tests to detelllulle if the value of Djis less than the value of STC-SCR. If the test result in step 409 is YES, step 410 in~e.l~llts the value of Dj. If the test result in step 409 is NO, control is returned to 5 step 402.
The alllUUlltS of the inclcll.ellts and dew~ ellls in the process of FIG. 4 depend on how fast an adaptation process is desired and upon how much stability is required in the audio and video outputs. Such det~rmin~ti-n~ are left to be chosen by the imple...f ..IO~ of the system.
FIG. 3 shows, in simplified block diagram form, details of a display control unit which may be employed for either video display control 203 or audiodisplay control 206. It is noted that for audio display control 206 only PTS values are employed. Specifically shown is depacketizer and DTS (PTS) extractor 301 which strips off packet headers and detects the presence of DTS and/or PTS. (The15 first packet received is required to contain a PTS.) If PTSIDTS is detected (set DTS=PTS if no DTS), then switch 302 is set to the A position via a signal from depacketizer and DTS (PTS) exLIaclol 301, and the DTS value is supplied to the Ainput of switch 302. In turn, the supplied DTS value is supplied as an output byswitch 302 as DTSl to DTS (PTS) register 303.
After stripping off packet headers, depacketizer and DTS (PTS) extractor 301 passes the Ic.~ining packet data upon request to plese .L~Iion unit (PU) detector 304. For video display control 203, a PU is an image lc~-~,se.~t~l;ûn (i.e., picture). For audio display control 206, a PU is an Audio Access Unit (AAU).
At the start of every first PU (and no others), p.cs~ -t~l;on unit ~etector 304 outputs a 25 clock pulse that clocks DTS (PTS) register 303, thus causing its input DTSl to be read, stored and then supplied as an output as DTS2 to subtractor 305 and adder 306.
Then, p~s~ nt~ t;OI~ unit clet~ctor 304 waits.
STC - Dj values are supplied to SUbL a~ r 305, where they are COIllpdl~l with the stored DTS2 values. The resuldng dif~lcnce STC-Dj-DTS2 30 is supplied to zero ~ete~tor 307. When STC- Dj increases to a value equal to DTS2, enable next PU signal is supplied as an output to plesentatiûn unit detector 304 and the set B input to switch 302. This allows the next PU to be passed to the decoder.
For video display control 203, upon receiving this enable next PU signal present~tion unit detector 304 transfers the data for the next PU to video decoder 204. Similarly, 35 for audio display control 206, the enable next PU signal causes p.eserltadon unit detector 304 to transfer the data for the next PU to audio decoder 207. As indir~te-l, 20973Ji~
,., the enable next PU signal also causes switch 302 to be set to the B position. Ifduring the output of the PU depac~ti7~r and DTS (PTS) extractor 301 detects a PTS/DTS, it sets switch 302 to the A position as before. However, if no PTS/DTS is detected, switch 302 remains in the B position.
At the end of a PU data transfer by ~l~sel-t~tion unit detector 304, it outputs a clock pulse to the clock input of DTS (PTS) register 303, as before. If a new DTS value has arrived, it is read, as before, from the A input of switch 302 and supplied as a DTSl value to register 303 and appears as a DTS output value from register 303. However, if no new DTS value has arrived, then switch 302 still 10 remains in the B position. In this sit~1ation, an extrapolated DTS value is supplied from adder 306 and is supplied as a new DTSl value to register 303 and appears at an output thereof as DTS2. This extrapolated DTS value is obtained by adding viaadder 306 a constant nominal picture duration value in units of STC to the previous DTS2 value. For example, if the nomin~l picture frequency is 29.97 Hz and the STC
15 frequency is 90 kHz, then constant is 3003.
P~sell~ion unit detector 304 then waits until STC-Dj increases to this new value of DTS2, whereupon it receives an enable next PU signal (pulse) from zero detector 307, thus repeating the data output cycle.
In critical, high quality application~ le.luiliilg a very stable video timing, 20 the stability of ~y~lellls time clock generator 208 may not be sllfficient to acquire the desired quality level. For example, MPEG specifications call for the STC stability of + 50ppm while the industry standard for the tran~mi~sion video clock stability is +
3ppm. Consequently an arrangement of enh~ncing the video timing and demllltirlexer unit 200is nçeded To this end, FIG. S shows in simplified block diagram form, a time base correction circuit that can be employed in place of zero detector 307 in FIG. 3 to reali~ the desired quality of the video timing. Thus, as shown in FIG. 5, a timing error signal STC-Dj-DTS2 is supplied via switch 501, filter 502 and clipper 503 to voltage control oscillator (VCO) 504. F.lem~nt~ 501 through 504 form an 30 ad-lition~l phase lock loop. VCO 504 supplies as an output a train of short pulses at a nearly constant frequency. These output pulses are the enable next PU signals supplied to present~tion unit detector 304 (~;IG. 3) and are also supplied to switch 501.
VCO 504 has a very stable center frequency confolll~illg to Video 35 Industrial Standards, e.g., 20.9Hz. Moreover, the frequency variation of VCO 504 is limi~d, for example, + 3ppm during normal operation, by having its input control ~ 20973~
voltage clipped to some small range by clipper 503. During startup of the system, it may be desirable to provide for a faster synchroni7~tion by increasing the allowable control voltage range. This is reali_ed by supplying a startup signal to clipper 503 to allow for the wider voltage control range. As infiir~ted above, the enable next PU
5 signals (pulses) from VCO 504 are also employed to enable switch 501. Each such enable next PU signal causes switch 501 to close, thereby allowing the inst~nt~neous timing error signal input to be supplied to filter 502. Filter 502 averages the sampled timing error signals, typically over some time window, and passes the results toclipper 503. Judicious choices of filter duration and gain determine the stability and 10 tracking rate of the phase lock loop of the time base c~~ or shown in FIG. 5.
Summary of the Invention The complications of timing recovery in an ATM receiver are overcome by employing a first phase lock loop including a phase comparator, filter, voltage controlled oscillator (VCO) and output counter to lock to systems clock reference (SCR) values which are asynchronously received from a remote ATM transmitter. The SCR
values represent the instantaneous values of a system timing clock (STC) at the instant of transmission of the asynchronous SCR values. In the receiver, the output counter is first set to the value of the initial received SCR value so that the derived STC is available for decoding data cells in the initial received packets. Then, so-called Presentation/Decode Time Stamps (PTS/DTS) included in the audio and video data are advantageously employed in conjunction with STC to display properly the received data.
In one embodiment, underflow of the receiver data buffers is alleviated by the addition of a "jitter-delay (Dj)" value which causes an extra accumulation of data in the data buffers prior to decoding. In the embodiment, dynamic tracking of the jitter-delay of the channel is obtained by monitoring the fullness of the data buffers and controllably adjusting the jitter-delay, accordingly.
In another exemplary embodiment, the stability of the decoder video timing is enhanced by employing an additional phase locked loop in a video display control which is supplied with a timing error signal. The additional phase locked loop includes a switch, filter, clipper and voltage controlled oscillator (VCO). The switch is enabled in response to output pulses from the VCO to supply the instantaneous error signal input to the filter for each so-called video presentation unit. The VCO has a very stable center frequency which variation is limited by clipping an input control voltage to some small voltage range. Output pulses from the VCO are employed to enable decoding of the presentation units. In one embodiment, a faster synchronization is provided at start-up by increasing, via control of the clipper, the allowable voltage range of the VCO
signal .
In accordance with one aspect of the invention there is provided apparatus for recovering timing in a receiver comprising: means for receiving an asynchronous digital signal including system clock reference (SCR) values, an initially received SCR
value being a start-up SCR value; means for extracting said SCR values from said 7 ~ 4 ~
-2a-received asynchronous digital signal; phase locked loop means having an input and an output for locking to said extracted SCR values being supplied to said input to generate a system timing clock (STC) signal at said output; means within said phase locked loop 5 means in circuit with said output and being directly supplied with said start-up SCR value for setting said STC signal at said output to said start-up SCR value upon start-up; and means for supplying said start-up SCR value directly to said means for setting.
Brief Description of the Drawing In the drawings:
FIG. 1 shows, in simplified block diagram form, details of a multiplexer unit employed in an ATM network transmitter;
_ 20973~J
FIG. 2 shows, in simplified block diagram form, details of a deml~ltiplexer unit employed in an ATM network ~cei~e., FIG. 3 shows, in simplified block diagram from, details of the display controls employed in the dem~ltirlexer unit of ~IG. 2;
S FIG. 4 is a flow chart illu~llaling the process of generating jitter-delay values in the compute jitter-delay unit of FIG. 2; and FIG. S shows, in simplified block diagram form, details of a time base corrector employed in the display control to enh~nre the stability of video timing.
Detailed Description At the outset, it is noted that for brevity and clarity of exposition, only a single channel of video and its coll~,s~,onding audio are illustrated in the multiplexer unit 100 of FIG. 1 and the dem~lltirlexer unit 200 of FIG. 2. In practice, it will be app~llt that a plurality of channels of video and coll~;,ponding audio will be employed to be multiplexed for tr~nsmi~sion in multiplexer unit 100 and a similar 15 plurality of ch~nn~l~ of video and coll~spollding audio will be obtain~d via demllltiplexer 200.
Specifir~lly, multiplexer unit 100, shown in FIG. 1 in simplified form, includes in the video channel insert PTS, DTS unit 101, video encoder 102 and video data buffer 103. The audio channel inr,l~ldes insert PTS unit 104, audio 20 encoder 105 and audio data buffer 106. Data from video data buffer 103 and audio data buffer 106 are supplied to ~y~;lllS encoder and SCR inserter 110. Systems time clock g~nel~lor 112 incl~ldes oscillator 114 and output counter 115. The output of counter 115 is the STC value which is supplied to insert PTS, STS unit 101, insert PTS unit 104 and ~y~cllls encoder and SCR inserter 110. It is noted that according 25 to the MPEG specifir~tinns~ the frequency for oscill~tor 114 shall be 90 kHz + 50 ppm. Ad-lition~lly, the frequency drift of oscill~tc?r 114 shall not exceed 250 mic~h.,.~/second. In this embodiment, counter 115 supplies a 33-bit STC value asan output that is inclr~ n~e-l once for each pulse supplied from oscill~t< rll4.The video input data is first supplied to insert PTS, DTS unit 101 which 30 inserts ~,se.~al;on Time Stamps (PTS) on some or all of the image l~,pl~,sent~tions, i.e., picture frames. If a PTS is inserted on a non-Bidirectionally Predicted Image Represent~fiQn (nonB-picture), then a Decoding Time Stamp (DTS) must also be inserted. For these image ~ ,sentations, PTS exceeds DTS (in picture periods) byone plus the number of bidirectional image l~;pl~senta~ions to be encoded. The 35 resulting "time stamped" video data then passes to video encoder 102 where it is encoded in known fashion. In turn, the encoded video data is supplied to video data 20973~
buffer 103 to await tr~n~mi~sion via :iy~enlS en~oder and SCR inserter 110.
The input audio is in the form of so-called Audio Access Units (AAU), which are supplied to insert PTS unit 104 where PTS values are inserted on some or all of the AAUs. Th~leaf~r, the AAUs are supplied to audio encoder 105 where 5 they are digitally encoded in well-known fashion and, thereafter, supplied to audio data buffer 106 to await tr~n~mi~ion via s~lcms encoder and SCR inserter 110.
The PTS/DTSs are employed to control the decoding and displaying of the audio and video data, in accordance with an aspect of the invention, in dem--ltiplexer unit 200 (FIG. 2). The decoding and displaying in response to the10 PTS/DTSs are such as to n~Ai~lAin synchronism and to avoid overflow and underflow of data buffers in demllltiplexer unit 200. Typically, the PTS/DTS values inserted by units 101 and 104 are equal to some constant value plus the in~lA--I;1neous STC
values from systems clock gene~atol 112.
Systems encoder and SCR inserter 110 forms packs and packets of data 15 and supplies them asynch~ ously to a data co~ atiQn~ sh~nnel Packs include packets from a plurality of video and audio encoders (not shown). Pack headers also contain SCR values that are the in~t~nt~nçous values of STC from systems time clock generator 112. According to MPEG specifi~ation~, packs must be tr~n~mittedat least every 0.7 second~ Additionally, the MPEG specifi~ti- n~ assume that the20 channel data rate is constant for the duration of the pack.
The packets in a pack contain video or audio data with the PTS/DTS
values, if any, moved to the packet header. Hence, for situations of more than one PTS/DTS per packet, all except the first are discarded.
Ri is a re~ ;se..~tiQn of the number of bits being tr~n~mitted to the data 25 channel during the coding of image leplese-ltation (picture) i. For a current image lep~ ion being tr~n~mitted, systems encoder and SCR inserter 110 supplies to video cl-~ode~ 102 the actual number of bits being tr~n~mitted For future image sen~lions, video encoder 102 supplies to systems encoder and SCR inserter 110 sllgg~st~d values for the number of bits to be tr~n~mitte~l for each image 30 I~;present~l;on Systems encoder and SCR inserter 110 then chooses the actual values according to prescribed principles which are known (see, for example, ourarticle entitled "Constraints on Variable Bit-Rate Video for ATM Nelwol~s", Document #AVC-56, CCITT STUDY GROUP XV WP XV/l, Experts Group for ATM Video Coding, May 21, 1991).
_ 2~97~L9 FIG. 2 shows, in simplified block diagram form, details of dem-lltiplexer unit 200. Specifir~lly, shown are system decoder and SCR extractor 201, which supplies video il~fc....~tion to be decoded to video data buffer 202 where it is stored awaiting display. Video data from buffer 202 is supplied to video display control 5 203 and, eventually, to video ~ecoder 204. Similarly, audio data is supplied from systems decoder and SCR extractor 201 to audio data buffer 205 where it is stored awaiting display. Audio data from buffer 205 is supplied to audio display control 206 and, eventually, to audio decoder 207. Systems decoder and SCR extractor 201also detects the received system clock reference (SCR) values and passes them to10 systems time clock ge~ alo 208 along with an enable signal which in-liriq~s when there is a valid SCR value being received and a start up value.
Systems time clock genel~lol 208 is a phase locked loop inchlding phase colllp~tor 210, filter 211, voltage controlled oscill~tor (VcO) 212 and output counter 214. The enable signal from ~s decoder and SCR extractor 201 is 15 supplied to enable filter 211 when a valid SCR value is received. The start up value is supplied to set counter 214 to the value of the initial SCR value being received, so that the initial audio or video data in the packets of the initial received pack may pr~,lly be displayed. The STC output from counter 214 is cOIllpalc;d in phase colllpalator 210 to the received SCR value. Filter 211 smooths the dirr~ ces 20 SCR-STC and gell~lalt;s a control voltage which is used to control the frequency of VCO 212.
In the absence of tr~n~mi~sion jitter delay, and as~ullling that the center frequency of VCO 212 is close to that of the oscillator 114 in multiplexer unit 100 (FIG. 1), the control signal output of filter 212 will eventually stabili~ to a small, 25 nearly COIlSklllt value. If the frequency of oscill~tor 114 (E~IG. 1) drifts slightly upward, then the SCR values will increase slightly, pro~ucing a corresponding increase in the control voltage being supplied to VCO 212 which, in turn, increases its fi~u~ . This, in turn, causes the STC values being supplied as an output from ~y~t~,llls time clock generator 208 to increase slightly, thus tracking the values of the 30 received SCR. Similarly, for a decrease in frequency of oscil1~or 114, the SCR and STC values in demultiplexer unit 200 track each other by also decreasing.
The amount of smoothing provided by filter 211, i.e., the time duration over which averaging occurs of the SCR-STC diLr~lellce signal, d~t~ ines how fast VCO 212 can respond. A small amount of smoothing by filter 211 can cause a 35 rapid alignment of STC and SCR. However, if audio and video clocks were also derived from VCO 212, such a rapid ~lipnm~nt could be de~;lll~,nlal to the audio and _ 2~973 ~9 video quality. In such an in~t~nre~ ~ignifif~ntly more smrothing by filter 211 may be n~ces~ry.
The gain of filter 211, or equivalently the input sensitivity of VCO 212, also has an effect on the frequency stability of the output pulses being supplied to 5 counter 214. If the gain is large, then a small dirrcl~nce between SCR and STC will cause a large frequency shift in the output of VCO 212. If the gain is too large, then VCO 212 may never stabilize. If the gain is too small, stable operation could occur even if SCR and STC were not close to each other.
The audio and video decoder timing is controlled via 10 P~csen~lion/Decode Time Stamps (PTStDTS) that are, as in~ t~.~ above, includcd in the le.pc.-live audio or video data. ~ssumin~ PTSs occur on every image fep.~;~n~;on the DTS (PTS, if no DTS) of the oldest image l~,plese .~ ;on storedin video data buffer 202 passes to video display control 203. Video display control 203 waits until the STC-Dj value increases to the value of the oldest DTS. It then 15 extracts the coded video data for the co l~;,poading image l~,~.cse .l~;Qn from video data buffer 202 and passes it to video decoder 204 for deco~ For each video image ..,p.~se~ ;on, input to decoder 204, the image l~ipl~ise ~ ;on is supplied as the video output for display. The video output may be the same image ,senli~lion as the input (e.g., for B-pictures), or it may be a stored previously 20 decoded picture (e.g., for nonB-pictures).
If an image l~plesen~lion does not have a DTS, then video display control 203 com~u~s an extr~rol~ted DTS value by simply adding the nomin~l picture duration to the DTS of the previous image l~,~lcse,-t~tion It is ~sllmPd that video decoder 204 always completes ~lecorling each image l~.esenl~l;Qn before the 25 next image l~plesent~tion is due to be decode-l When the oldest received (or e~ ~l~d) audio PTS equals STC-Dj, then a next audio access unit in audio data buffer 205 is supplied via audio display control 206 to audio decoder 207. The audio is imme~i~tely passed as the audio output corresponding to the video output to be displayed.
Details of the video and audio display controls are shown in FIG. 3 and described below.
If there is substantial transmi~sion jitter delay, then dem~lltiplexer 200 may not operate correctly. This results because filter 211 of sy~tellls time clock generator 208 must average over a much longer time interval than in a jitter free 35 situation. However, even if this is the case, a more serious problem is that the data arrival times may be considerably different than was assumed in multiplexer 100 20g~3~ '~
(FIG. 1). When such an occullcince happens, there is a possibility of overflow or und~lllo. ~ of the video and/or audio data buffers in demultiplexer 200.
Overflow of the data buffers can be readily avoided by increasing the buffer si~s beyond what was ~sllmed by the encoder in multiplexer 100.
5 Underflow of the data buffers can be alleviated by the ~d~lition of a jitter delay Dj, which causes an extra u~cllmlll~tion of data in the data buffers prior to decoding.
The additional stored data provides insurance against nn-1erfll~w. In fact, if bounds on jitter delay can be guaranteed, the possibility of underfiow of the data buffers can be substantially elimin~te~ by choosing sufficiently large buffers and a sufficiently 10 large value for Dj. This value of jitter delay Dj is then algebraically combined in subtractor 216 with STC to form STC-Dj. The amount of the delay for MPEG is given by Dj/90000 seconds. Then, the STC-Dj value is supplied to be utili~d in video display control 203 and audio display control 206 as described below.
Dynamic tracking of jitter delay for the channel is realized by 15 employing co,~ule jitter delay unit 217 which dyn~mir~lly generates jitter delay value Dj. The resulting dyn~mir~lly obtained value of Dj is supplied to a negative input of subtractor 216 to obtain the value STC-Dj. To subst~nti~lly elimin~te data buffer underflow, it is only necess~ry to insure that Dj is sufficiently large. Data buffer underflow may occur if data is late in arriving, i.e., STC>SCR. Thus, a 20 conservative choice of Dj is the largest measured value of STC-SCR. In actualoperation, Dj is very slowly increased to the desired value without much effect on audio and video quality.
In this embo liment~ the in~t~nt~n~ous fullness of video data buffer 202 is used to mrdul~t~ the value of jitter delay Dj. To this end, the fullness value of 25 video data buffer 202 is supplied to com~u~ jitter delay unit 217 along with the SCR- STC value output from phase colllp~ator 210.
The colll~ute jitter delay process is illu~llated in the flow chart of FIG.
4. S~ lly, at start of the process step 401 initi~li7Ps the Dj value to a nomin~l eAl~cb!~d jitter delay value. Step 402 then reads the fullness of video data buffer 202.
30 Step 403 tests to dele,ll~ine if the fullness value of video data buffer 202 is too large, infli~ ting too much jitter delay. If the test result in step 403 is YES, step 404 causes the value of Dj to be de~l~...f nled Th~ idrt.,~, control is passed to step 405. If the test result in step 403 is NO, step 406 tests to determine if the fullness of video data buffer 202 is too small. If the test result in step 406 is YES, step 407 causes the 35 value of Dj to be inc~ enled. Thereafter, control is passed to step 405. If the test result in step 406 is NO, step 405 reads the value of SCR-STC from phase 2~97~
compa~o~ 210. Step 408 causes the sign of the value obtained in step 405 to be ch~nge~l to obtain STC-SCR. Then, step 409 tests to detelllulle if the value of Djis less than the value of STC-SCR. If the test result in step 409 is YES, step 410 in~e.l~llts the value of Dj. If the test result in step 409 is NO, control is returned to 5 step 402.
The alllUUlltS of the inclcll.ellts and dew~ ellls in the process of FIG. 4 depend on how fast an adaptation process is desired and upon how much stability is required in the audio and video outputs. Such det~rmin~ti-n~ are left to be chosen by the imple...f ..IO~ of the system.
FIG. 3 shows, in simplified block diagram form, details of a display control unit which may be employed for either video display control 203 or audiodisplay control 206. It is noted that for audio display control 206 only PTS values are employed. Specifically shown is depacketizer and DTS (PTS) extractor 301 which strips off packet headers and detects the presence of DTS and/or PTS. (The15 first packet received is required to contain a PTS.) If PTSIDTS is detected (set DTS=PTS if no DTS), then switch 302 is set to the A position via a signal from depacketizer and DTS (PTS) exLIaclol 301, and the DTS value is supplied to the Ainput of switch 302. In turn, the supplied DTS value is supplied as an output byswitch 302 as DTSl to DTS (PTS) register 303.
After stripping off packet headers, depacketizer and DTS (PTS) extractor 301 passes the Ic.~ining packet data upon request to plese .L~Iion unit (PU) detector 304. For video display control 203, a PU is an image lc~-~,se.~t~l;ûn (i.e., picture). For audio display control 206, a PU is an Audio Access Unit (AAU).
At the start of every first PU (and no others), p.cs~ -t~l;on unit ~etector 304 outputs a 25 clock pulse that clocks DTS (PTS) register 303, thus causing its input DTSl to be read, stored and then supplied as an output as DTS2 to subtractor 305 and adder 306.
Then, p~s~ nt~ t;OI~ unit clet~ctor 304 waits.
STC - Dj values are supplied to SUbL a~ r 305, where they are COIllpdl~l with the stored DTS2 values. The resuldng dif~lcnce STC-Dj-DTS2 30 is supplied to zero ~ete~tor 307. When STC- Dj increases to a value equal to DTS2, enable next PU signal is supplied as an output to plesentatiûn unit detector 304 and the set B input to switch 302. This allows the next PU to be passed to the decoder.
For video display control 203, upon receiving this enable next PU signal present~tion unit detector 304 transfers the data for the next PU to video decoder 204. Similarly, 35 for audio display control 206, the enable next PU signal causes p.eserltadon unit detector 304 to transfer the data for the next PU to audio decoder 207. As indir~te-l, 20973Ji~
,., the enable next PU signal also causes switch 302 to be set to the B position. Ifduring the output of the PU depac~ti7~r and DTS (PTS) extractor 301 detects a PTS/DTS, it sets switch 302 to the A position as before. However, if no PTS/DTS is detected, switch 302 remains in the B position.
At the end of a PU data transfer by ~l~sel-t~tion unit detector 304, it outputs a clock pulse to the clock input of DTS (PTS) register 303, as before. If a new DTS value has arrived, it is read, as before, from the A input of switch 302 and supplied as a DTSl value to register 303 and appears as a DTS output value from register 303. However, if no new DTS value has arrived, then switch 302 still 10 remains in the B position. In this sit~1ation, an extrapolated DTS value is supplied from adder 306 and is supplied as a new DTSl value to register 303 and appears at an output thereof as DTS2. This extrapolated DTS value is obtained by adding viaadder 306 a constant nominal picture duration value in units of STC to the previous DTS2 value. For example, if the nomin~l picture frequency is 29.97 Hz and the STC
15 frequency is 90 kHz, then constant is 3003.
P~sell~ion unit detector 304 then waits until STC-Dj increases to this new value of DTS2, whereupon it receives an enable next PU signal (pulse) from zero detector 307, thus repeating the data output cycle.
In critical, high quality application~ le.luiliilg a very stable video timing, 20 the stability of ~y~lellls time clock generator 208 may not be sllfficient to acquire the desired quality level. For example, MPEG specifications call for the STC stability of + 50ppm while the industry standard for the tran~mi~sion video clock stability is +
3ppm. Consequently an arrangement of enh~ncing the video timing and demllltirlexer unit 200is nçeded To this end, FIG. S shows in simplified block diagram form, a time base correction circuit that can be employed in place of zero detector 307 in FIG. 3 to reali~ the desired quality of the video timing. Thus, as shown in FIG. 5, a timing error signal STC-Dj-DTS2 is supplied via switch 501, filter 502 and clipper 503 to voltage control oscillator (VCO) 504. F.lem~nt~ 501 through 504 form an 30 ad-lition~l phase lock loop. VCO 504 supplies as an output a train of short pulses at a nearly constant frequency. These output pulses are the enable next PU signals supplied to present~tion unit detector 304 (~;IG. 3) and are also supplied to switch 501.
VCO 504 has a very stable center frequency confolll~illg to Video 35 Industrial Standards, e.g., 20.9Hz. Moreover, the frequency variation of VCO 504 is limi~d, for example, + 3ppm during normal operation, by having its input control ~ 20973~
voltage clipped to some small range by clipper 503. During startup of the system, it may be desirable to provide for a faster synchroni7~tion by increasing the allowable control voltage range. This is reali_ed by supplying a startup signal to clipper 503 to allow for the wider voltage control range. As infiir~ted above, the enable next PU
5 signals (pulses) from VCO 504 are also employed to enable switch 501. Each such enable next PU signal causes switch 501 to close, thereby allowing the inst~nt~neous timing error signal input to be supplied to filter 502. Filter 502 averages the sampled timing error signals, typically over some time window, and passes the results toclipper 503. Judicious choices of filter duration and gain determine the stability and 10 tracking rate of the phase lock loop of the time base c~~ or shown in FIG. 5.
Claims (16)
1. Apparatus for recovering timing in a receiver comprising:
means for receiving an asynchronous digital signal including system clock reference (SCR) values, an initially received SCR value being a start-up SCR value;
means for extracting said SCR values from said received asynchronous digital signal;
phase locked loop means having an input and an output for locking to said extracted SCR values being supplied to said input to generate a system timing clock (STC) signal at said output;
means within said phase locked loop means in circuit with said output and being directly supplied with said start-up SCR value for setting said STC signal at said output to said start-up SCR value upon start-up; and means for supplying said start-up SCR value directly to said means for setting.
means for receiving an asynchronous digital signal including system clock reference (SCR) values, an initially received SCR value being a start-up SCR value;
means for extracting said SCR values from said received asynchronous digital signal;
phase locked loop means having an input and an output for locking to said extracted SCR values being supplied to said input to generate a system timing clock (STC) signal at said output;
means within said phase locked loop means in circuit with said output and being directly supplied with said start-up SCR value for setting said STC signal at said output to said start-up SCR value upon start-up; and means for supplying said start-up SCR value directly to said means for setting.
2. The apparatus as defined in claim 1 wherein said means for setting comprises a counter which is set to said start-up SCR value at start up for supplying said STC signal at said output.
3. The apparatus as defined in claim 1 wherein said phase locked loop means includes means supplied with said extracted SCR values and said STC signal for generating a phase error signal, and the apparatus further including buffer means for storing data from said received asynchronous signal, means for obtaining a fullness representation of said buffer means, means supplied with said phase error signal and said fullness representation for dynamically generating a jitter delay (D j) value, and means for algebraically combining said D j value with said STC signal to generate a modified version of the STC signal.
4. Apparatus for recovering timing in a receiver comprising:
means for receiving an asynchronous digital signal including system clock reference (SCR) values, an initially received SCR value being a start-up SCR value;
means for extracting said SCR values from said received asynchronous digital signal;
phase locked loop means having an input and an output for locking to said extracted SCR values being supplied to said input to generate a system timing clock (STC) signal at said output, said phase locked loop means including means supplied with said extracted SCR values and said STC signal for generating a phase error signal and means in circuit with said output and being directly supplied with said start-up SCR value for setting said STC signal at said outputto said start-up SCR value upon start-up;
buffer means for storing data from said received asynchronous signal;
means for obtaining a fullness representation of the amount of data stored in said buffer means;
means supplied with said phase error signal and said fullness representation for dynamically generating a jitter delay (D j) value; and means for algebraically subtracting said D j value from said STC signal to generate a modified representation of said system timing clock signal (STC-D j).
means for receiving an asynchronous digital signal including system clock reference (SCR) values, an initially received SCR value being a start-up SCR value;
means for extracting said SCR values from said received asynchronous digital signal;
phase locked loop means having an input and an output for locking to said extracted SCR values being supplied to said input to generate a system timing clock (STC) signal at said output, said phase locked loop means including means supplied with said extracted SCR values and said STC signal for generating a phase error signal and means in circuit with said output and being directly supplied with said start-up SCR value for setting said STC signal at said outputto said start-up SCR value upon start-up;
buffer means for storing data from said received asynchronous signal;
means for obtaining a fullness representation of the amount of data stored in said buffer means;
means supplied with said phase error signal and said fullness representation for dynamically generating a jitter delay (D j) value; and means for algebraically subtracting said D j value from said STC signal to generate a modified representation of said system timing clock signal (STC-D j).
5. The apparatus as defined in claim 4 wherein said modified representation of said system timing clock signal is utilized to control displaying video information received in said asynchronously received signal.
6. The apparatus as defined in claim 5 wherein said modified representation of said system timing signal is further utilized to play out audio information received in said asynchronously received signal.
7. The apparatus as defined in claim 6 wherein said buffer means comprises a video data buffer and said fullness representation is of the amount of video data stored in said video data buffer.
8. The apparatus as defined in claim 7 wherein the receiver further includes video display control means for controlling supplying video data presentation units stored in said video data buffer to a video decoder.
9. The apparatus as defined in claim 8 wherein the receiver further includes an audio data buffer and audio display control means for controlling supplying audio data representation units stored in said audio data buffer to an audio decoder.
10. The apparatus as defined in claim 9 wherein said video display control means is responsive to said modified representation of said system timing clock signal and to prescribed time stamp values received with said video data in saidasynchronously received signal for controlling the supplying of said video representation units to said video decoder.
11. The apparatus as defined in claim 10 wherein said audio display control means is responsive to said modified representation of said system timing clock signal and to prescribed time stamp values received with said audio data in saidasynchronously received signal for controlling the supplying of said audio representation units to said audio decoder.
12. The apparatus as defined in claim 10 wherein said video display control means includes time based corrector means for enhancing the transmission timing of said video representation units being supplied to said video decoder.
13. The apparatus as defined in claim 12 wherein said time based corrector means includes second phase locked loop means responsive to a control signal representative of an algebraic combination of said modified system timing clock signal and a decoding time stamp value corresponding to the video presentation unit to be supplied to said video decoder.
14. Apparatus for recovering timing in a receiver comprising:
means for receiving an asynchronous digital signal including system clock reference (SCR) values;
means for extracting said SCR values from said received asynchronous digital signal;
phase locked loop means having an input and an output for locking to said extracted SCR values being supplied to said input to generate a system timing clock (STC) signal at said output, said phase locked loop means including means supplied with said extracted SCR values and said STC signal for generating a phase error signal;
buffer means for storing data from said received asynchronous signal;
means for obtaining a fullness representation of the amount of data stored in said buffer means;
means supplied with said phase error signal and said fullness representation for dynamically generating a jitter delay (D j) value; and means for algebraically subtracting said D j value from said STC signal to generate a modified representation of said system timing clock signal (STC-D j).
means for receiving an asynchronous digital signal including system clock reference (SCR) values;
means for extracting said SCR values from said received asynchronous digital signal;
phase locked loop means having an input and an output for locking to said extracted SCR values being supplied to said input to generate a system timing clock (STC) signal at said output, said phase locked loop means including means supplied with said extracted SCR values and said STC signal for generating a phase error signal;
buffer means for storing data from said received asynchronous signal;
means for obtaining a fullness representation of the amount of data stored in said buffer means;
means supplied with said phase error signal and said fullness representation for dynamically generating a jitter delay (D j) value; and means for algebraically subtracting said D j value from said STC signal to generate a modified representation of said system timing clock signal (STC-D j).
15. The apparatus as defined in claim 14 wherein said modified representation of said system timing signal is utilized to control displaying video information received in said asynchronously received signal.
16. The apparatus as defined in claim 15 wherein said modified representation of said system timing signal is further utilized to play out audio information received in said asynchronously received signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US907,943 | 1986-09-10 | ||
| US07/907,943 US5287182A (en) | 1992-07-02 | 1992-07-02 | Timing recovery for variable bit-rate video on asynchronous transfer mode (ATM) networks |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2097349A1 CA2097349A1 (en) | 1994-01-03 |
| CA2097349C true CA2097349C (en) | 1999-01-19 |
Family
ID=25424899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002097349A Expired - Lifetime CA2097349C (en) | 1992-07-02 | 1993-05-31 | Timing recovery for variable bit-rate video on asynchronous transfer mode (atm) networks |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5287182A (en) |
| EP (1) | EP0577329A3 (en) |
| JP (1) | JP3053717B2 (en) |
| CA (1) | CA2097349C (en) |
Families Citing this family (155)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB9405914D0 (en) * | 1994-03-24 | 1994-05-11 | Discovision Ass | Video decompression |
| US5019826A (en) * | 1988-09-29 | 1991-05-28 | Hughes Aircraft Company | Coherent radar using recirculating delay line |
| US5475421A (en) * | 1992-06-03 | 1995-12-12 | Digital Equipment Corporation | Video data scaling for video teleconferencing workstations communicating by digital data network |
| US6034674A (en) * | 1992-06-30 | 2000-03-07 | Discovision Associates | Buffer manager |
| US5486864A (en) * | 1993-05-13 | 1996-01-23 | Rca Thomson Licensing Corporation | Differential time code method and apparatus as for a compressed video signal |
| US5381181A (en) * | 1993-05-13 | 1995-01-10 | Thomson Consumer Electronics, Inc. | Clock recovery apparatus as for a compressed video signal |
| JP3427416B2 (en) * | 1993-05-25 | 2003-07-14 | ソニー株式会社 | Multiplexed data separation apparatus and method |
| US5561466A (en) * | 1993-06-23 | 1996-10-01 | Nec Corporation | Video and audio data multiplexing into ATM cells with no dummy cell used and ATM cell demultiplexing |
| US5835792A (en) * | 1993-06-24 | 1998-11-10 | Discovision Associates | Token-based adaptive video processing arrangement |
| US5861894A (en) | 1993-06-24 | 1999-01-19 | Discovision Associates | Buffer manager |
| US5442390A (en) * | 1993-07-07 | 1995-08-15 | Digital Equipment Corporation | Video on demand with memory accessing and or like functions |
| JP3516450B2 (en) * | 1993-07-12 | 2004-04-05 | ソニー株式会社 | Bitstream transmission method and transmission system |
| JP3546889B2 (en) * | 1993-08-24 | 2004-07-28 | ソニー株式会社 | Multiplexing transmission method and apparatus |
| US5430485A (en) * | 1993-09-30 | 1995-07-04 | Thomson Consumer Electronics, Inc. | Audio/video synchronization in a digital transmission system |
| US5467139A (en) * | 1993-09-30 | 1995-11-14 | Thomson Consumer Electronics, Inc. | Muting apparatus for a compressed audio/video signal receiver |
| DE69430710T2 (en) * | 1993-12-24 | 2003-01-30 | Nippon Telegraph & Telephone | Device for retrieving image data |
| KR960008470B1 (en) * | 1994-01-18 | 1996-06-26 | Daewoo Electronics Co Ltd | Apparatus for transferring bit stream data adaptively in the moving picture |
| JPH07264214A (en) * | 1994-02-07 | 1995-10-13 | Fujitsu Ltd | Interface device |
| US5612981A (en) * | 1994-02-15 | 1997-03-18 | Philips Electronics North America Corporation | Apparatus and methods for improving timing recovery of a system clock |
| JP3197766B2 (en) * | 1994-02-17 | 2001-08-13 | 三洋電機株式会社 | MPEG audio decoder, MPEG video decoder and MPEG system decoder |
| CA2140850C (en) * | 1994-02-24 | 1999-09-21 | Howard Paul Katseff | Networked system for display of multimedia presentations |
| JP3762430B2 (en) * | 1994-02-25 | 2006-04-05 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Method and apparatus for transmitting data packets |
| JPH07264144A (en) * | 1994-03-16 | 1995-10-13 | Toshiba Corp | Signal compression coder and compression signal decoder |
| US5566174A (en) * | 1994-04-08 | 1996-10-15 | Philips Electronics North America Corporation | MPEG information signal conversion system |
| US5534937A (en) * | 1994-04-14 | 1996-07-09 | Motorola, Inc. | Minimum-delay jitter smoothing device and method for packet video communications |
| GB9408574D0 (en) * | 1994-04-29 | 1994-06-22 | Newbridge Networks Corp | Atm switching system |
| CA2146801C (en) * | 1994-05-27 | 1999-11-02 | Barin Geoffry Haskell | Timing recovery for variable bit-rate video on asynchronous transfer mode (atm) networks |
| DE4422015C1 (en) * | 1994-06-16 | 1995-08-03 | Bosch Gmbh Robert | Transmission and reception of digital audio with image, speech or text |
| DE4422615A1 (en) * | 1994-06-28 | 1996-01-04 | Philips Patentverwaltung | Image display device |
| DE69532228T2 (en) * | 1994-07-05 | 2004-09-16 | Koninklijke Philips Electronics N.V. | SIGNAL PROCESSING SYSTEM |
| KR100373942B1 (en) * | 1994-07-05 | 2003-05-12 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | Siganl processing system |
| US5541961A (en) * | 1994-08-15 | 1996-07-30 | At&T Corp. | Digitally controlled high resolution hybrid phase synthesizer |
| GB9512068D0 (en) * | 1995-06-14 | 1995-08-09 | Thomson Consumer Electronics | Bus and interface system for consumer digital equipment |
| US5583569A (en) * | 1994-08-19 | 1996-12-10 | Intel Corporation | Video camera having asynchronous digital output including header data |
| US5559999A (en) * | 1994-09-09 | 1996-09-24 | Lsi Logic Corporation | MPEG decoding system including tag list for associating presentation time stamps with encoded data units |
| NL9401525A (en) * | 1994-09-21 | 1996-05-01 | Nederland Ptt | Clock recovery for ATM receiver. |
| US5815634A (en) * | 1994-09-30 | 1998-09-29 | Cirrus Logic, Inc. | Stream synchronization method and apparatus for MPEG playback system |
| US5598352A (en) * | 1994-09-30 | 1997-01-28 | Cirrus Logic, Inc. | Method and apparatus for audio and video synchronizing in MPEG playback systems |
| US5594660A (en) * | 1994-09-30 | 1997-01-14 | Cirrus Logic, Inc. | Programmable audio-video synchronization method and apparatus for multimedia systems |
| CA2157066C (en) * | 1994-10-21 | 1999-09-21 | Nelson Botsford Iii | Method for controlling a compressed data buffer |
| SG34287A1 (en) * | 1994-10-28 | 1996-12-06 | Hitachi Ltd | Input-output circuit recording apparatus and reproduction apparatus for digital video signal |
| EP0710033A3 (en) * | 1994-10-28 | 1999-06-09 | Matsushita Electric Industrial Co., Ltd. | MPEG video decoder having a high bandwidth memory |
| JP3058028B2 (en) * | 1994-10-31 | 2000-07-04 | 三菱電機株式会社 | Image encoded data re-encoding device |
| US5901149A (en) * | 1994-11-09 | 1999-05-04 | Sony Corporation | Decode and encode system |
| US5517495A (en) * | 1994-12-06 | 1996-05-14 | At&T Corp. | Fair prioritized scheduling in an input-buffered switch |
| US5771075A (en) * | 1994-12-08 | 1998-06-23 | Lg Electronics Inc. | Audio/video synchronizer |
| KR0137701B1 (en) * | 1994-12-13 | 1998-05-15 | 양승택 | Pes packetizing apparatus of mpeg-2 system |
| US5526353A (en) * | 1994-12-20 | 1996-06-11 | Henley; Arthur | System and method for communication of audio data over a packet-based network |
| KR0136460B1 (en) * | 1994-12-24 | 1998-05-15 | 이헌조 | Data interleaving method for a variable bit rate coding device |
| DE69517966T2 (en) * | 1994-12-28 | 2001-02-15 | Koninkl Philips Electronics Nv | BUFFER MANAGEMENT IN COMPRESSION SYSTEMS WITH VARIABLE BITRATE |
| JP3149328B2 (en) * | 1995-01-09 | 2001-03-26 | 松下電器産業株式会社 | Transmitter and receiver |
| US5543853A (en) * | 1995-01-19 | 1996-08-06 | At&T Corp. | Encoder/decoder buffer control for variable bit-rate channel |
| US5621772A (en) * | 1995-01-20 | 1997-04-15 | Lsi Logic Corporation | Hysteretic synchronization system for MPEG audio frame decoder |
| US5533021A (en) * | 1995-02-03 | 1996-07-02 | International Business Machines Corporation | Apparatus and method for segmentation and time synchronization of the transmission of multimedia data |
| US5652749A (en) * | 1995-02-03 | 1997-07-29 | International Business Machines Corporation | Apparatus and method for segmentation and time synchronization of the transmission of a multiple program multimedia data stream |
| JP2964899B2 (en) * | 1995-02-28 | 1999-10-18 | 日本電気株式会社 | Encoding and decoding frequency synchronization method |
| JP4297518B2 (en) * | 1995-03-06 | 2009-07-15 | 沖電気工業株式会社 | Audio / video decoder |
| US5563884A (en) * | 1995-03-27 | 1996-10-08 | Zenith Electronics Corporation | Reducing multiplex jitter in an ATM/MPEG system |
| JPH08288880A (en) * | 1995-04-14 | 1996-11-01 | Toshiba Corp | Pll circuit and pll system |
| DE69623170T2 (en) | 1995-04-27 | 2003-05-15 | Hitachi Ltd | Method and device for receiving and / or reproducing digital signals |
| US5751694A (en) * | 1995-05-22 | 1998-05-12 | Sony Corporation | Methods and apparatus for synchronizing temporally related data streams |
| GB9511551D0 (en) * | 1995-06-07 | 1995-08-02 | Discovision Ass | Signal processing system |
| US6119213A (en) * | 1995-06-07 | 2000-09-12 | Discovision Associates | Method for addressing data having variable data width using a fixed number of bits for address and width defining fields |
| FR2735320B1 (en) * | 1995-06-09 | 1997-09-05 | Sgs Thomson Microelectronics | METHOD AND DEVICE FOR SYNCHRONIZING VISUAL INFORMATION WITH AUDIO INFORMATION |
| US5920572A (en) * | 1995-06-30 | 1999-07-06 | Divicom Inc. | Transport stream decoder/demultiplexer for hierarchically organized audio-video streams |
| FR2737367B1 (en) * | 1995-07-28 | 1997-10-17 | Thomson Multimedia Sa | METHOD AND DEVICE FOR SYNCHRONIZING CLOCK OF DIGITAL ENCODERS AND DECODERS |
| US6118581A (en) * | 1995-09-15 | 2000-09-12 | Accumed International, Inc. | Multifunctional control unit for a microscope |
| US5930732A (en) * | 1995-09-15 | 1999-07-27 | Accumed International, Inc. | System for simplifying the implementation of specified functions |
| US6091842A (en) * | 1996-10-25 | 2000-07-18 | Accumed International, Inc. | Cytological specimen analysis system with slide mapping and generation of viewing path information |
| US5690892A (en) * | 1995-09-15 | 1997-11-25 | Accumed, Inc. | Cassette for use with automated specimen handling system |
| US5963368A (en) * | 1995-09-15 | 1999-10-05 | Accumed International, Inc. | Specimen management system |
| KR0175395B1 (en) * | 1995-10-24 | 1999-03-20 | 김광호 | Stc error detect circuit for mpeg system decoder |
| KR100209880B1 (en) * | 1995-10-30 | 1999-07-15 | 윤종용 | System clock recovery apparatus in mpeg-2 image data decoder |
| US5699392A (en) * | 1995-11-06 | 1997-12-16 | Stellar One Corporation | Method and system for the recovery of an encoder clock from an MPEG-2 transport stream |
| US5877812A (en) * | 1995-11-21 | 1999-03-02 | Imedia Corporation | Method and apparatus for increasing channel utilization for digital video transmission |
| US5862140A (en) * | 1995-11-21 | 1999-01-19 | Imedia Corporation | Method and apparatus for multiplexing video programs for improved channel utilization |
| JPH09149411A (en) * | 1995-11-24 | 1997-06-06 | Ekushingu:Kk | Decoding device |
| SE9504316D0 (en) | 1995-12-01 | 1995-12-01 | Nokia Satellite Systems Ab | Methods and systems for data transmission |
| US5640388A (en) * | 1995-12-21 | 1997-06-17 | Scientific-Atlanta, Inc. | Method and apparatus for removing jitter and correcting timestamps in a packet stream |
| JP3405034B2 (en) * | 1995-12-27 | 2003-05-12 | ソニー株式会社 | Digital signal multiplexing method and apparatus, and digital signal recording medium |
| US5835493A (en) * | 1996-01-02 | 1998-11-10 | Divicom, Inc. | MPEG transport stream remultiplexer |
| US6148135A (en) * | 1996-01-29 | 2000-11-14 | Mitsubishi Denki Kabushiki Kaisha | Video and audio reproducing device and video decoding device |
| US5774497A (en) * | 1996-04-12 | 1998-06-30 | Hewlett-Packard Co | Method and apparatus for PCR jitter measurement in an MPEG-2 transport stream |
| GB9607667D0 (en) † | 1996-04-12 | 1996-06-12 | Snell & Wilcox Ltd | Looping of compressed video bitstreams |
| US6064673A (en) * | 1996-08-02 | 2000-05-16 | 3Com Corporation | Communications system having distributed control and real-time bandwidth management |
| JP4147592B2 (en) * | 1996-08-06 | 2008-09-10 | ソニー株式会社 | Packet processing method, recording method, and recording system |
| US5760836A (en) * | 1996-08-22 | 1998-06-02 | International Business Machines Corporation | FIFO feedback and control for digital video encoder |
| EP0932949B1 (en) * | 1996-10-11 | 2004-12-22 | Sarnoff Corporation | Apparatus and method for analyzing bitstreams |
| JP3063824B2 (en) * | 1996-10-29 | 2000-07-12 | 日本電気株式会社 | Audio / video synchronous playback device |
| US5912880A (en) * | 1996-11-07 | 1999-06-15 | Northern Telecom, Limited | System and method for ATM CBR timing recovery |
| KR0181915B1 (en) * | 1996-12-30 | 1999-04-15 | 삼성전자주식회사 | Frequency auto-controlling method |
| SE520064C2 (en) * | 1997-03-18 | 2003-05-20 | Telia Ab | Improvements to, or with respect to, MPEG-2 broadband multimedia terminals for audiovisual communication, or distribution |
| SE519917C2 (en) * | 1997-04-16 | 2003-04-22 | Telia Ab | Improvements to, or with respect to, transmission of variable bit rate MPEG-2 data |
| KR100438693B1 (en) * | 1997-06-04 | 2005-08-17 | 삼성전자주식회사 | Voice and video multiple transmission system |
| JP3024599B2 (en) * | 1997-07-22 | 2000-03-21 | 日本電気株式会社 | AAL5 jitter reduction method and apparatus |
| US6266091B1 (en) | 1997-07-31 | 2001-07-24 | Lsi Logic Corporation | System and method for low delay mode operation video decoding |
| US6122316A (en) * | 1997-07-31 | 2000-09-19 | Lsi Logic Corporation | MPEG decoding system meeting 2-frame store and letterboxing requirements |
| US6289053B1 (en) | 1997-07-31 | 2001-09-11 | Lsi Logic Corporation | Architecture for decoding MPEG compliant video bitstreams meeting 2-frame and letterboxing requirements |
| US6310918B1 (en) | 1997-07-31 | 2001-10-30 | Lsi Logic Corporation | System and method for motion vector extraction and computation meeting 2-frame store and letterboxing requirements |
| US6101221A (en) * | 1997-07-31 | 2000-08-08 | Lsi Logic Corporation | Video bitstream symbol extractor for use in decoding MPEG compliant video bitstreams meeting 2-frame and letterboxing requirements |
| JPH11112938A (en) | 1997-10-07 | 1999-04-23 | Matsushita Electric Ind Co Ltd | Image packet communication system |
| US6377588B1 (en) * | 1997-11-25 | 2002-04-23 | Nec Corporation | Method and apparatus for reducing jitter of a program clock reference in a transport stream of MPEG over ATM, and MPEG decoder |
| US6301258B1 (en) * | 1997-12-04 | 2001-10-09 | At&T Corp. | Low-latency buffering for packet telephony |
| US6556560B1 (en) | 1997-12-04 | 2003-04-29 | At&T Corp. | Low-latency audio interface for packet telephony |
| US6144714A (en) * | 1998-01-06 | 2000-11-07 | Maker Communications, Inc. | Programmable fractional frequency digital frequency synthesizer for synchronous residual time stamp service clock regenerator phase locked loop |
| US6122337A (en) * | 1998-01-06 | 2000-09-19 | Maker Communications, Inc. | Modular circuitry architecture for residual time stamp service clock regenerator phase locked loop |
| US6011823A (en) * | 1998-01-06 | 2000-01-04 | Maker Communications, Inc. | Combined synchronous residual time stamp generator and service clock regenerator architecture |
| US6292490B1 (en) | 1998-01-14 | 2001-09-18 | Skystream Corporation | Receipts and dispatch timing of transport packets in a video program bearing stream remultiplexer |
| US6246701B1 (en) | 1998-01-14 | 2001-06-12 | Skystream Corporation | Reference time clock locking in a remultiplexer for video program bearing transport streams |
| US6351471B1 (en) | 1998-01-14 | 2002-02-26 | Skystream Networks Inc. | Brandwidth optimization of video program bearing transport streams |
| US6195368B1 (en) | 1998-01-14 | 2001-02-27 | Skystream Corporation | Re-timing of video program bearing streams transmitted by an asynchronous communication link |
| US6351474B1 (en) * | 1998-01-14 | 2002-02-26 | Skystream Networks Inc. | Network distributed remultiplexer for video program bearing transport streams |
| US6097757A (en) * | 1998-01-16 | 2000-08-01 | International Business Machines Corporation | Real-time variable bit rate encoding of video sequence employing statistics |
| US8306170B2 (en) * | 1998-03-31 | 2012-11-06 | International Business Machines Corporation | Digital audio/video clock recovery algorithm |
| US7272298B1 (en) * | 1998-05-06 | 2007-09-18 | Burst.Com, Inc. | System and method for time-shifted program viewing |
| JPH11340938A (en) * | 1998-05-28 | 1999-12-10 | Sony Corp | Data multiplexer and its method |
| GB2340351B (en) * | 1998-07-29 | 2004-06-09 | British Broadcasting Corp | Data transmission |
| US7558472B2 (en) | 2000-08-22 | 2009-07-07 | Tivo Inc. | Multimedia signal processing system |
| US6233389B1 (en) * | 1998-07-30 | 2001-05-15 | Tivo, Inc. | Multimedia time warping system |
| US8380041B2 (en) | 1998-07-30 | 2013-02-19 | Tivo Inc. | Transportable digital video recorder system |
| US8577205B2 (en) * | 1998-07-30 | 2013-11-05 | Tivo Inc. | Digital video recording system |
| US6967963B1 (en) | 1998-12-01 | 2005-11-22 | 3Com Corporation | Telecommunication method for ensuring on-time delivery of packets containing time-sensitive data |
| US6212195B1 (en) | 1998-12-01 | 2001-04-03 | 3Com Corporation | Telecommunication apparatus and method for forwarding packets using separate collision domains |
| US6262979B1 (en) | 1998-12-01 | 2001-07-17 | 3Com Corporation | Telecommunication conferencing system and method |
| US6661811B1 (en) * | 1999-02-12 | 2003-12-09 | Koninklijke Philips Electronics N.V. | Method of and apparatus for communicating isochronous data |
| US6675031B1 (en) * | 1999-04-14 | 2004-01-06 | Mallinckrodt Inc. | Method and circuit for indicating quality and accuracy of physiological measurements |
| EP1089482A4 (en) | 1999-04-16 | 2005-11-02 | Sony Corp | Communication device, communication method, and recorded medium |
| JP3506960B2 (en) * | 1999-08-03 | 2004-03-15 | シャープ株式会社 | Packet processing device and storage medium recording packet processing program |
| WO2001022729A1 (en) | 1999-09-20 | 2001-03-29 | Tivo, Inc. | Closed caption tagging system |
| WO2001067744A2 (en) * | 2000-03-03 | 2001-09-13 | Avaz Networks | Method and apparatus for data rate synchronization |
| CA2301436A1 (en) * | 2000-03-20 | 2001-09-20 | Peter Renaud | Method and system for multi-protocol clock recovery and generation |
| US7145912B1 (en) * | 2000-03-23 | 2006-12-05 | Tut Systems, Inc. | Demultiplexing a statistically multiplexed MPEG transport stream into CBR single program transport streams |
| SE517245C2 (en) * | 2000-09-14 | 2002-05-14 | Ericsson Telefon Ab L M | Synchronization of audio and video signals |
| US20070230921A1 (en) * | 2001-04-05 | 2007-10-04 | Barton James M | Multimedia time warping system |
| US8880709B2 (en) * | 2001-09-12 | 2014-11-04 | Ericsson Television Inc. | Method and system for scheduled streaming of best effort data |
| DE10204190C1 (en) * | 2002-02-01 | 2003-06-18 | Infineon Technologies Ag | Clock phase control circuit for transceiver, has amplitude-limiting circuit whose limit value is dependent on setting signal used to control adaptive echo compensation circuit |
| US9432719B2 (en) * | 2002-10-22 | 2016-08-30 | Broadcom Corporation | A/V System and method supporting a pull data flow scheme |
| US7266147B2 (en) | 2003-03-31 | 2007-09-04 | Sharp Laboratories Of America, Inc. | Hypothetical reference decoder |
| US7474624B2 (en) * | 2003-05-29 | 2009-01-06 | Motorola, Inc. | Method and apparatus for reducing delay jitter |
| US7693222B2 (en) * | 2003-08-13 | 2010-04-06 | Ericsson Television Inc. | Method and system for re-multiplexing of content-modified MPEG-2 transport streams using PCR interpolation |
| KR101102639B1 (en) * | 2003-11-12 | 2012-01-04 | 파나소닉 주식회사 | Recording medium, playback apparatus and method, recording method, and computer-readable medium |
| US7593061B2 (en) * | 2004-06-22 | 2009-09-22 | Sarnoff Corporation | Method and apparatus for measuring and/or correcting audio/visual synchronization |
| US7969901B2 (en) | 2004-08-12 | 2011-06-28 | Lantiq Deutschland Gmbh | Method and device for compensating for runtime fluctuations of data packets |
| DE102004039185B4 (en) * | 2004-08-12 | 2008-06-12 | Infineon Technologies Ag | Method and device for compensating for runtime fluctuations of data packets |
| KR100640338B1 (en) * | 2004-09-20 | 2006-10-30 | 삼성전자주식회사 | Method for not cutting display on channel change in digital multimedia broadcasting and device thereof |
| US9967534B1 (en) | 2004-11-19 | 2018-05-08 | Tivo Solutions Inc. | Digital video recorder video editing system |
| US7480315B2 (en) * | 2004-12-31 | 2009-01-20 | Microsoft Corporation | Method and apparatus for synchronizing clocks |
| US7333468B1 (en) * | 2005-05-16 | 2008-02-19 | Sun Microsystems, Inc. | Digital phase locked loops for packet stream rate matching and restamping |
| JP2007215092A (en) * | 2006-02-13 | 2007-08-23 | Sanyo Electric Co Ltd | Audio data processing apparatus |
| JP4905060B2 (en) * | 2006-11-07 | 2012-03-28 | 富士通株式会社 | Reception device and data reproduction method |
| US8300530B2 (en) * | 2007-02-08 | 2012-10-30 | Ixia | Detecting media rate for measuring network jitter |
| US8139704B2 (en) * | 2008-01-02 | 2012-03-20 | Cisco Technology, Inc. | Phase compensated renormalizable dynamic phase locked loop |
| DE102008046914A1 (en) * | 2008-09-12 | 2010-03-18 | Deutsche Thomson Ohg | Method for synchronizing a receiver and a transmitter in a communication system, and a transmitting station and receiving station adapted for use in the method according to the invention |
| DE102009003851A1 (en) | 2009-04-30 | 2010-11-11 | Lear Corporation Gmbh | Method and device for reproducing digital audio signals |
| DE102010061076B8 (en) | 2010-09-30 | 2012-07-19 | Lear Corporation Gmbh | Method and device for sending digital audio signals |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4716575A (en) * | 1982-03-25 | 1987-12-29 | Apollo Computer, Inc. | Adaptively synchronized ring network for data communication |
| US5007070A (en) * | 1989-10-31 | 1991-04-09 | Bell Communications Research, Inc. | Service clock recovery circuit |
| US5138440A (en) * | 1990-10-29 | 1992-08-11 | General Instrument Corporation | Method and apparatus for communicating a plurality of asynchronous signals over a digital communication path |
| FR2669798B1 (en) * | 1990-11-23 | 1994-09-16 | Lmt Radio Professionelle | DEVICE FOR TRANSMITTING SYNCHRONOUS INFORMATION OVER AN ASYNCHRONOUS NETWORK, ESPECIALLY AN ATM NETWORK. |
| US5111292A (en) * | 1991-02-27 | 1992-05-05 | General Electric Company | Priority selection apparatus as for a video signal processor |
| US5159447A (en) * | 1991-05-23 | 1992-10-27 | At&T Bell Laboratories | Buffer control for variable bit-rate channel |
-
1992
- 1992-07-02 US US07/907,943 patent/US5287182A/en not_active Expired - Lifetime
-
1993
- 1993-05-31 CA CA002097349A patent/CA2097349C/en not_active Expired - Lifetime
- 1993-06-24 EP EP93304927A patent/EP0577329A3/en not_active Withdrawn
- 1993-06-29 JP JP18227693A patent/JP3053717B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0577329A2 (en) | 1994-01-05 |
| JPH0697927A (en) | 1994-04-08 |
| US5287182A (en) | 1994-02-15 |
| CA2097349A1 (en) | 1994-01-03 |
| JP3053717B2 (en) | 2000-06-19 |
| EP0577329A3 (en) | 1997-11-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2097349C (en) | Timing recovery for variable bit-rate video on asynchronous transfer mode (atm) networks | |
| EP0684740B1 (en) | Timing recovery for variable bit-rate video on asynchronous transfer mode (ATM) networks | |
| JP3168243B2 (en) | Video signal encoding device | |
| EP0699369B1 (en) | Apparatus and methods for improving timing recovery of a system clock | |
| KR100407085B1 (en) | Buffer management in variable bit-rate compression systems | |
| US6744782B1 (en) | Communications device, method thereof, communications system and recording medium | |
| US5828414A (en) | Reduction of timing jitter in audio-video transport streams | |
| KR100797624B1 (en) | System for digital data format conversion and bit stream generation | |
| US6516002B1 (en) | Apparatus for using a receiver model to multiplex variable-rate bit streams having timing constraints | |
| US6347119B2 (en) | Communication apparatus, communication method and storage medium | |
| CA2360244A1 (en) | Method and apparatus for detecting and preventing bandwidth overflow in a statistical multiplexer | |
| EP0920220A2 (en) | Method and apparatus for reducing jitter of a program clock reference in a transport stream of MPEG over ATM, and MPEG decoder | |
| US8104067B2 (en) | Apparatus for receiving and playing back data | |
| US6546013B1 (en) | Method and apparatus for delivering reference signal information within a specified time interval | |
| JP4081936B2 (en) | COMMUNICATION DEVICE, COMMUNICATION METHOD, AND RECORDING MEDIUM | |
| JP3207709B2 (en) | Multiplexed data intercommunication method, multiplexed data intercommunication system, gateway and terminal on asynchronous network | |
| JP3018335B2 (en) | Method and apparatus for reducing program clock reference jitter of MPEG over ATM and MPEG decoding apparatus | |
| WO1998047293A1 (en) | Transmission of mpeg-2 encoded video in atm networks | |
| Haskell et al. | Timing Recovery for Variable Bit-Rate Video on ATM | |
| KR100204060B1 (en) | Clock recovery control circuit of mpec-2 transport stream | |
| EP1161838A1 (en) | Method and apparatus for generating time stamp information |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKEX | Expiry |
Effective date: 20130531 |