CA2091034A1 - Graphics co-processor - Google Patents

Graphics co-processor

Info

Publication number
CA2091034A1
CA2091034A1 CA002091034A CA2091034A CA2091034A1 CA 2091034 A1 CA2091034 A1 CA 2091034A1 CA 002091034 A CA002091034 A CA 002091034A CA 2091034 A CA2091034 A CA 2091034A CA 2091034 A1 CA2091034 A1 CA 2091034A1
Authority
CA
Canada
Prior art keywords
region
source image
pixels
image
digital input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002091034A
Other languages
French (fr)
Inventor
Douglas E. Snyder
Daniel J. Clark
James Mcclure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adobe Inc
Original Assignee
Douglas E. Snyder
Daniel J. Clark
James Mcclure
Adobe Systems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Douglas E. Snyder, Daniel J. Clark, James Mcclure, Adobe Systems, Inc. filed Critical Douglas E. Snyder
Publication of CA2091034A1 publication Critical patent/CA2091034A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T17/00Three dimensional [3D] modelling, e.g. data description of 3D objects
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T11/002D [Two Dimensional] image generation
    • G06T11/40Filling a planar surface by adding surface attributes, e.g. colour or texture
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40Picture signal circuits
    • H04N1/405Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels
    • H04N1/4055Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels producing a clustered dots or a size modulated halftone pattern
    • H04N1/4058Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels producing a clustered dots or a size modulated halftone pattern with details for producing a halftone screen at an oblique angle

Abstract

ABSTRACT

The present invention provides an apparatus and method for rendering graphic images as bit maps. The system includes an input for receiving digital input commands, a command interpreter to interpret the input commands and convert them into commands suitable for use inside the system, and several inputand output buffers. A halftone screening section and a rendering section output data suitable for use by a raster display or marking engine. The system can render multiple output pixels during each machine iteration, typically four pixels per clock cycle. The system can also apply halftone screens or gray fills to an image, rendering multiple pixels per clock cycle. A preferred embodiment is a single-chip graphics co-processor (GCP).

Description

ù 3 ~

Our Ref: Ql 120,P014l17497. 12.
GRA~I~CS I~O-PROC~ES$Q~
FIELD OP THE I~VENTIO~
The system of this invention i~ a preferably single~hip control device S for high performance, high quality display devices used in typ~setters, image-set~ers, color printers and high throughput printers. The system is useful in interpreting input code and translating input instructions to provide graphical output, par~cularly in the form of source images, filled graphiu, halflone screens and characters, either in black, white or ifilled with a selected gray hali~one 10 pattern.

BACKGROU~
The present invention is usei~ul in many graphic~ co-processors. The ` system carl be used to improve raster imaging in many applications, particularly 15 when the desired output can be described in part using geome~ic primitives.
Many printing devices are controlled by page description lang~ges, including Ado~e Systems' PostScript3 language, Hcwlett Paclcard'~ Y, Canon's LlPS, NEC's NPDL and other languages by ~yocera and Xerox.

In a preferred embodiment, the system is used to implement Adobc Systems PostScript commands. Adobe ~ystems i3 the assigne~ of the subject invention. The PostScnpt system was developed to communicate high-level graphic information to digital laser printer~. It i~ a fle~ible, compsc~ and powerfiul language, both for e~pr~ssing graphic region~ and for pe~orming general 2~ programming ta~b. The preferTed embod~nent of the ~ystem of thi~ inYention isdescribed in the conte~ct of a PostScript printer, typesetter or imagc-setter.

The PostScnpt language, use and applications are thoroughly described in a number of boolcs published by Adobe Systems Inc., including PQStSÇri~t 30 Language Rçfer~nçe Manual (Second Edition) and ~QstScr~t Lan~u~g~ro~rarn Design. PostScri~pt and related page descripdon language3 are ~oful with typesçtters, image-setters, color printer~ and high throughput printers a~ well as highrcsolutio~ Yidco or other display de~ice~.

Grsphics Co-Processor - 1 -. . .

. .
. ~

. : -,~

a3l ~

Printing, video display and other such device~ are sometimes ealled marking devices or marking engines. A raster image processor (RIP) associated with a marking engine converts input information and commands into a rasterized ~bit-mapped) region suitable for display on the associated output device.
S Commereially available devices inelude the Apple L~erWriter~, the Linotronic3 100 and 300, the Adobe Atlas RIP and the: Emerald RIP. A marking engine may use vertical or hori70ntal sean lines, but for convenienc~ only horizontal scan lines are described here. The same or similar rnethods or devices can be used for verdeal scan lines.
Some raster image processors use a graphie accelerator chip. One such chip is the Hitachi ARCTC chip, which can implement simple fills of rectangles and eireles, simple line drawing, bit blitting and many Boolean eombinations of these functio~. NEC'~ 7220 ehip a]so i3 popular, but eannot render comple~c 15 geometrie features. Hyphen has announced a graphie eoproeessor chip, but that device is not yet publicly available for analysis.

SllMMARY OF THE INVENl~ON
The system of the present invention includes an input section for 20 receiving digital input eommands ineluding eommands whieh desc~ibe d region of the graphie image or specify a mode for filling the region. A eommand interpreter is eoupled to the input seetdon for interpredng the input eommands ar~ for translating the eommands into internal eommand~ for use inside the system. A
sereening seetion eoupled to the input section and the eommand interpreter sereens 25 multiple pi~cels (generate~ a sereened image) of a selected region of the graphic image with a halftone screen pattern during eaeh system iteration. A rendering seetion eoupled to the eommand interpreter and to the sc~eening seetion renders and outpuh deviee pixel data for a raster deviee. The system ean be enhaneed by incorporating a threshold memory coupIed to the screemng section for stoAng 30 valuu in a halftone thr~shold array. n~e system ean reDder multiple deviee pi~els during each machine iteration, typically four per clock cycle. In somc filling mode3, the system can render 32 devicc pi~els per clocl~ cycle.

I~e method of the present invention include~ ge~erating a r~terized 35 graphic image suitable for display on a raster display device or raster marking Graphic~ C~Processor - 2 -`~ ~v3;~

engine by re~iving a first digital input command which degcribes a region of a graphic image, receiving a second digital input cornmand which specifies a mode for filling the region with device pixel data corresponding to a specific rasterdevice and translating the first and second digital input commands into at least one 5 internal command to ~e executed in par~llel with another internal command.
Substantially simultaneously and for each one of a plurality of the raster device pi~els, if the region is to be filled with a selected gray level, correlating thP one ras~er device pixel with a corresponding threshold value in a reference array ofthreshold values, the reference array of threshold valua corresponding to an array 10 of pi~els in a halftone screen pattern, then comparing the selected gray level with the corresponding threshold value and rendering the region by setting devic~ pi~el data for the raster device pixel according to it3 correspo~ding threshold value, the selected gray level and the second digital input command, whereby the region i~
filled with device pixel data to form a halftone screen p~tern. Alternatively, if the 15 region i~q to be filled with a solid color, the region h rendered by set~ng device pi~el data for the one raster device pi~el to represent the solid color and outputting the de~ice pixel data in a form suitable ~or a raster displ3y device or a rastermar3~ing engine.

The system of this invention can render sc~eened region~q at a sustained ~ate of 50 million pi~els per second and a burst rate of up to 80 million pi~cels per second. This contrast~s with rendering rates of about 500,000 pi~eLq per second in a commercially available Atla~q RIP or a~out 2.5 million pi~el3 per ~cond in an ` Emerald RIP. Looked at another way, the dme to rend~ an 8 ~ 10~ 300 dpi 2~ scanr~ so~e imagc on a 1200 dpi ~pesetter RIP ~vith ~ ning wa~ about 1.4 seoond3 whe~ using the GCP, appro~imately a l~fold im~rovement over prior art devices or system3.

30 BRIE~ 12~1ION OF TH~ DRA~Y~G~
Flgurc 1 is a block diagram illus~ating the connection of thc GCP
system of this in~rendon to other component~q of a graph~ processing system.

Fgurc 2 illus~ates thc principal component~ ~ a preferred embodiment 35 of thi~ invendon.

Graphic~ Co-Proc~ssor - 3 -. . .

Figure 3 illustrates an arbitrary region divided into trapezoid~.

Figure 4 illustrate3 one embodiment of halRone screen tileg used to S display an arbitrary region.

Figure S illustrates an angled source image and the conversion from source pixels to device pi~els.

10 DET'AlLED DE~CRI~llON OF T~ INVENTIO~
The system of the present invention is designe~ to provide a c~
processor to render de~ailed, high quality images on ra3ter marking engine~ without requiring a host CPU to perform all of the rendering functions. RendeAng a low ~solutioll image may not require much time from a host CPU or from the c~
1~ processor in the system of this inYendon but rendering a high resolution image can takc a great deal of time. Using the system and method of the present invention ~lloWs much faster rendering of high resolution image~.

The system of this inYendon i~ desig~ for use in ~ c~proce~sor 20 architecture, particularly in the form of a single chi~. For convenience, thepreferred embodiment of the pre~nt imention will bc referred to ~ the graphic c~processor or ~GCP~. Thc GCP operates on input command~, gencrally in thc form of display list instructions, and sllocates various re~dering fimctions to units within the ~CP which can operate in parallel to render multiple pi~cels of an ou~put 25 image per cIock cyclc. The output may bc stored in a buffer within the GCP, in af~liate~ Of connected memory, or may bc sent to a storage device or dir~ctly to a marlcing engir#.

High resolution marl~ng engines which display a large number of lines 30 can only render a fi~ed number of lines at a time. lhis is due in part to the fact that a very large number of pi~els must bc stor~d in memosy at a time and constraints, incIu~ing the speod and price of memory, limit the amount of memoryavailable for any portion of a figure to ~e rendered. For devices ha~ing a resolution of more: than a~out 2400 dpi, a t~pical band i~ smaller than the height of 3~ a typical capital letter. The mar~ng engine and a3sociakcl prooessing de-ices must Graphic~ Co-Pro~ssor - 4-, . .

3 ~ --, therefore render even a single line of characterg as a serie~ of bands The current band is oRen stored in a buffer, which i~ referred to as a band buffer.

In a preferred embodiment, the system of this invention consist~ of a S single, relatively comple~ application-spe~ific integrated circuit (ASIC), designated herein a~ a graphics coprocessor (GCP) ~for convenience, connected to up to fourmegabytes of high-speed support static RAM, although more or le~s RAM may be used if desired. Alternatively, support RAM may be incorporated into the sarne chip as the ASIC. The primary filnction ~f the system is to render scanned or 10 synthetic source images in black and whit~, gray, or col~r using a fast, high-quality screening method into the RIP's i~arne or band buffer.

The system and method of thi3 invention is particulsrly usefiul for processing and output~ng hal~one image~, including synthetic and natural images.15 One halftoning method which may be implemented using the system and method ofthis invention is described and claimed in a co-pen~ing ~plication entitled ~Me~od of Producing Hal~one Images,' Serial No. 434,924, filed November 8, 1989, by Stephen Schiller and assigned to the same assignee a~ this invention, inco~porated herein by reference. That application de~ a ~Utah ~le~
20 halftoning method which permits nearly all screen anglct and ~equencies to bcrepresented with an e~emely high degr~e of accuracy. lhat method may use a threshold array of selected values as a reference for a region to be dispIayed.
O~er halftoning methocl~ also can be implemented by thc 9ystem and method of this inventioD, such as cla9sic~1 four-proa~s3 color scr&en anglu. The resulting2~ printed regions a~ lubstandally free of l~[oire pattern~.

ln the G~P, all commands and arguments which are ~:ific to a par~cuIar graphical operation, including set-up and configuration informadon, are passed via direct memory access (DMA), while 50me ini~alization data can be 30 passed under pro,grarnmed VO to registers inside the GCP hardware, for example, during power up. Completion of DMA transfer9 can ~e detect~ ~a polling or via an interrupt to tho central processing unit (CP~l).

Refe~ring to Pigure 1, Ihe system of thi~ tion, GCP 10, can be 35 used as a c~processor to host CPU 11 in a RIP, driven by a display list structure Graphics Co-Proc~ssor - S -.. .

h li 3 1 ~) 3 !1 which may ~e held in main memory system 13. GCP 10 utilizes direct memory access (DMA) to main memory system 13 to retrieve and to store data as needed for Yarious operation~, e.B. to render scanned source images by halhoning, to perform graphic primitive area filling and to transfer ch~racter masks to an S ar~itrary frame or band buffer in memory, which may bc in main memory system 13. Figure 1 illustrates the connection of conventional elements including instruction cache 1 and data cache 2 to CP'U 11 and to memory address bus 4 and memory data bus S. Main memory 3ystem 13 i3 conne~ed to memory address bus 4 and memory data bus 5. GCP 10 i9 connected to screen random access memory 10 (RAM) 1~ through screen data bus 14 and screen address bus 15. GCP 10 is alsoconnected to CPU 11, to memory data bus 5 and through main memory address latch 3 to memory address bus 4. GCP 10 may use main memory system 13 or other memory (not shown) as ex~ernal memory.

The system and method of this invention is capable o~ rendering trapezoids, run-array3 and masks Including compressed masks), each of which canbe filled with Uack, white, or a selected gray level. A~ entire display list for a ~ypical frarne or band buffer device may ~e rendered in ~ single invocation of GCP
10 while the host CPU performs other operation~ in parallel, ~uch as fetching the 20 display list for thc ne~t band from disk or proc~sing tbe ne~ct page.

The system of this invention is supported by other hardware within the RIP, including screen RAM 12, ~hich hold~ o~e or moq~ thre~hold ar~ays required to perform one or more selected screening method~. In one embodiment, screen 25 RAM ~2 is configured as 25~ ~ 32 bits. In o~her embodiment9, screen RAM 12 can be configw~ c 32 bits or other configura~io~, allowing the design engineer to trade off device design and manufacturing c~t versus scr~ening qualiq.

Using the PostScript system, a filled region is divided into graphic prirnitives and thes~ pnmitive~ are displayed as output. Figure 3 illustrate~ anarbitrary region 4a bounded by outlines 41 and 42. An outline can be described generally a3 a series of lines or curves defining the edge of a region to bc displayed. Ihe r~;oludon of ~he li~ or curve~ can ~ selected to ~e lower for a 35 relatively low-resoludon display and higher to rer~er fincr detail~. The image of Graphics Co-Processor - 6 -..

-~ ~ V~ 3i~

each filled region to be rendered can be divided into segments, e.g., horizontalsegment3, bounded by essentially straight edges of an outline to make trapezoids, run-arrays or other appropriate geometric figures in order to build a complete region.

The use of trapezoids as a basic primidve is particularly useful for a raster display device which builds an output region by tracing horizontal 3can lines.
The trapezoids are preferably oriented with their parallel sides in the direction of the scan lines. Referring to Figure 3, poltions of a region can be rendered as a10 plurality of trapezoids, e.g. trapezoids 43, 44, 45, and 47. Details can be rendered using one or more single scan lines, e.g. scan lines 4~, 48. A series of sc~n line segment3 can ~e stored a~ a run-array for more convenient storage and handling. A Nn-array is simply an array or assembly of runs specified, for e~ample, by the starting point and length of each included Nn. A PostScript 15 processor converts information a~out trapezoids into an output region on or for a raster marking engine, typically in the form of a complete bit map of the outputregion. A typical PostScript processor useful in conjunction with the system andme~hod of this invention prepares each scan line for ou~ut~ determining onè or more range~ of pi~els on that scan line which ~hould compn~e the output.
~0 Graphical operations in the preferred embodiment include trapezoid filling, mn-array filling, mask filling and source irnage operation3. Source image operations include imaging with trapezoid or with run-array based device regions.
In a preferred embodiment, all of the c4mmands and parameter~ required to render25 the primitiYes are pass~d in a main memory~ased data ~ucture called a displaylist. The fonnat of this display list and a descri~tion of the detailed operadon of repre~enta~e command3 is described below.

In a preferred embodiment, GCP 10 include~ a plurality of registers for 30 storing needed values. lllese values may include reference point3, c.g., thc memory location for the start of device coordinate space, the first rnemory location in tha band currently being rendered, certain pi~el coordi~ate~, thc scan line curlently being rendered and other piece~ of information. GCP 10 also includes aplurality of state machin~ designed to carry out ~pccific tasb depending on the 3~ input~ to each state machine.

Graphics Co-Proce~ssor - 7 -.~:

. , U ~ ~ ~ 3 `~ --In a preferred embodiment, data or commands are assumed to start on a 3~-bit boundary in main memory. Data types include main memory addresses, integers, device pixe] coordinates, pointers" character mas~, compressed character S mask~ and display list operator op codes. Certain fields are undefine~ and should be set to zero by the host CPU. Pi~el coordinates can be ~bsolute coordinates indevice coordinate space rela~ve to the start address of device coordinate space in memory. That start address is loaded into a register prior to commencing imagingoperations. Integer pi~el coordinates refer to the lower leR corner of the ideali~ed 10 device pixel in question, while fixed point pixel coordinatesl can refer to any point within the device pi~el. Fixed point pixel coordinates can ~e represented in thefamiliar l~bit whole plus l~bit ~actional coordinate ~ashion. One sl~lled in theart will recognize additional and alternative data structu~es and size3 which can be used wi~h the system and method of this invention.
1~
The base address of the device coor~inate space is s-tored iD a device coordinate base ~DCB) register. Sin~e the appropriate marking engine using the output of the present device will typically be a high resoludon b~ device where less than the entire device coordinate space buffer ~ill bc present in main memory 20 ~imultaneously, the l}CB register will ~quently contain a negative twos-complement nurnber, such that the pi~el addressing calculations which are performed produce addresses within the current band bu~er in memory~ Also~
sinu many marking cngines have a deYice coordinatç space wi~h g~eater than 2l6 pi~els along one or more dimensions, the DCB register may optionally be biased to 25 a point or location well within the devioe coordinate space. Ihe use of biased addresses within the DCB r~gister is supported in the preferred embodiment to achieve ~c~tended addressing- within thc devi~e coordinate ~pace~ -The present invention is par~cularly useful for four ~ of imaging 30 and graphic~ rendering work in a high-perforrnance RIP cnviromnent:
I) s&reening for hal~oning~ of scanned photographic images;
2) ares filling with color or gray scale levels which require screening;
3) area filIing with all white or all black values (typi&ally lines); and 4~ rendering under a mask (typ;cally character bit-maps), 3~

Graphics Co-Processor - 8 -.

h U ~ 3 ~1 ~

Although the host CPU in the intended environment will preferably be a fast processor capable of doing area filling of all white or all black at nearly main memory bandwidths, there can ~e additional RIP system level performance improvement by allowing the system and method of thi~ invention to perform 5 filling operations independently of the host. This c~processor ~rchitecture permits the host to perforrn display list pro~ssing, PostScript language program processing, disk file I/O processing or other tasks while the display list is being render~d by the system of this invention for a given band buffer.

When filling regions with gray sc~le or color lerels that must be scræned, the system and method of this invention has a decided advantage over host-based filling due to the complexity of most screening methods. Traditionally, filled regions which require a single gray Ievel can ~e filIed more rapidly by precomputing a 'gray brick~ or small pattern of pi~el~ which i~ based on the 15 cwTent gray-level setting screened against the curTent screen. For e~ample, a 50%
gray could consist of alternating vhite and black pixel3, while a 90% gray wouldhaYe an aYerage of 1 in 10 pi~els (in two dimen~ion~) white. The brick is used to ~tile' the device add~ss space with a simple repea~ng ~ttern of bit~ which represent the derice pi~els to be turned on at a fi~d gray level duriDg halftoning.
20 Since the gray level is fi~ed, most of the thresholding eomputation can be eliminated by performing this function for one or a sma~ number of halftor.e cells only, then replicating the bit-map so obtained when filling the region in question.
In modern, sophisticated halftone tiIe screening metho~, unli~e more primitive rational screening approaches, it is ger~erally not pos~le to determi~e a simple, repeating pat~ern of zeroes and 0~9 of limite~ size (typically 64 Rbytes or less).
l~is i9 becau~e some screens are rotated by angles whicb eause the periodicity of any pattern across a given scan line to be tens or hundr~s of scan-units long. Asc~n ~it i9 a computer word corresponding to one or more source image or output region device pL~els and i~ usually the size of the host processor's nadve word 30 size.

The filling method must individually determine the 3creen threshold comparison resul~ for each device pi~el. Even if the periodici~y of the gray paKern were ~gnificantly smaller than lhe imageable area, the computation of a ~gray 35 briclc- can s~ll bc prohibitively slow in comparison to t~e ordinary screening Graphic~ Co-Processor - 9 -~,a~:~3~
approach when using the system and method of this in~-ention. Tlli3 iS ~ause thespeed with which the hal~toning process proceeds using GCP 10 is limited only bymain memory bandwidth.

S Organi~atiQn31 Desi~ timization The present invention is designed ~o offer ma~imum perfo~nance in a somewhst special controller environment and for a range of high-resolution marking engine types. Additionally, the t~rget design of the present invention is optimized for the most frequent types of g~aphica~ or imaging operations and their 10 most common parameters.

In other environments, the system of the imention also offers improved performance rela~e to prior art devices but not a~ dr~madc as GCP 10 performance under ideal conditions. If, for e~ample, a rotated image is presented, 1~ source image samples must be obtained, which requira the time and e~nse of calculating main memory addresses for ~ach block of tbree or four device pi~els rendered, assuming typical sourcc and destdnadon resolution~. Ihe addidonal memory o~erhead required to stall ins~uction pipeline in S3CP 10 for each ~Iculadon can result in a reduction of imagir~ perform~nce by a f~tor of two or 20 more.

lheory o~Q~eratior~
MaJor FunctiQnaLUnit~ and Da!a Path~
In a prefeIIed embodiment, GCP 10 i~ div ded into thc following major 2~ functional units, mo~t of which operate as independent ltate nachiw which canfunction in paralld to render or calculate ~ariou~ porffoD~ of a region. ~ost of the major functional UDit~l are ffed to an internal bu3. Ille~c funcffonal UDit~ andinterconnectio~ are illu~trated in Figure 2.

Graphics Co-Processor - 10 -~ û ~
Unitldentifie~ Fur~Qa SIF 30 Screen Threshold Fetcher SF 29A Source Fetcher SI 29B Source Input SFU 29 Source Fetcher Unit P~ 2B Pi~el Assembler MCS 20 Main Control Sequencer MRH 26 Memory Request Handler DL ~IFO 23 DispSay l,ist First-In First~ut (FIFO) Bu~er DI FIFO ~4 Destination Input FIFO
DO FIFO 2S Destination Output ~IFO
Sl FIFO 27 Source Input FIFO
Screen RAM 12 1~ Each of the functionaS units serves to provide an additional degree ofparalIeSism in the graphics rendering process as well as to isolate the address;ng structure of the buffer or memory area being served by the state machine in question. ~unctionaS units operate in paralSel, advancing one state per clock cycle, with communication signals used between units to synchronize the operations.
~0 Each functional unit is designed such that a memory buffer for that unit ;s included only if needed and is directly associated with that functional unit, providing asimpler design for that unit in most ~.

GCP 10 was built as a single chip using standard, commercially aYailable cell libraries, selecfed and interconnected to give Ihe desired functionality.
lhe chip was manufactured at VLSI rechnology in San Jose, California. The masks used to make GCP 10 are being registered for mask wor3~ protection contemporaneously ~th the filing of this applicatioo. l~o~e masb arc incorporated herein by reference and a c~py of the registration information forms 30 ~he Appendi~c to this specification. One s~cillod in the art and having access to standard cell libraries can implement the system of thi9 i~vention without reference to those mas~s.

GCP 10 can render simultaneously four devicc pi~cel3, when performing 35 a gray fill or image operation, on each cloc~c cycle. At a cloc3c rate of 25 MHz, therefore, an ove~ll rate of up to 100 million pi~e~/second are rendered into the device frame or b~md buffer in main memory. With oplimal dispIay list primitivesorganized as largc objec~s of significant length in the ~can line direc~on, this rate of rendering was ac~ally achieved for sufficient peri~ of ~ue such that the Graphics Co-Proce~sor 2ù31~
overall rendering rate for typical display lists approached 80 mi~lion pixels/second.

To provide lhis kind of performance, &CP 10 perfolms many operations in parallel during each clock cycle - a benefit of functional unit parallelism through pipeline design techniques. While: rendering a given primitive, the actual pixel-by-pi:cel processing in each stage of the pipeline is handled by a series of "hard-wired~ sta~e machines so that the rendering rate of four pi~els per clock i3 achieved during the majority of the time.

Dis~lay List In a preferred embodiment, the primary input to GCP 10 i9 a display list which includes information about source images, regions, selected fill characteristics and character shapes, specifically run-array~, I}apezoids and masks.
The display list is preferably already c Iculated for a selected marl~ng engine.1~ Thus the system of the invention is r~sponsible only for con~er~ng the display list to a bit mapped output in memory at a selected resolution. For e~arnple, a certain display list could be calculated by CPU 11 (~igure 1) fo~ a targ~t mar~ing engine, for e~arnple, a video screen with a display of 1024 x 1024 pL~ at 7~ dpi. A
related but different display list might bc useful for outputting agentially the same 20 ou~put ~o a highr~solution printer, e.g., one capable of filling white space uith selected blac~ dots at a selected resolution, say 1200 dpL A typicsl display list will include a plurality of operation codes ~op codes) and thc relevant parameters required by each op code.

In a preferred embodiment, a display list i~ p~ar~ in bloc3cs of a certain sizc, for e~cample 1 Kbyte, with links to ~ubsequent bloc~3 as n~eded.
Display li~t~ can include subroudnes, e.g. for fill pattern~, with subroutine return commands bac~ to the point of departure in a parcnt display li~ In ano~er preferr~d embodiment, muItiple le~vels of subroutine~ are implemented.
One useful op code is a FillTrap instruction, which il used to fill trapezoids. A trapezoid is described geometrically by four points connected along a perimeter. In pr~ctice, trapezoid~ are preferably calculated with two horizontal edges and two slop~ing edges~ Thc number of hori~ontal sc~n lines to be rendered3S depends on the trapezoid to be rendered and may ~ary from a Yery small number, Graphics Co-Processor ~ u 3 ~
for example where ~ source image or filled region is very smaU, to a very large number, for example if a large, regular geomet~ic figure i~ to be displayed at high resolution. in a preferred embodiment, the FillTrap op code includes coordinatesof a lower hori~ontal edge, an upper holizont~l edge and starting and ending points S along each of the lower and upper horizontal edges. The instruction can calso include information about the slope of each of the angled edges, preferably pre-calculated, to avoid calculating the slope at the time of rendering.

In GCP 10, the interior and edges of the trapezoid are filled vith a pre-10 selected white, black or gray level or even with a ~creened source image such as asc~nned image. The fill characteristics can be specified in the da~a associated with the op code, or, alternatively, can be maintained in a memory location.

AdditionaI op codes may be defined for the ~cial cases of imaging 15 parallelograrns or trapezoids with one or more vertical edges, although one s1~1Ied in the art will ræognize that there is a trade off between a large, powerful set of instruction~ and a small, f~t set of instrucdon~.

Another op code is a RunArrayFill instruction. Thi~ instruc~on 20 include~ informa~on about the dimension~ of the a~ay, which in turn contains inforrnation about multiple horizontal regions along selected lines which should be filled. For e~ample, the information may include a lower and upper bound of incIuded scan li~ follow~d by information for each scan lilse, incIuding the number of horizontal regions on that Iine lo bc filled and tl}e starting and ending 2~i point~ of each 3uch horizontal region.

One ~Icilled in the art will recognize that a number of othcr op codes can be usefill in the display list. These op code~ can ir~lude ~anous modes of acce3sing selected registers which the designer cbooses to implement, information 30 about tasks or images or other infonnation required to display a region. Someuseful opcode~ include instrucdons to select a region from a designated memo~y location or create a region using specified coordinate~. Other opcodes include instruction3 to: fill a region with a halftone screen with ~ ~ified gray level; fill a region with at least one halftone screen with a s~cified color; fill a region using 35 black pi~els; fill a region using white pixels; fill a regioo using opaque pixels; and Graphics Co-Proc~ssor -13 -fill a region using a mask, where the mask can be found in a designated location in memory or can be generated using predetermined information. Still other opcodes are useful for manipulating or using source images and include instructions to:
define a source image; scale a source image; rotate a source image; shear a source 5 image; flip a source image; clip a source image; define an image mask; and fill a region with an image.

Main Control Se~que~ceL~C ~
Referring to Figure 2, MCS 20 is a central controlling unit for the I0 entire system and coordinates the chip function, assigning tas!~ !o the appropAate pr~essing unit. In a preferred embodiment, MCS 20 is responsible ~or all operations that require intelligent but infrequent intervention. MCS 20 is organized around a programmable, microcoded sequencer and i5 assisted by a general purpose arithmetic logic unit (ALU).
In a preferred embodiment, MCS 20 controll whether the system will be in a slave or master mode. &CP 10 powers up in ~lave mode. MCS ~0 recogmzes when an external device (e~ternsl to GCP 1~) such ~ the host CPU is seeking the attention of the system of this invention, f~ e~ca~le, to load registers 20 of the system or to begin rendering a region. Ihe e~nal dNice can then set status bits and control registers and perfonn any other initiali~ion that is required. The external device can send a star~ng memory address to MCS 20 via a bw or otherwise. MCS 20 then accesses that mem~y loc~fion and transfers some number of bytes of infonnation into a buffer far filrther processing. Typical information is in the form of a display li3t, desabed aba~e. A typic~l display list msy contain inidalization informadon as well.

When GCP 10 is instructed to begin rend~ing a region, GCP 10 goe~
into master modc and controls one or more e~cternal buses, such as the main 30 addr~ss bus and main data bus, as needed to access display li~t and memory information. In alternative embodiment5, GCP 10 may use one or more e~cternal buse~ for transferring source image or output r~gion infonnation. MCS 20 also manages the e:cchange of information internally between various registers snd storage areas within or closely associatcd with GCP 1~.
3~

Graphics Co-Proc~ssor - 14-3 t~ 3 ~
Display List FIFO (DL FIF0) 23 is connected to an internal bus of GCP 10 ard is controll~d by MCS 20. DL FIFO ~3 i~ a memory buffer, preferably configured to hold 16 or more words. Wh~n instructed, or as needed, MCS 20 loads a display list into DL FIFO 23. MCS 20 then analyzes the display S list, parses each instruction into an op c~sde and its associated operands and then passes the instruction or relevant inforrnation to the appropriate unit of GCP 10 for subsequent processing. MCS 20 can read subsequent display list instructions and can act on them or pass them to the appropriate unit of GCP 10. It is possible and, in fact, desirable for each unit of GCP 10 to be processing inforrnation in10 parallel whenever possible in order to render a region more quic~ly.

MCS ~0 provides data and sets registers for necessary memory accesses and other support functions as described below. For e~ample, if MCS 20 encounters a FillTrap instruction, it will find the devic pixel address for the first 15 point to be render~d in the trapezoid (scan line and p~sition on the scan line) and then load the coordinates of that pi~el address into registers. The FillTrap display list instruction also include~ the location of the co~t ending pi~el to ~e displayed on a scan line and, preferably, MCS 20 calculates the numb~r of intervening pixels along a given scan line and loads that information into register~. MCS 20 also 20 caIculate~ the ne~ct set of register parametera, for e~amplc, the starting and ending pixel for the ne~t scan line or region or the star~ng pL~el and number of pixels to be rendered and keeps them in ~phantom~ registers unt~ they can be moved to other unit~ of GCP 10 for subsequent processing. The appropriate unit of &CP 10 c~n copy the content~ of thesc phantom register~ when the information is needed.25 MCS 20 typically does not know when the phantom re~ters will b~ read so it calcula~3 and stor~ the ne~ct value for the phantom re~ister~. When another unitof GCP 10 (usually PIX 28) accesses those registers, it also gignal~ MCS 20 so that the phantom registers can be updated. Using this technique, most register update~ can be pipelirled.
In a pr~ferred embodiment, MCS 20 finishcs one trapezoid before handling the ne~ct trapewid in a display list. Some operations durLn~ processing of a trapezoid may require interlock within GCP 10 in order that v~rious units of G~P 10 properly complete their respective operation~. Interloclc i9 handled by the 35 variou~ state machine3 in GCP 10, with different lock a~d unlock schemes for Graphic~ C~Processor -15 -~ v 3 ~
different timing situations. Several methods of implementing interlock are well known to one sl~lled in the art.

DL FI~O 23 is kept current by MCS 2Q arld filled as needed by S memory request handler (MRH) 2C. MCS 20 keeps hac~ of what is in DL FIFO
23, what information is valid and when the buf~er should ~e flushed or refilled through the use of special hardware. In a preferred en~odiment, MCS 20 or MRH ~6 does these transfers using an e~cternal bus in b~st or page mode, which allows more efficient utilization of the bos~ Logic in MRH 26 controls how much 10 and what information to get from e~ternal memory. Ihe steps basically includeidentifying a relevant memory address which contains a pibtel or a first display list instruction of interest, getting the data, typically by dir~cl memory acces~ over an external bus and loading that data into the appropnate FIFO.

Whenever the normal cour~e of re~dering a pnmi~ve object is interrupted by a boundary condition, MCS ~0 generally intervene~ to handle the condition, then rendering resumes at hardware speed. E~amples of these boundary conditions include the start of a new row of souroc image ~el samples, whereupon MCS 20 calculates memory addre~se3 for t~e start of a new row and 20 increments the current row number. Another boundary a~ndition occur~ when thecurrent rendering operation reaches the cnd of the eur~ row in the current screen, whereupon MCS 20 calculates the staFting scree~l ~18 number, row number and starting pi~el position within the screen tile. MCS ~, PIX 28 or another GCP unit handte~ the condition involved and insert~ the re~i~d new data or address inforrnation into the appropriate hardware re~ds. Frequent boundary conditions, ~uch as the overflow of source image data &om ol~e 32-~it source word to t~c r~e~t sequent;al word, or the overflow of one 32bit de~ice ~uffer word to~he ne~ct sequen~al word, are handled directly by the sb~c machine~ imolved ll~erefore thc performancc of MCS 20 is not generally a ~gnificant factor in 30 overall rendering performance.

Graphics Co-Processor -16 -Ou~ut Renderin~
The principal GCP rendering components are destination inpul FIFO (Dl FIFO) ~4, destination output FlFO (DO FIFO) 25 and pixel assembler (PIX) ~8.
This unit of GCP 10 fills a selected region with a selected lSll or source image.
5 The FIFOs are memory devices, preferably high speed~ connec~ed to an internal bus of GCP 10. Memory request handler (MR~ 26 maintains the FIFQs, keeping input FIFO DI FIFO 24 close to full tsame for DL FIFO 23) ~nd output FIFO DO FIFO 25 nearly empty. PlX :~8 is a state machine and includes associated devices for loading data into comparator~ and outputting device pi~els.
DI FI~O 24 is used to hold pre-existing output band or frame buffer data, if any, for a unit of the band or frarne. Generally pixels are stored in external memory and accessed in a page mode DMA transfer, but other forms of memory or transfers can be used. In a preferred embodiment, all bits in a band 15 buffer are set to a selected initial state rather than starting with random state. For example, all bits in the buffer can be set to the backgrou~d pnnt color, often white. MCS 20 instructs MRH 26 to fill DL FIFO 24 with data from memory for pi~els of interest for a pending operation. In some instances, it is sufficienf to load only starting and ending pi~els of a scan line region into FIFO ~. This can20 be useful, for e~arnple, when a region is to be filled with all blac~ or all white device pi~els and any intervening, pre~cisting informa~on is irTelevant.

MCS 20 passes an op code or display list instruction to PIX 28, including coordinates and information about the sele~ted fill operation. Display list instructions or fill instructions ean instruct PlX 28 to fill opaque,~ that is, fill a seIected output region with opaque, e.g., white or blac~ pi~els or a selected gray or halRone source image, thereby coYering up any pre~ious source image information. Alternatively, PlX ~8 may ~fill with masl~,- that i~, ~est the current blaclc, white or gray fill sgainst a mask Where the mas~c include~ an empty 30 portion, any pre~isting source image information for that portion will be unchanged, thereby allowing selected portion~ of a pre~isting source image or output region to show through the current fill.

P~ 28, fill~ a selected scan line in a region f~om the selected starting 3S pixel through lho selected ending pixel with the selected maslc or fill. Note that Graphics Co-Pro~ssor - 17-, ,~; , ~ ~ h i) ~ 3 ~1 ?

some region~ may include a small number of pixels that fall entirely within a single scan unit (a computer word corresponding to multiple output region pixels).
In simple cases of painting opaque black or white, a rela~ively large number of pi~els (32 in a preferred embodiment) can be filled on each clock cycle.
s PIX ~8 outputs the relevant pi~els to DO FIFO 2S. PIX 28 and MRH
26 also manage DO FIFO 25 and copy the contents of DO FIFO 25 to external memory, e.g. a band buffer, as appropriate. Dl FIFO 24 and DO FI~O 25 are usually flushed at the end of each scan lil~e.
S~reen Threshold Fetcher Operaffon PIX 28 includes a threshold comparator which is invoked when the fill is gray or an image halftone pattern. Referring to Figure 4, a region S4 to be scaled and filled with one or more gray levels i~ rendered as a series of halftone 1~ cell3 ~3 computed using threshold array data from s~n RAM 12. The threshold comparator in PIX 28 tests each pixel in the source image (source pi~el) against a geome~ically corresponding value in the threshold amy and outputs a device pixelof a first binary value if the source pi~el value e~c~ the threshold value and otherwise outpus a device pixel of the other binary val~e, thereby filling a region, 20 e.g. region 5S.

The theory of one type of such screening is descri~ed in co-pending application Serial No. 434,924, discussed a~>ove. Ibis method i~ par~cularly useful for hal~tone or ssreen applications. In brief, a ~Jtah tile~ is a ~supertile~
2~ which itself LS typ;cally a series of smaller tiles. A typi~l Utah 81c will contain several hal~o~e ccll~ in an ~A~ rectangle, e.g. rectangb 51, and a ~B~ rectangle, e.g. reciangle ~. GCP 10 can use other threshold arrays as well. A threshold array can ~e precalculated and stored, generally a3 a rela8vely smoothly varyingfunction with a period equal to the spacing of a de~ir~ halRone screeD.
When MCS 20 interprets an op codc requiring screening, it activates screçn threshold f'etcher (Sl~) 30. MCS 20 iden8fie~ which pixel in a threshold array correspond9 to a starting pi~el in thc source ima~p or filled region. lllethreshold alTay is stored in a high-speed half'toning RAM, screen RAM 12. SrF
35 30 identifies the nppropriatc starting address in screen RAM 12 and inidates the Graphics Co-Processor - 18 -~ 2 ~ 3 ~ --transfer of data to PIX 28. In a preferred embodiment, the halftone threshold array consists of a series of 8-bit values and the dala pash is 32 bits wide. Thus, ~hreshold Yalues for four output pixels can be delivered on every clock cycle. STF
30 de~ermines when the edge of a threshold array scan line is reached, as well as S what corresponding threshold address should be used for the next source pi~el comparison. STF 30 can signal the com]parator to wait until valid th~shold data is available on the bus. A new threshold s~an line can be delivered in two clock cycles.

SIF 30 is also responsible for aligning data when the edge of a threshold array is not on a word boundary. PostScript maintains absolute screen phase (relative to the origin) for all objects on a given page. This allow5 objects to align with each other searnlessly and, more importantly, allows portions of aregion to be rendered separately from other portions of the same negion to give a 15 searnless final output. Some display models, such as Hewlett Packard's PCL and Macintosh~ Q-~ickdraw, do not maintain absolute screen phase, although others do.
SIF 30 aligns the pi~els of a region to be rendered according to the correct screen phase and corresponding starting point in the scraen threshold array. PI~Y 28 generates multipIe bits (a nibble) that are nibble-aligned within DO FIFO ~5, e.g.
20 4 bits in a nibble, aligned as a destination ~ord. Each bit of the nibble is generated from a comparator which requires an 8-bit threshold value. SrF 30 usesa byte shifter to allow each byte of tl~shold data input from screen RAM 12 to be shiRed to the appropriate comparator. PIX 28 can then u~e the pre-aligned, shifted threshold word. SI~; 30 also perforrns realignment when the end of a threshold 2~ lille i3 r~ached and a new threshold line i~ fetched.

UsiDg this mechanism, an area can ~e filled with an evenly sc~eened gray level. A preset gray level can be stored in a ~egister and compared againsteach threshold pi~el value, alig~ing scan lines a~ before. If the gray level is less 30 than the thresholcl level, the output pixel will be marked black. If the gray level is e~ual to ~ero (dark), each output pi~el i~ marked black If the gray level is equal to FF ~ight), each output pixel is marked whitc. O~e gl~lled in the art will retognize how to choose dark versus light colors on the appropria~e output device and can utili~e thi~s method accordingly. In a preferred embodiment, GCP 10 can 3S bc set to output either ~white~ or ~black~ when an output pi~cel is a logical 1.

Graphics Co-Processor - 19 ^

.

2 v ~ 1 ~ 3 ~

Thus by simply changing one flag, an entire region or portion of a region can bereversed black for white or vice versa.

In a preferred embodiment, P~ ~8 has multiple, e.g. four, comparator S units, one for each of the pixels which can be compared in a single clock cycle.
Source and threshold pi~els are shifted and masked as appropriate, depending on the instruction being implemented. The r~sulting ~alue is also shifted as required for the device coordinate space and rendered into DO FIFO 25. The comparator can keep track of both left and right edges, which correspond to a first and a last 10 scan unit of a region being rendered.

A bilevel output device has no g~ay scale capabili~ and can only display 'blac~ or ~white.~ PlX 28 outputs four comparisons per cycle, thus 8 cycles are required to fill a single scan unit in DO FIFO ~5 (8 cycles ~ 4 pixels =
1~ one 32bit word). When a region is filled with a ~ertical blend or gradually changing gray or color level, the display list can encode the region as a number of thin ~apezoids, each with an appropriate gray levd.

Mas~ng Masb can be useful for rendering certain region~, in par~cular characlers or te~t. A typical character i~ defined or repre~ented by an outline. At the time of rendering, the character outline usually already ha~ been converted to a bitmap at the appropriate resolution and size req~red for output and stored ;n memory. A typical display list instruction for a character will simply specify the 2~ star~ng memory coordina~ for the character ma~ and the star~ng c~ordinate in de~ice coordinate space where the character i~ to be plac~d. In a preferred embodiment, MCS 20 gets the needed information from e~ternal memory and plac~ the mask into source image FIFO (SI PIFO) 27.

Some~mes a mask may be clipped for use in rendeIinB a portion of the output. The clipping path may be linear, for e~ample a sheer left edge, or may follow an a~bitrary path, as in the case of an image maslc. Ibis method is most useful with a non~liE~d and non-compressed mask A ma~lc which has been compresscd, for e~cample, by using run length cncoding, should preferably be 3~ uncompressed andl placed into a portion of memory so as to bc accessible in non-Graphics C~Processor - 20 -- ~ v ~ i ~ 3 -1 --compressed form. For e~ample, using typical memory configurations, approximately ~56 scan lines are rendered in a band buffer before being transferred to a marking engine. For a high resolution typesetter with a resolution of 2400 dpi, this corresponds to only 0. l inch, which is less than the height of a typical S capital letter. Thus a typical line of te~t will cross more than one band. GCP 10 allows clipping ~on the fly~ for characteI~, e.g. taking only a certain vertical range of a character mask for rendering a particular band. Alternatively, one could use an expanded display list to render the lower third of a line of text, for e~arnple, followed by the rniddle third and top thind.
1~
The entire mask is read into Sl FIFO 27. It is then aligned bi~ by bit with the device buffer output as a function of the le~nost ~-value on the starting scan line. A typical fill will ~fill under mask,~ in which case the appropriate scan unit from DI ~IFO 24 must be aligned and merged with the input mask.
One preferred embodiment includes a special operator, a RenderImageMask instruction, which render3 o~e device pi~el per source pi~el.
Illis can ~e treated or processed like a masl~ but the pi~el assembler can assemble 32 bit~ per cloc~ cycle if the current fill color is black or white.
~0 ~ o~rce Fetcher Unit (SFU~
SFU 29 provides a mapping from a source image in an arbitrary coordinate space (source image space) to device coordin~e ~ace. Ihe mapping is frequently non-scalar and device resolution is usually gre~ter than source image25 resoludon. Mapping may also be one to one or to device resoludon less tha source imagc resolutdon, but the current method is most ~eneficial when device resolutdon is greater ~an source image resoludon. O~ cornmon e~ample is a deYice output of 2400 dpi for a source input of 300 dpi. In a preferred embodiment, GCP 10 makes special provision ~or three special cases: a unit scalar 30 and 0 rotation, in which the source image is ~nply treated a~ a mask; a 0 rotadon, that i~s, no rotation but rendered at an arbitrary ~cale and arbitrary rotation (e.g. 15) at an arbitraIy scaIe.

For the sp~cial case of 0 rotation and srbitra~y scale, GCP 10 can keep 35 SI FIFO ~7 filll b~ause the incoming data is, by definidon, consecudve and the Graphics Co~ sor - 21 -~ ~ 3 i ~ 3 !~

output region can be prepared portion by portion. MCS 20 doe~ not need to ~eep track of which output pixels are being rendered. It is sufficient to instruct PIX 28 where to find a source pixel in SI FIFO 27. A regisler can be set aside as a source address pointer which can be incrlemented as each source pi~el is rendered.
5 A typical source image may have 8 bits lxr pixel per channel (256 level gray scale per color component in color separations).

Referring to Figure 5, U and V are unit vectors in source image space and X and Y are unit vectors in device cl~ordinate space. For unit vectors IJ and 10 V rotated some angle from unit vectors X and Y, distances d~ du and dx dv (delta x over delta u and delta v, respectiYely~ can be determined easily.

Traditional PostScApt devices start with a sel~ed device or output pixel and look for the corresponding source pixel or pL~els. Rendering a large number 15 of device pixels per source pi~el re~uires calculation of small differencei in source pixel coordinates, sometimes leading to mathematical inaccuracies and an accumulating error. In prior art implementadons, incre~sing the output device resolution increased the potential for error.

GCP 10 ~Figure 2), in con~ast, starts with a source pi~el and calculates an increment vector to render corresponding devioe pi~. I~he result i5 independent of scale. The increment vector can be quite accurate and can even beimplemented using double precision number~. Using t~e system ard method of this invendon increases output image resolution and allows more accurate rendering 2~ of a source image.

Ima~e Fetch Method An image a~ defined by PostScript has an arbitrary sca~ing and rotation with ~es~ct to the device coordinate space of the rend~ing hardware. This 30 scaling and rotation is achieved by matri~c tr~nsformation using matrix multiplicadon. A given point in device coordinate space (~c, y) can be translated into a point in source image space (u, v) by the follo~ing matrL~ multiplication:
t a b 0] [~] [u]
3~ [ c d 0] * ~y3 = [v]
Etx ty~ 1] 1l] 11]

Graphics Go-Processor - 22 -2 i.3 3 a Tllis matri~ muldplication yields the following equations:
u = a~ + cy + ~
v = bx + dy + ty The matri~ [a b c d t~ ty] which defines the values for device coordinate space is available internally ;nside GCP 10~ These values a;re floating point numbers that are converted into 32-bit fi~ced point representation for use by the image rendering method. A 32-bit fi.~ed point value uses 16 bits to represent 10 the whole number portion and 16 bits to represent ~he fractional part.

The descripdon of the image to be render~ ncluding the above transformation matrix) along with a graphic object (or objects) in device coordinate space is passed to the imaBe rendering section. llli3 ~aphic object defines a series 15 of line segments to be rendered, oriented in the scan line direc~on. A line segment can ~oe described as a line ~etween two points (~1, y) and (~g, y), where ~1 is the minimum (lower) ~c value along a selected scan line and ~g is the maximum (greater) ~c value on that scan line. The two point~ have the same y value. A graphic object usuaUy has muldple ]ine segments and each line segment 20 may have different y, xl and ~g values.

Prior Art kle~hod One image rendering method is performed sg follow~ for each graphic object.
2~
1.Transform initial point (~1, y) to (u, v).
Save (~1, y) as (oldX, oldY).
2.Save integer portion (IntPartO) of (u, v) to (oldU, oldV).
30Use (oldU, oldV) to calcula~e initial pointer to image data.

Graphics Co-Processor - 23 -V Y ~ ~ 3 ~
3. For each new l~ne segment (~1, y) (deltaX, deltaY) = (;~1- oldX, y - oldY~
if IntPart (u) I= old~ adjus+t iCmdgoetapyinotldv ~ b*delta oldU = IntPart (u) if IntPart (v~ ! = oldV, iadjust image pointer oldV = IntPart (v~
(oldX, oldY) = (x, y) 10 4. For rest of pixels in line segment (~l, y) -> (xg, y) (deltax, deltaY) = (1, 0 ) by dlefinition (u, v) = (oldU ~ a, oldV + b) if IntPart(u) ! = oldlJ, adjust image pointer oldU = rntPart(u) if IntPart (v) ! = oldY, adjust iimage pointer oldV = ~ntPart(v) (oldX oldY) = (x, y) This prior art method can be used for any ~ansformation matri~
20 However for the most common case where there is no rotation, the values of b and c are 0 and the above method is fil~her optin~ized.

~ nvenbon The prior art method requireQ recalculabion of (u, v) for each device 25 pi~el. GCP 10 is capable of rendering multiple plxels througb a halfltone threshold screen, so a new method was developed to avoid calculating (u, v) coordiDates ofeach device pi~el. For each source image pi~el, this new method deter~unes how many device pi:cels can be rendered using the same souroe image coordinates. It also detenTun s what the ne~t (u, v) source image pi~el will be. With this new 30 method, when a source image pi cel maps onto multiplc devioe pi~el~ due to the image scalc> each iteration produces data used to render multiple device pi~el~.allow~ GCP 10 to render multiple de~ice pi~eLQ per deYice iteration.

Ihe method of this invention calculates several rariable for each image 35 which are constant for each unique imagc. Referring to ~gure 5, dx du = lla Number of device pi~els in the scan line direction (x) between ho~izontal (u~ image pi~els 40dx dv = lJb Number of device pixel~ in the scan line direcdon (x) between vertical (Y) image pLxel~
dy du = l~c Num~er of devi~e pixels in the vertic~l direction (v) betw~en horizontal (u) imagc pi~els G]raphics Co-Processor - 24 -3 1 ~ 3 `il dy dv = I/d Number of device pixels in the ~ertical direction (y) between vertical (v) image pi~el~
dxy du = dx du/dy du = c/a shift in scan line distance to the next horizon~al image pixel (u) when moving one device pixel in the ver1ical direction (y) dxy dv = d~ dv/dy dv = dlb shi~t in scan line distance to the next vertical image pixel (v) when moving one device pixel in the vertical direction (y) No~e that when a, b, c or d are zero (true with orthogonal images), certain variables become infinite and cannot be calculated. A modified method detailed below is used for these cases and for all rotated cases~

Non-Orthogonal RotatiQn GCP 10 follows this method for each graphic o~ject and ~or all rotated images.
O. Calculate d~c du = Fix (1.0/ a);
dx dv = Fix (1.0 l b);
d~i du = Fi~ ( c t a);
d~y dv = Fix ( d 1~);
This is donc only once per im~ge.
1. Transform inidal point (xl, y) (70 in ~:igure 5) to (u, v) in ~1oating point. 0 Comert (u, v) to fixed point.
Use IntPart (u), IntPart (v) to calculatc inidal pointer to image data.
Calculate ru, rv as follows:
ru = ~ du * FracPart (u) if (ru ~ 0) ~only if d~ du > O and FracPart (u) !=0) N ~ = dx du, ru i3 the remaining scan line distance in device pi~els to the next horizonal (u) image pixel rv ~ ~x dv * ~:racPart (v) if (rv ~: 0) (olrly if dx dv > O and FracPart (v) ! =0) n~ ~ = dx d~;
IV i~l Ihe remaining scan line distance in de~ce p~els to the next vertical (v) image pixel (oldX, oldY) = (x, y) Graphics Co~ xssor (oldRu, oldRv) = (m, rv) oldPointer = pointer go to step 3 5 2. For each new line segment (~cl, y) -> (~g, y) (deltaX, deltaY) = (xl - oldX, y - oldY) (ru, rv) = (oldRu, oldRv)-(deltaX + dxy du*deltaY, deltaX + dxy dv*deltaY~
pointer = oldPointer while (ru < 0) ru = ru + Idx dul pointer = ~ointer +
(sign(dx du) * si7e~image pixel)~
while(ru>= Idx~ul) ru = ru- Id~ dul pointer = pointer-(sign(dx du) ~ si~e (image pixel)) while (rv < 0) rv=rv+ Idxdvl pointer = pointer +
(sign(d~c dv) + width of image) while (rv > = Idx ~vl) rv = rv- Id~c dvl pointer = pointer-(sign(dx dv) * width of irnage) (old~c, ddY) = (~, y) (oldRu, oldRv) = (ru, IV) oldPoin~er = pointer 3. For each line segment ( cl, y) - > (xg, y) (E.g., when the distance is 5.~ pi~els, increment ru and rv by 1 to allow generatioa of 6 pixels ) (ru, rv) = (ru, IV) ~ (Fix(~
len = ~g - ~1 while ~en > 0) imglen = min(lntPart(ru), IntPart(rv)) if ~nglen ! = û), render image ~t pointer for len imglen len = len - imglen (ru, rv) = (ru, rv) - (Fixlmglen), Fi~lmglen if (ru < ~i~ (1)), we have crossed a horizontal (u) image pi~el ru = ru ~ Idx dul pointer = pointer +
(sign(d~c du) * si~e Image pi~el if (n~ ~ F~ (1)), we have crossed a verlical (v) imsge pi~el rr = rv + Idx dvl Graphics Co-Processor - 26 -~ v 3 :~ ~ 3 ~

pointer = pointer ~
(sign(dx dv) * width of image) Ortho~onal Rot~ion When dealing with an orthogonal image (0, ~0, 180 or 270 degrees rotation), the variables ~ or b will ~e zero. If both are zero, the image to be rendered has no width in the scan line di~rection. If b and d are zero, the image to be rendered has no height. Both of thes~ cases are illegal and should not be rendered.
The following method has been modified for when b i3 zero (the 0 or 180 degree rotated c~e). A similar method can ~e used when a is zero (the 90 or 270 degree case).
1~ 0. Calculate dx du = Fix(l.0 / a);
dy dv = Fix(l.0 I d);
d~y du = Fix( c / a);
This is done o;~ly once per image.
1. Transform initial point (~1, y) to (u, v).
Use IntPart(u), IntPart(~v) to calculate initial pointer to image data.
Calculate ru, r~ as follows ru = ~x du * FracPart(u) if (ru ~ û) (only if dx du > O and ~:racPart (u) != 0) ru += d~ du;
ru is the remaining scan line distance in device pi~els to the next honzontal (u) Lmage pixel nr = -dy dv * FracPart(~) if (n ~ O) (only if dy dv > O and FracPart (~v) ! = 0) n += dy dv;
n is the remaining vertical` (90 to scan line) distance in device pixels to the next vertical (v) iinage pkel (olclX, oldY) = (x, y) (oldRu, oldRv) = (ru, rv) oldPointer = pointer go to step 3 Graphics Co-Processor - 27 --~ _ 2~Y~a3~ ,., 2. For each new line segment (~1, y) -> ~xg, y) (deltaX, deltaY) = (~1- oldX, y - oldY) (ru, rv) = (oldRu, oldRv)-(deltaX + dxy du * deltaY, deltaY) pointer = oldPointer while (ru < 0) ru = ru + Id~c dul pointer = pointer +
(sign(d~c du) ~ si~e(ilmage pi~el)) while (N > = ¦dx du 1) ru = ru- Id~c dul pointer = pointer-(sign(dx du) * size (image pi~el)) while (rv < 0) rv = rv + Idy dvl pointer = pointer +
(sign(dy dv) * width of image) while (rv ~ = Idy dv ~) rv = rv- ldy dvl pointer = pointer-(sign(dy dv) * width of image) (oldX, oldY) = (~, y) ~oldRu, oldR~) = (ru, rv) oldPointer = pointer 3. For each line segment (~, y) -~ (~cg, y) ~E.g., when the dist~ is ~.~ pi~el3, increment ru by 1 to allow generation of 6 pi~els ) ru = ru ~ Fi~c(l) len = ~g - ~c while ~en > 0) imglen = IntPart~ru) if (imglen ! = 0), render image at pointer for len imglen len = len - imglea ru = FracPart(ru) + ld:c dul pointer = pointer + (sign(d~_du) * size~rnage pi~el) The prirnary difference between this and the previow method is tha~ rv now represents the vertical distance to the ne~t image pL~tel and i~ not used torender line segrnents. It is used when changing scan lines to detern~inc whether a 45 new sousce irnage pi~cel in the ~ertical direction is being rendered.

In certai~ special cases, rendering can bc cven fasler~ For the 0 rotation case where d~_du i3 greater than four (4) (more than four device pi~els per source pi~el), a pipeline can contain both the current and ne~t irnage ~ralues Where the Graphics C~Processor- 28 -.

.; . . ..

. . . - . , . :~
.. ; : ~. -- : . .

3`jl :

current device pixel is less than four (4) device pixel~ (I nibble) away from the next source pi~el value, the comparator can assume that the rest of the nibble belongs to the ne~t image value. This allows the assembler to ou~ut four device pixels per clock cycle.

Differences Ln Error~
Another advantage of the methcxi of this inven~on is that the errors obtained from the use of fixed point numlbers are smaller than the errors obtained using the old method. In particular, the errors generated using the old method 10 increased four (4) times whenever the resolution of the device doubled. The errors from the method of the invention decrease two (2) times when the resolution is doubled. The prior art method converts the transformation matrix into fixed point and adds the fi~ed point values for each device pi~el, witb a resulting error limited essentially ~o the round-off error times the number of device pi~els. The method1~ of this ;nvention uses the inverse of the transforrnation matri~ converted into fi~ed point and adds these values for each image pixel, vith a resulting error of essentially the round-off error times the number of source image pixels.

For a 3~ dpi image transferred onto a 300 dpi device, the transformation ~0 matri~ is scalar (i.e. 11.0 0 O, 1.0 0 O D. Both the plior ar;t method and the method of this invention have 16 bits of accuracy in representation of integer~ (1.0 and the inverse of 1.0) and the round-off error3 are the same. Fur~hermore, the number of device pL~els and image pi~el~ are the same. Therefo~e, the accumulated errors are about the same.
For the same 300 dpi image transferred onto a 1200 dpi device, the ~aDsforTnadon mat~L~ becomes 10.~ 0 O, 0.25 0 O]. Theprior art method use~ a fLced point number ~vith 14 bits of accuracy (0.25~ while the method of thi~
invendon u~ a fi~ed point number with 18 bits of accuracy ~1/0.25 = 4.0).
30 Ihis gi~es 16 dmes more accuracy in the round-off erro~ using the method of this invendon. Fur~hermore the number of device pi~els is i~creas~ by four (4) for the same number of source image pixels. Therefore the total accumulated error is64 tdmes greater using the prior art method.

Graph;cs Co-Processor - 29 -A similar calculation can be made when scaling the other direction (i.e.
300 dpi image -> 75 dpi device), where the method of this invention is 64 times less accurate than the prior art method. However it is not as important that themethod map device pixels into the correct image pixel when image pixels are being 5 skipped because of down-scaling.

Out~ut as Input Plus T nsfer Fu~
GCP 10 c~n also implement an arbitrary transfer funcdon. ~n a typical application, a selected gray level will be selected to have a resolution similar to 10 that available in the source image. For e~;ample, an 8 bit source will be rendered using an 8 bit gray level. It is sometimes necessary to adjust gray levels, for example, when using different marking engines. A look-up table can be prepared using dedicated RAM (e.g. 2~6 x 8), contained in SI 29B shown in Figurc 2. The output image is combined in P~ 28 using the source image value or the gray level15 from the look-up table. A look-up table can be downloaded from external memory in accor~ance wi~h a display list instluction.

Anti-~liasin~ Generator OyçratiQn Screening gives an image that is most suitable for reproduction. There ~0 are several types of scneening, only one of which is halftone screening. The latter method is implemented in the system a~d method of this invendon.

At high screen ~equencies, a halftone cell may oontain le~ than 256 pixels, at which point that scræn cannot accurately repre~ent a 256 level gray 25 scale. If the halftone cell i~ 10 ~c 10 pi~el~, that cell can only show 101 leYels of gray. This i3 a partic~ar limitation in a blend ~gray or color) becau~e discontinuitie~ behveen discrete, inde~ed gray levels show up as dis~nct ~bands~.
Ille o~urrenoe of this banding is quite common in bot~ gray and color screening,particularly in a region of slowly changing gray or color value~ a~ in a gradual30 blend or por~ons of a sky or wall.

Using prior art methods and introducing an e~mr term into the gray level for each halftond cell, adjacent cells will be a bit dar~er or lighter than adjacent cells that norninally have the samc gray level. Thi~ allows more ~ay levels but Graphiu Co-Processor - 30 -~ ~ .
. .
, h ~J ~

gives a 'noisier- appearance. If the error term is preeomputed, a fi~ed pattern of noise may be discernable in the final image.

The system and method of this invention can create a more random noisc 5 pattern by injecting differing amounts of noise when each source pi~el i3 compared with each threshold level, generating up to two bits of noise ~the least significant bits) in random pixels at the resolution of the ou~put device. Four separate, uncorrelated pseudo-random noise generators are used for each of the scrcen comparators. Each noise generator produces a new noise sarnple on every cloclc 10 cycle, which can be scaled from 0 to 2 ~its in amplitude. Il~e pseudo-random noise generators can be selectively turned on or off. l~is can be used for fi~edgray level fills or for image fills as well as for blends.

Banding problems actually get more severe as the resolution of pAnters 15 gets better. Sc~en frequencies of 133 or 1~0 line3 per inch ~Ipi) are traditional, but a modern, high quality press c~n print 175 to 250 ~i and printers and press operators prefer to use the full resolution available. Image-setters are also getting better. However, an image-setter capable of printing 2~ dpi can print a 200 Ipi screen as a 12 ~c 12 halflone cell, which can display only 145 gray levels. Blends 20 under these conditions using prior art techniques show ~evere banding. ll~e system and method of this in~ention diminishes that banding a~siderably.

A general description of th~ system and method of using the present inYention as well a~ a prefe~red embodiment of the pre~ent invention has been set 25 forth above. O~e sldlled in the art will recognize a~d be able to practice additional Ya~iation~ in the me~ho~ described and variation~ on the deYice described which .-fall within thc teachings of this invention.

Graphics Co-Processor - 31-

Claims (38)

1. A system for generating a rasterized graphic image comprising a region containing a plurality of device pixels, wherein said region is described by one or more digital input commands, said digital input commands including an instruction to fill said region with a halftone screen pattern, said system comprising:
an input section for receiving digital input commands including a command which describes a region of said rasterized graphic image and a command which specifies a mode for filling said region;
a command interpreter coupled to said input section for interpreting said digital input commands and for translating said digital input commands into internal commands for use inside said system;
a screening section coupled to said input section and to said command interpreter for screening a selected plurality of device pixels contained in a selected region of said rasterized graphic image with a halftone screen pattern during a system iteration; and a rendering section coupled to said command interpreter and to said screening section for rendering and outputting device pixel data for said selected plurality of device pixels, said device pixel data being suitable for display on a raster device.
2. The system of claim 1 further comprising a threshold memory coupled to said screening section for storing halftone threshold array values.
3. The system of claim 2 further comprising a means in said screening section for accessing a selected plurality of said halftone threshold array values from said threshold memory during a system iteration.
4. The system of claim 1 further comprising a means in said rendering section for rendering a selected plurality of device pixels during a system iteration.
5. The system of claim 1 further comprising a means in said rendering section for renering a selected plurality of device pixel during a clock cycle.
6. The system of claim 1 further comprising a means for determining absolute screen phase within said region of said rasterized graphic image and a means for aligning and rendering said halftone screen pattern in the absolute screen phase so determined.
7. The system of claim 1 implemented on a single semiconductor chip.
8. The system of claim 1 further comprising a first input buffer coupled to said command interpreter for storing a said digit input command.
9. The system of claim 1 further comprising:
memory means for storing device pixel data;
means for accessing preexisting device pixel data from said memory means, where said preexisting device pixel data has been previously set or previously rendered; and a second input buffer coupled to said rendering section to store preexisting device pixel data.
10. The system of claim 1 further comprising an output buffer coupled to said rendering section for storing said device pixel data.
11. The system of claim 1 further comprising a main control sequencer coupled to said command interpreter for parsing said digital input commands and for identifying and allocating tasks to various sections of said system.
12. The system of claim 1 further comprising means for using a source image comprised of a plurality of source image pixels where each said source image pixel is to be mapped to corresponding device pixels and rendered to display a device image corresponding to said source image, said system further comprising means for calculating, for one of said source image pixels, device pixel data for substantially each corresponding device pixel.
13. The system of claim 12 further comprising a source image which has been modified by scaling and rotation.
14. The system of claim 12 further comprising a third input buffer coupled to said rendering section to store a source image or a mask.
15. The system of claim 1 further comprising means for adding substantially random noise values to said device pixel data.
16. A method for generating a rasterized graphic image comprising a region containing a plurality of device pixels wherein said region is described by one or more digital input commands, said digital input commands including an instruction to fill said region with a halftone screen pattern, said rasterized graphic image suitable for display on a raster display device or raster marking engine, said method comprising:
receiving a first digital input command which describes said region;
receiving a second digital input command which specifies a mode for filling said region with device pixel data;
translating said first and second digital input commands into at least one internal command to be executed in parallel with a second internal command;
for each of a plurality of said device pixels, substantially simultaneously, if said region is to be filled with a selected gray level, correlating each device pixel with a corresponding threshold value in a reference array of threshold values, said reference array of threshold values corresponding to an array of pixels in a halftone screen pattern, comparing said selected gray level with said corresponding threshold value and rendering each device pixel by setting device pixel data for each device pixel according to said corresponding threshold value, said selected gray level and said second digital input command;
or if said region is to be filled with a solid color, rendering each device pixel by setting device pixel data for each device pixel according to said solid color and said second digital input command; and Graphics Co-Processor - 34 -outputting said device pixel data in a form suitable for a raster display device or a raster marking engine, whereby said region is filled with device pixel data to form a halftone screen pattern or a solid color.
17. The method of claim 16 wherein said first and said second digital input commands comprise a single command.
18. The method of claim 16 further comprising the step of aligning said halftone screen pattern for said region in absolute screen phase.
19. The method of claim 16 further comprising filling said region with a selected gray level by setting device pixel data for each device pixel to a first binary state if said selected gray level is greater than said corresponding threshold value and to the other binary state if said selected gray level is less than said corresponding threshold value.
20. The method of claim 16 wherein at least some device pixel data has been set, said method further comprising the step of accessing preexisting device pixel data and modifying said preexisting device pixel data in accordance with amode specified by said second digital input command.
21. The method of claim 20 wherein preexisting device pixel data for a plurality of device pixels is stored within a single memory word and said region includes one or more scan lines and wherein, for each scan line contained within said region, said region has a left boundary at the left-most pixel that is within said region, and on said scan line and a right boundary at the right-most pixel within said region and on saidscan line, said left-most pixel having corresponding first preexisting device pixel data stored in a first memory word and said right-most pixel having corresponding second preexisting device pixel data stored in a memory word which may be said first memory word or may be a second memory word, said method further comprising selectively accessing said first memory word and the memory word containing said second preexisting device pixel data Graphics Co-Processor - 35 -and rendering device pixel data for said scan line in said region between said left-most pixel and said right-most pixel.
22. The method of claim 16 further comprising the step of calculating or retrieving from memory a precalculated reference array of threshold values in the form of a halftone screen pattern at an arbitrary, specified spacing and arbitrary, specified screen angle.
23. The method of claim 16 further comprising the step of filling said region of said rasterized graphic image with a selected input image.
24. The method of claim 16 wherein said first and second digital input commands comprise display list information.
25. The method of claim 16 further comprising adding substantially random noise values to said device pixel data for each device pixel.
26. The method of claim 16 wherein said first digital input command is selected from the group consisting of:
select said region from a designated memory location; and create said region using specified coordinates.
27. The method of claim 16 wherein said second digital input command is selected from the group consisting of:
fill said region as a halftone screen with a specified gray level;
fill said region as at least one halftone screen with a specified color;

fill said region using black pixels;
fill said region using white pixels;
fill said region using opaque pixels; and fill said region using a mask, where said mask can be found in a designated location in memory or can be generated using predetermined information.

Graphics Co-Processor - 36 -
28. The method of claim 16 wherein a source image is comprised of source image pixels, said method further comprising a third digital input command selected from the group consisting of:
define a source image;
scale a source image;
rotate a source image;
shear a source image;
flip a source image;
clip a source image;
define an image mask; and fill said region with an image.
29. The method of claim 28 wherein said first, second and third digital input commands comprise one or two commands.
30. The method of claim 16 further comprising a fourth digital input command defining a clipping region.
31. The method of claim 30 wherein said first, second and fourth digital input commands comprise one or two commands.
32. The method of claim 16 further comprising using a system with a plurality of sections, each said section capable of operating independently and simultaneously, said method further comprising:
parsing one of said first or second input commands into one or more internal commands, each to be executed within or by a specified said section of said system;
distributing each of said internal commands to said specified section;
and rendering said region.
33. The method of claim 16 further comprising using a source image comprised of a plurality of source image pixels where each said source image pixel is to be mapped to corresponding device pixels and rendered to display a device image corresponding to said source image, said method further comprising Graphics Co-Processor - 37-calculating for one of said source image pixels substantially each correspondingdevice pixel.
34. The method of claim 33 wherein said source image has been modified by arbitrary scaling and rotation.
35. The method of claim 33 further comprising determining for one of said source image pixels the number of device pixels that can be rendered using said one source image pixel.
36. The method of claim 33 further comprising determining which source image pixel to use next.
37. The method of claim 33 further comprising determining an inverse transformation matrix to calculate corresponding device pixels based on one of said source image pixels.
38. A method for generating a rasterized graphic image comprising a region containing a plurality of device pixels, wherein said region is described by one or more digital input commands, said digital input commands including an instruction to fill said region with a halftone screen pattern, said rasterized graphic image being suitable for display on a raster display device or raster marking engine, said method comprising:
recieving a first digital input command which describes said region;
recieving a second digital input commands which specifies a mode for filling said region with device pixel data;
translating said first and second digital input commands into at least one internal command to be executed in parallel with a second internal command;
using a source image comprised of source image pixels where said source image has been modified by scaling and rotation and where each said source image pixel is to be mapped to a plurality of corresponding device pixels and rendered to display a device image corresponding to said source image;

Graphics Co-Processor - 38 -calculating for one of said source image pixels the corresponding device pixel; and determining for said one source image pixel the number of device pixels that can be rendered using said one source image pixel.

Graphics Co-Processor - 39 -
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EP0559318A3 (en) 1995-05-31
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EP0559318A2 (en) 1993-09-08
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DE69323919T2 (en) 1999-11-11
DE69323919D1 (en) 1999-04-22

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