CA2087429A1 - Processing microchips - Google Patents

Processing microchips

Info

Publication number
CA2087429A1
CA2087429A1 CA002087429A CA2087429A CA2087429A1 CA 2087429 A1 CA2087429 A1 CA 2087429A1 CA 002087429 A CA002087429 A CA 002087429A CA 2087429 A CA2087429 A CA 2087429A CA 2087429 A1 CA2087429 A1 CA 2087429A1
Authority
CA
Canada
Prior art keywords
layer
insulating layer
hole
conductive material
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002087429A
Other languages
French (fr)
Inventor
Edward A. Keible
Nicholas J. G. Smith
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raychem Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2087429A1 publication Critical patent/CA2087429A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01044—Ruthenium [Ru]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12033—Gunn diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/94—Laser ablative material removal

Abstract

Uniaxially conductive connector formed in situ on microchip by laser drilling an insulating layer at least 5 micrometres thick to provide holes communicating with the chip bonding sites, and depositing metal in the holes to establish electrical connection with the bonding sites. Excimer U.V. laser ablation of a polyimide insulating layer is preferred, followed by removal of a surface layer (preferably of amorphous polyamide) from the insulating layer to expose the ends of the metal deposited in the holes.

Description

Wo 92/02038 2 0 8 7 4 2 9 pcr/Gss1/o1 172 PROCES$ING MICROCHIPS

This invention relates to processing of integrated circuit semiconductor devices and in particular, to ~ method of providing such devices, for example an integrated circuit semi-conductor chip, wlth pro~ecting electrically conductive material on the device bonding sltes.

A known method of providing vertlcal interconnection betYveen the bonding pads of an integrated circuit chip and bonding sites of an associated package is the "flip chip" technique described, ~or example. in EP~A-0186818. In that techniquc.
solder balls are provided on the input/output bonding pads of 'che chip, which - are accessible through apertures in the 1-2 microme~res thlck passivatlon layer normally covering the chip sur~aee. Th~ technique si~er~ from the pn3blem t~at small solder balls or "bumps" tend to provlde lnadequate tolerance to thermal expanslon stresses owlng to thelr small helght and resulting low degree of compllance, wherea~-larger solder balls introduce limitatlo~s OIl ~e closeness-of pad spacing. The present inveniion provldes a modified-"flip-chip" ~n whlch these problems are : alleviated.
; .. . - , The invention accord~gly provldes a method of providing an .integrated circuit semiconductor : `desricé ~ with -electrieally conductlve material pro~écting-from the dëvioë bonding sites for bonding to a-matching array of-elect~càl-cont;~cts with which the - device ^wlll ~~ be face-to-face in ûse, comprislng (a) providing an `electrlc~lly insilla'dng layer at least 5 mLicromëtrès ~ck adhe~ng ~-to the surface~of t}ie~e~lce Wlth one or more holes through ihe insulating layer each communicating ~iiiit}i a bonding site, (b) depositlIlg electrically conductive material within the hole(s) to establ~sh 'eleetric~l iconnëctio~i to~thë ;bonding sité(s~, and (c) excluding, or if necé~sa~y removing, deposlted conductlve material , ., . . . . ;. , : ", . , ", , .
. ..

WO 92/02038 ~ PCI'/GB91/01172 2 0 8 7 4 2 9 2 fr~

from the main surface of the insulating layer, so as to provide the conductive material substantially only within the said hole(s).

At first sight. it was not clear that a per~orating operation could be success~ully carried out in situ on the sur~ace of the device. especially a microchip, without damaging the relatively delicate underlying bonding sites and nearby circuitry. However, it has proved possible to control the perforating operation so as to avoid damaging the bonding sites. as hereinafter described, even when the perforation is at least partly effected by the preferred high efficiency and high precision technique of ultraviolet laser ablation, preferably using an excimer laser at wave leng~hs of 193 l~F). 308 (XeCl), or preferably 249 (KrF) nanometres. Other perforation techniques, for example reactive ion etching, or chemlcal etching could be used, but excimer laser ablation is preferred for its high speed and ablll~y to perforate thick layers, possibly together with a ~al chemical etching step a~ hereinafter described.

: It was also not e~qpected to be possible to plate into one-ended "blind" holes of the diameters and depths prefelTed for this ... ..
inven~on, but this has also been achieved, for-example wlth hole diameters in the range of 5-200 micrometres, preferably l5-100 ~icrometres, and especially 25-50 micrometres.
..;. . , ^ Aftèr the deposition of the electrically conductive material, the méthod preferably include t~e~step of removi~g some or all of the insulatlng layer.to expose at least part of conductive material del~osited ?within .the .holes. - ln thi~ way, pro~ectlng- electrically condueti~e material.taller than the known solder balls can be ~ `provlded on chlp bondiag sites for subsequent connection to chip ,, pack~g ~rangements. ~ ?

Whén using the pre~er~ed laser ablattoIl perforat~ng technique, lt is theoretically possible to limit the number of laser pulses or "shots"
to drill exactly through the insulatlng layer adhering to the de~rlce .
- ; ,,, , - .
.
, , , , ': ', , '. "
'~ r surface and overlying the bonding sites, without damaging the underl~ing sites themselves. However, in practice, this can be difficult owtng to slight fluctuations in the thickness of the insulatlng layer and/or to variatlons in the light flux actually reaching the insulating surface to be ablated, for example owing to build-up of con~ants on the laser system optics.

These difficulties are inge~iously overcome aecordiIlg to the present invention by providing an indicator layer underlying the insulating layer, which indicator layer comprises material which genera~es a disremable indication when directly acted upon by a first perforating operation (for example the preferred laser ablation). The first perfora~ng oper tion can then be moderated.
or replaeed by a gentler second perforating operation, upon generation of the said ~ndica~on. :

It will be appreciate~ that any suitable perforating operation may be moderated or replaced i~ tlhls way to avoid damage to the bonding sites, and this technique is especially well suited to the prefe~Ted la~er ablatlon. which may be terminated upon genera~on of the said indication. The second per~orating operation, for e~ple chemteal etching, may - then be ùsed to complete the pe~foration through the indicator layer to the underlying bonding sit~s.

The method.according to this invention:may:lnclude the step Of applying the indicator. layer..preferably by spin :or -spray coating, althnugh=other-te~ique~may be .u~ed.~ e indicator layer may comprise any material whlch iwlll generate - a suitable -indication when the first perforatlng 03eration reaches it, for example by :gerlerating colourj~-ln -~an, f.etc~lng .t l~uidrrior by: emitting a characteArlstic j detectable .light if requerlcy .when ablated -by the aforeme~tloned,~Jult,r,aj,,violet~ excimer3~1aser,~ or,o.by..r:emltting character~stic ion~ which co~lld be detected by mass spectrometly.
By. way of example, the indicator layer might comprise the phosphosilicate glass laycr which i~ often already present and in .
, 20~7 42~3 PCr/GB91/01 l72 this case has not yet been etched away to reveal the bonding sites, and could the~ be finally etched away after it has served as the indicator layer for the present purposes. If the chip is passivated (nuker the indication layer~ with silica or silicon nitride, it amy be desirable to open the bond pad windows after the laser drilling. for example by known etching techniques such as CF4/02 plasma etching of silica. or SF6 etching of silicon nitride. Known etch resists such as the "Spectrum Mega" range available from Micro-Image Technology Ltd, of Derby, or "Shipley 14QO" plasma etch resists could be applied to protect the insulating layer if it is not itself sufficlently reslstant to the etching process used.
.
Alternatively, an additioIlal indicator layer could be applied before or af~er etching of the silica or other layer to reveal the bsnding sites, examples of suitable indicator layers of this kind including fllm-forming fluropolymers. Preferred examples of such polymers indude coatable pol~lmide~ av~lable ~om Hoechst under the Trade Marks "S~xef-33" and "S~cef-44" corresponding to the general formula t /co~ ~ ~
-, If applied ~after: the etchlng of thè ~ silica or other layer to . reveal.the.bo~ding sltes, this lndicator lay~r` w~ld rest directly on ~: the :bondlng sites. leavlng -only its o~m materi~l to bé-removed after -i~perforation of .the overlying insulator layer. ;; -: f -~

"~The, addltional indicator material ~could'~if preferred be ,iremoved,..e.g. by~chemical etching through5a'photoresist to leave ~^- the indicator layer overlylng only the bonding sites. ~

.. The method according to the invention may also include the : step of applylng the lnsulatlng layer, preferably by spi~i or spray .,.
..

WO 92J02038 ~0 8 7 ~ 2 9 PCr/CBgl/01172 :
coating, although other techni~ues may be used. The insuiating layer may comprise organic polymeric material. preferably polyimlde or ~1ternatiYely epoxies, or may alternatively comprise inorganic matenal such as phosphosilicate or borophosphosilica~e glass. The insula~dng layer may be subsequently removed, par~ly or completely. for example by etching or dissolving in a suitable solvent. Where only partial removal is desired in order to provide pro3ecting ends of the metal within the holes. a removable layer may be provlded overly~g the iIlsulating layer. which removable layer may be di~solved or etched away to expose the ends of the conduc~ve material deposlted within the holes and to expose the surface of the in~ulatlng layér. Such a removable layer may comprise, for example. organic polymeric material, preferably amosphous polyamlde.

The deposit~on opera~on preferably produces a tubular formatlon of the electrlcally conductive material in the holes, although deposltion may be conl:inued until the holes are completely fllled, or ~lternatl~vely fllllng ma~erlals such as solder may be lntroduced lnto khe tubular format:lan. A preferred deposltion operation in~olYes sputteriIlg of metal, preferably chromium followed by eopper. OIitO the bondixlg pads and ~hè
interlor surface of the holes. followed if neees~a~y by removal of ~hé
metal f~om the main sur~ce of the insula~ing layer. The chromium and copper are par~eularly us~ on bond~ng pads of aluminium to pro~de a surface onto Yrhlch further metal may be platéd; ~he deposlltion operation may in~rolYe élect:roless pla~g of n~e~al, for example nickel. onto the`su~fa~es wlthin the holes. ~oliowed~by the removal of any^metal which may have been elec1:rolessly plated on t~ie` m~i~` si~facè of t}~e ir~sula~g layer.; Such eléc~oless;pla~g mày`deposlt t}ie plated mètal d~ctly orlto the~suitably ca~alvsèd surfaces of the holes. or on~o pre~rlously deposited metal such as the aforementlorled sputtered metals. Electrolëss plating direetly onto the bonding pads wlll depend on the metals used in ~he pads and for the placing. The deposlt~on operat~on may also involve applica~on of solder, for example by èvaporaiion ihrough `a shadou-f WO 92/0203g pcr/cs9~ 31172 2~87 ~2~

mask. into the holes and/or onto metal already in the holes Any applied solder may subsequently be re-flowed to improve its formation and adhesion.

Other aspects included in this invention are an integrated circuit semiconductor devlce. especially a ~h~p, provided with electrically conduc~ve materlal on one or rnore of the bonding sites by a me~hod as here~before described; and an integrated circuit sem~conductor device. especially a chip, having on its sufface an adherent lndicator layer as hereinbefore descr:ibed, which may also have adhered to the indicator layer an i~sulating layer preferably as herelnbefore described.
r The various layers according to this invention may be applied to the integrated circuit chlps or to multi-chip modules or wafer-scale integrated circults by any approprlate mean5, for example by melt castir g or solvent cast~g instead of the pre~erred SpUl or s~ray coati~g methods akeady me~tioned.~ It is especially advantageous to per~o~m the method of the present invell~on on . , .. ... `, . . -. . . .
semlconductor w~fers bé~ore they are ~diced ~nto individual chips. ~
... ~ ...... . . ........ . . . .
: ~ ~Espécially prèferred po y~mide mate~lals ~or the insulat~glayer are those which a~e capable of being applied ~as a liquid solutlon~~ followé~d by evaporatiori of the liquid and thermal treatment to provide a sollcl layer. preferably a cured layer.
E~amplës of such maltor~ls ~ude well~ own coatable polyi~des su~ as ~osè ~vail~blé from National Starch and Chemicai Corp ~inder t~i`e '~e~mid" Trade Ma~k, or tl~ose ata~lable from Du Pont H~ ii and Brewër ~ienoe l~ic. (Missoûri).

Alternatively, it may be destrable to adhere films OI
polyimides such as ~io5e avallable under the Trade M~rk "UPILEX"
from Ube/ICI. One of these, "UPILE;X R", is bëlleved to be a relatively completely ~ycll~eei polymer h~g a repeat uni~ derived from blhenyl dianhydride and diaminodiphenylether, viz.
.

- ~ .. , ; :
, . .

WO 92/02038 2 0 3 7 4 2 9 PCl'/GB91/01172 ~N~ O~ j\

n Most preferred. however. is "UPILEX S", whlch is believed to ha~re a repeat unit derived from the same anhydride and phe~ylene : diamine, v~z.
. r ~ ~N~ ~ ~
... ......... . .... .. ...
The polyimide deriYed from the biphenyldianhydride and 4,4'-diaminobiphenyl may have thermal expanision characteristics which are par~icularly well suited to microcircuit requirements.
I~e ;corresponding polymers ~deri~ed ~from isomers of the diamines mentioned above. e.g. the 3,4'-or 3,3'-diamo isomers..may~`~lso be useful, as may the correspond~g polymers derived from py~om~tic1di,~hydride instead of.the biphenyldiarihyd~de. ~f riI,n~.these,case,ithe ma~erial used to adhere the:polyimide fllm to the microcircult device could serve as the indlcator.layer.;

'The polyimide could also be formed in situ by applying a precursor in the form of the appropriate polyamic acid and cyclislrl~ lt to ~orm the polytm~de on Ih- chip sur~ace.

.... . , :... . ;

- , . .. .

WO 92t02038 . . ~ Pcr/Gss1/0l172 20~7 ~ 8 -i For the through-holes previously mentioned. laser drilling, preferably by ablative photodecomposition using a U.Y. excimer laser, has the advantage of producing through-holes with less pronounced taper than altemative chemical etching methods, the lower degree of taper permltting closer pitch (hole-to-hole spacing). ThiS is clearly advantageous. given that microcircuits.
with which the present invention may be used, are becoming progressively smaller and more densely patterned. Through-holes with taper (measured on ~he substantially straight inner portions of the holes~ less than 10, preferably less than 8, more preferably less than 6, and especially less than 4 (relati~re ~o the axis of the through-hole) can advantageously be achieved by laser dr~ ng according to the present inventlon. Thls is especially usehll for the generally preferred holes of less than 200 micrometres diameter, e.g. S to 150 m~crometres or 10 to 100 micrometres, and especially less than 50 mlcrometr2s diameter.
.
;~; If a soluble over-layer is to be provided on the insulating layer, poly.amides are preferrèd as aforementioned. especially amorphous - polyamlde.
' .
It is an advantage of this im~en~on that the polyamides adhere tenaciously to the polyimide. fare readily and cleanly la~er-drillable . at the preIerred wavelengths, ancl are readily removable by suitable - solvents..when deslred. ~

, c~ ~r . ~;,., Preferred amorphous~ polyamidles include - âliphaiic`~aroma~ie (A) polyamides--based.on ~e conden~ation of tereph~halic acid wlth trlmethylhfexamethylene diamine (pre~erably containing ?a--~aimixture of a2~Z;4-~7i~`and s 2,~4,~-trimethylh~`xamethylene diamine isomers),~if~ ?:. r - ~ f.~ '; e .

., ,. . . . . . , . .. . _ , .... .
~ . ... 7 .
.. .. .

,. .... . .
. : ,~ , . :
.

2087~29 WO 92/02038 PCI~/CB91/(11172 (B) polyam~des formed from the condensation of one or more bisaminomethylnorbornane isomers with one or more aliphatic, cycloaliph2tic or aromatic dicarbo~ylic acids e.g.
terephthalic acid and opt~onally including one or more amino acid or lactam e.g. epsiloncaprolaet~n comonomers, (C) polyamides based on units derived from laurinlactam, isophthalic acid and bis-(4-amino-3-methylcyclohexyl) meth~e, (D) polyamides based on the condensation of 2,2-bis-(p-aminocyclohe~yl) propane with adipic and æeleic acids. and polyamides based on the condensation of trarls-cyclohexane-1.4-dicarboxylle acid with the trimethylhexamethylene diamine isomers mentioned aboYe.
,~
(EJ po~amides based on units derlved from m-~ylylenediamine and ad~pic acid.
~, , Other preferred polyamldes ~nclude those based on polyether and polyamide blocks, especiall~ the so called "polyether-ester a:mide block copolymers" of repeating unit: -., ;. ., -, , . - - : ~ -, .. ", ., "0 ,.0 - , - - ;, ,, -' - .-~ .- ., ,, 1 . . _ ~ ' ' ' ' _ ' ;. wherein A represents ;a polyamide~ sequence of average molecular -~ sveight ln the range of from 300 to 15,000,.preferably from 800 ~o ; ~ ;; 5000, ~ and B represents a linear or brar~ched - polyoxyalkylene ~se~uence of alrerage molecular weight in the range of frorn 200 to .,6000, preferably;from 400 to 3000~ o ~

Preferably the -polyamlde se~uence is formed from alpha,omega-aminocarboxyllc -acids, lactams- or - . .. .
,, , .. ~ i,~

, WO 92/02038 PC~/CB91/01172 20874~ - IO-diamine/dicarbo~ylic acid combinations having C4 to C14 carbon chains, and the polyoxyalkylene sequence is based on ethylene glycol and/or tetrameth~lene glycol, and the polyoxyalkylene sequence constltutes from 5 to 85%, especially from 10 to 50% of the total block copolymer by weight. These polymers and their preparat~on are descrlbed in UK Patent ~;pecification Nos.
1,473,972, 1,532,930, 1,55,644, 2,005,283A and 2,011,450A. the disclosures of which are incorporated herein by reference.

The polymer preferably has a C:H ratio of not more than 0.9, more preferably not more than 0.75, most preferably not more than 0.65 and especially not more than ().55.

The total thickness of the per~oratable layer is preferably greater than that no~mally used in l.C. or multi-chip module processing. ~r example 10-250 micrometres, preferably 20-100, more preferably 25-50 mierometres.

Preferably, the electrlcally conductlve materlal within the holes comprises.metal plated on the interior surface of'che holes, and preferably each such conductive hole is electrically separate from substar~tially all the other such holes. The inventton includes the preferred chlp or other devlce produced by removal of at least part of the polyamide layer(~) from the surface of the insulating layer so as to leave the electrically conductive material in the holes pro~ecting beyond the main sur~ace of l:he l~yer. Substant~ally complete removal of the polyamide layer(s) is pre~erred.

- ~ ~A further layer of material may be plaoed on top of the second .(preferably.~polyamide) layer, for example to assist in removal of catalyst or flash coatings of metal from` thë su~face`be~oré an electroless plating step.~ Sultable materials`~or such further iayers overlying the pol~ramide mat~lal may be`~:selected, for example.
from polyacrylates, polymethacrylates, cellulose esters, lacquers, mould release agerlts. `or any other materlals having adequate adheslon to the underlylng layer and ade~uate removability, .
,- , ., .
, ., , : .

WO 92/02038 2 0 3 7 4 2 9 Pcr/GBg1~01l72 - 1 1 - , . .

preferably by means of a solvent which does not dissolve the underlying layer.

- ~ An example of the method according to the present invention will now be described in more detail w~th reference to the accompanying drawlng which shows schematically, and not to l~
scale, successive steps in the method.
. . . .
In step A a ~vafer of integrated circuit devices 10 with bondlng sites 11 s~hematlcally indicated on ~ts sufface has an end-point layer A of fluoropolymer (from Hoechst) spin coated thereon and drled by conventional techniques. In step B there is applied to the surface of the end-point layes~ A a layer B of a coatable polyimide materlal as herelnbefore described from National Starch, Du Pont, or Hitachi, agai~ applied by spin coa~ing followed by dr~ing and curing in conventional manner.- In step C there is applied to the surface of the polyimlde layer B a layer C of one of the preferred amorphous polyamlde mate~ials hereinbefore described, again by spin co~ng and dryirlg in con~entional manner. In step D a Kr~
ultra~olet exc~ner laser is used wlth suitable pro~ection imaging opiies -to deli~er`-sùiEflclentlj~i;hig~ fluënee to drill through the polyamide layer C:and pO~ ae làyer B un~l it reaches the-end-point- layer-`A; whic~i génerates -ablation products hav~ng a chàracteristic mass spèctrograph pe~ which- can be detected by a mass spectrograph sampllng tube pos~oned ciose to the abla~ion target. ~ Upon detection of that` ch~acteristic péa~ ;genérated by the end-polnt layer A~ the ia~èr~ ig is stopp'ed ~`In stëp`É`- the; ënd po~nt layer A i~ etched away to ;expose the underlying bonding sites li? ~In step F,:`~hromi~im,;thesi a ~ ure of chromii~m and copper `~'and`then:`copper~are spùttered ~to the holes ~rough shadow mask F ~to-provlde `an a~here~t metal coàting on th'e bo~ding sitës and on the side~ of 1~iè holes. ~In ~tëp G~ a layer of ~i~ckèl is-êléc~ole~sly plated onto the preced~ng metal coat~ng ~s~ig ~3 fir~ ~élèc~roless "nickel strlke" bath e.g. "ACR 2090" ~rom American Chemical ... , , , , . , ~ .. . . . . ...
-Reflning Co, followed by the maln' electroless nlckel pla~ng bath - "ACR 1305", with the usual sleanlI~g,'preparatloIl and rinsing steps.

..

-. . : ~ ,. ' !
.` :' ' . `: ``~ ' `.: ~ :

.
" ` '' ' . '; ' ~ ~

Wo 92/02038 pcr/cssl/o1172 ~3~7~9 - 12- rg In step H, solder is. applied to the nickel-plated tubes, for example by wave coating, or preferably by evaporation through a shadow mask similar to that in step F. The solder may be applied beyond the edges of the holes and may then be re-flowed to position it more preclsely in 'che tubes as indicated at H'. In step I, the removable polyamide layer C is dissolved away to leave the ends of the solder-contalrling tubes I pro~ecting from the polymer coating ~or convenient bondlng to o'cher electrical circuitry, in a manner sim~lar to lsno~n "flip chip" techniques. If desired, the poly~mide layer B rn~y also be removed by means of suitable solvents or other techniques, as indicated at I', and the end-point layer A may similarly bc removed if desired as indicated at I". The soldering step (H) could be performed after the removal step (I) if solder is desired on the outside of the metal tubes as well as inside.
.
Thus, an integrated micro-clrcuit devlce with pro~ecting electrlcal connectinns of Felatively high aspect ratio is produced which is suitable for vertlcal con~ection to ~e aforementioned ot~er circuitryO

; For.~ermocompression bonding..the solder may be replaced ~th gold or.other ermocompression-bondable.metal plated or otherwlse applled to 'che ends of the,pl~ated metal b~bes within the holes in the polymer !ayers. In this ~case, especially pre~erred pol~de materials for the ~nsulating layer are those.which are ;capable ofiretaiTling at.least.50%. preferably at,least.75%, more preferably at.least 85%. of their original elorlga~on afterSi~nersion in water, of pH 10 at 100C for fsur days aceording to ~SIM Ds882.
It ~ll be .readily.~understood .that ,a ~sufficiently fullyrcyclised polylmide having less than 59fo, or if possib!e substantially. no open . imiide ~ings .or uncyclised amic acid grouplngs may~be preferable to survlve hot all~line metal plating.baths, ~which- attack.know pol~des sllch as Kapton ~) ~ n ~ J:?.~.'?"~ j OJ{~

I~e integrated circuit device5 referred to could ~r example be silicon or gallium arsenide microchips for "flip ch~p" mounting .
. . .

.. .
;, , ~ , ,: ,.
.. ..
.~

WO 92/02038 2 0 8 7 4 2 9 P~r/GBg1/01172 in intercomlect circuitry packages. for exa~nple ~an-out circuit boards or mul'ci-chip modules.
~;' ~rl Although one hole per chip bonding site may be sufficient in many cases, it is possible, owing to the high precision of the preferred techniques described, to drill more than one smaller hole per bonding site, so as to provide a degree of duplication and possibly hlgher reliabill~r in use. I~e holes wi~l preferably have a tortuosi'y factor (mean path length/sheet thickness) less than 3, preferably less than 1.2: and will preferably have an aspect ratio (length/diameter) of at least 2.5.

The preferred conductive materials are me~ls. preferably plated, especially electrolessly plated. on the inte~ior of the holes.
~xample~ of sultably applicable metals indude Ni. Cu, Au. Pd.

The tubular form of 'the plated metal can be used to pro~de rela$hely tall "posts" of solder or other fusible metals, e.g. indium, lead-tin, gold~ , lead, tin, lead-lndium. supported by the tubular formation.

. , - . : . .
.- ~ ,; ., :, : . .
- .. , .. , ~ .: : .

, . `, ~
.

. . .

Claims

CLAIMS:

1. A method of providing an integrated circuit semiconductor device with electrically conductive material projecting from the device bonding sites for bonding to a matching array of electrical contacts with which the device will be face-to-face in use, comprising (a) providing an electrically insulating layer at least 5 micrometres thick adhering to the surface of the device with one or more holes through the insulating layer communicating with a bonding site, (b) depositing electrically conductive material within the hole(s) to establish electrical connection to the bonding site(s), and (c) excluding, or if necessary removing, deposited conductive material from the main surface of the insulating layer, so as to provide the conductive material substantially only within the said hole(s).

2. A method according to claim 1, including the step of removing some or all of the insulating layer to expose at least part of the conductive material deposited within the hole(s).

3. A method according to claim 1 or 2, including the step of perforating the insulating layer to provide the said hole(s), the perforation preferably being at least partly effected by U.V. laser ablation, preferably using an excimer laser.

4. A method according to claim 3 wherein an indicator layer is provided at the interface of the said insulating layer and the device which indicator layer comprises material which generates a detectable indication when directly acted upon by a first perforating operation, and the first perforating operation is moderated, or is replaced by a gentler second perforating operation, upon detection of the said indication.

5. A method according to claim 4, wherein the first perforating operation is U.V. laser ablation, which is terminated upon detection of the said indication.

6. A method according to claim 4 or 5, wherein the second perforating operation is chemical etching and is used to complete the perforation through the indicator layer to the underlying bonding site(s).

7. A method according to claim 4, 5 or 6, including the step of applying the indicator layer, preferably by spin or spray coating.

8. A method according to any of claims 4 to 7, wherein the indicator layer comprises a fluoropolymer.

9. A method according to any preceding claim, including the step of applying the insulating layer, preferably by spin or spray coating.

10. A method according to any preceding claim, wherein the insulating layer comprises organic polymeric material, preferably polyimide.

11. A method according to any of claims 1 to 9, wherein the insulating layer comprises inorganic material, preferably phosphosilicate glass.

12. A method according to any preceding claim, wherein a removable layer is provided overlying the insulating layer with the said hole(s) passing through both layers, and the removable layer is removed to expose the end(s) of the conductive material deposited within the hole(s).

13. A method according to claim 12, wherein the removable layer comprises organic polymeric material, preferably amorphous polyamide.

14. A method according to any preceding claim, wherein the deposition operation produces a tubular formation of the electrically conductive material in the hole(s).

15. A method according to any preceding claim, wherein the said holes are 5 to 200 micrometres, preferably 10-100 micrometres in diameter.

16. A method according to any preceding claim, wherein the total thickness of the layer(s) on the said surface of the device is 10-250, preferably 20-100, more preferably 25-50 micrometres.

17. A method according to any preceding claim, wherein the deposition operation involves sputtering, evapouration, or ion plating of metal, preferably chromium followed by copper, onto the bonding pad(s) and the interior surface of the hole(s), followed by removal of the metal (if any) from the main surface of the insulating or other layer.

18. A method according to any preceding claim, wherein the deposition operation involves electroless plating of metal, preferably nickel, onto the surface(s) within the hole(s), followed by removal of any metal which may have been electrolessly plated on the main surface of the insulating or other layer.
19. A method according to any preceding claim, wherein the deposition operation is followed by application of solder, preferably by evaporation through a shadow mask, into the hole(s) and/or onto metal already in the hole(s).

22. An integrated circuit semiconductor device, preferably a chip, ahving on its surface an adherent indicator layer as specified in any of claims 4 to 8.

23. A device according to claim 22, having adhered to the indicator layer an insulating layer. preferably as specified in any of claims 10 to 13, with or without further removable layers overlying the insulating layer.
CA002087429A 1990-07-18 1991-07-16 Processing microchips Abandoned CA2087429A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB909015820A GB9015820D0 (en) 1990-07-18 1990-07-18 Processing microchips
GB9015820.5 1990-07-18
PCT/GB1991/001172 WO1992002038A1 (en) 1990-07-18 1991-07-16 Processing microchips

Publications (1)

Publication Number Publication Date
CA2087429A1 true CA2087429A1 (en) 1992-01-19

Family

ID=10679291

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002087429A Abandoned CA2087429A1 (en) 1990-07-18 1991-07-16 Processing microchips

Country Status (8)

Country Link
US (1) US5411918A (en)
EP (1) EP0539481B1 (en)
JP (1) JP3091222B2 (en)
AT (1) ATE171813T1 (en)
CA (1) CA2087429A1 (en)
DE (1) DE69130290T2 (en)
GB (1) GB9015820D0 (en)
WO (1) WO1992002038A1 (en)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4228274C2 (en) * 1992-08-26 1996-02-29 Siemens Ag Method for contacting electronic or optoelectronic components arranged on a carrier
US5843363A (en) * 1995-03-31 1998-12-01 Siemens Aktiengesellschaft Ablation patterning of multi-layered structures
US5587342A (en) * 1995-04-03 1996-12-24 Motorola, Inc. Method of forming an electrical interconnect
GB2307785B (en) * 1995-11-29 1998-04-29 Simage Oy Forming contacts on semiconductor substrates for radiation detectors and imaging devices
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US5874369A (en) * 1996-12-05 1999-02-23 International Business Machines Corporation Method for forming vias in a dielectric film
US6008070A (en) * 1998-05-21 1999-12-28 Micron Technology, Inc. Wafer level fabrication and assembly of chip scale packages
US6627998B1 (en) * 2000-07-27 2003-09-30 International Business Machines Corporation Wafer scale thin film package
US6521485B2 (en) * 2001-01-17 2003-02-18 Walsin Advanced Electronics Ltd Method for manufacturing wafer level chip size package
CN1287945C (en) * 2001-03-22 2006-12-06 埃克赛尔技术有限公司 A laser machining system and method
JP4672199B2 (en) * 2001-07-10 2011-04-20 富士通株式会社 Electrical interconnection method
TW533188B (en) * 2001-07-20 2003-05-21 Getters Spa Support for microelectronic, microoptoelectronic or micromechanical devices
US7361171B2 (en) 2003-05-20 2008-04-22 Raydiance, Inc. Man-portable optical ablation system
US7115514B2 (en) * 2003-10-02 2006-10-03 Raydiance, Inc. Semiconductor manufacturing using optical ablation
US8921733B2 (en) 2003-08-11 2014-12-30 Raydiance, Inc. Methods and systems for trimming circuits
US9022037B2 (en) 2003-08-11 2015-05-05 Raydiance, Inc. Laser ablation method and apparatus having a feedback loop and control unit
US8173929B1 (en) 2003-08-11 2012-05-08 Raydiance, Inc. Methods and systems for trimming circuits
US20050167405A1 (en) * 2003-08-11 2005-08-04 Richard Stoltz Optical ablation using material composition analysis
US20050253245A1 (en) * 2004-05-12 2005-11-17 Mark Lynch Package design and method for electrically connecting die to package
US7575999B2 (en) * 2004-09-01 2009-08-18 Micron Technology, Inc. Method for creating conductive elements for semiconductor device structures using laser ablation processes and methods of fabricating semiconductor device assemblies
US9929080B2 (en) * 2004-11-15 2018-03-27 Intel Corporation Forming a stress compensation layer and structures formed thereby
US8135050B1 (en) 2005-07-19 2012-03-13 Raydiance, Inc. Automated polarization correction
US8232687B2 (en) 2006-04-26 2012-07-31 Raydiance, Inc. Intelligent laser interlock system
US7444049B1 (en) 2006-01-23 2008-10-28 Raydiance, Inc. Pulse stretcher and compressor including a multi-pass Bragg grating
US8189971B1 (en) 2006-01-23 2012-05-29 Raydiance, Inc. Dispersion compensation in a chirped pulse amplification system
TWI287273B (en) * 2006-01-25 2007-09-21 Advanced Semiconductor Eng Three dimensional package and method of making the same
TWI293499B (en) 2006-01-25 2008-02-11 Advanced Semiconductor Eng Three dimensional package and method of making the same
US7822347B1 (en) 2006-03-28 2010-10-26 Raydiance, Inc. Active tuning of temporal dispersion in an ultrashort pulse laser system
CN102149509B (en) * 2008-07-09 2014-08-20 Fei公司 Method and apparatus for laser machining
US8125704B2 (en) 2008-08-18 2012-02-28 Raydiance, Inc. Systems and methods for controlling a pulsed laser by combining laser signals
EP2200412A1 (en) 2008-12-17 2010-06-23 Nederlandse Organisatie voor toegepast-natuurwetenschappelijk Onderzoek TNO Flexible electronic product and method for manufacturing the same
KR101023296B1 (en) * 2009-11-09 2011-03-18 삼성전기주식회사 Forming method of post bump
JP5609186B2 (en) * 2010-03-18 2014-10-22 株式会社リコー Toner carrier, developing device, and image forming apparatus
WO2012021748A1 (en) 2010-08-12 2012-02-16 Raydiance, Inc. Polymer tubing laser micromachining
WO2012037468A1 (en) 2010-09-16 2012-03-22 Raydiance, Inc. Singulation of layered materials using selectively variable laser output
US9070851B2 (en) 2010-09-24 2015-06-30 Seoul Semiconductor Co., Ltd. Wafer-level light emitting diode package and method of fabricating the same
US9245828B2 (en) 2012-07-11 2016-01-26 Mindspeed Technologies, Inc. High speed signal conditioning package
US9433083B2 (en) 2014-04-04 2016-08-30 Macom Technology Solutions Holdings, Inc. Edge mount connector arrangement with improved characteristic impedance
CN205944139U (en) 2016-03-30 2017-02-08 首尔伟傲世有限公司 Ultraviolet ray light -emitting diode spare and contain this emitting diode module
CN111508926B (en) 2019-01-31 2022-08-30 奥特斯(中国)有限公司 Component carrier and method for producing a component carrier

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3893156A (en) * 1973-06-29 1975-07-01 Ibm Novel beam lead integrated circuit structure and method for making the same including automatic registration of beam leads with corresponding dielectric substrate leads
US4398993A (en) * 1982-06-28 1983-08-16 International Business Machines Corporation Neutralizing chloride ions in via holes in multilayer printed circuit boards
US4417948A (en) * 1982-07-09 1983-11-29 International Business Machines Corporation Self developing, photoetching of polyesters by far UV radiation
JPS6130059A (en) * 1984-07-20 1986-02-12 Nec Corp Manufacture of semiconductor device
US4824802A (en) * 1986-02-28 1989-04-25 General Electric Company Method of filling interlevel dielectric via or contact holes in multilevel VLSI metallization structures
US4764484A (en) * 1987-10-08 1988-08-16 Standard Microsystems Corporation Method for fabricating self-aligned, conformal metallization of semiconductor wafer
JP2633586B2 (en) * 1987-10-21 1997-07-23 株式会社東芝 Semiconductor device having bump structure
FR2630588A1 (en) * 1988-04-22 1989-10-27 Philips Nv METHOD FOR MAKING AN INTERCONNECTION CONFIGURATION ON A SEMICONDUCTOR DEVICE, IN PARTICULAR A HIGH INTEGRATION DENSITY CIRCUIT
US4861425A (en) * 1988-08-22 1989-08-29 International Business Machines Corporation Lift-off process for terminal metals
JPH0279437A (en) * 1988-09-14 1990-03-20 Mitsubishi Electric Corp Manufacture of semiconductor device
DE68914080T2 (en) * 1988-10-03 1994-10-20 Ibm Contact stand structure for semiconductor devices.

Also Published As

Publication number Publication date
ATE171813T1 (en) 1998-10-15
DE69130290D1 (en) 1998-11-05
WO1992002038A1 (en) 1992-02-06
EP0539481A1 (en) 1993-05-05
DE69130290T2 (en) 1999-06-02
JP3091222B2 (en) 2000-09-25
US5411918A (en) 1995-05-02
EP0539481B1 (en) 1998-09-30
GB9015820D0 (en) 1990-09-05
JPH05509441A (en) 1993-12-22

Similar Documents

Publication Publication Date Title
CA2087429A1 (en) Processing microchips
EP0690490B1 (en) Method of making a flip chip using electrically conductive polymers and dielectrics
US6852931B2 (en) Configuration having an electronic device electrically connected to a printed circuit board
US7319275B2 (en) Adhesion by plasma conditioning of semiconductor chip
US6555460B2 (en) Methods for mask repattern process
US5007163A (en) Non-destructure method of performing electrical burn-in testing of semiconductor chips
Christiaens et al. UTCP: A novel polyimide-based ultra-thin chip packaging technology
Wang et al. Fabrication and characterization of flexible ultrathin chip package using photosensitive polyimide
CA1321659C (en) Uses of uniaxially electrically conductive articles
Govaerts et al. Fabrication processes for embedding thin chips in flat flexible substrates
US20090175022A1 (en) Multi-layer package structure and fabrication method thereof
Wang et al. Laser-assisted bumping for flip chip assembly
Kuo et al. Flexible and ultra-thin embedded chip package
EP4271145A1 (en) Manufacturing a component carrier using a protection layer
US6914328B2 (en) Electronic component with an insulating layer formed from fluorinated norbornene polymer and method for manufacturing the insulating layers
Topper et al. Thin film substrate technology and FC interconnection for very high frequency applications
Francomacaro et al. Ultra-thin flexible microcircuit assemblies using thinned die and multilayer thin-film substrates

Legal Events

Date Code Title Description
FZDE Discontinued