CA2087092A1 - Solid state electromagnetic radiation detector - Google Patents

Abstract

The present invention provides a large area, high pixel density solid state radiation detector (10) with a real-time and a non-destructive read-out. The solid state detector (10) comprises a plurality of field effect transistors (11) deposited onto a substrate (12) to form an array. A planarization layer (19) is deposited over the array of transistors (11). An energy sensitive layer (20) is deposited onto the planarization layer (19). Means (21) is provided for electrically connecting the energy sensitive layer (20) with each transistor (11) of the array. A top electrode layer (23) is deposited onto the energy sensitive layer (20). The solid state detector (10) also comprises circuitry means (17, 18) for providing electronic read-out from each field effect transistor (11) of the array.

Description

W092/02959 ~ 0 8 7 0 9 2 PCT/US91/~260 SOLID STATE ELECTROMAGNETIC RADIATIOh~ DETECTOR

. TECHNICAL FIELD

The present invention relates to a solid state detector for detecting electromagnetic radiation, and ~ ~;
. more particularly to a large area, high pixel density '~ solid state detector based on a two dimensional array of : field effect transistors and an energy sensitive layer . 10 coating the array.

~;: BACKGROUND ART
:,,.
Solid state electromagnetic radiation detectors :~ 15 have been developed for consumer, commercial, scientific, .~ medical, military and industrial applications. Consumer applications range from video to high density television.
. Industrial uses include robotic and machine vision;
` electronics imaging for advertising and communication;
integrated text; and images in office work and publishing. Image sensors are also used for medical (mammography, chest x-rays), astronomy, spectroscopy, surveillance, airport luggage inspection, inspection for . . - foreign objects-in.foodstuffs, non-destructive testing in ~; 25 .industry, and many other applications.
.. Solid state devices used for detecting . - electromagnetic radiation, such as x-rays, infrared radiation, ultraviolet radiation, and visible light, ~ store the imagé momen.tarily and then, after-a selected - 30 - time interval, convert the image to an electrical signal.
..- . A variety of solid state detectors are known. One type --.. of solid state detector is the "hybrid" detector. A
.hybrid detector..generally comprises a pyroelectric . material that is bonded to a field efect transistor ("FET"). The FET in such detectors is used as an amplification means to amplify the signal from the detector before the signal is sent to the read-out ,,. . ' ' ! ," " ' ' ' ' !: ' '.
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~; electronics. Crystalline pyroelectric materials such as strontium barium niobate, lead titanate, and triglycine -~-; sulfate ("TGS") are well known in the art. In addition, films of organic polymers such as polyvinylidene fluoride and polyacrylonitrile have also been used as pyroelectric materials.
For example, V.S. Pat. No . 3, 809, 920 ~eaches ; the use of a polyvinylidene fluoride film in conjunction with an FET as being an effective and useful infrared radiation detector.
~; U.S. Pat. No. 4,024,560 discloses an infrared detector which is a combination of a pyroelectric body secured by electrostatic bonding to the gate area of a field effect transistor such that the pyroelectric body is interposed between the semiconductor body and the gate electrode. In this position, the pyroelectric body forms the gate dielectric of the device. A pyroelectric crystal is typically cleaved, or cut, to form the pyroelectric body.
~ Japanese ~okai (Laid-Open) Publication JP58-182280 discloses a photodetector comprising a thin film FET an~ a pyroelectric material. The pyroelectric material forms-the gate dielectric layer in this device.
Previously ~nown hybrid structures suffer from a number of drawbacks. One drawback of hybrid structures concerns the pixel size of such devices. Generally, pixel size corresponds to the resolution of a detector.
A smaller pixel size means a higher density of pixels for higher-resolution. In previously~known hybrid structures, the pyroelectric material has been positioned ;:as thei-gate dielectric layer of the FET. As a result of - this approachj achieving smaller pixel sizes has been -- limited by the size^of the pyroelectric material.
:- ~ecause the pyroelectric material of these devices is .. .... . . .

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W092/02959 2 0 8 ~ 9 2 PCT/US91/04260 .
individually bonded to the field ef~ect transistor, it has been difficUlt to achieve pixel sizes on the order of 1 mm x 1 mm or less.
As another drawback, the aCtive detection area ~- 5 of such devices is, at most, only a few square ` centimeters in size.
: As another drawback, hybrid structures tend to be susceptible to harm caused by events such as radiation induced damage. For example, if too much voltage is applied to such detectors, such voltage can irreparably damage the pyroelectric material, i.e., the gate dielectric layer, of the FET. This kind of damage could impair the performance of, or even destroy, the detector.
As a consequence of these drawbacks, previously known hybrid structures have not been practical for high density, large area applications.
Solid state detector arrays have also been known. One type of solid state detector array is the charged coupled device ("CCD"). In essence, a CCD is a ~ shift register formed by a string of closely spaced MOS
capacitors. A CCD can store and transfer analog-charge signals, either electrons or holes, that may be introduced electrically or optically.
In Japanese Journal of Applied Physics, vol.
27, no. 12, December 1988, pp. 2404-2408, Hiroshi Tsunami et al. discuss the application of CCD's to take x-ray images of about 8 keV and 1.5 keV for different objects.
High resolution C~D sensors which have more than 2 to 4 million pixels have also been reported, for example, in 30 the Proceedings of Electronic Imaging West, Pasadena, California, pp. 210-213 (February 25-28, 1990); and in Electronic, pp. 61-62 (February 29, 1988).
- ~ - The high cost of the CCD, however, has been a ~- barrier to widespread commercial acceptance of these 3 - 35 devices. CCD's, too, require an optical system in order to enlarge the field of view. The use of an optical . . . ~ . , . , . ; , ,, , . ,, . ~

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system, unfortunately, causes a significant reduction in quantum efficiency. This makes it impractical to use the CCD for large area detectors. To date, the largest CCD
~ array reported has been less than one square inch in ;~ 5 size.
-~ Amorphous silicon recently has become a material of choice in many solid state detector applications due to its capability for large area deposition and the low cost of amorphous silicon -detectors. A~orphous silicon-based solid state detectors generally have been in the form of a linear array. Such devices have gained widespread acceptance for use as monolithic, full page high resolution detectors, due to the following advantages: (1) large area deposition capability, (2) low temperature deposition, (3) high photoconductivity, (4) spectral response in the visible light region and (5) high doping efficiency.
An amorphous silicon linear array is discussed by Toshihisa Hamano et al. (Proc. of the 13th Conference on Solid State Devices, Tokyo, 1981, Japanese Journal of ~ Applied Physics, Vol. 21 (1982) supplement 21-1, pp.
- 245-249). In this structure, metal (Au, Ni, or Cr, thickness of'3,000 angstroms) is'used for the bottom electrode and Indium Tin Oxide tr'ansparent conducting film is used for the top electrode'. Glass plates ' - (Corning 7059, PYREX) are used for the substrate.
'- Amorphous silicon (a-Si:H)'film with a thickness of l micron is deposited by plasma-enhanced chemical vapor -- deposition technique onto the substrate.' i - ~ For'x-ray applications', U.S. Pat. No. 4,675,739 describes a solid state linear array made from photosensing elements. -Each'photose'nsin~' e'lement - --'includes back-to-back diodes':"one a photoresponsive diode -' and the other, a blocking'diode.'' Each of the diodes has ' 35' an'associated capacitance;formed by its electrodes. The - magnitude of the charge''remainlng'on a given capacitor is sensed and relates back to the intensity of the incident , .

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, radiation impinging upon the photosensitive diode. In this structure, an amplifying means, i.e., a field effect ` transistor is not used.
Solid state detectors in the form of a linear array, however, must be moved in order to get a ` two-dimensional image. This introduces a long read-out ,- time, which makes real-time read-out impractical. This drawback prevents the linear array detector from being used in applications where high speed is required, e.g., medical x-ray applications.
UOS. Pat. No. 4,689,487 describes the use of a large area solid state detector (40 cm x 40 cm). The solid state detector includes pixels in the form of a 2,000 x 2,000 matrix. ~ach pixel consists of a - 15 photodiode conductively connected in parallel to a capacitor. ~he photodiode and the capacitor are both then conductively connected to the drain of a metal-oxide-semiconductor field effect transistor (MOSFET).
The photodiodes are of a polycrystalline or amorphous material. This diode-MOSFET device has at least four main drawbacks. First, a non-destructive read-out cannot be used. Second, the sensitivity of the device is low.
Third,, the diode,has to operated in the forward mode in order to turn on the transistor.- Fourth, the device - 25 requires at least 8 complex-microlithography and deposition steps for fabrication, causing yields to be low.~
, U.S. Pat.-Nos. 4,606,871, 4,615,848, and - 4,820,586 disclose a pyroelectric material that is a 30 blend of polyvinylidene fluoride ("PVF2") and at least ,-~one,polymer miscible therewith at a temperature above the ,l, ,melting point- of the PVF2. The film may be polarized to render the:PVF2 blend pyroelectric and isotropically ;~ ~piezoelectric. ,Example 10 in each of these-patents .35 "~describes,the coating of an integrated circuit,slice of a ; '' j ~, , I, ' , . . .

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single crystal silicon chip with the PVF2 blend, followed by the sputtering of gold onto the surface of the PVF2 for poling.
.~ 5 DISCLOSURE OF INVENTION

The present invention provides a large area, high pixel density, solid state detector with a real-time and a non-destructive read-out. It is believed that the solid state detector of the present invention is the first practical, large area, high pixel den~ity solid state detector that is based on a two-dimensional array of field effect transistors ("FET' S~ ) .
The solid state detector of the present invention comprises a plurality of field effect transistors ("F~T' 8" ) deposited onto a substrate to form an array. A planarization layer is deposited over the array of FET's. ~n energy sensitive layer is deposited onto the planarization layer. Means is provided for electrically connecting the energy sensitive layer with each.FET of the array. A top electrode layer is deposited onto the energy sensitive layer. The solid state detector also comprises circuitry means for :. providing electronic-read-out from each FET of the array.
: .. The present invention enjoys a unique' combinatiQn of advantages. Because the energy sensitive layer is coated over the entire array of FET' S, patter~ing or individual.placement of the energy . sensitive.layer.onto each FET is not required. This 30- .greatly'simpIi'fies the fabrication process,'e`'specially when:the energy:sensitive layer:is:relatively:thick, :.. .::i.e.:, thicker::.thanll0 microns.- As a'~consequence'', the .solid state detector.'is amenable to'mass production ..techniques so that~large areaj solid state detectors can .35 ..be fabricated in.large numbers:at -relatively low cost.
Large area means that the detector may have a radiation detecting area greater in siæe than 10 cm x 10 cm.

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Further, the present invention also differsfrom previously known FET-containing, solid state detectors in that the energy sensitive layer of the present invention is not positioned as the gate dielectric layer of the FET's. Instead, the energy sensitive layer functions as an additional capacitance which is, in effect, connected in series with the gate capacitance of each FET of the array.
This approach provides at least two advantages.
First, this approach provides solid state detectors with ~' higher pixel density than previously known structures that are based on the FET. Accordiny to the present invention, pixel size is determined by the size of the gate region on each FET of the array. In preferred embodiments of the present invention comprising a plurality of thin film FET~s, the gate region of each FET
is extremely small. Sizes of from 20 microns x 20 microns to 50 microns x 50 microns are typical. As a result, pixel densities as high as 250,000 pixels/cm2 can be achieved.
Second, this approach provides solid state detectors that are less susceptible to harm caused by ' events such'as radiation induced damage. According to the present invention,' it is the energy sensitive layer 25 -'that'protects the solid state radiation detector from such harm. If a high voltage is applied to the detector, - the voltage of preferred embodiments will tend to drop mainly in the energy sensitive layer, whose capàcitance is typically lower thanithe gate capacitance. In this 30'' way,`damage to'the FET's ofjthe array is minimized.
The present-invention is also a real-time detector. Read~-out time's of the'detector of'from 1 to 4 ~~~ seconds'are feasible. Read-out time'is defined as the :' -time ela'psing'between''the time an-object is-subjected to illumination and the time an image appears on-the monitor.

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The present invention also has a non-destructive read-out. Non-destructive read-out means that the charge stored in the energy sensitive layer will discharge gradually over a period of time. This allows - 5 several readings to be taken at each exposure. The signal can then be averaged, thereby enhancing the signal to noise ratio.

BRIEF DESCRIPTION OF DRAWINGS

FIG. l is a cut-away isometric vie?~ of the solid state detector of the present invention shown in schematic with parts broken away and shown in section.
FIG. 2 is an electronic circui-t diagram of the solid state detector of the present invention shown in FIG. l.
FIG. 3a is a side section of a substrate useful , in the practice of the present invention.
FIG. 3b is a side section of a substratP useful in the practice of the present invention.
.FIG. 3c is a side section of a substrate useful in the practice of the present invention.
. , FIG. 3d.,is,a side section of a substrate useful ~ - , - . . . .
in the practice of the present invention.
, FIG. 4 is a side section of a solid state ,detector of the present invention.
.. , FIG. 5a is a side section of tne solid state detector shown in FIG. 4, wherein the planarization layer . has a double layer structure.
~- :;?: ' FIG. 5D is a side section of .the.solid state ?.,detector shown in FIG. 41 wherein the planarization layer , - has.a triple.layer structure.
FIG..5c is a side section of ,the solid,state .} .detector shown in ~IG. 4 further comprising a phosphor layer~

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20870~2 W092/02959 ~ PCT/US~1/04260 (, . _ g _ FIG. 5d is a side section of the solid state detector shown in FIG. 4, further comprising an additional insulating layer for charye storage.
FIG. 6 is a side section of an alternative c embodiment of the present invention.
FIG. 7 is the equivalent circuitry for one FET
of a solid state detector of the present invention.
FIG. 8 shows an apparatus useful for poling an energy sensitive layer which comprises a PVF2 blend.
DETAILED DESCRIPTION

A preferred solid state detector 10 of the present invention will now be described with reference to 15 FIG. 1 and FIG. 2. ~A plurality of thin film, field effect transistors ("FET's") 11 are deposited onto a substrate 12 to form an array. Preferably, the FET's 11 are aligned on the substrate 12 in rows and columns as shown in FIG. 1. However, the FET's 11 may be arranged in other patterns on the substrate 12. For example, adjacent FET's 11 may be offset up, down, or diagonal from each other. Each of the FET's 11 has a source electrode 13, a drain electrode 14, and a gate electrode 15.- As seen hest in FIG. 2, each FET 11 also has a gate 25 CaPaCitanCe ~ CG -- The solid state-detector 10 comprises circuitry - means for providing electronic read-out-from each FET 11 of the array. The design requirements for such circuitry `' '..A are described, for example, in L. Tannas, Jr.,~ed., Flat ,30 Panel_D_splays and CRT's, pp. 91-137 (1987); and S.
. . - ~Sherr, Electronic Displays, pp. 182-320 ~1979).
- - Preferablyj the circuitry~means comprises a plurality of - , source lines 17 linking the source electrodes-13 in each ; . row of FET's 11 and a plurality of drain lines 18 linking the drain electrodes 14 in each column of FET's 11. For - ; . :. , ,,, u .

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example, for an array comprising a 2000 x 2000 matrix of FET's, there will be 2000 source lines and 2000 drain lines in the solid state detector.
The ~arious source lines 17 and drain lines 18 5 should not be in electrical contaCt with one another.
That is, a source line should not contact other source lines or any of the drain lines, and a drain line should not contact other drain lines or any of the source lines.
For this reason, at least one planarization layer l9 is deposited over the array of FET~ S 11 in order to electrically isolate the source lines 17 and the drain lines 18.
An energy sensitive layer 20 is deposited onto the planarization layer 19. Means 21 is provided for electrically connecting the energy sensitive layer 20 with each FET ll of the array. Preferably, such means 21 electrically connects the energy sensitive layer 20 with the gate electrode 15 of each FET 11 of the array. AS
seen best in FIG. 2, using this preferred approach, the energy sensitive layer 20 functions as an additional capacitance, C~, which is, in effect, electrically connected in series with the gate capacitance CG of each FET-ll in the array. -: A top electrode layer 23 is'deposited onto the energy sensitive layer 20 in order to complete the solid :' - state detector 10. The top electrode layer 23 shown in ' FIG. 1 has not been patterned to form a plurality of top -electrodè elements. However, the top'electrode layer 23 - optionally may be patterned in a variety of ways, so long as the various top electrode elements~are electrically connected'together so as to form a:common top electrode.
For example, the top electrode layer 23~may be patterned ~' - '- sûch that there'is one'top electrode'`element for each FET
ll of the array. As another example, the top electrode -~35 -'layer'23-may be patterned such that''there-is`one top' electrode element for each row or column of FET's 11 in the array.

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W092/02959 2 0 8 7 0 9 2 Pcr/us~l/0~260 enerally, the solid state detector 10 works as follows. A power source 28 is used to apply a charge to the energy sensitive layer 20. Incident ~adiation causes a corresponding change in the charge of the energy sensitive layer 20. This change in charge, in turn, cauSes the gate voltage of the FET's 11 to increase or decrease, depending upon the type of FET used in the array. This change in voltage is detected as a difference in the drain-source current of the FET 11.
The difference in current is then amplified and detected as an output signal by the read-out electronics. As seen in FIG. 2, one possible read-out electronics scheme may include operational amplifiers 24 for boosting the analog signal from the FET's 11. This analog signal is then converted into a digital signal by an A/D converter 25.
The digital signal is then stored in the memory of a memory storage device 26. As is also shown in FIG. 2, source lines 17 are coupled to shift register 27.
Preferred substrates useful in the practice of the present invention are shown in FIGs. 3a, 3b, 3c, and 3d. FIG. 3a shows a substrate 29 comprising a flexible base layer 30. Generally, the base layer 30 is planar in shape. Useful materials for forming the flexible base layer 30 include stainless steel and polymers such as polyimide, polysulfone, or polyester. If the base layer -30-is formed from a polymeric material, the base layer 30 ; should be subjected to a conventional outgassing treatment before any other layers are deposited onto the base layer. Preferably, the base layer 30 has a ~3.0:~n.thickness of about 50 microns.
When the base layer 30 is formed from a polymeric material, it is preferred that the base layer - :.30 is first coated on both sides with top and bottom layers 31 and 32 of stainless steel as described in assignee's copending application United States Serial No.
~07/471,670 filed January 24, 1990, which is a ~

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continuation of United States Serial No. 07/163,520 filed March 2, 1988, now abandoned. ~ach of the stainless steel layers 31 and 32 preferably has a thickness of about 200 angstroms. The stainless steel is used to prevent or suppress the outgassing of low mass residual contaminants from the base layer 30.
Next, an insulating layer 33 is coated onto the top stainless steel layer 31. The insulating layer 33 is - used to electronically isolate the base layer 30 from the field effect transistors subsequently deposited onto the substrate 29. The insulating layer 33 also helps prevent impurities in the base layer 30 from diffusing into the field effect transistors. The insulating layer 33 may be prepared from any suitable material such as Sio , SiNx, lS silicon oxide nitride, or combinations thereof.
Preferably, the insulating layer 33 has a thickness of about 1 micron. Optionally, an additional insulating layer 34 may be coated onto the bottom layer 32 of stainless steel as is shown in FIGo 3b for the substrate 29'.
Another embodiment of a substrate 35 useful in the practice of the present invention is shown in FIG.
3c. In FIG. 3c, the substrate 35 comprises a rigid, nonpolymeric base layer 36. Usef~l materials for forming the rigid base layer 36 include silicon, glass, quartz, alumina, or metal. In this embodiment, an insulating layer 37 may be preferably deposited directly onto the top surface of the base layer 36 as needed in order to prevent impurities-from migrating from the base layer 36 into the FET's and/or to electronically-isolate the FET's from the base layer 36. Optionally, as shown in FIG. 3d, an additional insulating layer 38 may be deposited onto the bottom surface of the base layer 36 of the substrate 35'. ; - ~ ;
-~35 ~ FIG. 4 is a cross-section of a portion of a preferred solid state radiation detector 40 of the present invention, in which two thin film, metal-oxide-.,. , : , ~ : :
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2087~92 092/02959 PCr/US91/0~260 -13- i semiconductor field effect transistors ("MOSFET's") 41 of the array are shown. For purposes of clarity, source lines and drain lines are not shown in FIG. 4. As is known to those skilled in the art, each thin ~ilm MOSF~T
41 generally comprises a channel layer 42; a gate dielectric layer 43, i~e., oxide layer; insulating shoulders 44; source and drain regions 45 and 46; source and drain electrodes 47 and 48; a polysilicon gate 49;
and a gate electrode 50; each of which will be described in more detail below. In FIG. 4, the vertical dimensions of the variolls l~yers are greatly exaggerated for purposes of illustration. In actual practice, the total thickness of the solid state radiation detector 40 is from about 3 to about 600 microns.
As shown in FIG. 4, a channel layer 42 of an undoped semiconducting material is formed on the substrate 51 for each thin film transistor of the array.
The channel layer 42 can be formed in a variety of ways.
For example, a layer of the undoped semiconducting material can be deposited onto the substrate 51 and then etched or laser scribed to form the channel layer 42 or each MOSFET 41. Alternatively, a mask can be used to deposit the discrete islands of undoped semiconducting material onto the substrate 51 to directly form the channel layer 42.
- The channel layer 42 may be formed from any - undoped semiconducting material-suitable for large area - applications. Examples of such materials include hydroge~ated amorphous silicon, cadmium selenide, single-30- -crystal-silicon, and polysilicon. Single-crystal silicon-based FET' s are well known in the art and are -described,- for example, in S.M. Sze, Physics of -- Semiconductor Devices, 2d edition,~pp. 431-510 (1981).
When forming the channel layer-42 from : hydrogenated amorphous siliconj the hydrogenated ~~: amorphous silicon may be deposited using plasma-enhanced chemical vapor deposition at 200C to 350C from a , - ,.
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W092t02959 PCT/US~1/0~26~-2~87 0~2 gaseous mixture of SiH4 and hydrogen. Cadmium selenide may be deposited onto the substrate 51 by deposition techniques well known in the art. For example, by using a cadmium selenide source, thermal evaporation or sputterinq techniques may be used to deposit the cadmium selenide. Alternatively~ a cadmium layer and a selenium layer may be deposited onto the substrate 51 and then heat treated at 100C to 400C in an atmosphere comprising hydrogen selenide and argon in order to form the cadmium selenide layer. The cadmium and selenide layers may be deposited using electroplating or sputtering techniques.
Preferably, the channel layer 42 is formed from polysilicon. When forming the channel layer 42 from polysilicon, polysilicon can be deposited onto the substrate 51 using a variety of techniques, including:
(i) low pressure chemical vapor deposition at a temperature from 620C to 650C;
(iiJ deposition of amorphous silicon by low pressure chemical vapor deposition at a temperature from 520C to 540C, followed either by annealing at 620C to 1000C for 2 to 24 hours in a nitrogen atmosphere to form ` - ~ polysilicon, or by rapid thermal annealing at 620C for 1 to 4-minutes in a nitrogen atmosphere to form polysilicon;
(iii) deposition of amorphous silicon at 200C
to 300C via plasma-enhanced chemical vapor deposition, followed by furnace annealing, laser annealing, or rapid thermal-annealing;
~ (iv) high-temperature chemical vapor deposition of polysilicon at 620C, conversion of the polysilicon to amorphous silicon via ion implantation with-silicon ions, followed-by annealin~ at 620~C for 4 to 24 hours to form polysilicon. . ~
; ~ Typically, the channel layer 42 of undoped - ~ ; polysilicon has a thickness of from about 1000 to 3000 angstroms.-: Because polysilicon is deposited onto the :
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20870~2 92/02959 PCT/US91/0~260 .... -15-substrate 51 at relatively high temperatures, the base layer of the substrate 51 for the polysilicon-based MOSFET's should comprise a material that does not degrade at such temperatures, e.g., quartz, silicon, alumina, or glas.s.
An oxide, i.et, gate dielectric, layer 43 and insulating shoulders 44 are formed on the channel layer 42. To accomplish this, a layer of an insulating material, such as SiOX; SiNx, silicon oxide nitride, or combinations thereof, is grown by thermal oxidation on the channel layer 42. The layer of insulating material is then etched, or laser scribed, to form the insulating shoulders 44 and the gate dielectric layer 43. This process also uncovers two spaced apart surfaces on the : 15 channel layer 42 for the subsequent formation of source :: and drain electrodes 47 and 48, respectively.
A polysilicon gate 49 is deposited onto the - gate dielectric layer 43. Typically, the polysilicon gate 49 has a thickness of about 500 to about 3500 angstroms. Preferably, the polysilicon gate 49 is deposited onto the layer of insulating material before the layer is etched, or laser scribed, to form the insulating shoulders 44 and..the gate dielectric layer 43.
. ... Using the polysilicon gate 49 and insulating 25 ~ shoulders 44 as;a mask, the source and drain regions 45 and 46 are formed by using conventional ion implantation techniques to dope the source and.drain regions.45 and 46 with either boron ions (p-type) or phosphorous ions . In-type).. The~ion.concentration will vary with the 30 -~particular.electrical characteristics and sensitivity of ~ the desired detector.: As.an example, ion concentrations ; of lxl0l4.-:ions/cm2.. to 9x10l5 ions/cm2 are typical.
. . Ion~implantation to form.the source and drain regions 45.and.46.can.occur either.before or~after the layer of insulating material is etched, or laser scribed, to form the insulating shoulders 44 and the gate r W092/02959 2 0 8 7 ~ 9 2 Pcr/us9l/0426~

dielectric layer 43. If ion implantation occurs before such etching or laser scribing, then the polysilicon gate 49 should be relatively thick in order to stop the ions from entering the channel;.region 52 beneath the polysilicon gate 49. Préferably, ion implantation occurs after such etching or laser scribing. One advantage of this preferred approach is that the polysilicon gate 49 may be relatively thinner, since less ion implantation energy is used to form the drain and source regions 45 and 46. As another advantage of the preferred approach, plasma hydrogenation treatment of the FET's 41 is easier when the polysilicon gate 49 is relatively thinner. Such treatment is used to passivate the grain boundaries of the channel layer 42.
The source and drain regions 45 and 46 may or may not be of the same conductivity type. For example, both the source and drain regions 45 and 46 may comprise either p-type ions or n-type ions. Alternatively, one of the regions may comprise p-type ions, and the other region may comprise n-type ions.
When forming the drain and source regions 95 and 46, use of the polysilicon gate 49 as a mask provides - accurately defined source and drain regions 45 and 46.
Even when the size of the FET's 41 is extremely small, i.e., 10 to 20 ~m, ion implantation.will occur in the ~ source and drain regions 45 and 4~,:.but not in the ~ .- channel region 52 between the source and drain regions.
. .. The.various source electrodes 47, source lines -(not shown in FIG.:4), drain electrodes 48, and-gate 30 ~ electrodes-50 arelsimultaneously formed. Each source - : r- electrode 47 and drain electrode 48 is in ohmic contact with:the source region 45 and drain region 46, .respectively..; Each gate electrode 50 is positioned in : intimate contact with the polysilicon gate 49. -35 ~ ...... .. . . . - .
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, The various source electrodes 47, source lines, drain electrodes 98, and gate electrodes 50 may be formed by first growing a masking layer over the array.
Portions of the masking layer corresponding to the positions of the source electrodes, source lines, drain electrodes, and gate electrodes are then selectively removed. The electrodes and source lines are then formed by vapor or sputter deposition of a suitable contact metal over the entire surface of the masking layer.
Thereafter, unwanted metal is selectively removed from :' the masking layer by standard'photolithographic and etching techniques.
Sultable contact metals for forming the electrodes and the source lines include the common contact metals, such as molybdenum, chromium, aluminum, silicon-doped aluminum, nickel, silver, tin, indiu~, palladium, titanium, copper, platinum, and the like.
Typically, the electrodes and source lines have a thickness of from about 1000 to about 10,000 angstroms, and more commonly from about 1500 to about 5000 ' angstroms.
~he array of FET's 41 thus formed is then ....; .-. ;.annealed in a forming.gas of nitrogen and hydrogen at ' : about 400C for 30-minutes. Annealing enhances the . quality of ohmic contact between the source electrode 47 -. and the source region.45 and between the drain electrode 48 and the'drain regi.on 46. Annealing is followed by a plasma hydrogenation treatment at about 300C for 10-60 minutes~ This treatment passivates the grain boundaries ,of the-channel layer 42 with' hydrogen, thereby reducing ~ the amount:-of,~leakage current~from-the FET's 41 of the ~..;. ..~array. ~ ^ ~ 'J ' '`;' .~ .. A'planarization layer 53 is'coated over the ~ array of FET.'s~41.: -The planarization layer'~53-'is formed .from an:.insulating material such as SiOx,' SiNx,'`'silicon : '. oxide:nitride,~ orjcomb'inations thereofi ''-'The ''i--. . .
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. W092/02959 ' PCT/U~9]/0~2~
2087 0~2 pl~narization may also be formed from a polyimid~ such as Probimide 408 commercially available from Ciba-Geigy Corporation. Typically, the planarization layer 53 has a thickness of about l to 2 microns.
In some cases, as shown in FIG. 5a for the .:, solid state detector 40a, the planarization layer may be . a double layer comprising a first layer 53a of SiNX
having a thickness of about 3000 angstroms and a second layer 53b of SiOy having a thickness of about 3000 angstroms. Alternatively, as shown in FIG. 5b for the solid state detector 40b, the planarization layer may be a triple layer comprising .a first layer 53c of SiNy having a thickness of 2000 angstroms, a second layer 53d . of SiOx having a thickness of 2000 angstroms, and a third layer 53~ of SiNx having a thickness of 2000 angstroms.
Preferably, the planarization layer 53 has a "planarized", i.e., smooth, upper surface. The : planarization layer 53 may be planarized by coating the planarization layer with a 2 to 3 microns thick layer of a photoresist material. After forming the layer of photoresist material, the layer of photoresist material is etched down to the planarization layer to provide a , ,,smooth upper surface. Etching.:may be accomplished using ,reactive ion etching techniques in a gaseous.mixture of 25 CF4 and 2. The photoresist.mater.ial should be selected .so that the photoresist material has the same etch rate ,as the planarization layer 53.- Examples of such photoresist materials found to be.suitable in the practicc of the present invention are, for:example, ~- 30 ,Shipley AZ 5209 and Shipley AZ S214~ : As :another example,;~ a planarized surface.may be obtained..when using.Probimide 408 by first coating the material over the array of FET's ! ' ' -to a ,th,ickness of ~3 to 5 microns;.;After this, the , , Probimide 408 is.etched until a~smooth-sur.faced layer having a thickness of about -1 to 2.microns-.-is achieved.
Such etching may.be. accomplished.using.a reactive ion .:
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~087092 W092/02959 P~r/US91/04260 ~ ~ --19--etching technique in 2 plasma. In those cases where the energy sensitive layer 54 is relatively thick, i.e., thicker than about 10 microns, it is not necessary to planarize the planarization layer 53.
An energy sensitive layer 54 is deposited onto the planarization layer 53 to further coat the array of thin film transistors 41. Preferably, the energy sensitive layer 54 is deposited as a continuous layer over the entire planarization layer 53 without the need for any patterning steps. Advantageously, this feature of the invention significantly simplifies the fabrication process, especially when the energy sensitive layer 54 is - relatively thick, e.g., having a thickness of from about 10 to about 500 microns.
The energy sensitive layer 54 comprises a material for which incident radiation causes a corresponding change in the charge of the material. Many such materials are known and include amorphous selenium;
cadmium telluride; cadmium selenide; cadmium sulfide;
mercury cadmium telluride; selenium-based alloys;
telluride-based alloys; selenium-tellurium; hydrogenated amorphous silicon and alloys thereof; polyvinylidene fluoride ("PVF2-");~a blend of PVF2 and at least one polymer which is miscible ~ith PVF2 at a temperature above the melting point of PVF2; vinyl fluoride; vinyl chloride; vinylidene chloride; chlorofluorovinylidene;
trifluoroethylene; poly-N-vinyl-carbazole; trinitro-fluorenone; lithium niobate; lithium tantalate;
- Sr1 ~Ba20x; pyrargyrite; Tl3AsSe3; PbO;-ZnO; organic - 30 photoconductive materials; and the like.- -: The various materials useful for forming the energy sensitive layer 54 may be sensitive to x-ray, ultravioletj-infrared, and/or visible electromagnetic ~ radiation. For example, x-ray sensitive materials include amorphous selenium; cadmium selenide; cadmium ~-telluride; mercury cadmium telluride; cadmium sulfide :

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selenium-based alloys tellurium-based alloys; selenium-tellurium; hydrogenated amorphous silicon and alloys thereof; PbO; ZnO; or combinations thereof. Ultraviolet ; sensitive materials include PVF2; hydrogenated amorphous silicon and alloys thereof;"such as silicon carbide.
Visible light sensitive materials include hydrogenated amorphous silicon and alloys thereof; amorphous seleniu~;
cadmium selenide; cadmium telluride; cadmium sulfide selenium-based alloys; telluride-based alloys; selenium-tellurium; mercury cadmium telluride; and organic photoconductive materials. Infrared, i.e., pyroelectric materials, include PVF2; vinyl fluoride; vinylidene chloride; chlorofluorovinylidene; trifluoroethylene;
lithium niobate; lithium tantalate; Sr1 ~Ba2Ox;
pyrargyrite; and Tl3AsSe3.
When using hydrogenated amorphous silicon and alloys thereof to form the energy sensitive layer 54, the amorphous silicon generally is doped to obtain a high resistivity, i.e., 101 3 Q-cm, and a high photoconductivity, i.e., photocurrent to dark current ratio of 103 to 104. To provide an energy sensitive layer with such properties, the amorphous silicon may be doped with about 1 to 100 ppm of both boron and oxygen atoms. Alternatively, the amorphous silicon may be doped ,^ 25 with about 1 to 100 ppm of chemical elements from Group VI of the Periodic Table, .such as selenium or sulfur.
Such doping-techniques are well known in the art and are described, for example, in U.S. Pat. No. 4,265,991;
- -Shimizu, Semiconductors and Semimetals, vol. 21, part D, Academic Press, pp. 55 to 73 (1984): and Shimizu, Journal - of Non-Crystalline-Solids, vols. 77 and 78, pp. 1363 to 1372 ~1985). - -' ;- ; After forming the planarization layer 53, drain leads 60, drain lines (not shown in FIG. 4), and means for electrically connecting the energy sensitive layer 54 ~- with each FET 41 of the array are formed. Preferably, .

. .

! .. , ~ ' ' ', , 20~70~2 `~'~92/02959 ~ PCT/US91/04~6 such means is formed such that the additional capacitance of the energy sensitive layer 54 is e~fectively connected in series with the gate capacitance, i.e., gate dielectric layer 43, of each FET 41 of the array. Such means preferably comprises a contact plug 55 and a bottom electrode 56.
The drain lead 60, drain line, contact plug 55, and bottom electrode 56 may be formed by first using standard etching or lift-off techniques to uncover the drain electrode 48 and gate electrode 50. After this, the drain lead 60, drain line, contact plug 55, and bottom electrode 56 are formed from a suitable contact metal, such as those metals described above with respect to the various electrodes and the source lines.
For infrared applications, the top electrode layer 57 may comprise a conductive, radiation absorbing material for which incident radiation causes the temperature of the material to change. Examples of such materials include metals such as nickel, aluminum, gold, tin, indium, palladium, titanium, copper, and base metals thereof. Of these materials, gold and aluminum are more preferred.
For other applic-ations, the top electrode layer - 57 may comprise a transparent, conductive material which allows incident radiation to pass through and be absorbed by the energy sensitive layer and which functions as an antireflection layer to maximize the amount of light photons that reac~ the energy sensitive layer. Examples .
- of such materials inclur3e transparent conducting oxide ("TCO") materials, such as indium tin oxide,-tin oxide, cadmium tin oxidej and zinc oxide. Stacked structures, such as a TCO/Ag/TC0 structure or a~TCO/(Ag/TCO)n structure where n is preferably an integer from 1 to 3, ~ may also be used. Stacked structures are described, for example, in assignee's copending application, United States-Serial No. 280,838 filed December 7, 1988.

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W092/029~9~ ~ 8 7 0 9 2 PCT/~S91/042 The top electrode layer 57 can be formed by depositing the top electrode material over the entire energy sensitive layer 54. Optionally, the top electrode layer 57 may be patterned tb form a plurality of discrete top electrode elements, wherein all of the discrete elements are electrically connected to form a common top electrode. Patterning may be accomplished by removing unwanted material in between the FET' s 41 using standard etching techniques. Alternatively, using thermal evaporation or sputtering techniques, the common, top electrode elements can be deposited onto the energy sensitive layer 59 through a mask to directly form the discrete electrode elements without the requirement of a patterning step. Typically, the top electrode layer 57 has a thickness of from about 500 angstroms to 6000 angstroms for transparent conducting materials, and fro~
5000 angstroms to 3 microns for radiation absorbing materials. The lesser thicknesses are more responsive to ~'' incident radiation.
~ As shown in FIG. 5c for the solid state detector 40c, a phosphor layer 58 optionally may be deposited, or physically placed, onto the top electrode ~- layer 57 to make a-solid-state detector for detecting ; x-rays. For placing the phosphor layer 58 onto the top electrode layer, an-optically matched glue is preferably used to maximize the number of photons that reach the - energy sensitive layer 54. The phosphor layer'58 comprises a material that converts x-rays into light.
Examples-of su~h~materials include Gd2O2S:Tb; BaFBr:Eu;
~30 sr5Sio4; srS04; RbBr:Tl; and ZnS:Cu:Pb.' Such materials are:described, for example, in U."S. Pat. No.`4,011,454 and~European Patent Application No. 0175578-A3.
-; -As shown in FIG. 5d for the solid-state detector 40d,~ at least one additional, insulating'layer 35 ~ 59 may be interposed between the~planarization'layer 53 and-the'energy sensitive'layer' 54. 'The additional ,. :~ . ,, -; :
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: , :.: ,, , 2o87o92 f~/09~/0295~ p~T/ussl/o426o insulating layer 59 is used as a capacitance f~r ; additional charge storage and may comprise insulating materials such as SiNX, SiOy, and the like.
FIG. 6 shows another preferred solid state radiation detector 60 of the present invention in which the field effect transistors 61 are hydrogenated amorphous silicon-based MOSFET's. In FIG. 6, the ' materials and thicknesses of each layer are th- same as the corresponding layers described with reference to FIG.
4, unless otherwise noted. In FIG. 6, source and drain electrodes fi2 and 63 are deposited onto the substrate 64.
As one option, the substrate 64 may contain a base layer that is formed from a material such as quartz, glass, silicon, or metal. Yet, because hydrogenated amorphous silicon may be deposited onto the substrate ~4 at relativ~ly low temperatures, the base layer of the substrate 64 may also be formed from a flexible, polymeric material, e.g., polyimide, polyester, or polysulfone. Using conventional masking techniques, a 500 angstrom thick layer of n-type hydrogenate~ amorphous ~ silicon is deposited by plasma-enhanced chemical vapor ; deposition onto each source and drain electrode 62 and 63 to form the source and drain regions 65'and ~6, respectively.
A channel layer 67 of hydrogenated amorphous ~` silicon is deposited over the source and drain'regions 65 ' and 66. Typically, the channel layer-67 of hydrogenated amorphous silicon has a thickness of about 1000 to 10,000 angstroms,- and more preferably of about 5000'angstroms.
- ~ -A ga'te dielectric layer 68 is-'deposited onto ~ ~: the channel:layer-67; The gate dielectric layer S8 has a : thickness of from l000 to 5000 angstroms.' A~'gate ; eleetrode 69 (3000 to 5000 angstroms)'-comprising aluminum, chromium, or any other-suitable electrode '~ 35 material, is then deposited onto the gate dielectric '~ layer 68. Drain lead 63a is formed to provide ohmic ., .
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contact between the drain region 66 and the corresponding drain line (not shown in FIG. 6). An array of thin film, hydrogenated amorphous silicon-based MOSFET~s 61 supported upon the substrate 64 is thereby formed.
A planarization~layer 70 is then deposited over the array of FET's 61 in order to electrically isolate the drain and source lines (not shown in FIG. 5). An energy sensitive layer 71 is deposited onto the planarization layer 71. A contact plug 72 and bottom electrode 73 electrically connect the energy sensitive layer 71 with the gate electrode 69 of each FE~ 61 of the array. A top electrode layer 74 is deposited ~nto the , energy sensitive layer 70.
The invention will be further described with reference to the following examples.

A polysilicon-based solid state dete-tor for detecting x-rays was made as follows:
First, an array of polysilicon-based MOSFETs ~ supported on a substrate was prepared as follo-~s. An '; insulating layer of SiOx was grown,by thermal oxidation in dry oxygen~at 1050C for 3-hours on a-silicon wafer base layer. Next, a layer of undoped amorphous silicon having a thickness of 1500 angstroms was deposited onto the insulating layer at 560C and 180 millitorr by . pyrolytic decomposition of silane using the low pressure ,`' ; chemical vapor deposition ("LPCVD") technique. The amorphous silicon was,then annealed in a-nitrogen , 30 ~ atmosphere (1.5 Torr) at 620C for 24 hours to form a -- , ,,polysilicon layer, i.-e.,-"LPCVD polysilicon". ~The LPCVD
polysilicon layer,was!then patterned into-islands using '~ miceolithography-techniques to form a channel layer for ,each transistor,of the array.

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20~7092 t,,~'"~O 92/02959P~r/US91/04260 -25- ';;
,, Next, a 1000 angstrom layer of SiOx was deposited over the polysilicon channel layers by thermal . oxidation of the LPCVD polysilicon layer at 1150C in dry : oxygen f or 30 minutes. Using the techniques described above, a gate layer of LPCVD polysilicon was formed at 620C over the gate oxide layer. For each MOSFET, the polysilicon gate layer was etched to form the polysilicon gate.
In order to obtain a device having n-type . 10 characteristics, 3.7 x 10~5/cm2 phosphorous was implanted : to dope the source, the drain, and the polysilicon gate.
:~ The energy of the ion implanter was 175 keV. The dopants were activated during a 30 minute nitrogen anneal at 1050~C. The SiOx layer was then etched to open the drain and source region for-electrode contact.
Next, a first layer of an aluminum alloy (l.0 : Si, 0.4 ~ Cu, 1000 angstroms) and a second layer of chromium (2000 angstroms) were sputtered onto the gate .~ region, source region, and drain region to form the gate . 20 electrode, the source electrode, and the drain electrode, :~ respectively. Source lines were also deposited at this ~ time. Sputtering took place at a chamber pressure of 9 x ~ :10~7.Tor.r.:~-Argon gas pressure was.7 millitorr, and the ~ sputtering apparatus was operated at 500 W. The 25: sputtering time:for the aluminum alloy layer was 7 ; minutes, and the sputtering time for the chromium layer was 11 minutes.
:; . The~resulting array of thin film, field effect ;~ j transistors was annealed in a forming gas (85% N2, 15%
30~ 2) at.. ;400C.for. 30 minutes in order to enhance the ;~ adhesion.and .the .contact of-the electrodes to thé source, - :-.drain, and gate regions.. After this, the array ~of thin . film" field.effect transistors was subjected to a plasma .hydrogenation:~.treatment in order to reduce :the~dangling 35 ;~bonds-at-the grain boundaries of the polysilicon channel .ilayer; .This treatment took place at;300C~and~0.55 Torr .

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WO~2t02gS9 PCT/US91/042~R
208~ o92 -26~ '' for 1.5 hours in an atmosphere of 50% H2 and 50~ N2. The flow rates of the hydrogen and nitrogen were each 70 sccm, and power density was 1.36 W/cm2. The equipment used for the treatmen~ was operated with an electrode ,distance of .875 inches and a radio frequency of 13.56 MHz. Suitable equipment for performing the plasma hydrogenation treatment is commercially available, for example, from Plasma Technoloyy, Concord, Massachusetts, or ~lass TechSolar, Boulder, Colorado.
A planarization layer was deposited over the array of thin film, field effect transistors as follows.
A first layer of SiNx having a thickness of 3000 ~ , angstroms was deposited over the array at 300C using the ,~ plasma-enhanced chemical vapor technique. This was ~, 15 followed by depositing a second layer of sioX having a thickness of 2000 angstroms also at 300C usin~ the plasma-enhanced chemical vapor technique. This was ' followed by depositing a third layer of SiNX having a thickness of 2000 angstroms using the same plasma-~20 ,enhanced chemical vapor deposition technique. Deposition ',conditions for SiNX were a flow rate of SiH4 of 17.3 ,, sccm, a flow rate of NH3 of 10.8 sccm, and a power ~,density~of 0.4 W~cm2. Deposition conditions for SiOx ',were a-flow rate of SiH4 of 4.71 sccm, a flow rate of N2 -25 of 60 sccm, a flow rate of NzO of 17.1 sccm, and a power ,, density of 0.06 W/cm2. ~ ' Holes exposing the gate electrode of each field ,, effect transistor of the array were formed in the ~; ,,,, planarization layer by using,the gate electrode as a mask ~,for the reactive :ion etching of the planarization layer.
-,. ,I -, Reactive ion etching was accomplished with'40 sccm CF4 ,and 0.84 2 at 250 W for 16 minutes.~-'After~form'ing the ,; holes, the holes:were,filled with-plugs of chromium 7 having a thickness of 6000 angstroms. Next,~a-3000 '`'.3j5j,-- angstrom thick chromium layer,was,deposited over the ~
r - planarization layer.~ This layer-was then patterned to ,, , ~
"

., : .:. ..
:: , , , , -. : :,. : : :, .~092/02959 2 0 8 7 0 9 2 pCT/Vs91/oq260 form a discrete, bottom electrode for each transistor of the array. The size of the bottom electrode for each FET
determined the gate size of the FET, and therefore, the pi~el size of the resulting solid state detector. Drain lines wer~ also deposited at this time.
Next, a layer of SiNX having a thickness of 3000 angstrbms was deposited over the array using plasma-enhanced chemical vapor deposition techniques.
The purpose of this layer was to provide additional ~ capacitance for charge storage. An energy sensitive layer of hydrogenated amorphous silicon having a ...
thickness of 1 micron was.deposited over the entire array . and was not patterned.
- Next, a layer of indium tin oxide ("ITO") having a thickness of 6000 angstroms was deposited onto the energy sensitive layer at 100C and 200 w in 100 millitorr of argon gas using the sputtering technique.
The ITO was then patterned to form common top electrode elements, each element covering the FET's in a column of the array.
A phosphor layer of Gd2O2S:Tb, commercially ~:` available as Trimax 12B from Minnesota Mining And .- Manufacturing Company, was physically laid on-top of the ~ detector. This layer was used to convert incident x-rays: : 25 into visible light having a wavelength of 545 nm.
:~ Optionally, the phosphor layer may be omitted.:: In such a case, the resulting solid state detector could be used for detecting visible light rather than for . detecting x-ray radiation.
~ Operation of.the solid state detector.in which , - the-phosphor layer was.deposited onto.the.top of the ~ detector was~as follows.i ~ uniform charge was formed on : the.surface of the energy sensitive layer by applying a . DC voltage as.high.as-10-20 volts between.the.drain electrode and.the source.electrode of.each FET of the :-..- array.. The voltage between the common, top electrode ~ ~,- ~ , , "'' , . ' ' ' , .

W092/0~ ~ 87 9 ~ -28- PC~/US~1/0426 elernents and each source electrode of the array, i.e., - the gate voltage, was adjusted for optimum sensitivity between -5V and 15V. The energy sensitive layer of amorphous hydrogenated~silicon acted as a capacitor ~Csi) which was effectively connected in series with the gate capacitor (floating gate, CG )- An equivalent circuitry of of the solid state detector, depicting a single FET of the array, is shown in FIG. 7. In this circuitry, C5i, Cs~ Cd and Cg are the capacitance of the energy sensitive `; 10 layer, the source, the drain and the gate, respectively.
he solid state detect~r was exposed to x-ray ~` illumination (90 kVp, 200 mA, 100 microseconds, 20 mm aluminum filter). The incident radiation was eonverted into green light (wavelength of 545 nm) by the phosphor layer which was then absorbed by the energy sensitive .`C layer. This caused the charge in the energy sensitive ` layer to decrease, causing a drop in the gate voltage.
his, in turn, caused a drop in the drain-source current.
The change in the drain-source current was converted into a voltage by a resistor, R, and was detected as an output voltage signal. This signal was amplified, converted ; into digital by an A/D converter, and then stored in a ~` memory.
. .

- - A polysilicon-based solid state detector for - directly detecting x-rays without requiring a phosphor layer would be prepared as follows. The procedure for making such a detector would be the same as-the procedure described-in Example 1, except that an energy sensitive layer of amorphous selenium having a thickness of 300 to :~ - - 500 microns is substituted for the energy sensitive layer r of~hydrogenated amorphous silicon. The amorphous selenium is deposited at room temperature, using the 35 : thermal evaporation technique. It should-be noted that selenium~can undergo a phase change from-the amorphous : ' : .' :' , ., ,~, .. .. ..
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~ 92/02959 2 0 8 7 0 9 2 PCT/U~1/04260 -29- , ,~

phase to a polycrystalline phase at temperatures as low as 50-60C. Thus, the deposition of amorphous selenium should he done in several steps to avoid this phase change.

, A polysilicon-based solid state detector for detecting infrared radiation was prepared as follows. The procedure for making such a detector was the same as the procedur~ described in Example 1, except that an energy sensitive layer containing PVF2 was substituted for the ~- energy sensitive layer of hydrogenated amorphous silicon.
The energy sensitive layer containing the PVF2 was a blend of polyvinylidene fluoride ("PVF2") and dimethylmethacrylate ("PMMAI') as described in U.S. Pat.
~' Nos. 4,606,871; 4,615,848; and 4,820,586. The blend was poled to establish pyroelectric propercies. Preferred ~-~ thickness of the energy sensitive layer ranged from about 3 to about 7 microns. Deposition and poling of the ,, 20 energy sensitive layer was as-follows:
,~ - 24 grams of PMMA were dissolved in 35 grams of methyl ethyl ketone ("MEK") and mixed thoroughly. 36 ;grams of PVF2 and-304 grams of dimethylformamide ("DMF") were added to-the PMMA solution, and the solution was , 25, thoroughly mixed again.
, The resulting solution was coated over the array of,thin film~transistors by spin coating.
- Alternatively,,the resulting solution may also be coated .`. ?'- over,the array by immersing the arrayJin a container containing the PVF2l blend-and then'withdrawing the array - --- from,the container~at-a rate of about 1.2 cm/minute.
- This':would result in a coating thickness of about 5 mic~ons; ~he coated array was then'air dried at about :,,.room temperature in a dust-free environment until the coating-became~white,~which~was indicative of dryness.

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W092/029S9 ; P~T/USlJ]/0~26~
208~ ~92 -30- ~

After this, the coated array was heated in an oven for about 10 minutes at 60C to drive off the MEK.
Then, the the temperature was raised to 140C and maintained at 140C for about 10 minutes in order to drive off the DMF. The temperature was increased again ;` to 200C and maintained at 200C for about 5 minutes.
The array was then cooled to room temperature, allowing the beta state of the PVF2 to set.
Poling of the PVF2 blend was accomplished by placing the coated array in an electric field of suitable strength to set the dipole moment of the PVF2. The apparatus 75 of Fig. 8 is useful to accomplish the poling function. The coated array 76 was supported on a conductive support plate 77 which was placed in an oven 78. A corona generating array 79, comprising a ` conductive screen 80 and a pattern of conductive needles 81 was supported in, and electrically isolated from, the ` oven chamber by insulating support members B2. ~ corona power supply 83 (for example, CORONATROLTM, manufactured ~;; 20 by Monroe Electronics, Inc., Lyndonville, NY) was connected to support plate 77 and the corona array 79 by leads 84 and 85. The needles 81 were disposed in a -~ two-dimensional geometrical pattern with separation between adjacent needles of about 12 mm. A distance of about 50 mm was maintained between the tips of needles 81 and the top surface of coated array 76. Poling was then achieved by inserting the coated array 76 into the oven ., 78, generating a corona discharge on the PVF2 surface of -900 volts,-gradually increasing the oven temperature to about 105~C while maintaining said surface charge, and allowing--the oven temperature to decline back to room - temperature while still-maintaining said surface charge.
. i. Finally, the common, top electrode elements of -:~ aluminum were deposited over the gate-region of each "-transistor of the array. In this structure, the~common, top electrode elements absorbed and were heated by i ', ; i ; ~ ' !

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r~O92/02Os9 7092i ~ ., ,, ICI/US9l/D4260 infrar~d radiation. The increase in temperature caused a corresponding increase in temperature of pyroelectric layer 29, which in turn caused a change in the gate voltage, and therefore a change in the drain~source current of the polysilicon-based thin film transistors.

-~ EXAMPLE: 4 `~ . A hydrogenated amorphous silicon-based solid state detector for detecting infrared radiation was prepared as follows. A layer of sio2 having a thickness of 1 micron was deposited onto a 3 inch x 3 inch single crystal silicon wafer by thermal oxidation in dry oxygen.
;~ Next, a layer of chromium having a thickness of 3000 angstroms was deposited onto the layer of sio2. ~his was - followed by using plasma-enhanced chemical deposition techniques to deposit a layer of n-type hydrogenated amorphous silicon (500 angstroms) onto the chromium layer. The n-type hydrogenated amorphous silicon was deposited using a process temperature of 250C, a flow rate of 5iH4 of 21.2 sccm, a flow rate of 1% PH3 diluted in hydrogen of 5.5 sccm, a flow rate of hydrogen of 76.4 sccm, and a power density of 0.043 W/cm2. The chromium layer and the layer of n-type hydrogenated amorphous silicon were then etched to form the drain and source electrodes and the drain and source regions, respectively, for each FET of the array.
The entire array was then coated with a layer of intrinsic a Si:H using the plasma-enhanced chemical vapor deposition technique. The layer of intrinsic 30 a-si :H was then patterned ts form the channel layer for each thin film transistor of the array. A dielectric layer of SiNX (3000 angstroms) was then deposited onto the channel layer of each transistor, followed by the deposition of a gate electrode onto each dielectric layer. An energy sensitive layer of a PVF2 blend and common, aluminum top electrode elements were coated over the array, and the PVF2 blend was then poled as described in Example 3 to complete the detector.

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W092/0~959 ~ o 3~ 09 2 3~ PCr/US9l/042 .; Other embodiments of this inven~ion will be :~ apparent to those skilled in the art from a consideration of this specification or from practice of the invention disclosed herein. Various omissions, modifications, and : 5 changes to the principles described herein may be made by . one skilled in the art without departing from the true scope and spirit from the invention which is indicated by ` the following claims.

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Claims (6)

What is claimed is:

1. A solid state detector for detecting electromagnetic radiation, comprising:
(a) a substrate;
(b) a plurality of field effect transistors deposited onto the substrate to form an array;
(c) a planarization layer deposited over the array of field effect transistors;
(d) an energy sensitive layer deposited onto the planarization layer;
(e) means for electrically connecting the energy sensitive layer with each field effect transistor of the array;
(f) a top electrode layer deposited onto the energy sensitive layer; and (g) circuitry means for providing electronic read-out from each field effect transistor of the array.

2. The solid state detector of claim 1, further comprising a phosphor layer deposited onto the top of the solid state detector.

3. The solid state detector of claim 1, further comprising an insulating layer for additional charge storage interposed between the planarization layer and the energy sensitive layer.

4. A solid state detector for detecting electromagnetic radiation, comprising:
(a) a substrate;
(b) a plurality of thin film, field effect transistors deposited onto the substrate and arranged in rows and columns to form an array, wherein each transistor has a source electrode, a drain electrode, a gate electrode, and a gate dielectric layer having a gate capacitance;
(c) a plurality of source lines for linking the source electrodes in each row of transistors;

(d) a plurality of drain lines for linking the drain electrodes in each column of transistors;
(e) a planarization layer deposited over the array for electrically isolating the source lines from the drain lines;
(f) an energy sensitive layer deposited over the planarization layer, wherein the energy sensitive layer has an additional capacitance;
(g) means for electrically connecting the gate electrode of each field effect transistor of the array with the energy sensitive layer such that the additional capacitance of the energy sensitive layer is effectively connected in series with the gate capacitance of each transistor of the array; and (h) a top electrode layer deposited onto the energy sensitive layer.

5. The solid state detector of claim 4, further comprising an insulating layer for additional charge storage interposed between the planarization layer and the energy sensitive layer.

6. A method of making a solid state detector for detecting electromagnetic energy, comprising the steps of:
(a) depositing a plurality of field effect transistors onto a substrate to form an array, wherein each of the field effect transistors has a gate electrode and has a gate dielectic layer having a gate capacitance;
(b) depositing a planarization layer over the array of field effect transistors;
(c) depositing an energy sensitive layer onto the planarization layer, wherein the energy sensitive layer has an additional capacitance;
(d) depositing means for electrically connecting the gate electrode of each field effect transistor to the energy sensitive layer such that the additional capacitance of the energy sensitive layer is effectively connected in series with the gate capacitance;

(e) depositing a top electrode layer onto the energy sensitive layer; and (f) depositing circuitry means for providing electronic read-out from each field effect transistor of the array.