CA2079623A1 - Method and apparatus for providing two parties transparent access to a single-port memory storage device - Google Patents

Method and apparatus for providing two parties transparent access to a single-port memory storage device

Info

Publication number
CA2079623A1
CA2079623A1 CA2079623A CA2079623A CA2079623A1 CA 2079623 A1 CA2079623 A1 CA 2079623A1 CA 2079623 A CA2079623 A CA 2079623A CA 2079623 A CA2079623 A CA 2079623A CA 2079623 A1 CA2079623 A1 CA 2079623A1
Authority
CA
Canada
Prior art keywords
access control
memory
control unit
port
memory access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2079623A
Other languages
French (fr)
Other versions
CA2079623C (en
Inventor
James L. Mckenna
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Standard Microsystems LLC
Original Assignee
James L. Mckenna
Standard Microsystems Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by James L. Mckenna, Standard Microsystems Corporation filed Critical James L. Mckenna
Publication of CA2079623A1 publication Critical patent/CA2079623A1/en
Application granted granted Critical
Publication of CA2079623C publication Critical patent/CA2079623C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols

Abstract

A data communication controller having a memory access control unit characterized by a symmetrical access port architecture. The memory access control unit allows both a host processor and the medium access control (MAC) unit of the data communication controller to transparently access a single-port data packet buffer memory while operating a full specified operating speed and without interference between simultaneous memory access requests. The memory access control unit arbitrates asynchronous memory access requests from both the host processor and the medium access control unit, while permitting each of these processors unlimited access to the single-port buffer memory as if it alone had the full memory available to itself at all times. The above capabilities are achieved using automatic address incrementation and data-byte prefetching operations, without requiring the use of a port processor or additional internal data buses.
CA002079623A 1991-10-03 1992-10-01 Method and apparatus for providing two parties transparent access to a single-port memory storage device Expired - Fee Related CA2079623C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US770,695 1991-10-03
US07/770,695 US5392412A (en) 1991-10-03 1991-10-03 Data communication controller for use with a single-port data packet buffer

Publications (2)

Publication Number Publication Date
CA2079623A1 true CA2079623A1 (en) 1993-04-04
CA2079623C CA2079623C (en) 2000-12-12

Family

ID=25089395

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002079623A Expired - Fee Related CA2079623C (en) 1991-10-03 1992-10-01 Method and apparatus for providing two parties transparent access to a single-port memory storage device

Country Status (2)

Country Link
US (1) US5392412A (en)
CA (1) CA2079623C (en)

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5799161A (en) * 1993-06-25 1998-08-25 Intel Corporation Method and apparatus for concurrent data routing
US5594926A (en) * 1993-07-19 1997-01-14 Efar Microsystems, Inc. Hard disk accelerating system for computer
EP0685949A3 (en) * 1994-06-03 2002-07-10 Philips Patentverwaltung GmbH Packet transmission system
US5745732A (en) * 1994-11-15 1998-04-28 Cherukuri; Ravikrishna V. Computer system including system controller with a write buffer and plural read buffers for decoupled busses
US5838934A (en) * 1995-06-07 1998-11-17 Texas Instruments Incorporated Host port interface
US5829042A (en) * 1996-02-15 1998-10-27 Hewlett-Packard Company Prefetch operation for network peripheral device having shared memory
US6112319A (en) * 1998-02-20 2000-08-29 Micron Electronics, Inc. Method and system for verifying the accuracy of stored data
US6983350B1 (en) 1999-08-31 2006-01-03 Intel Corporation SDRAM controller for parallel processor architecture
US6668317B1 (en) * 1999-08-31 2003-12-23 Intel Corporation Microengine for parallel processor architecture
US6427196B1 (en) * 1999-08-31 2002-07-30 Intel Corporation SRAM controller for parallel processor architecture including address and command queue and arbiter
US6606704B1 (en) * 1999-08-31 2003-08-12 Intel Corporation Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
US7546444B1 (en) 1999-09-01 2009-06-09 Intel Corporation Register set used in multithreaded parallel processor architecture
ATE475930T1 (en) 1999-09-01 2010-08-15 Intel Corp BRANCH INSTRUCTION FOR A MULTIPLE PROCESSOR
US7191309B1 (en) 1999-09-01 2007-03-13 Intel Corporation Double shift instruction for micro engine used in multithreaded parallel processor architecture
US6532509B1 (en) 1999-12-22 2003-03-11 Intel Corporation Arbitrating command requests in a parallel multi-threaded processing system
US6694380B1 (en) 1999-12-27 2004-02-17 Intel Corporation Mapping requests from a processing unit that uses memory-mapped input-output space
US7620702B1 (en) 1999-12-28 2009-11-17 Intel Corporation Providing real-time control data for a network processor
US6631430B1 (en) * 1999-12-28 2003-10-07 Intel Corporation Optimizations to receive packet status from fifo bus
US6625654B1 (en) * 1999-12-28 2003-09-23 Intel Corporation Thread signaling in multi-threaded network processor
US6307789B1 (en) * 1999-12-28 2001-10-23 Intel Corporation Scratchpad memory
US6661794B1 (en) * 1999-12-29 2003-12-09 Intel Corporation Method and apparatus for gigabit packet assignment for multithreaded packet processing
US6584522B1 (en) * 1999-12-30 2003-06-24 Intel Corporation Communication between processors
US6976095B1 (en) 1999-12-30 2005-12-13 Intel Corporation Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch
US7480706B1 (en) 1999-12-30 2009-01-20 Intel Corporation Multi-threaded round-robin receive for fast network port
US6952824B1 (en) 1999-12-30 2005-10-04 Intel Corporation Multi-threaded sequenced receive for fast network port stream of packets
US6631462B1 (en) * 2000-01-05 2003-10-07 Intel Corporation Memory shared between processing threads
US7681018B2 (en) * 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US20020053017A1 (en) * 2000-09-01 2002-05-02 Adiletta Matthew J. Register instructions for a multithreaded processor
US7020871B2 (en) * 2000-12-21 2006-03-28 Intel Corporation Breakpoint method for parallel hardware threads in multithreaded processor
US6868476B2 (en) * 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US7225281B2 (en) 2001-08-27 2007-05-29 Intel Corporation Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
US7487505B2 (en) 2001-08-27 2009-02-03 Intel Corporation Multithreaded microprocessor with register allocation based on number of active threads
US7216204B2 (en) * 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US7126952B2 (en) * 2001-09-28 2006-10-24 Intel Corporation Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion method
US8935297B2 (en) * 2001-12-10 2015-01-13 Patrick J. Coyne Method and system for the management of professional services project information
US20030144970A1 (en) * 2001-12-10 2003-07-31 Coyne Patrick J. Project management database and method of managing project related information
US7158964B2 (en) * 2001-12-12 2007-01-02 Intel Corporation Queue management
US7107413B2 (en) * 2001-12-17 2006-09-12 Intel Corporation Write queue descriptor count instruction for high speed queuing
US7269179B2 (en) * 2001-12-18 2007-09-11 Intel Corporation Control mechanisms for enqueue and dequeue operations in a pipelined network processor
US7895239B2 (en) 2002-01-04 2011-02-22 Intel Corporation Queue arrays in network devices
US7181573B2 (en) * 2002-01-07 2007-02-20 Intel Corporation Queue array caching in network devices
US6934951B2 (en) 2002-01-17 2005-08-23 Intel Corporation Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section
US7610451B2 (en) 2002-01-25 2009-10-27 Intel Corporation Data transfer mechanism using unidirectional pull bus and push bus
US7181594B2 (en) * 2002-01-25 2007-02-20 Intel Corporation Context pipelines
US7149226B2 (en) * 2002-02-01 2006-12-12 Intel Corporation Processing data packets
US7437724B2 (en) * 2002-04-03 2008-10-14 Intel Corporation Registers for data transfers
US7471688B2 (en) * 2002-06-18 2008-12-30 Intel Corporation Scheduling system for transmission of cells to ATM virtual circuits and DSL ports
US7337275B2 (en) 2002-08-13 2008-02-26 Intel Corporation Free list and ring data structure management
US7352769B2 (en) 2002-09-12 2008-04-01 Intel Corporation Multiple calendar schedule reservation structure and method
US7433307B2 (en) * 2002-11-05 2008-10-07 Intel Corporation Flow control in a network environment
US6941438B2 (en) * 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
US7443836B2 (en) 2003-06-16 2008-10-28 Intel Corporation Processing a data packet
US7213099B2 (en) * 2003-12-30 2007-05-01 Intel Corporation Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches
CN100388252C (en) * 2004-12-14 2008-05-14 威瀚科技股份有限公司 Method for realizing double port synchronous memory device and related apparatus thereof
US7739433B2 (en) * 2008-03-05 2010-06-15 Microchip Technology Incorporated Sharing bandwidth of a single port SRAM between at least one DMA peripheral and a CPU operating with a quadrature clock
US8819663B2 (en) * 2012-06-18 2014-08-26 Lsi Corporation Acceleration of software modifications in networked devices

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4604683A (en) * 1984-12-10 1986-08-05 Advanced Computer Communications Communication controller using multiported random access memory
JPH02117243A (en) * 1988-10-27 1990-05-01 Toshiba Corp Packet communication equipment
CA2011935A1 (en) * 1989-04-07 1990-10-07 Desiree A. Awiszio Dual-path computer interconnect system with four-ported packet memory control
US4967398A (en) * 1989-08-09 1990-10-30 Ford Motor Company Read/write random access memory with data prefetch
US5210749A (en) * 1990-05-29 1993-05-11 Advanced Micro Devices, Inc. Configuration of srams as logical fifos for transmit and receive of packet data
US5175732A (en) * 1991-02-15 1992-12-29 Standard Microsystems Corp. Method and apparatus for controlling data communication operations within stations of a local-area network

Also Published As

Publication number Publication date
US5392412A (en) 1995-02-21
CA2079623C (en) 2000-12-12

Similar Documents

Publication Publication Date Title
CA2079623A1 (en) Method and apparatus for providing two parties transparent access to a single-port memory storage device
US9959593B2 (en) Memory controller having plurality of channels that provides simultaneous access to data when accessing unified graphics memory
JP2571067B2 (en) Bus master
US5420984A (en) Apparatus and method for rapid switching between control of first and second DMA circuitry to effect rapid switching beween DMA communications
US6189062B1 (en) Apparatus and method for address translation in bus bridge devices
EP1047994A2 (en) Intelligent data bus interface using multi-port memory
CA2307816A1 (en) Buffering data that flows between buses operating at different frequencies
EP0275157A3 (en) Direct memory access controlled system
US6061748A (en) Method and apparatus for moving data packets between networks while minimizing CPU intervention using a multi-bus architecture having DMA bus
US4878197A (en) Data communication apparatus
CA2234635A1 (en) Method and device for exchanging data
CA2210822A1 (en) Simplified interface to a time-division multiplexed communications medium
CA2052364A1 (en) Common bus communication system with reduced interface memories
JP2778623B2 (en) Prefetch control device
JPS6448124A (en) Data transfer device
EP0568678B1 (en) Device for transmission of data
JPS6263351A (en) Disk cache device
KR0159437B1 (en) Data transfer interface circuit
JP2003330901A (en) Multiprocessor system
GB2248128A (en) A single board computer
JPS6217879Y2 (en)
KR20020058364A (en) Router for Packet Dual Process
JPS6269347A (en) Direct memory access controller
JPH04361349A (en) Input/output controller
JPH104420A (en) Data transfer method

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed