CA2076779C - Multiprocessor system with program change function - Google Patents
Multiprocessor system with program change functionInfo
- Publication number
- CA2076779C CA2076779C CA002076779A CA2076779A CA2076779C CA 2076779 C CA2076779 C CA 2076779C CA 002076779 A CA002076779 A CA 002076779A CA 2076779 A CA2076779 A CA 2076779A CA 2076779 C CA2076779 C CA 2076779C
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- cpu
- storage means
- program
- signal
- control
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
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- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Stored Programmes (AREA)
- Multi Processors (AREA)
Abstract
In a multiprocessor system with program change function according to the present invention, a special CPU among a plurality of CPU's inputs program data from outside and outputs the control signal to cancel the control over the storage means of another CPU during program data input, and outputs the switching signal to specify the storage means to store the program data among a plurality of storage means. Then, switching signal from the special CPU causes the decoder as the selection means to select one of the plurality of storage means and the special CPU serially executes program data storing to the selected storage means, which results in change of the program data in each storage means.
Description
~7~77~
MULTIPROCESSOR SYSTEM WITH PROGRAM CHANGE FUNCTION
FIELD OF THE INVENTION
This invention relates to a method to change the program to be executed by a CPU in a multiprocessor system comprising a plurality of CPU's.
DESCRIPTION OF THE PRIOR ART
Conventionally, a multiprocessor system comprising a plurality of CPU's in its package is provided with a RAM or other storage means to store the program data to be executed for each CPU. To change program data in such a multiprocessor system, program data must be down loaded from outside to the plurality of CPU's. For this reason, a multiprocessor system having the first and the second CPU is provided with a storage means for data exchange between the two CPU's such as a dual port memory.
To change the program data, the first CPU receives the program data given from outside and changes the program data in its own RAM and at the same time uses the dual port memory RAM to pass the program data from outside to the second CPU. Then, the second CPU reads out the program data stored in the dual port memory RAM, and stores this program data to its own RAM in order to change the program.
However, in this conventional method for program 2 Q 7 ~ 7 7 Y
change in a multlprocessor system, the flrst CPU ls requlred to have not only a means to receive the program data from outslde and change lts own program, but also another means to pass the data to the second CPU. Further, the second CPU also requlres a means to recelve data from the flrst CPU. The need of several means to pass the program data from outslde to each CPU and communlcatlon among them results ln complicated processing for program change. Besides, a speclal storage means such as a dual port memory RAM ls requlred for program data exchange among a plurality of CPU's.
SUMMARY OF THE INVENTION
An ob~ect of the present invention ls to provlde a multlprocessor system wlth program change functlon whlch enables easy program data change without compllcated program data communication.
Another object of the present invention ls to provlde a multlprocessor system provided with a program change functlon whlch does not requlre any speclal storage means for program data change such as a dual port memory.
According to an embodiment of the present invention there ls provlded, a multlprocessor system wlth program change function comprising a plurality of CPU's, lncluding a particular CPU; a plurality of storage means for storlng program data to be executed by said CPU's, each of sald storage means operatlng under control of a correspondlng one of said CPU's during normal processing, sald particular CPU
lncludlng: lnput means for lnputtlng program data from 2~7~77~
outside, flrst output means for outputtlng a control slgnal to others of sald CPU's to cancel control over sald storage means by sald others of sald CPU's durlng program data lnput, and second output means for outputtlng a swltchlng slgnal ldentlfylng one of sald plurallty of storage means to store sald program data; selection means for selecting wlth a selection signal one of said plurality of storage means identified by sald swltching signal from sald particular CPU;
transfer means responsive to said selection slgnal for selectlvely connectlng data signals from said particular CPU
to sald storage means; means responslve to said control signal for selectlvely connectlng read/wrlte and address signals from sald partlcular CPU to sald storage means; and gate means disposed between said selectlon means and sald storage means for connecting sald selection slgnal to sald storage means selected by sald particular CPU.
Accordlng to another embodlment of the lnventlon there ls provlded, a multlprocessor system comprlslng: a plurallty of CPU's lncludlng at least a flrst CPU and a second CPU; a plurallty of storage means for storlng program data each lndlvldual storage means belng selectlvely connected to sald flrst and second CPU, each of said storage means oper-ating under control of corresponding one of sald plurallty of CPU's durlng normal processlng; sald first CPU belng prog-rammed to perform a program change functlon accordlng to a single program change control program, means in sald first CPU
for provldlng a storage control slgnal ln response to lnput of 2 0 7 0 7 7 ~
a program data to said flrst CPU, said storage control slgnal releasing said storage means from being under control of said second CPU during program data input state; buffer means responslve to said storage control signal for selectively connecting read/wrlte and address signals under control of said first CPU to sald storage means; means in said first CPU
for providing a selection signal accordlng to a control data contained in said program data input to said first CPU for storing said program data lnto an ldentlflëd storage means, and means responsive to said selection signal for selectively connecting data signals from sald flrst CPU to sald storage means for loading sald program data lnto said identified storage means.
According to a further embodiment of the lnvention there is provided, a multiprocessor system comprlsing: a first CPU recelvlng program data from an external source, sald flrst CPU executing program load of said program data, said first CPU outputting a control out slgnal indlcating a program load state and outputtlng a select slgnal to select a memory to load said program data; a first memory receiving read/write, address and data signals under control of sald flrst CPU under a non program load state condltlon; at least one other CPU
receivlng sald control out slgnal from sald flrst CPU; a second memory receiving read/write, address and data slgnals under control of sald other CPU during sald non program load state condition, said other CPU being responslve to said control out slgnal to stop outputtlng said read/wrlte, address ~ S~
2 ~ 7 ~ 7 7 9 and data signals to sald second memory; buffer means respon-slve to sald control out slgnal and sald select signal for selectlvely connectlng said readtwrlte, address and data signals under control of sald flrst CPU to sald second memory;
a decoder connected to sald flrst CPU to provlde a flrst and second chlp select slgnal to said flrst and second memorles in response to sald select slgnal provlded from sald flrst CPU;
and whereln said control out slgnal and sald select slgnal provlded control by sald flrst CPU over sald read/wrlte, address and data signals connected to said flrst and second memories, thereby allowlng sald flrst CPU to selectlvely perform program load lnto said flrst and second memorles.
Other ob~ects, characterlstlcs and effects of the present invention wlll be clarifled in the detalled descrlp-tion below.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 ls a block dlagram to show the conflguratlon of a multlprocessor system havlng program change functlon accordlng to a flrst embodlment of the present lnventlon;
Flg. 2 ls a dlagram to show the address maps of the multlprocessor system accordlng to the flrst embodlment ln normal status;
Flg. 3 ls a dlagram to show the address map of the multlprocessor system accordlng to the flrst embodlment when program data is lnput;
Fig. 4 ls a block dlagram to show the conflguratlon of a multlprocessor system wlth program change functlon accordlng to a second embodiment of the present 2~767~g invention;
Fig. 5 is a diagram to show the address maps of the multiprocessor system according to the second embodiment in normal status; and Fig. 6 is a diagram to show the address map of the multiprocessor system according to the second embodiment when program data is input.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to the attached figures, a multiprocessor system with program change function according to a first embodiment of the present invention will be described below. Fig. 1 is a block diagram to show the configuration of a multiprocessor system which adopts the program change method according to a first embodiment of the present invention. This multiprocessor system comprises two CPU's 101 and 102, four RAM's 103, 104, 105 and 106, five OR circuits 107, 108, 109, 110 and 111, a unidirectional buffer 112, a bidirectional buffer 113, a decoder 114 and a ROM 120.
The RAM's 103 through 106 are storage areas to store program data. Usually, the RAM's 103 and 104 store the program data for the CPU 101 and RAM's 105 and 106 store the program data for the CPU 102.
The decoder 114 decodes bank switching signal from the CPU 101 when program data is input so as to output ~7~779 the selection signal to specify one of the RAM's 103 to 106 as the area where the input program data i8 to be stored.
The ROM 120 stores a program for loading to control loading of the program data from outside. The unidirectional buffer 112 is a circuit to transfer the write/read control signal and the address signal from the CPU 101 to the write/read control signal port R/W
and the address signal port ADD at the RAM 105 and the RAM 106 in the CPU 102. This transfer is controlled by the control signal output from the CPU 101 described later. The bidirectional buffer 113 transfers the program data input from outside to the CPU 101 to the RAM 105 and the RAM 106 in the CPU 102 and serves for mutual transfer of program data between the RAM 103 and the RAM 104 and the RAM 105 and the RAM 106 when required. This transfer is controlled by the selection signal from the decoder 114 with the transfer direction being controlled by the write/read control signal from the CPU 101.
A program data input terminal 115 for program data input from outside is connected to the data input port DATA IN at the CPU 101. The write/read control signal port R/W, the address signal port ADD and the data signal port DATA of the CPU 101 are connected with the corresponding write/read control signal port R/W, the ~7~779 address slgnal port ADD and the data slgnal port DATA of the RAM's 105 and 106 respectively. The data slgnal port DATA of the CPU 101 ls further connected wlth the dlrect lonal buffer 113. The wrlte/read control signal port RtW of the CPU 101 ls connected wlth the dlrectlon control lnput port DIR of the bidlrectional buffer 113, the input port of the buffer 112 and the ROM 120. The address signal port ADD of the CPU 101 is connected wlth the lnput port of the buffer 112. The selectlon slgnal ports CS2 and CSl correspondlng to the RAM's 103 and 104 of the CPU 101 are connected wlth the OR clrcults 110 and 111 and the output from the OR clrcults 110 and 111 are connected wlth the selectlon slgnal port CS of the RAM's 103 and 104.
The output port SEL OUT to output the bank swltchlng slgnal of the CPU 101 ls connected wlth the lnput port S~L IN
of the decoder 114. The control slgnal output port CON OUT of the CPU 101 to output the control slgnal to speclfy that the program is belng lnput ls connected wlth the output control port of the buffer 112 and the control slgnal lnput port CON
IN of the CPU 102.
The wrlte/read control slgnal port R/W, the address slgnal port ADD and the data slgnal port DATA of the CPU 102 are connected wlth the corresponding wrlte/read control slgnal port R~W, the address slgnal port ADD and the data slgnal port DATA of the RAM's 103 and 104 respect lvely . The data slgnal port DATA of the CPU 102 ls further connected wlth the bldlrectional buffer 113. The write/read control signal port 2~7~77~
R/W and the address slgnal port ADD of the CPU 102 are connected wlth the output port of the buffer 112. The selectlon signal ports CSl and CS2 for the RAM' s 105 and 106 of the CPU 102 are connected with the OR circults 107 and 108 and the output from these OR clrcults 107 and 108 are connected with the selectlon slgnal port CS of the RAM 105 and the RAM 106 respectlvely.
The selection slgnal ports CSl, CS2, CS3 and CS4 of the decoder 114 are connected wlth the lnput of the OR
clrcults 107, 108, 109, 110 and 111 respectlvely. The output from the OR clrcuit 109 ls connected wlth the enable slgnal port EN to authorize the transfer by the bidirectional buffer 113.
Then, the processing for program change of the multlprocessor system conflgured as above accordlng to the flrst embodlment ls descrlbed.
The program data used by the CPU's 101 and 102 are sent to the CPU 101 vla the program data lnput termlnal 115.
In normal status when program data from outslde is not input, the CPU 101 and the CPU 102 operate accordlng to the address maps as shown ln Figs. 2A and 2B.
The CPU 101 controls the program data input from ~g ~
outside using the program for loading stored in the ROM
120. When the program data from outside is input, the CPU 101 outputs the control signal to indicate that program data is being input from the control signal output port CON OUT, which is input to the control signal input port CON IN of the CPU 102. The input of this control signal causes the CPU 102 to cease the control over the RAM 103 and the RAM 104.
At this point, the bank switching signal from the output port SEL OUT of the CPU 101 is input to the input port SEL IN of the decoder 114 and the selection signal to specify one of the RAM's 103 to 106 is output from the selection signal ports CS1, CS2, CS3 and CS4 of the decoder 114. The selection signal from the selection signal ports CS1 or CS2 is output to the selection signal port CS of the RAM's 103 and 104 via the OR
circuits 110 and 111. The selection signal from the selection signal port CS3 or CS4 is output to the selection signal port CS of the RAM's 105 and 106 vla the OR circuits 107 and 103.
Provision of the control signal from the CPU 101 to the output control input port of the unidirectional buffer 112 enables input of the signals from the write/read control signal port R/W and the address signal port ADD of the CPU 101 to the write/read control signal port R/W and the address signal port ADD of the 2~7~3179 RAM 105 and the RAM 106 via the unidirectional buffer 112. Further, input of the selection signal from the selection signal ports CS3 and CS4 of the decoder 114 to the enable signal port EN of the bidirectional buffer 113 via the OR circult 109 enables data communlcatlons via the bidirectional buffer 113 between the data signal port DATA of the CPU 101 and the data signal ports ADD
of the RAM 105 and the RAM 106. The change of direction at the bidirectional buffer 113 is controlled by the signal from the write/read control signal port R/W of the CPU 101, which is lnput to the direction control input port DIR.
Thus, the RAM 105 and the RAM 106 are selected according to the selection signal from the selection signal ports CS3 and CS4 of the decoder 114, so that they can be controlled by the CPU 101. At the same time, the RAM 103 and the RAM 104 which serve for the CPU 101 itself can be controlled by the selection signal from the selection slgnal ports CS1 and CS2 of the decoder 114. The decoder 114 is controlled by the bank switching signal from the CPU 101.
Therefore, by specifying one of the RAM's 103 to 106 using the bank switching signal, RAM's 103, 104, 105 and 106 can be assigned to a certain address area in the CPU 101. Fig. 3 shows the address map for the CPU 101 under such situation. In Fig. 3, the address area of 2 ~ 7 ~ 9 the RAM 104 ln the CPU 101 is used as the bank switching area and the RAM's 103 to 106 are selectively assigned to the bank switching area.
By serially storing program data from outside to the RAM's 103 to 105 with bank switching using the decoder 114 under such situation, the program data in the RAM's 103 to 106 can be changed.
Upon completion of program data input, the control signal showing that the program data is being lnput at the CPU 101 is canceled. This enables control over the RAM's lOS and 106 of the CPU 102 and disables transfer by the unidirectlonal buffer 112. This causes the write/read signal and the address signal of the CPU 101 to be separated from the RAM's 105 and 106, resulting in the status shown by the address maps in Figs. 2A and 2B.
Once the control signal to show that the program data is being input is canceled, the CPU 102 can make processing using the changed program stored in the RAM's 105 and 106. Thus, the program data in a plurality of CPU's (101 and 102) can be changed using a simple procedure.
Since the RAM's 103 to 106 of the CPU's 101 and 102 are selectively assigned to the bank switching area in this first embodiment, the program data can be serlally stored to the RAM's 103 to 106 without any change in the address map of the CPU 101.
Referring now to Fig. 4, a multiprocessor system ~7~77~
where a program change method accordlng to a ~econd embodlment of the present lnventlon ls descrlbed now.
Flg. 4 ls a block diagram to show the configuratlon of the second embodiment.
In the second embodlment, a RAM 105 and a RAM 106 corresponding to a CPU 102 are controlled by a decoder 124. A
RAM 103 and a RAM 104 are controlled by a CPU 101 as they are ln the flrst embodlment. Conse~uently, the OR clrcults 110 and 111 ln Flg. 1 are omltted here. In additlon, the decoder 124 ls provlded with selectlon slgnal ports CSl and CS2 only, which are to be connected wlth the RAM 105 and the RAM 106.
Except these polnts, the conflguratlon of the second embodlment ls the same as that ln Flg. 1.
Then, the processing for program change of a multl-processor system as configured as above accordlng to the second embodlment is now descrlbed.
In normal status when any program data ls not belng lnput from outslde, the CPU's 101 and 102 operate accordlng to the address maps shown ln Flgs. 5A and 5~.
The address map of the CPU 101 ln thls embodlment ls, unllke the one ln Flg. 2A, provlded wlth the bank swltchlng area for asslgnment of RAM s 105 and 106 ln advance.
The CPU 101 controls the program data lnput from outslde uslng the program for loadlng stored ln a ROM 120.
When program data from outslde ls lnput, the CPU 101 outputs the control slgnal to lndlcate that the program data ls belng ~û7~77~
input from the control slgnal output port. This slgnal ls lnput to the control signal input port of the CPU 102. Input of the control slgnal cancels the control over the RAM's 105 and 106 by the CPU 102.
At this point, the bank swltchlng slgnal from the output port SEL OUT of the CPU 101 ls lnput to the lnput port SEL IN of the decoder 124, and selection signals are output from the select lon signal ports CSl and CS2 of the decoder 124. The selection signal from the selection signal port CSl and CS2 are output to the select ion slgnal port CS of the RAM 105 and the RAM 106 vla the OR clrcults 107 and 108.
The control signal from the CPU 101 is provlded to the output control lnput port of a unldirectlonal buffer 112, enabllng lnput of the slgnal from the wrltetread control slgnal port R/W and the address slgnal port ADD of the CPU 101 to the wrlte/read control slgnal port R/W and the address slgnal port ADD of the RAM 105 and the RAM 106 vla the buffer 112.
Elesldes, the selectlon slgnals from the selectlon slgnal ports CSl and CS2 of the decoder 124 are input to the enable slgnal port EN of a bldlrectlonal buffer 113 vla an OR clrcuit 109, enabllng data communicatlons between the data signal port DATA
2~7~7~
the CPU 101 and the data signal port ADD of the RAM 105 and the RAM 106 vla the bldirectlonal buffer 113. The change of direction at the bidirectional buffer 113 is controlled by the signal from the write/read control signal port R/W of the CPU 101, which is input to the direction control lnput port DIR.
Thus, the RAM's 105 and 106 are controlled by the selection signals from the selection signal ports CS1 and CS2 of the decoder 114, which enables control by the CPU 101. The RAM's 103 and 104 serving for the CPU 101 are controlled by the selection signal from the selection signal ports CSl and CS2 of the CPU 101. The decoder 114 is controlled by the bank switching control signal from the CPU 101.
Therefore, switching between the RAM 105 and the RAM 106 using the bank switching signal enables selective assignment of the RAM's 105 and 106 to the address of the bank switching area in the CPU 101 as shown in the address map shown in Fig. 5A. Fig. 6 shows the address map of the CPU 101 under such status. By sequentially storing the program data from outside to the RAM's 103 and 104 of the CPU 101 itself and to the RAM's 105 and 106 assigned to the bank switching area according to the selection by the decoder 114 under such status, the program data in the RAM's 103 to 106 are changed.
2~P~'S79 Upon completion of program data input, the control signal showlng that the program data is being input at the CPU 101 is canceled. This causes separation from the CPU 102 and returns to the address maps shown in Figs. 5A and 5B. Cancellation of the control signal showing that program data is being input enables the CPU
102 to perform processing using the changed program stored in the RAM's 105 and 106.
Obviously many modifications and variations of the present invention are possible. It is intended to cover in the appended claims all such modifications as fall within the true spirit and scope of the invention.
MULTIPROCESSOR SYSTEM WITH PROGRAM CHANGE FUNCTION
FIELD OF THE INVENTION
This invention relates to a method to change the program to be executed by a CPU in a multiprocessor system comprising a plurality of CPU's.
DESCRIPTION OF THE PRIOR ART
Conventionally, a multiprocessor system comprising a plurality of CPU's in its package is provided with a RAM or other storage means to store the program data to be executed for each CPU. To change program data in such a multiprocessor system, program data must be down loaded from outside to the plurality of CPU's. For this reason, a multiprocessor system having the first and the second CPU is provided with a storage means for data exchange between the two CPU's such as a dual port memory.
To change the program data, the first CPU receives the program data given from outside and changes the program data in its own RAM and at the same time uses the dual port memory RAM to pass the program data from outside to the second CPU. Then, the second CPU reads out the program data stored in the dual port memory RAM, and stores this program data to its own RAM in order to change the program.
However, in this conventional method for program 2 Q 7 ~ 7 7 Y
change in a multlprocessor system, the flrst CPU ls requlred to have not only a means to receive the program data from outslde and change lts own program, but also another means to pass the data to the second CPU. Further, the second CPU also requlres a means to recelve data from the flrst CPU. The need of several means to pass the program data from outslde to each CPU and communlcatlon among them results ln complicated processing for program change. Besides, a speclal storage means such as a dual port memory RAM ls requlred for program data exchange among a plurality of CPU's.
SUMMARY OF THE INVENTION
An ob~ect of the present invention ls to provlde a multlprocessor system wlth program change functlon whlch enables easy program data change without compllcated program data communication.
Another object of the present invention ls to provlde a multlprocessor system provided with a program change functlon whlch does not requlre any speclal storage means for program data change such as a dual port memory.
According to an embodiment of the present invention there ls provlded, a multlprocessor system wlth program change function comprising a plurality of CPU's, lncluding a particular CPU; a plurality of storage means for storlng program data to be executed by said CPU's, each of sald storage means operatlng under control of a correspondlng one of said CPU's during normal processing, sald particular CPU
lncludlng: lnput means for lnputtlng program data from 2~7~77~
outside, flrst output means for outputtlng a control slgnal to others of sald CPU's to cancel control over sald storage means by sald others of sald CPU's durlng program data lnput, and second output means for outputtlng a swltchlng slgnal ldentlfylng one of sald plurallty of storage means to store sald program data; selection means for selecting wlth a selection signal one of said plurality of storage means identified by sald swltching signal from sald particular CPU;
transfer means responsive to said selection slgnal for selectlvely connectlng data signals from said particular CPU
to sald storage means; means responslve to said control signal for selectlvely connectlng read/wrlte and address signals from sald partlcular CPU to sald storage means; and gate means disposed between said selectlon means and sald storage means for connecting sald selection slgnal to sald storage means selected by sald particular CPU.
Accordlng to another embodlment of the lnventlon there ls provlded, a multlprocessor system comprlslng: a plurallty of CPU's lncludlng at least a flrst CPU and a second CPU; a plurallty of storage means for storlng program data each lndlvldual storage means belng selectlvely connected to sald flrst and second CPU, each of said storage means oper-ating under control of corresponding one of sald plurallty of CPU's durlng normal processlng; sald first CPU belng prog-rammed to perform a program change functlon accordlng to a single program change control program, means in sald first CPU
for provldlng a storage control slgnal ln response to lnput of 2 0 7 0 7 7 ~
a program data to said flrst CPU, said storage control slgnal releasing said storage means from being under control of said second CPU during program data input state; buffer means responslve to said storage control signal for selectively connecting read/wrlte and address signals under control of said first CPU to sald storage means; means in said first CPU
for providing a selection signal accordlng to a control data contained in said program data input to said first CPU for storing said program data lnto an ldentlflëd storage means, and means responsive to said selection signal for selectively connecting data signals from sald flrst CPU to sald storage means for loading sald program data lnto said identified storage means.
According to a further embodiment of the lnvention there is provided, a multiprocessor system comprlsing: a first CPU recelvlng program data from an external source, sald flrst CPU executing program load of said program data, said first CPU outputting a control out slgnal indlcating a program load state and outputtlng a select slgnal to select a memory to load said program data; a first memory receiving read/write, address and data signals under control of sald flrst CPU under a non program load state condltlon; at least one other CPU
receivlng sald control out slgnal from sald flrst CPU; a second memory receiving read/write, address and data slgnals under control of sald other CPU during sald non program load state condition, said other CPU being responslve to said control out slgnal to stop outputtlng said read/wrlte, address ~ S~
2 ~ 7 ~ 7 7 9 and data signals to sald second memory; buffer means respon-slve to sald control out slgnal and sald select signal for selectlvely connectlng said readtwrlte, address and data signals under control of sald flrst CPU to sald second memory;
a decoder connected to sald flrst CPU to provlde a flrst and second chlp select slgnal to said flrst and second memorles in response to sald select slgnal provlded from sald flrst CPU;
and whereln said control out slgnal and sald select slgnal provlded control by sald flrst CPU over sald read/wrlte, address and data signals connected to said flrst and second memories, thereby allowlng sald flrst CPU to selectlvely perform program load lnto said flrst and second memorles.
Other ob~ects, characterlstlcs and effects of the present invention wlll be clarifled in the detalled descrlp-tion below.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 ls a block dlagram to show the conflguratlon of a multlprocessor system havlng program change functlon accordlng to a flrst embodlment of the present lnventlon;
Flg. 2 ls a dlagram to show the address maps of the multlprocessor system accordlng to the flrst embodlment ln normal status;
Flg. 3 ls a dlagram to show the address map of the multlprocessor system accordlng to the flrst embodlment when program data is lnput;
Fig. 4 ls a block dlagram to show the conflguratlon of a multlprocessor system wlth program change functlon accordlng to a second embodiment of the present 2~767~g invention;
Fig. 5 is a diagram to show the address maps of the multiprocessor system according to the second embodiment in normal status; and Fig. 6 is a diagram to show the address map of the multiprocessor system according to the second embodiment when program data is input.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to the attached figures, a multiprocessor system with program change function according to a first embodiment of the present invention will be described below. Fig. 1 is a block diagram to show the configuration of a multiprocessor system which adopts the program change method according to a first embodiment of the present invention. This multiprocessor system comprises two CPU's 101 and 102, four RAM's 103, 104, 105 and 106, five OR circuits 107, 108, 109, 110 and 111, a unidirectional buffer 112, a bidirectional buffer 113, a decoder 114 and a ROM 120.
The RAM's 103 through 106 are storage areas to store program data. Usually, the RAM's 103 and 104 store the program data for the CPU 101 and RAM's 105 and 106 store the program data for the CPU 102.
The decoder 114 decodes bank switching signal from the CPU 101 when program data is input so as to output ~7~779 the selection signal to specify one of the RAM's 103 to 106 as the area where the input program data i8 to be stored.
The ROM 120 stores a program for loading to control loading of the program data from outside. The unidirectional buffer 112 is a circuit to transfer the write/read control signal and the address signal from the CPU 101 to the write/read control signal port R/W
and the address signal port ADD at the RAM 105 and the RAM 106 in the CPU 102. This transfer is controlled by the control signal output from the CPU 101 described later. The bidirectional buffer 113 transfers the program data input from outside to the CPU 101 to the RAM 105 and the RAM 106 in the CPU 102 and serves for mutual transfer of program data between the RAM 103 and the RAM 104 and the RAM 105 and the RAM 106 when required. This transfer is controlled by the selection signal from the decoder 114 with the transfer direction being controlled by the write/read control signal from the CPU 101.
A program data input terminal 115 for program data input from outside is connected to the data input port DATA IN at the CPU 101. The write/read control signal port R/W, the address signal port ADD and the data signal port DATA of the CPU 101 are connected with the corresponding write/read control signal port R/W, the ~7~779 address slgnal port ADD and the data slgnal port DATA of the RAM's 105 and 106 respectively. The data slgnal port DATA of the CPU 101 ls further connected wlth the dlrect lonal buffer 113. The wrlte/read control signal port RtW of the CPU 101 ls connected wlth the dlrectlon control lnput port DIR of the bidlrectional buffer 113, the input port of the buffer 112 and the ROM 120. The address signal port ADD of the CPU 101 is connected wlth the lnput port of the buffer 112. The selectlon slgnal ports CS2 and CSl correspondlng to the RAM's 103 and 104 of the CPU 101 are connected wlth the OR clrcults 110 and 111 and the output from the OR clrcults 110 and 111 are connected wlth the selectlon slgnal port CS of the RAM's 103 and 104.
The output port SEL OUT to output the bank swltchlng slgnal of the CPU 101 ls connected wlth the lnput port S~L IN
of the decoder 114. The control slgnal output port CON OUT of the CPU 101 to output the control slgnal to speclfy that the program is belng lnput ls connected wlth the output control port of the buffer 112 and the control slgnal lnput port CON
IN of the CPU 102.
The wrlte/read control slgnal port R/W, the address slgnal port ADD and the data slgnal port DATA of the CPU 102 are connected wlth the corresponding wrlte/read control slgnal port R~W, the address slgnal port ADD and the data slgnal port DATA of the RAM's 103 and 104 respect lvely . The data slgnal port DATA of the CPU 102 ls further connected wlth the bldlrectional buffer 113. The write/read control signal port 2~7~77~
R/W and the address slgnal port ADD of the CPU 102 are connected wlth the output port of the buffer 112. The selectlon signal ports CSl and CS2 for the RAM' s 105 and 106 of the CPU 102 are connected with the OR circults 107 and 108 and the output from these OR clrcults 107 and 108 are connected with the selectlon slgnal port CS of the RAM 105 and the RAM 106 respectlvely.
The selection slgnal ports CSl, CS2, CS3 and CS4 of the decoder 114 are connected wlth the lnput of the OR
clrcults 107, 108, 109, 110 and 111 respectlvely. The output from the OR clrcuit 109 ls connected wlth the enable slgnal port EN to authorize the transfer by the bidirectional buffer 113.
Then, the processing for program change of the multlprocessor system conflgured as above accordlng to the flrst embodlment ls descrlbed.
The program data used by the CPU's 101 and 102 are sent to the CPU 101 vla the program data lnput termlnal 115.
In normal status when program data from outslde is not input, the CPU 101 and the CPU 102 operate accordlng to the address maps as shown ln Figs. 2A and 2B.
The CPU 101 controls the program data input from ~g ~
outside using the program for loading stored in the ROM
120. When the program data from outside is input, the CPU 101 outputs the control signal to indicate that program data is being input from the control signal output port CON OUT, which is input to the control signal input port CON IN of the CPU 102. The input of this control signal causes the CPU 102 to cease the control over the RAM 103 and the RAM 104.
At this point, the bank switching signal from the output port SEL OUT of the CPU 101 is input to the input port SEL IN of the decoder 114 and the selection signal to specify one of the RAM's 103 to 106 is output from the selection signal ports CS1, CS2, CS3 and CS4 of the decoder 114. The selection signal from the selection signal ports CS1 or CS2 is output to the selection signal port CS of the RAM's 103 and 104 via the OR
circuits 110 and 111. The selection signal from the selection signal port CS3 or CS4 is output to the selection signal port CS of the RAM's 105 and 106 vla the OR circuits 107 and 103.
Provision of the control signal from the CPU 101 to the output control input port of the unidirectional buffer 112 enables input of the signals from the write/read control signal port R/W and the address signal port ADD of the CPU 101 to the write/read control signal port R/W and the address signal port ADD of the 2~7~3179 RAM 105 and the RAM 106 via the unidirectional buffer 112. Further, input of the selection signal from the selection signal ports CS3 and CS4 of the decoder 114 to the enable signal port EN of the bidirectional buffer 113 via the OR circult 109 enables data communlcatlons via the bidirectional buffer 113 between the data signal port DATA of the CPU 101 and the data signal ports ADD
of the RAM 105 and the RAM 106. The change of direction at the bidirectional buffer 113 is controlled by the signal from the write/read control signal port R/W of the CPU 101, which is lnput to the direction control input port DIR.
Thus, the RAM 105 and the RAM 106 are selected according to the selection signal from the selection signal ports CS3 and CS4 of the decoder 114, so that they can be controlled by the CPU 101. At the same time, the RAM 103 and the RAM 104 which serve for the CPU 101 itself can be controlled by the selection signal from the selection slgnal ports CS1 and CS2 of the decoder 114. The decoder 114 is controlled by the bank switching signal from the CPU 101.
Therefore, by specifying one of the RAM's 103 to 106 using the bank switching signal, RAM's 103, 104, 105 and 106 can be assigned to a certain address area in the CPU 101. Fig. 3 shows the address map for the CPU 101 under such situation. In Fig. 3, the address area of 2 ~ 7 ~ 9 the RAM 104 ln the CPU 101 is used as the bank switching area and the RAM's 103 to 106 are selectively assigned to the bank switching area.
By serially storing program data from outside to the RAM's 103 to 105 with bank switching using the decoder 114 under such situation, the program data in the RAM's 103 to 106 can be changed.
Upon completion of program data input, the control signal showing that the program data is being lnput at the CPU 101 is canceled. This enables control over the RAM's lOS and 106 of the CPU 102 and disables transfer by the unidirectlonal buffer 112. This causes the write/read signal and the address signal of the CPU 101 to be separated from the RAM's 105 and 106, resulting in the status shown by the address maps in Figs. 2A and 2B.
Once the control signal to show that the program data is being input is canceled, the CPU 102 can make processing using the changed program stored in the RAM's 105 and 106. Thus, the program data in a plurality of CPU's (101 and 102) can be changed using a simple procedure.
Since the RAM's 103 to 106 of the CPU's 101 and 102 are selectively assigned to the bank switching area in this first embodiment, the program data can be serlally stored to the RAM's 103 to 106 without any change in the address map of the CPU 101.
Referring now to Fig. 4, a multiprocessor system ~7~77~
where a program change method accordlng to a ~econd embodlment of the present lnventlon ls descrlbed now.
Flg. 4 ls a block diagram to show the configuratlon of the second embodiment.
In the second embodlment, a RAM 105 and a RAM 106 corresponding to a CPU 102 are controlled by a decoder 124. A
RAM 103 and a RAM 104 are controlled by a CPU 101 as they are ln the flrst embodlment. Conse~uently, the OR clrcults 110 and 111 ln Flg. 1 are omltted here. In additlon, the decoder 124 ls provlded with selectlon slgnal ports CSl and CS2 only, which are to be connected wlth the RAM 105 and the RAM 106.
Except these polnts, the conflguratlon of the second embodlment ls the same as that ln Flg. 1.
Then, the processing for program change of a multl-processor system as configured as above accordlng to the second embodlment is now descrlbed.
In normal status when any program data ls not belng lnput from outslde, the CPU's 101 and 102 operate accordlng to the address maps shown ln Flgs. 5A and 5~.
The address map of the CPU 101 ln thls embodlment ls, unllke the one ln Flg. 2A, provlded wlth the bank swltchlng area for asslgnment of RAM s 105 and 106 ln advance.
The CPU 101 controls the program data lnput from outslde uslng the program for loadlng stored ln a ROM 120.
When program data from outslde ls lnput, the CPU 101 outputs the control slgnal to lndlcate that the program data ls belng ~û7~77~
input from the control slgnal output port. This slgnal ls lnput to the control signal input port of the CPU 102. Input of the control slgnal cancels the control over the RAM's 105 and 106 by the CPU 102.
At this point, the bank swltchlng slgnal from the output port SEL OUT of the CPU 101 ls lnput to the lnput port SEL IN of the decoder 124, and selection signals are output from the select lon signal ports CSl and CS2 of the decoder 124. The selection signal from the selection signal port CSl and CS2 are output to the select ion slgnal port CS of the RAM 105 and the RAM 106 vla the OR clrcults 107 and 108.
The control signal from the CPU 101 is provlded to the output control lnput port of a unldirectlonal buffer 112, enabllng lnput of the slgnal from the wrltetread control slgnal port R/W and the address slgnal port ADD of the CPU 101 to the wrlte/read control slgnal port R/W and the address slgnal port ADD of the RAM 105 and the RAM 106 vla the buffer 112.
Elesldes, the selectlon slgnals from the selectlon slgnal ports CSl and CS2 of the decoder 124 are input to the enable slgnal port EN of a bldlrectlonal buffer 113 vla an OR clrcuit 109, enabllng data communicatlons between the data signal port DATA
2~7~7~
the CPU 101 and the data signal port ADD of the RAM 105 and the RAM 106 vla the bldirectlonal buffer 113. The change of direction at the bidirectional buffer 113 is controlled by the signal from the write/read control signal port R/W of the CPU 101, which is input to the direction control lnput port DIR.
Thus, the RAM's 105 and 106 are controlled by the selection signals from the selection signal ports CS1 and CS2 of the decoder 114, which enables control by the CPU 101. The RAM's 103 and 104 serving for the CPU 101 are controlled by the selection signal from the selection signal ports CSl and CS2 of the CPU 101. The decoder 114 is controlled by the bank switching control signal from the CPU 101.
Therefore, switching between the RAM 105 and the RAM 106 using the bank switching signal enables selective assignment of the RAM's 105 and 106 to the address of the bank switching area in the CPU 101 as shown in the address map shown in Fig. 5A. Fig. 6 shows the address map of the CPU 101 under such status. By sequentially storing the program data from outside to the RAM's 103 and 104 of the CPU 101 itself and to the RAM's 105 and 106 assigned to the bank switching area according to the selection by the decoder 114 under such status, the program data in the RAM's 103 to 106 are changed.
2~P~'S79 Upon completion of program data input, the control signal showlng that the program data is being input at the CPU 101 is canceled. This causes separation from the CPU 102 and returns to the address maps shown in Figs. 5A and 5B. Cancellation of the control signal showing that program data is being input enables the CPU
102 to perform processing using the changed program stored in the RAM's 105 and 106.
Obviously many modifications and variations of the present invention are possible. It is intended to cover in the appended claims all such modifications as fall within the true spirit and scope of the invention.
Claims (7)
1. A multiprocessor system with program change function comprising:
a plurality of CPU's, including a particular CPU;
a plurality of storage means for storing program data to be executed by said CPU's, each of said storage means operating under control of a corresponding one of said CPU's during normal processing, said particular CPU including:
input means for inputting program data from outside, first output means for outputting a control signal to others of said CPU's to cancel control over said storage means by said others of said CPU's during program data input, and second output means for outputting a switching signal identifying one of said plurality of storage means to store said program data;
selection means for selecting with a selection signal one of said plurality of storage means identified by said switching signal from said particular CPU;
transfer means responsive to said selection signal for selectively connecting data signals from said particular CPU
to said storage means;
means responsive to said control signal for selectively connecting read/write and address signals from said particular CPU to said storage means; and gate means disposed between said selection means and said storage means for connecting said selection signal to said storage means selected by said particular CPU.
a plurality of CPU's, including a particular CPU;
a plurality of storage means for storing program data to be executed by said CPU's, each of said storage means operating under control of a corresponding one of said CPU's during normal processing, said particular CPU including:
input means for inputting program data from outside, first output means for outputting a control signal to others of said CPU's to cancel control over said storage means by said others of said CPU's during program data input, and second output means for outputting a switching signal identifying one of said plurality of storage means to store said program data;
selection means for selecting with a selection signal one of said plurality of storage means identified by said switching signal from said particular CPU;
transfer means responsive to said selection signal for selectively connecting data signals from said particular CPU
to said storage means;
means responsive to said control signal for selectively connecting read/write and address signals from said particular CPU to said storage means; and gate means disposed between said selection means and said storage means for connecting said selection signal to said storage means selected by said particular CPU.
2. A multiprocessor system with program change function of claim 1 wherein said selection means comprises a decoder to decode said switching signal from said particular CPU and selectively output said selection signal for said plurality of storage means.
3. A multiprocessor system with program change function of claim 1 wherein said particular CPU assigns said selected storage means to the address area of its own storage means.
4. A multiprocessor system with program change function of claim 1 wherein said transfer means comprises a bidirectional buffer provided between said particular CPU and said other CPU storage means.
5. A multiprocessor system with program change function of claim 1 wherein an address area of said particular CPU is provlded with an address area for assigning said storage means of other CPU selected by said selection means in addition to the address area of the storage means for the particular CPU
itself.
itself.
6. A multiprocessor system comprising:
a plurality of CPU's including at least a first CPU and a second CPU;
a plurality of storage means for storing program data each individual storage means being selectively connected to said first and second CPU, each of said storage means operating under control of corresponding one of said plurality of CPU's during normal processing;
said first CPU being programmed to perform a program change function according to a single program change control program, means in said first CPU for providing a storage control signal in response to input of a program data to said first CPU, said storage control signal releasing said storage means from being under control of said second CPU during program data input state;
buffer means responsive to said storage control signal for selectively connecting read/write and address signals under control of said first CPU to said storage means;
means in said first CPU for providing a selection signal according to a control data contained in said program data input to said first CPU for storing said program data into an identified storage means, and means responsive to said selection signal for selectively connecting data signals from said first CPU to said storage means for loading said program data into said identified storage means.
a plurality of CPU's including at least a first CPU and a second CPU;
a plurality of storage means for storing program data each individual storage means being selectively connected to said first and second CPU, each of said storage means operating under control of corresponding one of said plurality of CPU's during normal processing;
said first CPU being programmed to perform a program change function according to a single program change control program, means in said first CPU for providing a storage control signal in response to input of a program data to said first CPU, said storage control signal releasing said storage means from being under control of said second CPU during program data input state;
buffer means responsive to said storage control signal for selectively connecting read/write and address signals under control of said first CPU to said storage means;
means in said first CPU for providing a selection signal according to a control data contained in said program data input to said first CPU for storing said program data into an identified storage means, and means responsive to said selection signal for selectively connecting data signals from said first CPU to said storage means for loading said program data into said identified storage means.
7. A multiprocessor system comprising:
a first CPU receiving program data from an external source, said first CPU executing program load of said program data, said first CPU outputting a control out signal indicating a program load state and outputting a select signal to select a memory to load said program data;
a first memory receiving read/write, address and data signals under control of said first CPU under a non program load state condition;
at least one other CPU receiving said control out signal from said first CPU;
a second memory receiving read/write, address and data signals under control of said other CPU during said non program load state condition, said other CPU being responsive to said control out signal to stop outputting said read/write, address and data signals to said second memory;
buffer means responsive to said control out signal and said select signal for selectively connecting said read/write, address and data signals under control of said first CPU to said second memory;
a decoder connected to said first CPU to provide a first and second chip select signal to said first and second memories in response to said select signal provided from said first CPU; and wherein said control out signal and said select signal provided control by said first CPU over said read/write, address and data signals connected to said first and second memories, thereby allowing said first CPU to selectively perform program load into said first and second memories.
a first CPU receiving program data from an external source, said first CPU executing program load of said program data, said first CPU outputting a control out signal indicating a program load state and outputting a select signal to select a memory to load said program data;
a first memory receiving read/write, address and data signals under control of said first CPU under a non program load state condition;
at least one other CPU receiving said control out signal from said first CPU;
a second memory receiving read/write, address and data signals under control of said other CPU during said non program load state condition, said other CPU being responsive to said control out signal to stop outputting said read/write, address and data signals to said second memory;
buffer means responsive to said control out signal and said select signal for selectively connecting said read/write, address and data signals under control of said first CPU to said second memory;
a decoder connected to said first CPU to provide a first and second chip select signal to said first and second memories in response to said select signal provided from said first CPU; and wherein said control out signal and said select signal provided control by said first CPU over said read/write, address and data signals connected to said first and second memories, thereby allowing said first CPU to selectively perform program load into said first and second memories.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3-236904 | 1991-08-26 | ||
| JP03236904A JP3092116B2 (en) | 1991-08-26 | 1991-08-26 | Program change method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2076779A1 CA2076779A1 (en) | 1993-02-27 |
| CA2076779C true CA2076779C (en) | 1998-08-18 |
Family
ID=17007480
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002076779A Expired - Fee Related CA2076779C (en) | 1991-08-26 | 1992-08-25 | Multiprocessor system with program change function |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5333278A (en) |
| JP (1) | JP3092116B2 (en) |
| CA (1) | CA2076779C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6023758A (en) * | 1995-05-25 | 2000-02-08 | Matsushita Electric Industrial Co., Ltd. | Method and processor for changing program by replacing instruction stored in ROM with predetermined value to be interpreted as an instruction |
| US5867394A (en) * | 1996-03-01 | 1999-02-02 | The Standard Register Company | Document dispenser operational program downloading |
| JP6565389B2 (en) * | 2015-07-02 | 2019-08-28 | セイコーエプソン株式会社 | Printer firmware rewriting method and printer |
| US10108567B2 (en) * | 2016-12-22 | 2018-10-23 | Integrated Device Technology, Inc. | Memory channel selection control |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4181940A (en) * | 1978-02-28 | 1980-01-01 | Westinghouse Electric Corp. | Multiprocessor for providing fault isolation test upon itself |
| US4539656A (en) * | 1982-11-01 | 1985-09-03 | Gte Automatic Electric Incorporated | Memory access selection circuit |
| JPS60157646A (en) * | 1984-01-27 | 1985-08-17 | Mitsubishi Electric Corp | Memory bank switching device |
| JPS61180352A (en) * | 1984-12-30 | 1986-08-13 | Fujitsu Ltd | Down-loading system for program |
| JPS62174844A (en) * | 1986-01-29 | 1987-07-31 | Hitachi Ltd | Switching system for memory priority |
| CA1330596C (en) * | 1986-11-19 | 1994-07-05 | Yoshiaki Nakanishi | Memory cartridge and data processing apparatus |
| JPS63184155A (en) * | 1987-01-27 | 1988-07-29 | Toshiba Corp | Down load system for multiprocessor system |
| JP2741514B2 (en) * | 1987-08-05 | 1998-04-22 | 株式会社安川電機 | Multi CPU system |
| US4959776A (en) * | 1987-12-21 | 1990-09-25 | Raytheon Company | Method and apparatus for addressing a memory by array transformations |
| US5146581A (en) * | 1988-02-24 | 1992-09-08 | Sanyo Electric Co., Ltd. | Subprogram executing data processing system having bank switching control storing in the same address area in each of memory banks |
| US5167028A (en) * | 1989-11-13 | 1992-11-24 | Lucid Corporation | System for controlling task operation of slave processor by switching access to shared memory banks by master processor |
-
1991
- 1991-08-26 JP JP03236904A patent/JP3092116B2/en not_active Expired - Fee Related
-
1992
- 1992-08-25 CA CA002076779A patent/CA2076779C/en not_active Expired - Fee Related
- 1992-08-26 US US07/935,198 patent/US5333278A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US5333278A (en) | 1994-07-26 |
| CA2076779A1 (en) | 1993-02-27 |
| JPH0553787A (en) | 1993-03-05 |
| JP3092116B2 (en) | 2000-09-25 |
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