CA2059027C - Switching system with time-stamped packet distribution input stage and packet sequencing output stage - Google Patents
Switching system with time-stamped packet distribution input stage and packet sequencing output stageInfo
- Publication number
- CA2059027C CA2059027C CA002059027A CA2059027A CA2059027C CA 2059027 C CA2059027 C CA 2059027C CA 002059027 A CA002059027 A CA 002059027A CA 2059027 A CA2059027 A CA 2059027A CA 2059027 C CA2059027 C CA 2059027C
- Authority
- CA
- Canada
- Prior art keywords
- packet
- packets
- timeslot
- timeslot number
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/15—Interconnection of switching modules
- H04L49/1515—Non-blocking multistage, e.g. Clos
- H04L49/153—ATM switching fabrics having parallel switch planes
- H04L49/1538—Cell slicing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/15—Interconnection of switching modules
- H04L49/1553—Interconnection of ATM switching modules, e.g. ATM switching fabrics
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/565—Sequence integrity
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3009—Header conversion, routing tables or routing tags
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/50—Overload detection or protection within a single switching element
- H04L49/501—Overload detection
- H04L49/503—Policing
Abstract
In a fast packet switching system, packet distributers are associated respectively with input ports for receiving successive packets therefrom and attaching a timeslot number to each of the received packets, and uniformly distributing the packets to output terminals of each distributer.
Packet switches are provided corresponding in number to the output terminals of each packet distributer. Each packet switch has input terminals corresponding in number to the packet distributers and output terminals corresponding in number to the output ports. The input terminals of each packet switch are coupled to respective output terminals of the distributers for switching a packet from one of its input terminals to one of its output terminals in accordance with a destination address contained in the packet. Packet sequencers are associated respectively with the output ports. Each packet sequencer has input terminals coupled to respective output terminals of the packet switches for examining the timeslot numbers attached to packets from its input terminals and delivering the packets to the associated output port in accordance with the examined timeslot numbers.
Packet switches are provided corresponding in number to the output terminals of each packet distributer. Each packet switch has input terminals corresponding in number to the packet distributers and output terminals corresponding in number to the output ports. The input terminals of each packet switch are coupled to respective output terminals of the distributers for switching a packet from one of its input terminals to one of its output terminals in accordance with a destination address contained in the packet. Packet sequencers are associated respectively with the output ports. Each packet sequencer has input terminals coupled to respective output terminals of the packet switches for examining the timeslot numbers attached to packets from its input terminals and delivering the packets to the associated output port in accordance with the examined timeslot numbers.
Description
~ NE-386 _ TITLE OF THE INVENTION
2 "Switching System With Time-Stamped Packet Distribution Input Stage 3 And Packet Sequencing Output Stage"
s The present invention relates generally to packet switching systems, 6 and more specifically to a fast packet switching system for ISDN
7 (Integrated Services Digital Network).
8 Research effort has currently been focused on fast packet switching g systems for transporting and switching all classes of information by 1 o segmenting signals into small packets and transporting them using 1 1 simplified protocols. An architecture of such a fast packet switching 12 system is described in a paper "A shared buffer memory switch for an 13 ATM exchange", H. Kuwahara et al, (CH2655-9/89/0000-011 8) 1989, 1 4 IEEE. According to this technique, incoming packets are bit-sliced by a 1 s serial-to-parallel converters into packet segments for coupling to 1 6 respective connection oriented sub-switching systems, and sequenced 17 again by parallel-to-serial converters into the original packet at the output 18 port. If the incoming packet has an L-bit length, it can be bit sliced to a 19 maximum of L packet segments, allowing the sub-switching systems to operate at a speed l/L of the speed of serial processing.
21 The switching speed of the prior art packet swikhing systems is given 22 by the relation N x V/K, where V is the line transmission speed, N the 23 number of input ports, and K the number of packet segments into which 24 each packet is bit-sliced. For a given switching speed, the line speed and the number of input ports can be increased by increasing the K value 26 whose maximum value is equal to the bit length L. Typical values are N =
27 32, V = 4.8 Gbps, and L = K = 53 bytes for a switching speed of 362 28 Mbps. However, this value is still too high for implementing packet 29 switching systems.
.~
~ NE-386 SUMMARY OF THE INVENTION
2 It is therefore an object of the present invention to provide a packet 3 switching system which is allowed to operate at a switching speed which 4 is suitable for practical implementations.
According to the present invention, there is provided a packet 6 switching system having a plurality of input ports and a plurality of output 7 ports. The system comprises a plurality of packet distributers associated 8 respectively with the input ports for receiving successive packets 9 therefrom, each of the packet distributers attaching a timeslot number to 10 each of the received packets, and uniformly distributing the packets to a 11 plurality of output terminals thereof. A plurality of packet switches 12 comprise the center stage of the system. These packet switches 13 correspond in number to the output terminals of each of the packet 14 distributers, and each of the packet switches has a plurality of input 15 terminals corresponding in number to the packet distributers and a 16 plurality of output terminals corresponding in number to the output ports.
17 The input terminals of each packet switch are coupled to respective 18 output terminals of the packet distributers for switching a packet from one 19 of the input terminals thereof to one of the output terminals thereof in 20 accordance with a destination address contained in the packet. A
21 plurality of packet sequencers are associated respectively with the output 22 ports. Each of the packet sequencers has a plurality of input terminals 2 3 coupled to respective output terminals of the packet switches for 24 examining the timeslot numbers attached to packets from the input 2 s terminals thereof and delivering the packets to the associated output port 26 in accordance with the examined timeslot numbers.
27 For uniform distribution of packets to the center stage, each of the 28 packet switches generates a traffic-related signal indicating the amount of 2 9 packets outstanding in the packet switch. Each packet distributer receives -the trafflc-related signal from each packet switch and gives prlorlty to the output termlnals of the packet dlstrlbuter according to the amounts of packets outstandlng ln the respectlve packet swltches. In this way, packets from the associated lnput port are dlstributed with priority to those of the packet switches containing a smaller amount of outstanding packets.
Accordlng to a broad aspect, the invention provides a packet swltchlng æystem having a plurallty of input ports and a plurality of output ports, comprising, a plurallty of packet distributers associated respectively with the input ports for recelving successive packets therefrom, each of said packet distrlbuters attachlng a tlmeslot number to each of the recelved packets, and unlformly dlstrlbutlng the packets to a plurallty of output termlnals thereof;
a plurallty of packet swltches correspondlng ln number to the output termlnals of each of the packet dlstrlbuters, each of the packet swltches having a plurality of input terminals corresponding in number to the packet distributers and a plurality of output termlnals corresponding in number to said output ports, the input terminals of each packet switch being coupled to respectlve output termlnals of sald packet dlstrlbuters for swltchlng a packet from one of the input terminals thereof to one of the output terminals thereof in accordance with a destinatlon address contalned in the packet; and : .
`~ 2059027 - 3a -a plurallty of packet sequencers assoclated respectlvely wlth said output ports, each of the packet sequencers havlng a plurallty of input termlnals coupled to respectlve output termlnals of the packet swltches for examlnlng the tlmeslot numbers attached to packets from the lnput terminals thereof and dellverlng the packets to the assoclated output port ln accordance wlth the examlned tlmeslot numbers.
Although self-routlng swltches are of beneflt for certaln appllcatlons, blt-sllclng technlque can be used for hlgher speed swltchlng appllcatlon. If blt-sllclng technlque ls used for the center swltchlng stage, the swltchlng speed of the system can be decreased to N x V/P x L, where P ls the number of swltches of the center stage.
~RIEF DESCRIPTION OF THE DRAWINGS
The present lnventlon wlll be descrlbed ln further detall wlth reference to the accompanylng drawlngs, ln whlch:
Flg. 1 ls a block dlagram of a packet swltchlng system of the present lnventlon;
Flg. 2 ls a block dlagram showlng detalls of each packet dlstrlbuter of Flg. l;
Flg. 3 ls a block dlagram showlng detalls of each packet swltch;
Flg. 4 ls a block dlagram showlng one embodlment of a packet sequencer, Flgs. 4A to 4D showlng data sets movlng through packet reorderlng clrcult of the sequencer;
~,., - 3b -Flg. 5 ls a block dlagram showlng a flrst modlflcatlon of the packet sequencer;
Flg. 6 ls a block dlagram of a second modlflcatlon of the packet sequencer;
Flg. 7 ls a block dlagram of a thlrd modlflcatlon of the packet sequencer;
Flg. 8 ls a block dlagram of a fourth modlflcatlon of the packet _ 1 sequencer;
2 Fig. 9 is a block diagram of the packet switching system according to3 a second embodiment of this invention;
4 Fig. 10 shows details of a packet distributer of Fig. 9;
s Fig. 11 shows details of a packet switch of Fig. 9;
6 Fig. 12 shows details of a modified form of the packet distributer of7 Fig. 9; and 8 Fig. 13 shows details of a modified form of the packet switch of Fig. 9 g associated with the modified packet distributer of Fig. 12.
DETAILED DESCRIPTION
1 1 Referring now to Fig. 1, there is shown a packet switching system 12 according to one embodiment of the present invention. For purposes of 1 3 illustration, the switching system has four input ports 1 l through 104 for 14 receiving packets of a predetermined bit length from user stations at a line clock rate specified by the system and switching the received packets to 1 6 one of four output ports 141 through 144. Each packet contains a label 17 indicating a destination user station. The system comprises a plurality of 18 packet distributers 111 ~ 114 corresponding respectively to the input ports 19 1 l - 104, a plurality of 4 x 4 self-routing packet switches 121 ~ 12420 corresponding in number to the packet distributers, and a like plurality of 21 packet sequencers 131 - 134 corresponding respectively to the output 2 2 ports 141 - 144. Each packet distributer 1 1 j has four output terminals 2 3 coupled respectively to the ith input terminals of all packet switches 12.
2 4 The output terminals of each packet switch 12; are coupled respectively to 25 the ith input terminals of all packet sequencers 13.
2 6 On receiving a packet, each packet distributer 11; extracts the label 27 from the packet and uses it to reference a routing table 15 to attach an 28 outgoing address identifying one of the output ports 14. The distributer 29 proceeds to attach a timeslot number to the packet, selects one of the s 2059027 packet switches 12 and applies the packet to the selected packet switch 2 so that packets received successively from a given user are distributed 3 uniformly to the packet switches. To assign a timeslot number, a series of 4 referencé timeslot numbers is cyclically generated by a system time base S 16 and supplied to all packet distributers 11. In each self-routing packet 6 swikh 12, each packet is examined for its destination and routed to one of 7 the packet sequencers 13 according to the outgoing identifier contained 8 in the label. Because of the parallel switching of successive packets by g packet switches 121 ~ 124, each packet switch is given an interval for 10 switching which is four times longer than would otherwise be allowed if ~
11 the burden is placed on a single packet switch.
12 Packets destined to a given output port may arrive at the packet 13 sequencer associated with that port at different times. To secure packet 14 sequence integrity, each packet sequencer extracts the time stamp from 15 each packet and uses it to rearrange successive packets in the original 16 sequence.
17 Details of the system components will now be described. In Fig. 2, 18 each packet distributer 11 j of Fig. 1 comprises a packet detector 20 19 coupled to the associated input port 1 0j for extracting a label from each incoming packet and applies it to the routing table 15 to rewrite its label 21 with an outgoing address obtained from the routing table and applies its 22 output to a multiplexer 22. Simultaneously, it informs the arrival of a 2 3 packet to a timeslot number (TSN) assignment circuit 21 to which the 24 reference timeslot number is supplied from the time base 16. In a practical embodiment, each of the packet switches may hold a sequence 26 of a maximum of, say, 100 outstanding packets. In order to allow 27 identification of packets arriving at a given packet sequencer, timeslot 28 numbers #1 through #100 are assigned respectively to one hundred 29 packets of each successive sequence and the same numbers are cyclically - 6 - 2 05 9 ~ 27 used. The TSN assignment CiKUit 21 assigns a timeslot number to each 2 packet in response to an output signal from packet detector 20 and 3 applies the assigned number to multiplexer 22 so that the packet is 4 mulbplexed with the assigned timeslot number which is unique to the ~5 sequence of 100 packets to which it belongs.
6 ~- An input port address generator 23 is also connected to multiplexer 7 22 to append an identifier identifying the input port 1 0j. This identifier will 8 be used by the packet sequencers constructed according to one g embodiment of this invention.
0 The output of multiplexer 22 is applied to a switch 24 which applies ~
11 packets from multiplexer 22 to latches 26 in accordance with a switching 12 signal supplied from a controller 25. The outputs of latches 261 ~ 264 of 13 packet distributer 11 j are respectively connected to the ith input terminals 14 of packet switches 121 ~ 124. Controller 25 sequentially selects latches 26 5 so that successive packets are sequentially distributed to all latches 26. At 16 periodic clock intervals, the packets stored in latches 26 are 17 simultaneously forwarded to the corresponding packet switches 12.
18 As shown in Fig. 3, each self-routing packet switch 12; comprises a 19 multiplexer 30 for multiplexing signals from the ith outputs of all packet distributers 11 and forwarding the multiplexed signal onto a common bus 21 31 to which are connected address filters 321 ~ 324 having filter addresses 22 identifying respectively the output ports 141 ~ 144. First-in-first-out 23 memories 331~334 are connected respectively to the outputs of address 24 filters 321 - 324, the outputs of FIFO memories 331~334 of each packet switch 1 2j being connected to the ith inputs of packet sequencers 1 31 ~
26 134, respectively. Each address filter 32 examines the outgoing address 27 contained in each of packets arriving from the dirrere"t packet distributers2 8 11 and detects a match or mismatch with the address of the filter 32. On 29 detecting a match, each address filter 32; allows a packet to be passed therethrough to corresponding FIFO memory 33j. The outputs of FIFO
2 memories 331, 332, 333 and 334 of packet switch 12; are connected to the 3 ith input terminals of packet sequencers 131, 132, 133 and 134, 4 respectively.
s Fig. 4 shows one embodiment of packet sequencer 13;. Sequencer 6 13; comprises a multiplexer 40 for multiplexing signals from the ith output 7 terminals of packet switches 121 ~ 124 into a single data bit stream for 8 coupling to a timeslot number detector 41 in which the timeslot number g of each packet is removed from the packet and applied to a multiplexer 10 48, while packets destined to the same output port are supplied to a 11 packet memory (dual-port RAM) in sequence. A write address generator 12 43 applies sequential write address data to memory 44 so that packets 13 are stored into memory 44 in the order of arrival at the packet sequencer.
14 The write address data is also applied to multiplexer 48 in which it is 15 combined with a timeslot number to form a data set. Latches 491 - 49n 16 are connected in a series circuit to store and shift a data set from one latch 17 to the next and from one latch to a corresponding one of compare-and-18 select circuits 501 - 50n which are also connected in series between the 19 output of multiplexer 48 and latch 49n. A difference detector 45 is 20 supplied with the rererellce timeslot number from time base 16 to detect 21 the difference between it and the timeslot number contained in the output 22 of latch 491. The output of difference detector 45 is applied to a 23 comparator 46 in which it is compared with a threshold value which 24 represents a maximum delay time allowable for each packet and 2s corresponds to the maximum number of packets outstanding in the 26 packet switches. Comparator 46 generates an output signal when the 27 difference output from detector 45 is greater than the threshold value and 28 enables a gate 47 for coupling the address component of a data set from 29 latch 491 to RAM 44 as a read address pointer for reading a packet therefrom corresponding to the timeslot number of that data set.
2 Compare-and-select circuit 501 compares the timeslot number of the 3 output of multiplexer 48 with the bmeslot number of a data set stored in 4 latch 491 and transfers the data set from multiplexer 48 to the next 5 compare-and-select circuit 52 if the timeslot number from multiplexer 48 6 is greater than the timeslot number from latch 491 and interchanges the 7 compared data sets and transfers the data set from latch 491 to the next 8 compare-and-select circuit if the timeslot number from multiplexer 48 is 9 smaller than the other. Likewise, each of the succeeding compare-and-10 select circuits 50; compares the timeslot number of the output of the 11 preceding compare-and-select circuit with the timeslot number of a data 12 set stored in corresponding latch 49; and transfers the data set from the 13 preceding compare-and-select circuit to the next compare-and-select 14 circuit if the timeslot number from the preceding circuit is greater than the timeslot number from the corresponding latch and interchanges the 16 compared data sets and transfers the data set from the corresponding 17 latch to the next compare-and-select circuit if the timeslot number from 18 the preceding circuit is smaller than the other.
19 The operation of this packet sequencer will best be understood with reference to Figs. 4A ~ 4D. For purposes of simplicity, it is assumed that 21 only three sets of compare-and-select circuits and corresponding latches 22 are provided. Assume that a given packet has a timeslot number "15"
23 and is stored in RAM 44 in a location identified by write address data "6".
24 This timeslot number is combined by multiplexer 48 with the timeslot number "15' supplied from write address generator 43 to produce a data 2 6 set ("6"/~15"). Up to this point, data sets ("8"/"10"), (nl 2"/"20") and 27 (115"/n22~) are assumed to have been stored respectively in latches 491, 2 8 492 and 493, as shown in Fig. 4A. The output of multiplexer 48 is applied 29 to compare-and-select circuit 51 in which the timeslot number "15" is compared with the timeslot number "10" of the data set stored in latch 2 491. Compare-and-select circuit 50l transfers the data set (116n/1l15~) to the3 next circuit 52 for comparison with the timeslot number "20" stored in 4 corresponding latch 492. Compare-and-select circuit 52 thus s interchanges data sets with latch 492 and transfer data set (~12n/"20~) to 6 compare-and-select circuit 503 (Fig. 4B) for making a comparison with the 7 timeslot number "22" stored in corresponding latch 493. Thus, data sets in 8 latch 493 and compare-and-select circuit 503 are interchanged and data 9 set ("5"/n22") from latch 493 is transferred to the next compare-and-select 10 circuit (Fig. 4C).
1 1 In this way, data sets stored in latches 491 ~ 493 are arranged in the 12 order of timeslot numbers with the timeslot number stored in latch 491 13 being always the smallest of all timeslot numbers stored in latches 49. At 14 the end of this process, the timeslot number stored in latch 491 is applied 15 to the difference detector 45. If the difference betweén it and the 16 reference timeslot number is greater than the threshold value, 17 comparator 46 enables gate 47 to pass the address component of the 18 data set stored in latch 491 to RAM 44 as a read address pointer for 1 9 reading the given packet mentioned above. Simultaneously, data sets 20 stored in all latches 49 are shifted to the left as shown in Fig. 4D.
21 Since the reference timeslot number represents the real time, the 22 output of difference detector 45 indicates the amount of time a packet has 2 3 elapsed from the time at which a timeslot number is assigned to it by a 24 packet distributer 11 ;. Thus, each packet is read out of memory 44 25 following the detection of a maximum delay time within which an 26 outstanding packet having a smaller timeslot number than any of the 27 packets in the sequencer 13j may possible exist in a packet switch 12.
2 8 Thus, the packet read out of memory 44 is ensured that it is the earliest of2 9 all packets in a packet sequencer 13; for a given instant of time.
_ NE-386 - lo- 2059027 The packet sequencers are modified in several forms as shown in 2 Figs. S to 8. In Fig. 5, sequencer 13; includes a multiplexer 60 in which the 3 output signals from the ith output terminals of all packet switches 12 are 4 multiplexed into a series of packets. The output of multiplexer 60 is S connected to.address filters 611 - 614 to which dual-port RAMs 621 - 624 6 are respectively connected. The address of each filter 61; (where i = 1, 2, 7 3, 4) corresponds to the address of the input port 10;. Each address filter 8 61; examines each packet for the input-port address generated by the 9 address generator 23 of a packet distributer 11 j (Fig. 2) and detects a 10 match or mismatch with the own filter address. If a match is detected, the 11 address filter passes the matched packet to the associated memory 62.
12 Therefore, packets coming from the same input port 1 0j are passed 13 through address filter 61 j and stored into packet memory 62j. Memory 14 controllers 63j are associated respectively with address filters 61 j and 15 packet memories 62j to provide read/write control on associated packets 16 for sequential.delivery to a multiplexer 64 in which the packets having the same destination but coming from different input ports 11 are sequentially 8 arranged and delivered to output port 14;.
7 (Integrated Services Digital Network).
8 Research effort has currently been focused on fast packet switching g systems for transporting and switching all classes of information by 1 o segmenting signals into small packets and transporting them using 1 1 simplified protocols. An architecture of such a fast packet switching 12 system is described in a paper "A shared buffer memory switch for an 13 ATM exchange", H. Kuwahara et al, (CH2655-9/89/0000-011 8) 1989, 1 4 IEEE. According to this technique, incoming packets are bit-sliced by a 1 s serial-to-parallel converters into packet segments for coupling to 1 6 respective connection oriented sub-switching systems, and sequenced 17 again by parallel-to-serial converters into the original packet at the output 18 port. If the incoming packet has an L-bit length, it can be bit sliced to a 19 maximum of L packet segments, allowing the sub-switching systems to operate at a speed l/L of the speed of serial processing.
21 The switching speed of the prior art packet swikhing systems is given 22 by the relation N x V/K, where V is the line transmission speed, N the 23 number of input ports, and K the number of packet segments into which 24 each packet is bit-sliced. For a given switching speed, the line speed and the number of input ports can be increased by increasing the K value 26 whose maximum value is equal to the bit length L. Typical values are N =
27 32, V = 4.8 Gbps, and L = K = 53 bytes for a switching speed of 362 28 Mbps. However, this value is still too high for implementing packet 29 switching systems.
.~
~ NE-386 SUMMARY OF THE INVENTION
2 It is therefore an object of the present invention to provide a packet 3 switching system which is allowed to operate at a switching speed which 4 is suitable for practical implementations.
According to the present invention, there is provided a packet 6 switching system having a plurality of input ports and a plurality of output 7 ports. The system comprises a plurality of packet distributers associated 8 respectively with the input ports for receiving successive packets 9 therefrom, each of the packet distributers attaching a timeslot number to 10 each of the received packets, and uniformly distributing the packets to a 11 plurality of output terminals thereof. A plurality of packet switches 12 comprise the center stage of the system. These packet switches 13 correspond in number to the output terminals of each of the packet 14 distributers, and each of the packet switches has a plurality of input 15 terminals corresponding in number to the packet distributers and a 16 plurality of output terminals corresponding in number to the output ports.
17 The input terminals of each packet switch are coupled to respective 18 output terminals of the packet distributers for switching a packet from one 19 of the input terminals thereof to one of the output terminals thereof in 20 accordance with a destination address contained in the packet. A
21 plurality of packet sequencers are associated respectively with the output 22 ports. Each of the packet sequencers has a plurality of input terminals 2 3 coupled to respective output terminals of the packet switches for 24 examining the timeslot numbers attached to packets from the input 2 s terminals thereof and delivering the packets to the associated output port 26 in accordance with the examined timeslot numbers.
27 For uniform distribution of packets to the center stage, each of the 28 packet switches generates a traffic-related signal indicating the amount of 2 9 packets outstanding in the packet switch. Each packet distributer receives -the trafflc-related signal from each packet switch and gives prlorlty to the output termlnals of the packet dlstrlbuter according to the amounts of packets outstandlng ln the respectlve packet swltches. In this way, packets from the associated lnput port are dlstributed with priority to those of the packet switches containing a smaller amount of outstanding packets.
Accordlng to a broad aspect, the invention provides a packet swltchlng æystem having a plurallty of input ports and a plurality of output ports, comprising, a plurallty of packet distributers associated respectively with the input ports for recelving successive packets therefrom, each of said packet distrlbuters attachlng a tlmeslot number to each of the recelved packets, and unlformly dlstrlbutlng the packets to a plurallty of output termlnals thereof;
a plurallty of packet swltches correspondlng ln number to the output termlnals of each of the packet dlstrlbuters, each of the packet swltches having a plurality of input terminals corresponding in number to the packet distributers and a plurality of output termlnals corresponding in number to said output ports, the input terminals of each packet switch being coupled to respectlve output termlnals of sald packet dlstrlbuters for swltchlng a packet from one of the input terminals thereof to one of the output terminals thereof in accordance with a destinatlon address contalned in the packet; and : .
`~ 2059027 - 3a -a plurallty of packet sequencers assoclated respectlvely wlth said output ports, each of the packet sequencers havlng a plurallty of input termlnals coupled to respectlve output termlnals of the packet swltches for examlnlng the tlmeslot numbers attached to packets from the lnput terminals thereof and dellverlng the packets to the assoclated output port ln accordance wlth the examlned tlmeslot numbers.
Although self-routlng swltches are of beneflt for certaln appllcatlons, blt-sllclng technlque can be used for hlgher speed swltchlng appllcatlon. If blt-sllclng technlque ls used for the center swltchlng stage, the swltchlng speed of the system can be decreased to N x V/P x L, where P ls the number of swltches of the center stage.
~RIEF DESCRIPTION OF THE DRAWINGS
The present lnventlon wlll be descrlbed ln further detall wlth reference to the accompanylng drawlngs, ln whlch:
Flg. 1 ls a block dlagram of a packet swltchlng system of the present lnventlon;
Flg. 2 ls a block dlagram showlng detalls of each packet dlstrlbuter of Flg. l;
Flg. 3 ls a block dlagram showlng detalls of each packet swltch;
Flg. 4 ls a block dlagram showlng one embodlment of a packet sequencer, Flgs. 4A to 4D showlng data sets movlng through packet reorderlng clrcult of the sequencer;
~,., - 3b -Flg. 5 ls a block dlagram showlng a flrst modlflcatlon of the packet sequencer;
Flg. 6 ls a block dlagram of a second modlflcatlon of the packet sequencer;
Flg. 7 ls a block dlagram of a thlrd modlflcatlon of the packet sequencer;
Flg. 8 ls a block dlagram of a fourth modlflcatlon of the packet _ 1 sequencer;
2 Fig. 9 is a block diagram of the packet switching system according to3 a second embodiment of this invention;
4 Fig. 10 shows details of a packet distributer of Fig. 9;
s Fig. 11 shows details of a packet switch of Fig. 9;
6 Fig. 12 shows details of a modified form of the packet distributer of7 Fig. 9; and 8 Fig. 13 shows details of a modified form of the packet switch of Fig. 9 g associated with the modified packet distributer of Fig. 12.
DETAILED DESCRIPTION
1 1 Referring now to Fig. 1, there is shown a packet switching system 12 according to one embodiment of the present invention. For purposes of 1 3 illustration, the switching system has four input ports 1 l through 104 for 14 receiving packets of a predetermined bit length from user stations at a line clock rate specified by the system and switching the received packets to 1 6 one of four output ports 141 through 144. Each packet contains a label 17 indicating a destination user station. The system comprises a plurality of 18 packet distributers 111 ~ 114 corresponding respectively to the input ports 19 1 l - 104, a plurality of 4 x 4 self-routing packet switches 121 ~ 12420 corresponding in number to the packet distributers, and a like plurality of 21 packet sequencers 131 - 134 corresponding respectively to the output 2 2 ports 141 - 144. Each packet distributer 1 1 j has four output terminals 2 3 coupled respectively to the ith input terminals of all packet switches 12.
2 4 The output terminals of each packet switch 12; are coupled respectively to 25 the ith input terminals of all packet sequencers 13.
2 6 On receiving a packet, each packet distributer 11; extracts the label 27 from the packet and uses it to reference a routing table 15 to attach an 28 outgoing address identifying one of the output ports 14. The distributer 29 proceeds to attach a timeslot number to the packet, selects one of the s 2059027 packet switches 12 and applies the packet to the selected packet switch 2 so that packets received successively from a given user are distributed 3 uniformly to the packet switches. To assign a timeslot number, a series of 4 referencé timeslot numbers is cyclically generated by a system time base S 16 and supplied to all packet distributers 11. In each self-routing packet 6 swikh 12, each packet is examined for its destination and routed to one of 7 the packet sequencers 13 according to the outgoing identifier contained 8 in the label. Because of the parallel switching of successive packets by g packet switches 121 ~ 124, each packet switch is given an interval for 10 switching which is four times longer than would otherwise be allowed if ~
11 the burden is placed on a single packet switch.
12 Packets destined to a given output port may arrive at the packet 13 sequencer associated with that port at different times. To secure packet 14 sequence integrity, each packet sequencer extracts the time stamp from 15 each packet and uses it to rearrange successive packets in the original 16 sequence.
17 Details of the system components will now be described. In Fig. 2, 18 each packet distributer 11 j of Fig. 1 comprises a packet detector 20 19 coupled to the associated input port 1 0j for extracting a label from each incoming packet and applies it to the routing table 15 to rewrite its label 21 with an outgoing address obtained from the routing table and applies its 22 output to a multiplexer 22. Simultaneously, it informs the arrival of a 2 3 packet to a timeslot number (TSN) assignment circuit 21 to which the 24 reference timeslot number is supplied from the time base 16. In a practical embodiment, each of the packet switches may hold a sequence 26 of a maximum of, say, 100 outstanding packets. In order to allow 27 identification of packets arriving at a given packet sequencer, timeslot 28 numbers #1 through #100 are assigned respectively to one hundred 29 packets of each successive sequence and the same numbers are cyclically - 6 - 2 05 9 ~ 27 used. The TSN assignment CiKUit 21 assigns a timeslot number to each 2 packet in response to an output signal from packet detector 20 and 3 applies the assigned number to multiplexer 22 so that the packet is 4 mulbplexed with the assigned timeslot number which is unique to the ~5 sequence of 100 packets to which it belongs.
6 ~- An input port address generator 23 is also connected to multiplexer 7 22 to append an identifier identifying the input port 1 0j. This identifier will 8 be used by the packet sequencers constructed according to one g embodiment of this invention.
0 The output of multiplexer 22 is applied to a switch 24 which applies ~
11 packets from multiplexer 22 to latches 26 in accordance with a switching 12 signal supplied from a controller 25. The outputs of latches 261 ~ 264 of 13 packet distributer 11 j are respectively connected to the ith input terminals 14 of packet switches 121 ~ 124. Controller 25 sequentially selects latches 26 5 so that successive packets are sequentially distributed to all latches 26. At 16 periodic clock intervals, the packets stored in latches 26 are 17 simultaneously forwarded to the corresponding packet switches 12.
18 As shown in Fig. 3, each self-routing packet switch 12; comprises a 19 multiplexer 30 for multiplexing signals from the ith outputs of all packet distributers 11 and forwarding the multiplexed signal onto a common bus 21 31 to which are connected address filters 321 ~ 324 having filter addresses 22 identifying respectively the output ports 141 ~ 144. First-in-first-out 23 memories 331~334 are connected respectively to the outputs of address 24 filters 321 - 324, the outputs of FIFO memories 331~334 of each packet switch 1 2j being connected to the ith inputs of packet sequencers 1 31 ~
26 134, respectively. Each address filter 32 examines the outgoing address 27 contained in each of packets arriving from the dirrere"t packet distributers2 8 11 and detects a match or mismatch with the address of the filter 32. On 29 detecting a match, each address filter 32; allows a packet to be passed therethrough to corresponding FIFO memory 33j. The outputs of FIFO
2 memories 331, 332, 333 and 334 of packet switch 12; are connected to the 3 ith input terminals of packet sequencers 131, 132, 133 and 134, 4 respectively.
s Fig. 4 shows one embodiment of packet sequencer 13;. Sequencer 6 13; comprises a multiplexer 40 for multiplexing signals from the ith output 7 terminals of packet switches 121 ~ 124 into a single data bit stream for 8 coupling to a timeslot number detector 41 in which the timeslot number g of each packet is removed from the packet and applied to a multiplexer 10 48, while packets destined to the same output port are supplied to a 11 packet memory (dual-port RAM) in sequence. A write address generator 12 43 applies sequential write address data to memory 44 so that packets 13 are stored into memory 44 in the order of arrival at the packet sequencer.
14 The write address data is also applied to multiplexer 48 in which it is 15 combined with a timeslot number to form a data set. Latches 491 - 49n 16 are connected in a series circuit to store and shift a data set from one latch 17 to the next and from one latch to a corresponding one of compare-and-18 select circuits 501 - 50n which are also connected in series between the 19 output of multiplexer 48 and latch 49n. A difference detector 45 is 20 supplied with the rererellce timeslot number from time base 16 to detect 21 the difference between it and the timeslot number contained in the output 22 of latch 491. The output of difference detector 45 is applied to a 23 comparator 46 in which it is compared with a threshold value which 24 represents a maximum delay time allowable for each packet and 2s corresponds to the maximum number of packets outstanding in the 26 packet switches. Comparator 46 generates an output signal when the 27 difference output from detector 45 is greater than the threshold value and 28 enables a gate 47 for coupling the address component of a data set from 29 latch 491 to RAM 44 as a read address pointer for reading a packet therefrom corresponding to the timeslot number of that data set.
2 Compare-and-select circuit 501 compares the timeslot number of the 3 output of multiplexer 48 with the bmeslot number of a data set stored in 4 latch 491 and transfers the data set from multiplexer 48 to the next 5 compare-and-select circuit 52 if the timeslot number from multiplexer 48 6 is greater than the timeslot number from latch 491 and interchanges the 7 compared data sets and transfers the data set from latch 491 to the next 8 compare-and-select circuit if the timeslot number from multiplexer 48 is 9 smaller than the other. Likewise, each of the succeeding compare-and-10 select circuits 50; compares the timeslot number of the output of the 11 preceding compare-and-select circuit with the timeslot number of a data 12 set stored in corresponding latch 49; and transfers the data set from the 13 preceding compare-and-select circuit to the next compare-and-select 14 circuit if the timeslot number from the preceding circuit is greater than the timeslot number from the corresponding latch and interchanges the 16 compared data sets and transfers the data set from the corresponding 17 latch to the next compare-and-select circuit if the timeslot number from 18 the preceding circuit is smaller than the other.
19 The operation of this packet sequencer will best be understood with reference to Figs. 4A ~ 4D. For purposes of simplicity, it is assumed that 21 only three sets of compare-and-select circuits and corresponding latches 22 are provided. Assume that a given packet has a timeslot number "15"
23 and is stored in RAM 44 in a location identified by write address data "6".
24 This timeslot number is combined by multiplexer 48 with the timeslot number "15' supplied from write address generator 43 to produce a data 2 6 set ("6"/~15"). Up to this point, data sets ("8"/"10"), (nl 2"/"20") and 27 (115"/n22~) are assumed to have been stored respectively in latches 491, 2 8 492 and 493, as shown in Fig. 4A. The output of multiplexer 48 is applied 29 to compare-and-select circuit 51 in which the timeslot number "15" is compared with the timeslot number "10" of the data set stored in latch 2 491. Compare-and-select circuit 50l transfers the data set (116n/1l15~) to the3 next circuit 52 for comparison with the timeslot number "20" stored in 4 corresponding latch 492. Compare-and-select circuit 52 thus s interchanges data sets with latch 492 and transfer data set (~12n/"20~) to 6 compare-and-select circuit 503 (Fig. 4B) for making a comparison with the 7 timeslot number "22" stored in corresponding latch 493. Thus, data sets in 8 latch 493 and compare-and-select circuit 503 are interchanged and data 9 set ("5"/n22") from latch 493 is transferred to the next compare-and-select 10 circuit (Fig. 4C).
1 1 In this way, data sets stored in latches 491 ~ 493 are arranged in the 12 order of timeslot numbers with the timeslot number stored in latch 491 13 being always the smallest of all timeslot numbers stored in latches 49. At 14 the end of this process, the timeslot number stored in latch 491 is applied 15 to the difference detector 45. If the difference betweén it and the 16 reference timeslot number is greater than the threshold value, 17 comparator 46 enables gate 47 to pass the address component of the 18 data set stored in latch 491 to RAM 44 as a read address pointer for 1 9 reading the given packet mentioned above. Simultaneously, data sets 20 stored in all latches 49 are shifted to the left as shown in Fig. 4D.
21 Since the reference timeslot number represents the real time, the 22 output of difference detector 45 indicates the amount of time a packet has 2 3 elapsed from the time at which a timeslot number is assigned to it by a 24 packet distributer 11 ;. Thus, each packet is read out of memory 44 25 following the detection of a maximum delay time within which an 26 outstanding packet having a smaller timeslot number than any of the 27 packets in the sequencer 13j may possible exist in a packet switch 12.
2 8 Thus, the packet read out of memory 44 is ensured that it is the earliest of2 9 all packets in a packet sequencer 13; for a given instant of time.
_ NE-386 - lo- 2059027 The packet sequencers are modified in several forms as shown in 2 Figs. S to 8. In Fig. 5, sequencer 13; includes a multiplexer 60 in which the 3 output signals from the ith output terminals of all packet switches 12 are 4 multiplexed into a series of packets. The output of multiplexer 60 is S connected to.address filters 611 - 614 to which dual-port RAMs 621 - 624 6 are respectively connected. The address of each filter 61; (where i = 1, 2, 7 3, 4) corresponds to the address of the input port 10;. Each address filter 8 61; examines each packet for the input-port address generated by the 9 address generator 23 of a packet distributer 11 j (Fig. 2) and detects a 10 match or mismatch with the own filter address. If a match is detected, the 11 address filter passes the matched packet to the associated memory 62.
12 Therefore, packets coming from the same input port 1 0j are passed 13 through address filter 61 j and stored into packet memory 62j. Memory 14 controllers 63j are associated respectively with address filters 61 j and 15 packet memories 62j to provide read/write control on associated packets 16 for sequential.delivery to a multiplexer 64 in which the packets having the same destination but coming from different input ports 11 are sequentially 8 arranged and delivered to output port 14;.
19 Each memory controller 63j comprises a timeslot number detector 65 20 coupled to the associated address filter 61 j to extract a timeslot number 21 from each packet for coupling to a timeslot-to-address conversion table 22 66. There is a map in the conversion table 66 uniquely specifying 23 relationships between all timeslot numbers and corresponding storage 24 locations of memory 62j. It is seen therefore that conversion table 66 can 25 produce a write address corresponding to each timeslot number, and 26 hence all packets stored in RAM 62; can be sequentially readable. The 27 write address data from table 66 is applied to packet memory 62j. A
2 8 read control circuit 67 monitors the output of address filter 61; to supply a 29 read enable pulse to a read address generator 68 when the highest of . . .
~ NE-386 timeslot numbers is reached to start sequential reading of packets from 2 RAM 62;. In this way, packets which might have arrived out of sequence 3 are arranged into the right order.
4 A simplified form of sequencer 1 3j is shown in Fig. 6. Sequencer 1 3j s includes first-in-first-out memories 701 - 704 for storing packets from the 6 ith output terminals of packet switches 121 ~ 124, respectively. Timeslot 7 number detectors 711 - 714 are respectively coupled to the end storage 8 cell of the memories 701 - 704 for examining packets of earliest arrival -tog detect their timeslot numbers. The outputs of timeslot number detectors 711 - 714 are applied to a read control and minimum detection circuit 72 11 for detecting the smallest of the timeslot numbers supplied from timeslot 12 number detectors 71 and applies a shift-out pulse to one of the FIFO
13 memories corresponding to the smallest time slot number. In this way, a 14 packet arriving earliest of those stored in the output ends of FIFO
memories 701 - 704 is shifted out of a FIFO memory 70k to output port 16 14;. The same process is repeated to deliver a packet of second arrival 17 from the output end of another FIFO memory. A full empty detector 73 is 18 connected to~all FIFO memories 70 to disable the read control and 19 minimum detection circuit 72 when at least one of the packet memories 70 is all empty to prevent an out-of-sequence situation which might occur 21 if there is a packet outstanding in a packet switch 12 which is earlier than22 any of those in the FIFO memories 70.
23 In Fig. 7, a third modification of the packet sequencer 1 3j is illustrated 24 as comprising timeslot number (TSN) detectors 801 - 804 connected respectively to the ith output terminals of all packet switches 12. TSN
26 detectors 80 extract timeslot numbers from received packets and stores 27 the timeslot numbers into TSN memories (FIFO) 821 - 824, respectively.
2 8 read control circuit 67 monitors the output of address filter 61; to supply a 29 read enable pulse to a read address generator 68 when the highest of . . .
~ NE-386 timeslot numbers is reached to start sequential reading of packets from 2 RAM 62;. In this way, packets which might have arrived out of sequence 3 are arranged into the right order.
4 A simplified form of sequencer 1 3j is shown in Fig. 6. Sequencer 1 3j s includes first-in-first-out memories 701 - 704 for storing packets from the 6 ith output terminals of packet switches 121 ~ 124, respectively. Timeslot 7 number detectors 711 - 714 are respectively coupled to the end storage 8 cell of the memories 701 - 704 for examining packets of earliest arrival -tog detect their timeslot numbers. The outputs of timeslot number detectors 711 - 714 are applied to a read control and minimum detection circuit 72 11 for detecting the smallest of the timeslot numbers supplied from timeslot 12 number detectors 71 and applies a shift-out pulse to one of the FIFO
13 memories corresponding to the smallest time slot number. In this way, a 14 packet arriving earliest of those stored in the output ends of FIFO
memories 701 - 704 is shifted out of a FIFO memory 70k to output port 16 14;. The same process is repeated to deliver a packet of second arrival 17 from the output end of another FIFO memory. A full empty detector 73 is 18 connected to~all FIFO memories 70 to disable the read control and 19 minimum detection circuit 72 when at least one of the packet memories 70 is all empty to prevent an out-of-sequence situation which might occur 21 if there is a packet outstanding in a packet switch 12 which is earlier than22 any of those in the FIFO memories 70.
23 In Fig. 7, a third modification of the packet sequencer 1 3j is illustrated 24 as comprising timeslot number (TSN) detectors 801 - 804 connected respectively to the ith output terminals of all packet switches 12. TSN
26 detectors 80 extract timeslot numbers from received packets and stores 27 the timeslot numbers into TSN memories (FIFO) 821 - 824, respectively.
28 With the timeslot numbers being removed, the packets from TSN
29 detectors 801 - 804 are stored into FIFO memories 81 1 - 814, 2059~27 respectively, whose outputs are coupled together to output ports 1 4j. A
2 read control and sequential selection (RCSS) circuit 83 is connected to the 3 output ends of TSN memories 82 to sequentially read the timeslot 4 numbers of earliest arrivals and sequentially apply a select command S signal to a shift pulse generator 8. The read timeslot numbers 6 sequentially read out from memories 82 are supplied from RCSS circuit 83 7 to a comparator 85 for comparison with a timeslot number supplied from 8 a local timeslot number generator 86. When the timeslot numbers are 9 equal, comparator 8S supplies an enable pulse to shift pulse generator 84 0 to allow it to apply the select command signal from RCSS circuit 83 to a 1 1 packet memory 81 k to shift out the packet from that memory to output 12 port 14;. The same shift pulse is applied to the corresponding timeslot 13 memory 82k. If they mismatch, comparator 85 causes timeslot number 14 generator 86 to increment its value by one. A full empty detector 87 is 15 provided for disabling the RCSS circuit 83 if at least one of the memories 16 81 is all empty to prevent the possible out-of-sequence situation as 17 mentioned above.
18 A fourth embodiment of the packet sequencer 1 3j is shown in Fig. 8.
19 Respective packets from the packet switches 12 are supplied to timeslot number detectors 91 ~ 904 on the one hand and stored into FIFO packet 21 memories 911 ~ 914 on the other hand. To the output ends of FIFO
22 memories 91 are respectively connected timeslot number detectors 92 23 whose outputs are, in turn, connected to a read control and sequential 24 selection (RCSS) circuit 93 which sequentially read the outputs of timeslot detectors 92 for coupling to a comparator 94 in which it is compared with 26 the output of a local timeslot number generator 95. The RCSS circuit 93 27 supplies a select command signal which is sequentially applied to a shift 28 pulse generator 96 when enabled in response to the detection of a match 29 by comparator 94 between the two timeslot numbers in a manner similar to the embodiment of Fig. 7, so that one of the packet memories 91 is 2 shifted in response to a shift-out pulse supplied from generator 96. TSN
3 generator 9S is in~emented by one in response to the detection of a 4 mismatch between the timeslot numbers by comparator 94.
s A full empty detector 98 is connected to all packet memories 91 to 6 enable the TSN detectors 90 when at least one of the packet memories is 7 empty, while disabling the RCSS circuit 93. The output of TSN generator 8 9S is further applied to a comparator 97 for comparison with the outputs g of TSN detectors 90 when enabled by the full empty detector 98. TSN
0 generator 9S is also incremented by one in response to an output signal ~
11 from comparator 97 which is generated when the locally generated 12 timeslot number is determined by the comparator as being smaller than 13 any of the detected timeslot numbers.
14 To the outputs of packet memories 91 are respectively connected 5 end-of-sequence detectors 991 - 994. Each of these end-of-sequence 16 detectors 99 monitors successive output packets from the associated 17 packet memory to detect the absence of a packet to follow. If the 18 absence of a~subsequent packet is detected, each end-of-sequence 19 detector 99 causes the TSN generator 9S to increment its value by one.
20 If one of the packet memories 91 is empty, a situation arises that a 21 subsequent packet to fill that vacant memory will have a timeslot number 22 greater than the current value of the locally generated timeslot number. If 2 3 this is the case, the locally generated timeslot number is smaller than any 24 of the detected timeslot numbers, and comparator 97 produces an output 25 signal for incrementing TSN generator 9S. On the other hand, when there 2 6 is no subsequent output packet from one of the packet memories 91, the 27 corresponding end-of-sequence detector 99 supplies an increment 2 8 command signal to the TSN generator 9S. By incrementing the TSN
29 generator in this way, the total amount of time taken to process packets in the sequencers can be decreased.
2 Fig. 9 is a block diagram of a modified packet switching system in 3 which each packet switch 12 produces a trafffic load signal indicating the 4 count of packets outstanding in the packet switch and transmits this signal s to all packet distributers 11. The purpose of this modification is to evenly 6 distribute packets over packet switches 12.
7 As shown in Fig. 10, each packet distributer includes a priority 8 controller 100 which receives packet count signals from packet switches 9 121 ~ 124. In Fig. 11, each packet switch 12 is shown including a packet lo counter 110 having inputs coupled respectively to the FIFO memories 33j 1 1 - 334. Packet counter 110 produces a signal indicating the total count of12 packets stored in the FIFO memories 33.
3 Returning to Fig. 10, the priority controller 100 uses the packet counts 14 from all packet switches and controls the switch 24 for selecting the 15 latches 26 so that those associated with the packet switches having a 16 smaller number of outstanding packets are selected with higher priority 17 than those associated with the packet switches in which a greater number 18 of packets are outstanding. More specifically, priority controller 100 19 determines whether the count of outstanding packets in one or more 20 packet switches exceeds a predetermined value, and if so, it proceeds to 21 select the packet switches other than the packet switch of which the 22 packet count value is determined as exceeding the predetermined value.
2 3 In Fig. 12, each packet distributer 1 1 j is preferably provided with a 24 destination address detector 120 coupled to the packet detector 20. The 25 output of this detector is applied to a priority controller 121 to which 26 traffic load signals are supplied from all packet switches. As shown in Fig 27 13, each packet switch 12 includes a destination address detector 130 28 coupled to the FIFO memories 33 to detect the destination addresses of 29 the packets stored therein. The packet counter 110 produces traffic load signals each indicating the packet count for each destination, so that the 2 signal indicates the traffic condition the destination packet sequencer 13 as - 3 well as the intermediate packet switches. In each packet distributer 11, 4 priority controller 121 uses the output of destination address detector 120 5 to analyze the traffic signals from packet switches 12 and makes a search 6 through the packet switches 121 to 124 to determine one or more packet 7 switches of which the packet count value of the same destination address 8 exceeds a predetermined value. If this is the case, priority controller 121 9 selects the packet switches other than such modules with priority.
10 The foregoing description shows only preferred embodiments of the 11 present invention. Various modifications are apparent to those skilled in 12 the art without departing from the scope of the present invention which is 3 only limited by the appended claims. Therefore, the embodiments 4 shown and described are only illustrative, not restrictive.
2 read control and sequential selection (RCSS) circuit 83 is connected to the 3 output ends of TSN memories 82 to sequentially read the timeslot 4 numbers of earliest arrivals and sequentially apply a select command S signal to a shift pulse generator 8. The read timeslot numbers 6 sequentially read out from memories 82 are supplied from RCSS circuit 83 7 to a comparator 85 for comparison with a timeslot number supplied from 8 a local timeslot number generator 86. When the timeslot numbers are 9 equal, comparator 8S supplies an enable pulse to shift pulse generator 84 0 to allow it to apply the select command signal from RCSS circuit 83 to a 1 1 packet memory 81 k to shift out the packet from that memory to output 12 port 14;. The same shift pulse is applied to the corresponding timeslot 13 memory 82k. If they mismatch, comparator 85 causes timeslot number 14 generator 86 to increment its value by one. A full empty detector 87 is 15 provided for disabling the RCSS circuit 83 if at least one of the memories 16 81 is all empty to prevent the possible out-of-sequence situation as 17 mentioned above.
18 A fourth embodiment of the packet sequencer 1 3j is shown in Fig. 8.
19 Respective packets from the packet switches 12 are supplied to timeslot number detectors 91 ~ 904 on the one hand and stored into FIFO packet 21 memories 911 ~ 914 on the other hand. To the output ends of FIFO
22 memories 91 are respectively connected timeslot number detectors 92 23 whose outputs are, in turn, connected to a read control and sequential 24 selection (RCSS) circuit 93 which sequentially read the outputs of timeslot detectors 92 for coupling to a comparator 94 in which it is compared with 26 the output of a local timeslot number generator 95. The RCSS circuit 93 27 supplies a select command signal which is sequentially applied to a shift 28 pulse generator 96 when enabled in response to the detection of a match 29 by comparator 94 between the two timeslot numbers in a manner similar to the embodiment of Fig. 7, so that one of the packet memories 91 is 2 shifted in response to a shift-out pulse supplied from generator 96. TSN
3 generator 9S is in~emented by one in response to the detection of a 4 mismatch between the timeslot numbers by comparator 94.
s A full empty detector 98 is connected to all packet memories 91 to 6 enable the TSN detectors 90 when at least one of the packet memories is 7 empty, while disabling the RCSS circuit 93. The output of TSN generator 8 9S is further applied to a comparator 97 for comparison with the outputs g of TSN detectors 90 when enabled by the full empty detector 98. TSN
0 generator 9S is also incremented by one in response to an output signal ~
11 from comparator 97 which is generated when the locally generated 12 timeslot number is determined by the comparator as being smaller than 13 any of the detected timeslot numbers.
14 To the outputs of packet memories 91 are respectively connected 5 end-of-sequence detectors 991 - 994. Each of these end-of-sequence 16 detectors 99 monitors successive output packets from the associated 17 packet memory to detect the absence of a packet to follow. If the 18 absence of a~subsequent packet is detected, each end-of-sequence 19 detector 99 causes the TSN generator 9S to increment its value by one.
20 If one of the packet memories 91 is empty, a situation arises that a 21 subsequent packet to fill that vacant memory will have a timeslot number 22 greater than the current value of the locally generated timeslot number. If 2 3 this is the case, the locally generated timeslot number is smaller than any 24 of the detected timeslot numbers, and comparator 97 produces an output 25 signal for incrementing TSN generator 9S. On the other hand, when there 2 6 is no subsequent output packet from one of the packet memories 91, the 27 corresponding end-of-sequence detector 99 supplies an increment 2 8 command signal to the TSN generator 9S. By incrementing the TSN
29 generator in this way, the total amount of time taken to process packets in the sequencers can be decreased.
2 Fig. 9 is a block diagram of a modified packet switching system in 3 which each packet switch 12 produces a trafffic load signal indicating the 4 count of packets outstanding in the packet switch and transmits this signal s to all packet distributers 11. The purpose of this modification is to evenly 6 distribute packets over packet switches 12.
7 As shown in Fig. 10, each packet distributer includes a priority 8 controller 100 which receives packet count signals from packet switches 9 121 ~ 124. In Fig. 11, each packet switch 12 is shown including a packet lo counter 110 having inputs coupled respectively to the FIFO memories 33j 1 1 - 334. Packet counter 110 produces a signal indicating the total count of12 packets stored in the FIFO memories 33.
3 Returning to Fig. 10, the priority controller 100 uses the packet counts 14 from all packet switches and controls the switch 24 for selecting the 15 latches 26 so that those associated with the packet switches having a 16 smaller number of outstanding packets are selected with higher priority 17 than those associated with the packet switches in which a greater number 18 of packets are outstanding. More specifically, priority controller 100 19 determines whether the count of outstanding packets in one or more 20 packet switches exceeds a predetermined value, and if so, it proceeds to 21 select the packet switches other than the packet switch of which the 22 packet count value is determined as exceeding the predetermined value.
2 3 In Fig. 12, each packet distributer 1 1 j is preferably provided with a 24 destination address detector 120 coupled to the packet detector 20. The 25 output of this detector is applied to a priority controller 121 to which 26 traffic load signals are supplied from all packet switches. As shown in Fig 27 13, each packet switch 12 includes a destination address detector 130 28 coupled to the FIFO memories 33 to detect the destination addresses of 29 the packets stored therein. The packet counter 110 produces traffic load signals each indicating the packet count for each destination, so that the 2 signal indicates the traffic condition the destination packet sequencer 13 as - 3 well as the intermediate packet switches. In each packet distributer 11, 4 priority controller 121 uses the output of destination address detector 120 5 to analyze the traffic signals from packet switches 12 and makes a search 6 through the packet switches 121 to 124 to determine one or more packet 7 switches of which the packet count value of the same destination address 8 exceeds a predetermined value. If this is the case, priority controller 121 9 selects the packet switches other than such modules with priority.
10 The foregoing description shows only preferred embodiments of the 11 present invention. Various modifications are apparent to those skilled in 12 the art without departing from the scope of the present invention which is 3 only limited by the appended claims. Therefore, the embodiments 4 shown and described are only illustrative, not restrictive.
Claims (14)
1. A packet switching system having a plurality of input ports and a plurality of output ports, comprising:
a plurality of packet distributers associated respectively with the input ports for receiving successive packets therefrom, each of said packet distributers attaching a timeslot number to each of the received packets, and uniformly distributing the packets to a plurality of output terminals thereof;
a plurality of packet switches corresponding in number to the output terminals of each of the packet distributers, each of the packet switches having a plurality of input terminals corresponding in number to the packet distributers and a plurality of output terminals corresponding in number to said output ports, the input terminals of each packet switch being coupled to respective output terminals of said packet distributers for switching a packet from one of the input terminals thereof to one of the output terminals thereof in accordance with a destination address contained in the packet; and a plurality of packet sequencers associated respectively with said output ports, each of the packet sequencers having a plurality of input terminals coupled to respective output terminals of the packet switches for examining the timeslot numbers attached to packets from the input terminals thereof and delivering the packets to the associated output port in accordance with the examined timeslot numbers.
a plurality of packet distributers associated respectively with the input ports for receiving successive packets therefrom, each of said packet distributers attaching a timeslot number to each of the received packets, and uniformly distributing the packets to a plurality of output terminals thereof;
a plurality of packet switches corresponding in number to the output terminals of each of the packet distributers, each of the packet switches having a plurality of input terminals corresponding in number to the packet distributers and a plurality of output terminals corresponding in number to said output ports, the input terminals of each packet switch being coupled to respective output terminals of said packet distributers for switching a packet from one of the input terminals thereof to one of the output terminals thereof in accordance with a destination address contained in the packet; and a plurality of packet sequencers associated respectively with said output ports, each of the packet sequencers having a plurality of input terminals coupled to respective output terminals of the packet switches for examining the timeslot numbers attached to packets from the input terminals thereof and delivering the packets to the associated output port in accordance with the examined timeslot numbers.
2. A packet switching system as claimed in claim 1, wherein each of said packet switches comprises means for generating a traffic-related signal indicating the amount of packets outstanding in the packet switch, and wherein each of the packet distributers comprises means for receiving said traffic-related signal from each of the packet switches and giving priority of packet distribution to the output terminals of the packet distributer according to the amounts of packets outstanding in the respective packet switches so that packets from the associated input port are distributed with priority to those of the packet switches having a smaller amount of outstanding packets.
3. A packet switching system as claimed in claim 1, wherein each of said packet switches comprises:
means for detecting destination addresses from packets respectively destined to said output ports; and means for generating a traffic-related signal indicating the respective amounts of said packets having said detected destination addresses, and wherein each of the packet distributers comprises:
means for detecting the destination addresses of incoming packets from the associated input port; and means for receiving said traffic-related signal from each of the packet switches and giving priority of packet distribution to the output terminals of the packet distributer according to the amounts of packets indicated by the traffic-related signal and according to the detected destination addresses of said incoming packets so that the incoming packets are distributed with priority to those of the packet switches having a smaller amount of packets containing the same destination address as said incoming packets.
means for detecting destination addresses from packets respectively destined to said output ports; and means for generating a traffic-related signal indicating the respective amounts of said packets having said detected destination addresses, and wherein each of the packet distributers comprises:
means for detecting the destination addresses of incoming packets from the associated input port; and means for receiving said traffic-related signal from each of the packet switches and giving priority of packet distribution to the output terminals of the packet distributer according to the amounts of packets indicated by the traffic-related signal and according to the detected destination addresses of said incoming packets so that the incoming packets are distributed with priority to those of the packet switches having a smaller amount of packets containing the same destination address as said incoming packets.
4. A packet switching system as claimed in claim 1, wherein each of said packet sequencers comprises:
multiplexer means for multiplexing packets from the input terminals thereof;
timeslot detector means for detecting the timeslot number of said multiplexed packets;
address generator means for generating address signals corresponding to said multiplexed packets, respectively;
memory means responsive to said address signals for storing said multiplexed packets in locations respectively identified by said address signals;
combiner means for combining the address signals and the detected timeslot numbers to produce data sets;
packet arranging means for arranging said data sets according to the timeslot numbers contained therein; and gate means for applying the address signals contained in the arranged data sets to said memory means for reading packets stored therein.
multiplexer means for multiplexing packets from the input terminals thereof;
timeslot detector means for detecting the timeslot number of said multiplexed packets;
address generator means for generating address signals corresponding to said multiplexed packets, respectively;
memory means responsive to said address signals for storing said multiplexed packets in locations respectively identified by said address signals;
combiner means for combining the address signals and the detected timeslot numbers to produce data sets;
packet arranging means for arranging said data sets according to the timeslot numbers contained therein; and gate means for applying the address signals contained in the arranged data sets to said memory means for reading packets stored therein.
5. A packet switching system as claimed in claim 4, wherein said packet arranging means comprises:
a plurality of latches series-connected in a first circuit; and a like plurality of compare-and-select circuits series-connected in a second circuit, said compare-and-select circuits being connected to corresponding ones of said latches and to said combiner means for receiving the data set from the combiner means, each of the compare-and-select circuits comparing the timeslot number of each data set in said first circuit with the timeslot number of each data set in said second circuit and interchanging the data sets between said first and second circuits and applying the data set from the first circuit to a subsequent compare-and-select circuit when the timeslot number of the data set in said second circuit is smaller than the timeslot number of the data set in said first circuit, so that data sets stored in said latches are arranged according to the timeslot numbers thereof.
a plurality of latches series-connected in a first circuit; and a like plurality of compare-and-select circuits series-connected in a second circuit, said compare-and-select circuits being connected to corresponding ones of said latches and to said combiner means for receiving the data set from the combiner means, each of the compare-and-select circuits comparing the timeslot number of each data set in said first circuit with the timeslot number of each data set in said second circuit and interchanging the data sets between said first and second circuits and applying the data set from the first circuit to a subsequent compare-and-select circuit when the timeslot number of the data set in said second circuit is smaller than the timeslot number of the data set in said first circuit, so that data sets stored in said latches are arranged according to the timeslot numbers thereof.
6. A packet switching system as claimed in claim 5, wherein said gate means comprises:
means for detecting a difference between the timeslot number of each data set stored in one of said latches and a reference timeslot number; and means for comparing said difference with a threshold value and applying the address signal contained in the data set stored in said one of said latches to said memory means when said difference exceeds said threshold value.
means for detecting a difference between the timeslot number of each data set stored in one of said latches and a reference timeslot number; and means for comparing said difference with a threshold value and applying the address signal contained in the data set stored in said one of said latches to said memory means when said difference exceeds said threshold value.
7. A packet switching system as claimed in claim 6, wherein said threshold value represents a maximum number of packets outstanding in each of said packet switches.
8. A packet switching system as claimed in claim 1, wherein each of said packet distributers comprises means for attaching an input-port address identifying the associated input port, and wherein each of said packet sequencers comprises:
first multiplexer means for multiplexing packets from the input terminals of the packet sequencer;
a plurality of address filter means corresponding respectively to said input ports, each of the address filter means being coupled to said first multiplexer means and having the input-port address of the corresponding input port for detecting packets from the output of the first multiplexer means having the same input-port address as the address filter means;
a plurality of memory means coupled respectively to said address filter means;
a plurality of memory control means associated respectively with said address filter means and with said memory means, each of the memory control means comprising means for detecting timeslot numbers from the packets detected by the associated address filter means, means for generating write address signals corresponding to said detected timeslot numbers for storing the packets detected by the associated address filter means into said associated memory means according to said write address signals, and means for sequentially generating read address signals for reading packets from the associated memory means according to said read address signals; and second multiplexer means for multiplexing packets read out of said plural memory means.
first multiplexer means for multiplexing packets from the input terminals of the packet sequencer;
a plurality of address filter means corresponding respectively to said input ports, each of the address filter means being coupled to said first multiplexer means and having the input-port address of the corresponding input port for detecting packets from the output of the first multiplexer means having the same input-port address as the address filter means;
a plurality of memory means coupled respectively to said address filter means;
a plurality of memory control means associated respectively with said address filter means and with said memory means, each of the memory control means comprising means for detecting timeslot numbers from the packets detected by the associated address filter means, means for generating write address signals corresponding to said detected timeslot numbers for storing the packets detected by the associated address filter means into said associated memory means according to said write address signals, and means for sequentially generating read address signals for reading packets from the associated memory means according to said read address signals; and second multiplexer means for multiplexing packets read out of said plural memory means.
9. A packet switching system as claimed in claim 1, wherein each of said packet sequencers comprises:
a plurality of first-in-first-out memory means having input ends connected respectively to the input terminals of the packet sequencer and having output ends coupled together to the associated output port;
a plurality of timeslot number detectors connected respectively to the output ends of said first-in-first-out - 20a -memory means; and control means for detecting a minimum value of said detected timeslot numbers and shifting one of said first-in-first-out memory means corresponding to the timeslot number of the detected minimum value.
a plurality of first-in-first-out memory means having input ends connected respectively to the input terminals of the packet sequencer and having output ends coupled together to the associated output port;
a plurality of timeslot number detectors connected respectively to the output ends of said first-in-first-out - 20a -memory means; and control means for detecting a minimum value of said detected timeslot numbers and shifting one of said first-in-first-out memory means corresponding to the timeslot number of the detected minimum value.
10. A packet switching system as claimed in claim 9, wherein each of said packet sequencers further comprises means for detecting when at least one of said first-in-first-out memory means is empty and disabling said control means.
11. A packet switching system as claimed in claim 1, wherein each of said packet sequencers comprises:
a plurality of timeslot number detectors coupled respectively to the input terminals of the packet sequencer for extracting timeslot numbers from packets arriving at said input terminals;
a first plurality of first-in-first-out memory means having input ends connected respectively to said timeslot number detectors for storing the packets from the timeslot number detectors and having output ends coupled together to the associated output port;
a second plurality of first-in-first-out memory means having input ends connected respectively to said timeslot number detectors for storing the timeslot numbers detected respectively by the timeslot number detectors;
timeslot number generator means for sequentially generating a local timeslot number; and control means connected to the output ends of the first plurality of first-in-first-out memory means for sequentially reading the timeslot numbers stored in said output ends, comparing said local timeslot number and each of the timeslot numbers read out of said memory means to detect a match or mismatch therebetween, and shifting one of said first plurality of first-in-first-out memory means and one of said second plurality of first-in-first-out memory means when there is a match between said timeslot numbers and incrementing said timeslot number generator means when there is a mismatch between said timeslot numbers.
a plurality of timeslot number detectors coupled respectively to the input terminals of the packet sequencer for extracting timeslot numbers from packets arriving at said input terminals;
a first plurality of first-in-first-out memory means having input ends connected respectively to said timeslot number detectors for storing the packets from the timeslot number detectors and having output ends coupled together to the associated output port;
a second plurality of first-in-first-out memory means having input ends connected respectively to said timeslot number detectors for storing the timeslot numbers detected respectively by the timeslot number detectors;
timeslot number generator means for sequentially generating a local timeslot number; and control means connected to the output ends of the first plurality of first-in-first-out memory means for sequentially reading the timeslot numbers stored in said output ends, comparing said local timeslot number and each of the timeslot numbers read out of said memory means to detect a match or mismatch therebetween, and shifting one of said first plurality of first-in-first-out memory means and one of said second plurality of first-in-first-out memory means when there is a match between said timeslot numbers and incrementing said timeslot number generator means when there is a mismatch between said timeslot numbers.
12. A packet switching system as claimed in claim 11, wherein wherein each of said packet sequencers further comprises means for detecting when at least one of said first plurality of first-in-first-out memories is empty and disabling said control means.
13. A packet switching system as claimed in claim 1, wherein each of said packet sequencers comprises:
a plurality of first-in-first-out memory means having input ends connected respectively to the input terminals of the packet sequencer and having output ends;
a first plurality of timeslot number detectors connected respectively to the output ends of said first-in-first-out memory means for detecting timeslot numbers from packets stored in said output ends;
timeslot number generator means for sequentially generating a local timeslot number;
control means connected to the first plurality of timeslot number detectors for sequentially reading the timeslot numbers detected by the first plurality of timeslot number detectors, comparing said local timeslot number and each of the timeslot numbers detected by the first plurality of timeslot number detectors to detect a match or mismatch therebetween, and shifting one of said first-in-first-out memory means when there is a match between said timeslot numbers and incrementing said timeslot number generator means when there is a mismatch between said timeslot numbers;
a second plurality of timeslot number detectors for detecting, when enabled, timeslot numbers from packets arriving at the input terminals of the packet sequencer;
means for detecting when at least one of said first-in-first-out memories is empty, disabling said control means and enabling said second plurality of timeslot number detectors to allow detection of said timeslot numbers;
means for detecting when each of the timeslot numbers detected by the second plurality of timeslot number detectors is greater than the local timeslot number and incrementing said timeslot number generator means; and a plurality of end-of-sequence detector means connected respectively to the output ends of said first-in-first-out memory means for detecting when there is no packet to follow and incrementing said timeslot number generator means.
a plurality of first-in-first-out memory means having input ends connected respectively to the input terminals of the packet sequencer and having output ends;
a first plurality of timeslot number detectors connected respectively to the output ends of said first-in-first-out memory means for detecting timeslot numbers from packets stored in said output ends;
timeslot number generator means for sequentially generating a local timeslot number;
control means connected to the first plurality of timeslot number detectors for sequentially reading the timeslot numbers detected by the first plurality of timeslot number detectors, comparing said local timeslot number and each of the timeslot numbers detected by the first plurality of timeslot number detectors to detect a match or mismatch therebetween, and shifting one of said first-in-first-out memory means when there is a match between said timeslot numbers and incrementing said timeslot number generator means when there is a mismatch between said timeslot numbers;
a second plurality of timeslot number detectors for detecting, when enabled, timeslot numbers from packets arriving at the input terminals of the packet sequencer;
means for detecting when at least one of said first-in-first-out memories is empty, disabling said control means and enabling said second plurality of timeslot number detectors to allow detection of said timeslot numbers;
means for detecting when each of the timeslot numbers detected by the second plurality of timeslot number detectors is greater than the local timeslot number and incrementing said timeslot number generator means; and a plurality of end-of-sequence detector means connected respectively to the output ends of said first-in-first-out memory means for detecting when there is no packet to follow and incrementing said timeslot number generator means.
14. A packet switching system as claimed in claim 1, wherein each of said packet switches is a self-routing switch.
Applications Claiming Priority (6)
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| JP3-529 | 1991-01-08 | ||
| JP5797191A JP3163638B2 (en) | 1991-02-27 | 1991-02-27 | Packet switching method |
| JP3-57971 | 1991-02-27 | ||
| JP3-72822 | 1991-04-05 | ||
| JP7282291A JP3163640B2 (en) | 1991-01-08 | 1991-04-05 | Packet switching method |
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| CA2059027A1 CA2059027A1 (en) | 1992-08-09 |
| CA2059027C true CA2059027C (en) | 1996-07-02 |
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| CA002059027A Expired - Fee Related CA2059027C (en) | 1991-01-08 | 1992-01-08 | Switching system with time-stamped packet distribution input stage and packet sequencing output stage |
Country Status (4)
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| US (1) | US5253251A (en) |
| EP (1) | EP0497097B1 (en) |
| CA (1) | CA2059027C (en) |
| DE (1) | DE69214968T2 (en) |
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| JPS63246055A (en) * | 1987-03-31 | 1988-10-13 | Nec Corp | Packet transmitter-receiver |
| JPS6444148A (en) * | 1987-08-11 | 1989-02-16 | Canon Kk | Routing system in packet exchange network |
| GB2211697B (en) * | 1987-10-15 | 1992-01-02 | Peter Newman | Self routing-switching element for an asynchronous time switch |
| US4899334A (en) * | 1987-10-19 | 1990-02-06 | Oki Electric Industry Co., Ltd. | Self-routing multistage switching network for fast packet switching system |
| DE3742941A1 (en) * | 1987-12-18 | 1989-07-06 | Standard Elektrik Lorenz Ag | PACKAGE BROKERS |
| JP2659421B2 (en) * | 1988-02-17 | 1997-09-30 | 日本電信電話株式会社 | Self-routing channel |
| IT1219458B (en) * | 1988-02-18 | 1990-05-18 | Bordoni Ugo Fondazione | NXN INTERCONNECTION NETWORKS CONSTITUTED BY DELTA NETWORKS, AND METHOD FOR THE INTAKE OF INPUT-OUTPUT PERMUTATIONS |
| JP2753254B2 (en) * | 1988-04-06 | 1998-05-18 | 株式会社日立製作所 | Packet exchange system |
| US4891803A (en) * | 1988-11-07 | 1990-01-02 | American Telephone And Telegraph Company | Packet switching network |
| WO1991002419A1 (en) * | 1989-08-09 | 1991-02-21 | Alcatel N.V. | Resequencing system for a switching node |
-
1992
- 1992-01-08 CA CA002059027A patent/CA2059027C/en not_active Expired - Fee Related
- 1992-01-08 DE DE69214968T patent/DE69214968T2/en not_active Expired - Lifetime
- 1992-01-08 US US07/817,893 patent/US5253251A/en not_active Expired - Lifetime
- 1992-01-08 EP EP92100201A patent/EP0497097B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0497097A2 (en) | 1992-08-05 |
| EP0497097A3 (en) | 1992-09-09 |
| DE69214968T2 (en) | 1997-05-28 |
| EP0497097B1 (en) | 1996-11-06 |
| DE69214968D1 (en) | 1996-12-12 |
| CA2059027A1 (en) | 1992-08-09 |
| US5253251A (en) | 1993-10-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |