CA2054431A1 - Disk controller with separate data and command paths - Google Patents
Disk controller with separate data and command pathsInfo
- Publication number
- CA2054431A1 CA2054431A1 CA002054431A CA2054431A CA2054431A1 CA 2054431 A1 CA2054431 A1 CA 2054431A1 CA 002054431 A CA002054431 A CA 002054431A CA 2054431 A CA2054431 A CA 2054431A CA 2054431 A1 CA2054431 A1 CA 2054431A1
- Authority
- CA
- Canada
- Prior art keywords
- data
- transfer
- signal
- local microprocessor
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
Abstract
ABSTRACT
DISK CONTROLLER WITH SEPARATE DATA AND COMMAND PATHS
A SCSI bus controller which has a separate data path from the SCSI bus to the host bus and a separate command path for use to communicate with a local microprocessor. The local microprocessor is connected to a dual port RAM, the other port of which is connected to a bus master controller linked to the host system. Commands and status are passed via the dual port RAM. Data is passed through a FIFO. The local microprocessor does not have access to the data path but only controls direction of the data flow, the initiation of the sequence and the completion of the sequence.
DISK CONTROLLER WITH SEPARATE DATA AND COMMAND PATHS
A SCSI bus controller which has a separate data path from the SCSI bus to the host bus and a separate command path for use to communicate with a local microprocessor. The local microprocessor is connected to a dual port RAM, the other port of which is connected to a bus master controller linked to the host system. Commands and status are passed via the dual port RAM. Data is passed through a FIFO. The local microprocessor does not have access to the data path but only controls direction of the data flow, the initiation of the sequence and the completion of the sequence.
Description
DISK CONTROLLER WITH SEPARATE DATA AND COMMAND PAT~lS
The present invention relates to peripheral device controllers used in computer ~ystems, and more particularly to controllers having an onboard processor for local supervisory control and supervising a secondary bus.
A common peripheral bus specification used for connecting disk drives, tape back-up units and other peripheral items to a computer system is the Small Computer System Interface or SCSI standard. The SCSI
bus interface has been developing over a period of years and has entered a second qeneration referred to as SCSI-2. Up to seven different peripheral devices can be connected to a SCSI bus and be controlled through a single SCSI bus controller unit. In personal computers the SCSI bus controller is preferably in the form of a interchangeable circuit board or adapter which is installed in one of the slots in the personal computer. In this manner the microprocessor forming the basis of the personal computer system can interact with the SCSI bus controller and access the particular 5 peripheral devices in a given installation.
one of the reasons for the growing interest in the S~SI bus is the relatively high data transfer rates which are available, particularly with the advent of higher performance peripheral devices. This interest is further enhanced by the development of intelligent ~ ?, ~
bus mastering controller units which can be installed in the various newer computer buses, such as those according to the Extended Industry Standard Architecture (EISA) or the Micro Channel Architecture (MCA). The bus mastering chips allow very high data transfer rates between the memory in the personal computer and the local adaptor, and when combined with the high data rates p~ssible in the SCSI bus, theoretically very high performance peripheral systems could be developed. However, one problem which develops relates to the transfer of data between the devices residing on the SCSI bus and the computer system bus. Because the two buses are operating asynchronously and at different data rates, it is required that some sort of buffering memory be utilized on the SCSI bus controller card. A further problem is that commands must also be transferred between the system and the SCSI bus and SCSI bus controller. If the main system processor is used to provide control of the various operations, then the performance of the bus controller is ~reatly diminished. If a local onboard processor is utilized, then performance can be improved, but the buffering problem still remains.
Conventionally, the local microprocessor is involved both in the transfer of the data from the SCSI
bus and the transfer of data to the host bus, thus limitinq data transfer operations to the effeGtive speed of the local processor. Given the high data transfer rates possible on both the computer system bus and the SCSI bus, this inclusion of the local processor and its multiple operations generally results in reduction of the potential data rates. Therefore it is desirable that the local microprocessor be removed from the actual data transfer operations between the SCSI
J .:., bus and the host computer bus, thus allowing higher data throughput.
one technique for resolving the problem has been the use of a caching controller, where large amounts of data are transferred into a cache memory on the controller and then transferred under control of the local microprocessor to the host system. The cache is sized so that a majority of the requests can be serviced from or by the cache, thus increasing computer system performance. But if a miss occurs, problems still exist. Additionally, large amounts of cache memory can be required, thus increasing expense.
SUMMARY OF THE INVENTION
A SCSI bus controller according to the present invention utilizes a data channel which, once operations have commenced, operates without any interaction with the local microprocessor and at the available data rate of both the SCSI controller unit and the bus mastering unit located in the controller, until a logical operation is almost completed. The local microprocessor issues a command to complete the transfer and the remaining data is transferred.
A first in, first out (FIFO) memory is utilized to perform the interface between the SCSI chip, which contr~l~ and coordinates the actual interface to the SCSI bus, and a bus master controller chip, which controls the actual interface to the personal computer system bus. The FIFO is used for all transfer of data information between the SCSI bus and the host bus and operates without interference from the local microprocessor once transactions are commenced ~nd until transactions are essentially completed.
Commands are provided to the local processor via a separate channel on the bus master interface circuit to a dual ported random access memory (RAM), which is also 2 ~
connected to the local microprocessor. Thus in this manner all command information, be it operations requests or status returns, are performed without impact or interference with the data transfer which is occurring in a ~eparate path. This allows optimization of the data path between the two units and the use of the FIFO.
The local microprocessor only performs actual command interpretation, status response and scheduling of operations between the SCSI bus and the host bus, and does not participate in the actual data transfer once it is commenced except for a minor completion of a data transfer at the end of a command, and even then without actually interpreting or receiving any of the data being transferred.
By removing the local microprocessor from the actual data flow and utilizing it only in a supervisory manner, data throughput is increased to values closer to that of the theoretical capabilities of the various buses.
A better understanding of the present invention can be obtained when the following detailed description of the preferred embodiment is considered in conjunction with the followin~ drawings, in which:
Figure 1 is block diagram of a SCSI bus controller according to the present invention;
Figures 2 and 3 indicate the relationships of Figures 2A, 2B and 2C and ~igures 3A, 3B and 3C, respectively; as shown with Figure 2;
Figures 2A~ 2B and 2C are schematic diagrams of porti~ns of the control logic for use with the FIFO of Figure l; and ' r~?.~ ~ ;
t .
Figures 3A, 3B and 3C are schematic diagrams of portions of the logic used in conjunction with the dual port ~AM of Figure 1.
Referring now to Figure 1, t~e letter S generally refers to a SCSI bus controller according to the present invention. A bus ~astering integrated circuit (BMIC) 20, preferably the 82355 produced by Intel Corporation for use with the EISA bus, is used to communicate between the host bus, the EISA bus in the preferred embodiment, in the personal computer in which the SCSI bus controller S is located and the various components located on the SCSI bus controller S. A
SCSI controller ch~p 22, preferably the 53C95 from the National Cash Register Corporation, is coupled to the SCSI bus to perform control of operations on the SCSI
bus, thus allowing increased speed of operations.
Preferably the BMIC 20 contains two local transfer channels, thus allowing separation of commands and data. Preferably the SCSI chip 22 includes a separate data port and ~ separate command or control port, both ports having data and control portions. Reference to the data sheets for the preferred BMIC 20 and SCSI chip 22 i~ desirable and an understandinq of the operations and interfaces of these devices is gener~lly assumed in this description. In addition, understanding of the operation of the SCSI bus is generally assumed, with reference being made to the SCSI-2 specification available from Global Engineering Documents in Irvine, California.
The SCSI chip 22 is connected to the data, address ~nd control lines of a local microprocessor 24, preferably zn &028~ operating at 25 MHz from Harris Semiconductor.
By means of this interface between the SCSI chip 22 and the local microprocessor 24, command information can be transferred between the local microprocessor 24 to the SCSI chip 22. Also connected to the local microprocessor 24 is read only memory (ROM) 26 and random access memory (RAM) 28, which is used to hold the operating sequences of the local microprocessor 24 and for its temporary data storage. Preferably the local microprocessor 24 operates under a real time, multitasking operating system. A timer 30 is connected to the local microprocessor 24 to receive timer information for u~e in the various sequences performed by the local microprocessor 24 and to an interrupt controller 32 to provide interrupt information. The interrupt controller 32 is also coupled to the local microprocessor 24. The interrupt controller 32 further receives interrupt information from the SCSI chip 22 and the BMIC 20 to allow interrupt driven operation of the local micr~processor 24 by the two controller chips ~0 ~nd 22. Additionally, a control bit register 34 is connected to the local microprocessor 24. This control bit register 34 is used to provide certain single bits which are used to control various operations of the SCSI bus controller S.
A dual ported RAM 36 has one port connected to the lQGal ~icroprocessor 24 and has its second port coupled to the BMIC 20 by me~ns of control logic 38 and a counter 40. The du31 port RAM 36 is used for holding command ~nd status information passed betwePn the host system vi~ the BMIC 20 and the local microproce~sor 24.
The dual port R~M 36 of the preferred embodiment includes chip and ~utput enable, upper and lower byte and r~d~wrî~e inpUtfi for each port. The B~IC 20 provides starting address information to the counter 40 ~nd thereafter the counter 40 increments to provide addressing information to the ~econd port of the dual port RAM 36. The data bus of the BMIC 20 is referred to as the BMDAT bus and is connected to the counter 40 and to the dual port RAM 36 while the control outputs of the BMIC 20 form the BMCONT bus and are provided to the dual port control logic 38.
A first in, first out (FIFO) memory 42 is used in the data channel between the SCSI chip 22 and the BMI~
20. Preferably the FIF0 42 is a synchronous, unidirectional FIFO having a lk by 18 bit sîze, preferably the IDT72225 from Integrated Device Technology, Inc. The FIFO 42 preferably contains write enable and write clock inputs to control the writing of information to the FIF0 42 and read enable and read clock inputs to control removal of information from the FIF0 42. Additionally, the FIFO 42 preferably includes a series of flag outputs to indicate the amount of data present in the FIF0 42. Preferably the flags include an empty flag, a full flag, a half-full flag and two programmable flags which indicate almost full and almost empty. Preferably the almost empty flag is set at 1/8 capacity of the FIFO 42 or 128 bytes, while the al~ost full flag is set at 7/~ or 896 bytes. The data inputs of the FIF0 42 are connected to the outputs of a buffer 44 whose inputs are connected to the BMDAT bus from the BMIC 20 ~nd to the outputs of a buffer 46 whose inputs are connected to the SDAT or data bus from the S~SI chip ~2. The data outputs from the FIF0 42 are preferably connected to the inputs of a buffer 48 w~ose outputs are connected to the BMDAT bus and to the inputs of ~ buffer 50 whose outputs are connected to the S~AT bus.
The variou~ g~te or enabling inputs of the buffers 44, 46, 48 and 50 are provided as outputs of a FIF0 control block 52. Additionally, the FIF0 control block r~ . ;, "~ ,?
is connected to the FIFO 42 to receive the flag information from the FIFO 42 and to provide the read and write enable and clocking signals to the FIFO 42.
Additionally the control bit register 34 is connected to the FIFO control 52 to provide certain control information from the local microprocessor 286. The BMCONT or control bus from the BMIC 20 is connected to FIFO control 52 to allow control of the direction and timing of data transfers with the BMIC 20. Further, the SCONT or SCSI chip control bus is provided from a SCSI chip 22 to the FIFO control logic 52 to allow transfer of data between the SCSI chip 22 and the FIFO
42.
It can be seen that the local microprocessor data bus, referred to as LD, is not provided to the actual data path between the SCSI chip 22 and the BMIC 20, but is connected only to the dual port RAM 36 and directly to the SCSI chip 22 command or control port. Thus, the local microprocessor 24 cannot perform the actual data transfer between the BMIC 20 and the SCSI chip 22.
The local microprocessor 24 only performs command and control functions and does not perform actual data transfer operations between the SCSI bus and t~e host bus. The host system develops a commmand block in its memory, provides the host memory ~tarting address to the BMIC 20 and causes the BMIC 20 to interrupt the local ~icroprocessor 24. The local microprocessor 24 programs the BMIC 20 to transfer the command block from the system memory to the dual port RAM 36. The local microprocessor 24 is interrupted by t~e BMIC 20 when the command block has been placed in the dual port RAM
36~ The local microprocessor 24 retrieves the command information and operates ~n it as appropriate. If it is an information request, and the SCSI chip 22 is not otherwise busy, the local microprocessor 24 ~ets up the FIF0 42 for the transfer and provides the proper commands to the SCSI chip 22 and the BMIC 20, which perform the commands. The SCSI chip 22, the BMIC 20 and the FIF0 control logic 52 interact to transfer the S data between the buses. If the transfer is from the B~IC 20 to the SCSI chip 22, the BMIC 20 completes its portion of the transfer first and indicates this completion to the local ~icroprocessor 24. If the transfer is from the SCSI chip 22 to the BMIC 20, the SCSI chip 22 will complete its transfer first and 60 inform the local microprocessor 24. These task completions are indicated by interrupts. Upon receiving the interrupt the local microprocessor 24 responds. The response generally includes flushing the FIF0 42 to complete the data transfer. When both the BMIC 20 and the SCSI chip 22 have completed their transfers, the local microprocessor 24 then places status or completion information in the dual port RAM
36 and causes the BMIC 20 to transfer the information to the host system me~ory and to interrupt the host system after the transfer is complete, cignalling task completion. The actual set up and flushinq of the FIF0 42 and data transfer is described in more detail below.
Referring now to Figures 2A, 2B and 2C, the interface of the FIF0 control logic 52 with SCSI chip 22 is according to a DMA protocol which includes a DMA
request line, a DMA acknowledge line and a direction of transfer or writelread signal. These signals ~re referred to ~s the DREQ, DACK* and DBWR* ~ignals and are contained in the SCONT bus. In general when referring to signals in this description, an asterisX
(*) after a signal ~nemonic indicates th~t it is logically true when a low voltage level is present and is the inverse of the same signal mnemonic without the asterisk. Angle br2cket included numbers after a signal mnemonic are used to indicate single or multiple bit positions in a wider logical signal, ~uch as the data or address fields.
The interface between the BMIC 20 and the FIFO
control 52 preferably is according to that of channel 1 of a 82~55 from Intel Corporation, as indic~ted in the specifications for that particular device as published in the 1990 Peripherals volume by Intel Corporation, at pages 1-3~4 to 1-392. To this end several signals are utilized from or provided to the BMIC 20 and they are referred to as the TDIR or transfer direction signal;
the TCLK signal which provides the clock or sequencing information; the TCHAN signal, which indicates if channel 1 or channel O of the B~IC 20 ic being utilized; the TREQ* signal, which in combination with the TACK* signal, form the handshake cignals for the request of information transfer; and the TLD* signal, which is the local address output load signal.
Several signals are received from the control bit register 34 by the FIFO control logic 52 and these are the LOOPBACK signal, the BITBUKT ~ignal, ~he CPYMODE
~ignal and the CPYDIR signal. The LOOPBACK signal is used to ~et whether a loopback operation with the BMIC
20 i~ being utilized SQ that partial checki~g of operations ca~ be performed by the B~IC 20. The BITBUKT signal is used to ignore information from the SCSI chip ~2 for cert~in opera~ions. The CP~D~R signal is used in combinatiQn with the CPYMODE signal for loopback operation of the SCSI chip 22 to indicate whether data is being pro~ided to ~r from the FIFO 42.
When the CPYMODE ~ignal is set, SCSI loopback is being perform~d. ~h~ CPYDIR signal controls fillin~ or emptying of the FI~O 42.
A siynal referred to as RESET1* is xeceived from 35 the host computer ~ystem over the host bus and ~-~ r~
indicates, when active low, that ~ system reset is being performed. A 4 bit decoder 100 (Fig. 2A) has its A and B ~election inputs connected to the LA or address bus of the local ~icroprocessor 24 and its active low S enable input connected to the CHAN1* signal. The CXANl* signal is produced by address decode logic (not ~hown) so that when the local microprocessor 24 addresses a particular address space, a low strobe is provided to the enable input of the decoder 100. The O
position inverted output of the decoder 100 provides the ClRST* signal or CHANNEL 1 RESET* signal which is used to cause a reset of the FI~O control loqic 52.
The 1 inverted output of the decoder 100 is the DIRSTB*
~ignal or DIRECTlON STROBE signal which is used to control the direction of data transfer between the host and SCSI buses. The bit 2 output of the decoder 100 is the ClFL~SH* ~ignal, which indicates a request to flush the FIFO 42. This flushing is utilized to empty the FIFO 42 at the end of an operation of transferring data. During normal operations the FIFO 42 is preferably kept partia~ly f`ull of data to prevent certain register reloads from occurring, thus simplifying logic operation. However, at the end of a command, it is required that the conventional control logic be overridden to allow the FIFO 42 to be completely emptied and therefore the flush input is provided.
The ClFLUSH* cignal is provided to the clocking input of a D-type flip-flop 102. The inverted preset and D input~ of the flip-flop 10~ are connected to a high logic level, while the inverted clear input is connected to the output of a two input NAND gate 104.
The non-inverted output of the flip-flop 102 is provid~d to a first D input of a multibit D-type flip-flop 106. The clocking signal for the flip-flop 106 is the TCLK 6ignal provided to the BMIC 20. The first non-inverted or Q ~utput of the flip-flop 10~ is provided to a 6econd D input of the flip-flop 106. The second non-inverted output of the flip-flop 106 is provided as one input to the NAND gate 104 and is provided to ~ third D input of the flip-flop 106. The third non-inverted or Q output of the flip-flop 106 is provided to the ~econd input of the NAND gate 104.
Thus in this manner the FLUSH signal is synchronized by the TCLK cignal and is provided for a given duration.
The output of the NAND gate 104 is ~lso provided as one input referred to as UFLSH* of a programmable array logic (PAL) device 108 referred to as the FIFO
control PAL. The FIFO control PAL 108 is one of a series of PAL's used in the FIFO control 52 to control operations. Other inputs to the FIFO con~rol PAL 108 are tbe TCHAN signal; the FFREN* signal, which is the FIFO read enable signal; the TLD* 6ignal; the ClRST*
signal; the DIRSTB* ~ignal; the FFEM* or FIFO empty ~ignal; the FFHF~ ~ignal or the FIFO half full signal;
the FFAF* sig~al, which is the FIFO almost full signal;
the FFAE* signal, which is the FIFO almost empty signal; and the RESET1* signal.
The various outputs of the FIFO control PAL 108 ar~ the DR2H* ignal, which is provided to the output enable input of the ~uf~er ~6; a DUM~Y signal, which is provided to one inpu~ of ~ 2 input NAND gate 110; the F~USH* signal, which when active low indicates that flushing is occurri~g or ~a~ occurred; the ALLOW*
~ignal, which when active low indicates that data ic all~w~d to enter the FIFO 42, the RELEASE* signal, which when low indica~es t~at data can he removed fro~
the FIFO 42, the S~RST* cignal, which is used to reset the FIEO d2 ~nd t~e FIFO control logic 52; and the H2DR~ signal, which i6 provided to the output enable input of the buffer 50.
The various equations used in the PAL 10~ to develop its operations ~re as follows:
SMRST - ClRST ~ ~ESET1 H2DR = DIRSTB SMRST* + H2DR SMRST*
DR2H = H2DR*
RELEASE = FFHF SMRST* I RELEASE . FFAE* . SMRST*
ALLOW = SMRST ~ FFHF* . FFEM* + ALLOW . FFAF*
FLUSH = UFLSH . SMRST* + FLUSH . SMRST*
DUMMY c DUMMY . SMRST* + FFREN
Thus the SMRST 6ignal is high and the SMRST*
signal is low when reset occurs or the FIFO 42 is to be cleared. The ~2DR signal is active when the system is not being reset and the DIRSTB signal has been received. The DR2H signal i5 simply the inverse of the H2DR signal so that only one ~et of buffers is activated at a time. The RELEASE* ~ignal is set when the FIFO 42 is half full and is cleared when the FIFO
is almost empty. The ~LLOW* signal is ~ctive low on reset and when the FIFO is between empty and half full and i5 cleared when the FIFO is al~ost filled. The FLUSH ~ignal is produced when the UFLSH signal has ~een received fro~ the decoder 100. Flushing is ceased upon reset of the FIFO 42. The DUMMY ~ignal is made active when reads to the FIFO are enabled ~nd is cleared on reset.
The FFEM* or FIFO EMPTY signal is provided as the ~econd input to the NAND gate 110. The output of tAe N~ND gate 110 i~ referred to as the DUMY* ~ignal provided as one input to a SCSI chip ~ontrcl PAL 114.
Other input~ o~ th~ SCSI control PAL 114 are the LOOPBACK ~ignal; the BIT~KT ~ignal; the CPYM03E
signal; the F~æENl* signal which indicates that the BMIC 20 wi~hes to write informationf the FFREN1*
signal, which is an indication that the BMIC 20 wishes to read data from the FIFO 42; the FLUSH~ signal; the SDREQ~ signal, which is a synchronized version of the data request signal from the SCSI chip 22, the ALLOW*
signal, the RELEASE~ cignal~ the TREQ cignal, which is an indication that a request is being received from the 8MIC 20; and the DR2H* cignal. The TCLX Qignal is provided as the clock to several flip-flops located in the SCSI chip control PAL 114 to provide registered operation.
The SDREQ* signal is provided by the output of a two input NAND gate 116. One input to the NAND gate 116 is the DREQ signal provided from the SCSI chip 22 over the SCONT bus. The DREQ signal is also provided to ~ fourth D input of the flip-flop 106. The respective fourth output of the flip-flop 106 is provided to a fifth D input of the ~lip-flop 106. The fifth output of the flip-flop 106 is provided to the second input of the NAND gate 116, so that a data request from the SCSI chip 22 is synchronized and delayed, while a removal request happens immediately.
Preferably the SCSI control PAL 114 contains 4 D-type flip-flops. Two of the flip-flops produce signals referred to as FFWEN2 and FFREN2, which are used in developing the read and write enable signals provided to the FI~O 42. The preferred FIFO 42 operates such that when the particular enable signal is low, the data is clocked on the ri~ing edge of the clock signal, in the preferred embodiment the TCLK ~ignal, provided to 3Q that particular input ~et. The other two outputs of the flip-flops in the SCSI control PAL 114 are the DACK* and DBWR* ~ignals, which are provided to the SCSI
chip 22 to indicate acknowledgement of the data transfer request ~nd whether the transfer request will be a read or a write. The two remaining outputs of the ? .
PAL 114 are the FFWEN* and the FFREN* signals which ~re provided, respectively, to the write and read enable inputs of the FIFO 42. The eguations for the SCSI PAL
114 are as follows:
FFWEN2 :z DACK FFWEN2* CPYDIR* ALLOW
~ DACK FFWEN2~ CPYDIR* CPYMODE
FFREN2 := SDREQ DACX* FLSREL CPYDIR -FFREN2*
+ FFREN* DUMY CPYDIR* CPYMODE*
+ FFREN* DUMY LOOPBACK
+ SDREQ DACK* CPYMODE CPYDIR -FFREN2*
DACK := SDREQ DACK* ALLOW CPYDIR*
+ DACK FFWEN2* ALLOW CPYDIR*
~ SDREQ DACK* FLSREL ~ CPYDIR
+ DACK FFREN FLSREL CPYDIR
+ SDREQ DACK* CPYMODE
+ DACK FFWEN2* CPYMODE ^ CPYDIR~
+ DACR FFREN CPYMODE ~ CPYDIR
DBWR := SDREQ FLSREL CPYDIR ~ DACK 9 CPYDIR
+ SDREQ CPYMODE CPYDIR
FFWEN = FFWENl TREQ + FFWEN2 BITBUXT*
FFREN = FFREN1 TREQ + FFREN2 FLSREL ~ FLUSH + RELEASE
Thus the FFWEN2 signal toggles when the SCSI chip 22 has an acknowledged request, the direction indicates a write to the FIFO 42 and the FIFO 42 can receive data or loopback operations are occurring. The FFREN2 signal toggles on data ~eing requested by the SCSI chip 22, reads of the FIFO 42, and flushing, released or in loopback ~ode. The DACK ~ignal is 6et to toggle once per word transfer with the SCSI chip 22~ The DBWR
signal is high during reads. Th~ FFWEN signal tracks the FFWENl signal for BMIC 20 transfers and the FFWEN2 ~ign~l when the SC5I data i~ not being ignored. The FFREN signal tracks the FFREN1 signal for BMIC 20 transfers and the FFREN2 signal for SCSI chip 22 transfers.
A BMIC control PAL 118 is also contained in the S FIFO control logic 52. The BMIC control PAL 118 preferably c~ntains 4 D-type flip-flops and receives the TCLR signal as the clocking input to those flip-flops. The FLUSH*, ALLOW*, RELEASE*, LOOPBACK, TLD~, TREQ*, TCHAN, and TDIR signals are provided as inputs to the PAL 118. Two registered outputs from the BMIC control PAL 118 are the FFWENl* and FFRENl*
signals, which indicate that the BMIC 20 is desiring to do read or write ~perations respectively. The re~ai~ing two flip-flop outputs are the TACKl and TACK2 signals which are used to provide internal operation of the PAL 118. The TACR* signal is provided by the PAL
118 to the BMIC 20 to indicate an acknowledgement of a data transfer request. The tri-state control of the TACK* signal is provided by the TACK2 signal. The FF2BEN* signal is provided to the output enable input of the buffer 48 ~nd the B2FFEN~ ~ignal is provided to the output control of the buffer 44. The equations for the ~MIC control PAL 118 are as follows:
FFRENl := TREQ RELEASE . TDIR* . TCHAN .
LOOPBACK*
TREQ FLUSH o TDIR* ~ TCHAN . LOOPBACR*
+ TREQ RELEASE TDIR~ TCHAN
LOOPBACK
~ TREQ ~ FLUSH . TDIR~ o TCHAN . LOOPBACR
FFWENl := TREQ ^ ALLOW . TDIR TCHAN
TACXl := TREQ ~ RELEASE . TDIR* . TCHAN .
LOOPBA~K*
+ TREQ o FLUSH . TCHAN ~ LOOPBACK*
TREQ ~ ALLOW ~ TDIR . TC~AN
TREQ . RELEASE TDIR* . TCHAN~ .
LOOPBACK
~ TREQ . FLUSH . TDIR* . TCHAN* LOOPBACK
+ TLD . TCHAN . TACR~
+ TLD . TCHAN* . TACK* . LOOPBACX
TACK2 := LOOPBACK ~ TCHAN
B2FFEN - TCHAN TDIR . LOOPBACR~ TREQ
~ TDIR . LOOPBACK . TREQ
FF2BEN ~ TCHAN TDIR* . LOOPBACK* TREQ
~ TDIR* LOOP~ACK TREQ
TACK = TACKl . TREQ
~ TACK1 TLD
Thus the FFRENl signal is active when the BMIC 20 is requesting a transfer, the FIFO 42 is being read and is released or flushed and the data path channel is active for normal data transfers or the com~and path channel of the BMIC 20 is active for loopback operati~ns. The FFWENl signal is active when the BMIC
20 is reguesting a write transf~r, the FIFO 42 can receive data and the d~ta path channel is active. The transfer request i5 acknowledged by the TACK signal when proper and the buffers 44 and 48 are activated in the proper directions durinq the tr~nsfers, Operation ~f the data channel is generally as follows. The local microproce~sor 24 receives a transfer command from the host processor vi~ the BMIC
20 and the dual port RAM 36. The local micropro~essor ~4 resets the FIFO 42 and the FIFO control logic 52, ~ets the directio~ if necessary and set~ up the SCSI
chip 22. T~e first described oper~tion i5 ~ transfer from the BMIC 20 to tbe SCSI chip 22. When the local pr~cessor 24 notifies the BMIC 28 to initi~te the transfer, the BMIC ~0 begins pr~viding d~ta at a high r~te to the FI~O 42 after the BMIC 2Q gains ~ccess to the host bus. The SCSI chip 22 begins receiving the data at its rate. If the BMIC 20 is exceeding the reading rate of the SCSI chip 22, as generally occurs because the BMIC 20 is bursting data, the BMIC 20 halts operations when the FIF0 42 becomes almost full.
Preferably the almost full point allows several sectors of data to be transferred in a burst, improving host bus efficiency. The BMIC 20 restarts transmitting data when the FIF0 42 goes below half full. This process continues until the BMIC 20 has transferred all desired data. ~eanwhile, the SCSI chip 22 has been steadily removing data. When the BMIC 20 completed operations, the local microprocessor 24 was interrupted to set the FLUSH bit to allow the FIF0 42 to be emptied. The SCSI
chip 22 proceeds to read the FIF0 42 until its internal counters reach zero. The continued readinq would be stopped if the flush bit had not been set until the flush bit was set, because releasing stops at the ~lmost empty point. When complete, the SCSI chip 22 interrupts the local microprocessor 24 to inform it that flush can be released and the FIF0 is available for another transfer. The local microprocessor 24 informs the host system via the BMIC 20 that tne transfer is complete~
Another c~mmand is received by the local microprocessor 24. This is a read command to transfer data to the host cystem. Again the local microprocessor 24 resets the FIF0 42 and the FIF0 control logic 52 and ~e~s the direction. Additionally, the SCSI chip 22 and the BMIC 20 are programmed for the transfer. The transfer begins with the SCSI c~ip 22 providing data to the ~IF0 42. When the FIF0 42 reaches half full, the BMIC 20 is sllowed to read the data The BMIC 20 rapidly transfers the data until the almost empty level is reached, where operations pause until half full or flushing. Eventually the SCSI chip 22 completes its portion of the transfer and notifies the local microprocessor 24 by way of an interrupt.
The local microprocessor 24 6ets the flush mode and the BMIC 20 can complete transfer of the data. When complete the BMIC 20 notifies the local microprocessor 24 and a new operation can commence. Again the local microprocessor 24 then notifies the host system that the transfer is complete.
Thus the local microprocessor 24 only performs ~et up control operations and flush enablement and does not handle any data i~ the transfer, allowing the data to be transferred at the rate of the 610wer of the BMIC 20 or the SCSI chip 22. If these devices are designed to operate at their bus maximums, the transfer can be performed at a rate near the theoretical maximums.
Referring now to Figures 3A, 3B and 3C, the memory interface between the dual port RAM 36 and the local processor 24 is relatively straightforward. The address lines from the local processor 24, the LA bus, are provided to the address inputs of one side of the dual ported RAM 36, while the 16 bits of the local microprocessor data bus referred to as LD are provided to the data inputs of the port of the RAM 36. The various control lines fro~ the local processor 24 such as MWR*, BHE* and MRD* for writes/reads and high bytes are provided to the various control inputs of the port.
Additionally, a signal referred to as CLRAMCS0* or command channel RAM chip 6elect, which is developed by address decode from the local microprocessQr 24 and is not 6hown for clarity, is provided to the chip enable input of that p~rt o~ t~e RAM 36.
The interface to the BMIC 20 is ~lightly morc complicated because an address counter must be ~eveloped to allow proper addre~sing of the RAM 36 ~nd latches must be utilized to allow data ~ynchronization.
Four 4 bit synchronous counters 200, 202, 204 and 206 and three 3 input AND gates 208, 210 and 212 ~re combined to form a synchronous 16 bit counter. The data load inputs of the counters 200, 202, 204 and 206 receive values from the BNDAT or data bus from the BMIC
chip 20 and the counter or Q outputs of the counters 200, 202, 204 and 206 are provided to tAe address inputs of the second port of the RAM 36. The clocking signal of the counters 200, 202, 204 and 206 is provided by the TCK 6ignal, which is an output of a channel control PAL 214. Similarly, the inverted load input of the counters 200, 202, 204 and 206 receives the CLD* output of the channel control PAL 214. The inverted clear inputs of the counters 200-206 receive the RESETl* signal. One enable input of the counters 200-206 is connected to a logic high level, while the second enable inputs of the counters 200-204 are connected to the outputs of the AND qates 208-212. The second enable input of the counter 206, the least 6ignificant counter, is connected to the CLCE0 output of the PAL 214.
A pair of 8 bit D-type flip-flops 216 and 218 act ns ctorage registers for transfers of data from the B~IC 20 to the RAM 36. The D inputs of the flip-flops 216 and 218 are connected to the BMDAT bus, while the outputs are connected to the CLD or dual port RAM data bus for the BMIC port of the RAM 36. The TCK signal is provided to the clock inputs of the ~lip-flops 216 and 218, while a signal referred to as WE*, which is provided by the PAL 214, is provided to the output enable inputs of the flip-flops 216 and 218.
A pair of 8 bit flip-flops 220 and 222 are .provided for data transfers from the RAM 36 to the BMIC
20. To this end the data inpllts to the flip-flops 220 and 222 are connected to the CLD bus, while the outputs are connected to the BMDAT bus. The clocking 6ignal for the flip-flops 220 and 222 is provided by the CRD*
~ignal, which is provided as an output of the channel control PAL 214. The inverted output e~able inputs of the flip-flops 220 and 222 receives the RE* signal, which is provided as an output of a RAM control PAL
215. The read/write input for the BMIC port in the dual port RAM 36 is provided by a CWR* ~ignal provided by the PAL 214. The port or chip enable input is provided by a CLCE* signal, which is provided by the PAL 216, while the output enable input receives the CLOE* signal provided by the PAL 215. An additional signal provided by the PAL 214 is the TCLK signal, which is used as a transfer clock signal by the BMIC
20, the FIFO 42 and the FIFO control logic 52.
The channel control PAL 214 receives as inputs the CLKIN2 signal, which is a preferably a 20 MHz square wave signal produced by a free running oscillator on the SCSI bus controller S. Additional inputs to the PAL 214 are the CKDLY signal, which is a version of the CLKIN2 signal delayed 200 nanoseconds; the TLD* signal received from the BMIC 20; the TCHAN signal; the TDIR
~ign~l; the TREQ* signal; the C~DL5 signal, which is a 50 nanosecond delay of the CLKIN2 ~ignal; the LOOPBACK
sign~l and two signals referred to as TLDL* ~nd TRQL*
produced by the PAL 215.
The equations for the ~hannel control P~L 214 are as follows:
TCLK* = CLKIN2 + CKDL5 CLCE0* - TRQL* ~ TACK* ~ TRQL~ ~ TDR
~ TACK* ~ TDIR* + LOOPBACK
TCK* - CLXIN2 ~ CKDL5 CLD = TLDLA ~ TCHAN* ~ TLD ~ L~OPBAC~C* TACK*
CRD = TDIR* TCHAN* TREQ CKDL5 -LOOPBACK*
+ TLDL CLDL5 TACK TDIR* TCHAN* -LOOPBACK*
CWR = TDIR TCHAN* TRQL CKDL5 LOOPBACK*
+ TDIR TCHAN* TRQL CKDLY* -LOOPBACK*
TACK = TLDL TCHAN~ LOOPBACK*
+ TCHAN* LOOPBACK* TREQ
~ TACK TLD TCRAN* LOOPBACK*
WE - TDIR LOOPBACK* TCHAN* TRQL
~ TDIR LOOPBACK* TCHAN* TREQ
The RAM csntrol PAL 215 is preferably a PAL
containing 4 internal D-type flip-flops and the TCLK
lS signal is u~ed t~ clock these flip-flops. The inputs of the RAM control PAL 215 are the LOOPBACK signal, TREQ* signal, TDIR signal, the TCHAN signal, and the TLD* signal. Se~eral ~ignals are used internally by the RAM control PAL 215 and these are the TDL* signal, TWRL~ signal and the FLCNTE signal. Other signals provided by the RAM control PAL 215 have been previously mentioned. The equations for the RAM
co~tr~l PAL 215 are ~s follows~
CLOE = TDIR* TCHAN* LOOPBACK*
TRDL := TDIR* TCHANh TREQ LOOPBACK*
TWRL := TDIR ~ TCHAN* TREQ o LOOPBACK*
TRQL : = TCHAN* ^ TRE~ 4 LOOPBACK*
TLDL : = TCHAN* ~ TLD LOOPBACK* TLDL*
CLCE ~ TCHAN* TREQ L~VPBACK~ ~ TRQL
~ TCHAN* ~ TL~ LOOPBACX* ~ T~DL
RE - TDIR* TC~AN* LOC~BACX* T~D*
The TCLK and TCK 6ignals are ~imilar ~nd provided for fanout reasons. The operation of the dual port R~M
channel is disabled during loopback operations ~s indicated by the presenc~ of the LOOP~ACK* term. ~he IRQL signal is a latched version of a valid data transfer request by the BMIC 20. The TLDL is a toggled, latched version of the TLD signal for channel 0. The TRDL and TWRL signals are latched versions of the read and write str~bes produced by the BMIC 20 for channel 0. The CLOE signal is active during channel O
reads, while the CLCE signal is active during any channel 0 request or address load. The RE signal is active during data reads, while the WE signal is active during all write operations. The TACK signal is active when appropriate. The CLD signal is active when a channel 0 address is present. The CRD signal is active during reads, while the CWR is active during writes.
Therefore, this interface allows the BMIC 20 to read and write the dual port RAM 6 to allow command information to be passed to the local microprocessor 24 and status information to be received from the local microprocessor 24.
The foregoing disclosure and description of the invention are îllustrative and explanatory thereof, and various changes in the size, shape, materials, components, circuit elements, wiring connections and contacts, as well as in the details o the illustrated circuitry and con truction and method of operation may be made without departing from the spirit of the invention.
The present invention relates to peripheral device controllers used in computer ~ystems, and more particularly to controllers having an onboard processor for local supervisory control and supervising a secondary bus.
A common peripheral bus specification used for connecting disk drives, tape back-up units and other peripheral items to a computer system is the Small Computer System Interface or SCSI standard. The SCSI
bus interface has been developing over a period of years and has entered a second qeneration referred to as SCSI-2. Up to seven different peripheral devices can be connected to a SCSI bus and be controlled through a single SCSI bus controller unit. In personal computers the SCSI bus controller is preferably in the form of a interchangeable circuit board or adapter which is installed in one of the slots in the personal computer. In this manner the microprocessor forming the basis of the personal computer system can interact with the SCSI bus controller and access the particular 5 peripheral devices in a given installation.
one of the reasons for the growing interest in the S~SI bus is the relatively high data transfer rates which are available, particularly with the advent of higher performance peripheral devices. This interest is further enhanced by the development of intelligent ~ ?, ~
bus mastering controller units which can be installed in the various newer computer buses, such as those according to the Extended Industry Standard Architecture (EISA) or the Micro Channel Architecture (MCA). The bus mastering chips allow very high data transfer rates between the memory in the personal computer and the local adaptor, and when combined with the high data rates p~ssible in the SCSI bus, theoretically very high performance peripheral systems could be developed. However, one problem which develops relates to the transfer of data between the devices residing on the SCSI bus and the computer system bus. Because the two buses are operating asynchronously and at different data rates, it is required that some sort of buffering memory be utilized on the SCSI bus controller card. A further problem is that commands must also be transferred between the system and the SCSI bus and SCSI bus controller. If the main system processor is used to provide control of the various operations, then the performance of the bus controller is ~reatly diminished. If a local onboard processor is utilized, then performance can be improved, but the buffering problem still remains.
Conventionally, the local microprocessor is involved both in the transfer of the data from the SCSI
bus and the transfer of data to the host bus, thus limitinq data transfer operations to the effeGtive speed of the local processor. Given the high data transfer rates possible on both the computer system bus and the SCSI bus, this inclusion of the local processor and its multiple operations generally results in reduction of the potential data rates. Therefore it is desirable that the local microprocessor be removed from the actual data transfer operations between the SCSI
J .:., bus and the host computer bus, thus allowing higher data throughput.
one technique for resolving the problem has been the use of a caching controller, where large amounts of data are transferred into a cache memory on the controller and then transferred under control of the local microprocessor to the host system. The cache is sized so that a majority of the requests can be serviced from or by the cache, thus increasing computer system performance. But if a miss occurs, problems still exist. Additionally, large amounts of cache memory can be required, thus increasing expense.
SUMMARY OF THE INVENTION
A SCSI bus controller according to the present invention utilizes a data channel which, once operations have commenced, operates without any interaction with the local microprocessor and at the available data rate of both the SCSI controller unit and the bus mastering unit located in the controller, until a logical operation is almost completed. The local microprocessor issues a command to complete the transfer and the remaining data is transferred.
A first in, first out (FIFO) memory is utilized to perform the interface between the SCSI chip, which contr~l~ and coordinates the actual interface to the SCSI bus, and a bus master controller chip, which controls the actual interface to the personal computer system bus. The FIFO is used for all transfer of data information between the SCSI bus and the host bus and operates without interference from the local microprocessor once transactions are commenced ~nd until transactions are essentially completed.
Commands are provided to the local processor via a separate channel on the bus master interface circuit to a dual ported random access memory (RAM), which is also 2 ~
connected to the local microprocessor. Thus in this manner all command information, be it operations requests or status returns, are performed without impact or interference with the data transfer which is occurring in a ~eparate path. This allows optimization of the data path between the two units and the use of the FIFO.
The local microprocessor only performs actual command interpretation, status response and scheduling of operations between the SCSI bus and the host bus, and does not participate in the actual data transfer once it is commenced except for a minor completion of a data transfer at the end of a command, and even then without actually interpreting or receiving any of the data being transferred.
By removing the local microprocessor from the actual data flow and utilizing it only in a supervisory manner, data throughput is increased to values closer to that of the theoretical capabilities of the various buses.
A better understanding of the present invention can be obtained when the following detailed description of the preferred embodiment is considered in conjunction with the followin~ drawings, in which:
Figure 1 is block diagram of a SCSI bus controller according to the present invention;
Figures 2 and 3 indicate the relationships of Figures 2A, 2B and 2C and ~igures 3A, 3B and 3C, respectively; as shown with Figure 2;
Figures 2A~ 2B and 2C are schematic diagrams of porti~ns of the control logic for use with the FIFO of Figure l; and ' r~?.~ ~ ;
t .
Figures 3A, 3B and 3C are schematic diagrams of portions of the logic used in conjunction with the dual port ~AM of Figure 1.
Referring now to Figure 1, t~e letter S generally refers to a SCSI bus controller according to the present invention. A bus ~astering integrated circuit (BMIC) 20, preferably the 82355 produced by Intel Corporation for use with the EISA bus, is used to communicate between the host bus, the EISA bus in the preferred embodiment, in the personal computer in which the SCSI bus controller S is located and the various components located on the SCSI bus controller S. A
SCSI controller ch~p 22, preferably the 53C95 from the National Cash Register Corporation, is coupled to the SCSI bus to perform control of operations on the SCSI
bus, thus allowing increased speed of operations.
Preferably the BMIC 20 contains two local transfer channels, thus allowing separation of commands and data. Preferably the SCSI chip 22 includes a separate data port and ~ separate command or control port, both ports having data and control portions. Reference to the data sheets for the preferred BMIC 20 and SCSI chip 22 i~ desirable and an understandinq of the operations and interfaces of these devices is gener~lly assumed in this description. In addition, understanding of the operation of the SCSI bus is generally assumed, with reference being made to the SCSI-2 specification available from Global Engineering Documents in Irvine, California.
The SCSI chip 22 is connected to the data, address ~nd control lines of a local microprocessor 24, preferably zn &028~ operating at 25 MHz from Harris Semiconductor.
By means of this interface between the SCSI chip 22 and the local microprocessor 24, command information can be transferred between the local microprocessor 24 to the SCSI chip 22. Also connected to the local microprocessor 24 is read only memory (ROM) 26 and random access memory (RAM) 28, which is used to hold the operating sequences of the local microprocessor 24 and for its temporary data storage. Preferably the local microprocessor 24 operates under a real time, multitasking operating system. A timer 30 is connected to the local microprocessor 24 to receive timer information for u~e in the various sequences performed by the local microprocessor 24 and to an interrupt controller 32 to provide interrupt information. The interrupt controller 32 is also coupled to the local microprocessor 24. The interrupt controller 32 further receives interrupt information from the SCSI chip 22 and the BMIC 20 to allow interrupt driven operation of the local micr~processor 24 by the two controller chips ~0 ~nd 22. Additionally, a control bit register 34 is connected to the local microprocessor 24. This control bit register 34 is used to provide certain single bits which are used to control various operations of the SCSI bus controller S.
A dual ported RAM 36 has one port connected to the lQGal ~icroprocessor 24 and has its second port coupled to the BMIC 20 by me~ns of control logic 38 and a counter 40. The du31 port RAM 36 is used for holding command ~nd status information passed betwePn the host system vi~ the BMIC 20 and the local microproce~sor 24.
The dual port R~M 36 of the preferred embodiment includes chip and ~utput enable, upper and lower byte and r~d~wrî~e inpUtfi for each port. The B~IC 20 provides starting address information to the counter 40 ~nd thereafter the counter 40 increments to provide addressing information to the ~econd port of the dual port RAM 36. The data bus of the BMIC 20 is referred to as the BMDAT bus and is connected to the counter 40 and to the dual port RAM 36 while the control outputs of the BMIC 20 form the BMCONT bus and are provided to the dual port control logic 38.
A first in, first out (FIFO) memory 42 is used in the data channel between the SCSI chip 22 and the BMI~
20. Preferably the FIF0 42 is a synchronous, unidirectional FIFO having a lk by 18 bit sîze, preferably the IDT72225 from Integrated Device Technology, Inc. The FIFO 42 preferably contains write enable and write clock inputs to control the writing of information to the FIF0 42 and read enable and read clock inputs to control removal of information from the FIF0 42. Additionally, the FIFO 42 preferably includes a series of flag outputs to indicate the amount of data present in the FIF0 42. Preferably the flags include an empty flag, a full flag, a half-full flag and two programmable flags which indicate almost full and almost empty. Preferably the almost empty flag is set at 1/8 capacity of the FIFO 42 or 128 bytes, while the al~ost full flag is set at 7/~ or 896 bytes. The data inputs of the FIF0 42 are connected to the outputs of a buffer 44 whose inputs are connected to the BMDAT bus from the BMIC 20 ~nd to the outputs of a buffer 46 whose inputs are connected to the SDAT or data bus from the S~SI chip ~2. The data outputs from the FIF0 42 are preferably connected to the inputs of a buffer 48 w~ose outputs are connected to the BMDAT bus and to the inputs of ~ buffer 50 whose outputs are connected to the S~AT bus.
The variou~ g~te or enabling inputs of the buffers 44, 46, 48 and 50 are provided as outputs of a FIF0 control block 52. Additionally, the FIF0 control block r~ . ;, "~ ,?
is connected to the FIFO 42 to receive the flag information from the FIFO 42 and to provide the read and write enable and clocking signals to the FIFO 42.
Additionally the control bit register 34 is connected to the FIFO control 52 to provide certain control information from the local microprocessor 286. The BMCONT or control bus from the BMIC 20 is connected to FIFO control 52 to allow control of the direction and timing of data transfers with the BMIC 20. Further, the SCONT or SCSI chip control bus is provided from a SCSI chip 22 to the FIFO control logic 52 to allow transfer of data between the SCSI chip 22 and the FIFO
42.
It can be seen that the local microprocessor data bus, referred to as LD, is not provided to the actual data path between the SCSI chip 22 and the BMIC 20, but is connected only to the dual port RAM 36 and directly to the SCSI chip 22 command or control port. Thus, the local microprocessor 24 cannot perform the actual data transfer between the BMIC 20 and the SCSI chip 22.
The local microprocessor 24 only performs command and control functions and does not perform actual data transfer operations between the SCSI bus and t~e host bus. The host system develops a commmand block in its memory, provides the host memory ~tarting address to the BMIC 20 and causes the BMIC 20 to interrupt the local ~icroprocessor 24. The local microprocessor 24 programs the BMIC 20 to transfer the command block from the system memory to the dual port RAM 36. The local microprocessor 24 is interrupted by t~e BMIC 20 when the command block has been placed in the dual port RAM
36~ The local microprocessor 24 retrieves the command information and operates ~n it as appropriate. If it is an information request, and the SCSI chip 22 is not otherwise busy, the local microprocessor 24 ~ets up the FIF0 42 for the transfer and provides the proper commands to the SCSI chip 22 and the BMIC 20, which perform the commands. The SCSI chip 22, the BMIC 20 and the FIF0 control logic 52 interact to transfer the S data between the buses. If the transfer is from the B~IC 20 to the SCSI chip 22, the BMIC 20 completes its portion of the transfer first and indicates this completion to the local ~icroprocessor 24. If the transfer is from the SCSI chip 22 to the BMIC 20, the SCSI chip 22 will complete its transfer first and 60 inform the local microprocessor 24. These task completions are indicated by interrupts. Upon receiving the interrupt the local microprocessor 24 responds. The response generally includes flushing the FIF0 42 to complete the data transfer. When both the BMIC 20 and the SCSI chip 22 have completed their transfers, the local microprocessor 24 then places status or completion information in the dual port RAM
36 and causes the BMIC 20 to transfer the information to the host system me~ory and to interrupt the host system after the transfer is complete, cignalling task completion. The actual set up and flushinq of the FIF0 42 and data transfer is described in more detail below.
Referring now to Figures 2A, 2B and 2C, the interface of the FIF0 control logic 52 with SCSI chip 22 is according to a DMA protocol which includes a DMA
request line, a DMA acknowledge line and a direction of transfer or writelread signal. These signals ~re referred to ~s the DREQ, DACK* and DBWR* ~ignals and are contained in the SCONT bus. In general when referring to signals in this description, an asterisX
(*) after a signal ~nemonic indicates th~t it is logically true when a low voltage level is present and is the inverse of the same signal mnemonic without the asterisk. Angle br2cket included numbers after a signal mnemonic are used to indicate single or multiple bit positions in a wider logical signal, ~uch as the data or address fields.
The interface between the BMIC 20 and the FIFO
control 52 preferably is according to that of channel 1 of a 82~55 from Intel Corporation, as indic~ted in the specifications for that particular device as published in the 1990 Peripherals volume by Intel Corporation, at pages 1-3~4 to 1-392. To this end several signals are utilized from or provided to the BMIC 20 and they are referred to as the TDIR or transfer direction signal;
the TCLK signal which provides the clock or sequencing information; the TCHAN signal, which indicates if channel 1 or channel O of the B~IC 20 ic being utilized; the TREQ* signal, which in combination with the TACK* signal, form the handshake cignals for the request of information transfer; and the TLD* signal, which is the local address output load signal.
Several signals are received from the control bit register 34 by the FIFO control logic 52 and these are the LOOPBACK signal, the BITBUKT ~ignal, ~he CPYMODE
~ignal and the CPYDIR signal. The LOOPBACK signal is used to ~et whether a loopback operation with the BMIC
20 i~ being utilized SQ that partial checki~g of operations ca~ be performed by the B~IC 20. The BITBUKT signal is used to ignore information from the SCSI chip ~2 for cert~in opera~ions. The CP~D~R signal is used in combinatiQn with the CPYMODE signal for loopback operation of the SCSI chip 22 to indicate whether data is being pro~ided to ~r from the FIFO 42.
When the CPYMODE ~ignal is set, SCSI loopback is being perform~d. ~h~ CPYDIR signal controls fillin~ or emptying of the FI~O 42.
A siynal referred to as RESET1* is xeceived from 35 the host computer ~ystem over the host bus and ~-~ r~
indicates, when active low, that ~ system reset is being performed. A 4 bit decoder 100 (Fig. 2A) has its A and B ~election inputs connected to the LA or address bus of the local ~icroprocessor 24 and its active low S enable input connected to the CHAN1* signal. The CXANl* signal is produced by address decode logic (not ~hown) so that when the local microprocessor 24 addresses a particular address space, a low strobe is provided to the enable input of the decoder 100. The O
position inverted output of the decoder 100 provides the ClRST* signal or CHANNEL 1 RESET* signal which is used to cause a reset of the FI~O control loqic 52.
The 1 inverted output of the decoder 100 is the DIRSTB*
~ignal or DIRECTlON STROBE signal which is used to control the direction of data transfer between the host and SCSI buses. The bit 2 output of the decoder 100 is the ClFL~SH* ~ignal, which indicates a request to flush the FIFO 42. This flushing is utilized to empty the FIFO 42 at the end of an operation of transferring data. During normal operations the FIFO 42 is preferably kept partia~ly f`ull of data to prevent certain register reloads from occurring, thus simplifying logic operation. However, at the end of a command, it is required that the conventional control logic be overridden to allow the FIFO 42 to be completely emptied and therefore the flush input is provided.
The ClFLUSH* cignal is provided to the clocking input of a D-type flip-flop 102. The inverted preset and D input~ of the flip-flop 10~ are connected to a high logic level, while the inverted clear input is connected to the output of a two input NAND gate 104.
The non-inverted output of the flip-flop 102 is provid~d to a first D input of a multibit D-type flip-flop 106. The clocking signal for the flip-flop 106 is the TCLK 6ignal provided to the BMIC 20. The first non-inverted or Q ~utput of the flip-flop 10~ is provided to a 6econd D input of the flip-flop 106. The second non-inverted output of the flip-flop 106 is provided as one input to the NAND gate 104 and is provided to ~ third D input of the flip-flop 106. The third non-inverted or Q output of the flip-flop 106 is provided to the ~econd input of the NAND gate 104.
Thus in this manner the FLUSH signal is synchronized by the TCLK cignal and is provided for a given duration.
The output of the NAND gate 104 is ~lso provided as one input referred to as UFLSH* of a programmable array logic (PAL) device 108 referred to as the FIFO
control PAL. The FIFO control PAL 108 is one of a series of PAL's used in the FIFO control 52 to control operations. Other inputs to the FIFO con~rol PAL 108 are tbe TCHAN signal; the FFREN* signal, which is the FIFO read enable signal; the TLD* 6ignal; the ClRST*
signal; the DIRSTB* ~ignal; the FFEM* or FIFO empty ~ignal; the FFHF~ ~ignal or the FIFO half full signal;
the FFAF* sig~al, which is the FIFO almost full signal;
the FFAE* signal, which is the FIFO almost empty signal; and the RESET1* signal.
The various outputs of the FIFO control PAL 108 ar~ the DR2H* ignal, which is provided to the output enable input of the ~uf~er ~6; a DUM~Y signal, which is provided to one inpu~ of ~ 2 input NAND gate 110; the F~USH* signal, which when active low indicates that flushing is occurri~g or ~a~ occurred; the ALLOW*
~ignal, which when active low indicates that data ic all~w~d to enter the FIFO 42, the RELEASE* signal, which when low indica~es t~at data can he removed fro~
the FIFO 42, the S~RST* cignal, which is used to reset the FIEO d2 ~nd t~e FIFO control logic 52; and the H2DR~ signal, which i6 provided to the output enable input of the buffer 50.
The various equations used in the PAL 10~ to develop its operations ~re as follows:
SMRST - ClRST ~ ~ESET1 H2DR = DIRSTB SMRST* + H2DR SMRST*
DR2H = H2DR*
RELEASE = FFHF SMRST* I RELEASE . FFAE* . SMRST*
ALLOW = SMRST ~ FFHF* . FFEM* + ALLOW . FFAF*
FLUSH = UFLSH . SMRST* + FLUSH . SMRST*
DUMMY c DUMMY . SMRST* + FFREN
Thus the SMRST 6ignal is high and the SMRST*
signal is low when reset occurs or the FIFO 42 is to be cleared. The ~2DR signal is active when the system is not being reset and the DIRSTB signal has been received. The DR2H signal i5 simply the inverse of the H2DR signal so that only one ~et of buffers is activated at a time. The RELEASE* ~ignal is set when the FIFO 42 is half full and is cleared when the FIFO
is almost empty. The ~LLOW* signal is ~ctive low on reset and when the FIFO is between empty and half full and i5 cleared when the FIFO is al~ost filled. The FLUSH ~ignal is produced when the UFLSH signal has ~een received fro~ the decoder 100. Flushing is ceased upon reset of the FIFO 42. The DUMMY ~ignal is made active when reads to the FIFO are enabled ~nd is cleared on reset.
The FFEM* or FIFO EMPTY signal is provided as the ~econd input to the NAND gate 110. The output of tAe N~ND gate 110 i~ referred to as the DUMY* ~ignal provided as one input to a SCSI chip ~ontrcl PAL 114.
Other input~ o~ th~ SCSI control PAL 114 are the LOOPBACK ~ignal; the BIT~KT ~ignal; the CPYM03E
signal; the F~æENl* signal which indicates that the BMIC 20 wi~hes to write informationf the FFREN1*
signal, which is an indication that the BMIC 20 wishes to read data from the FIFO 42; the FLUSH~ signal; the SDREQ~ signal, which is a synchronized version of the data request signal from the SCSI chip 22, the ALLOW*
signal, the RELEASE~ cignal~ the TREQ cignal, which is an indication that a request is being received from the 8MIC 20; and the DR2H* cignal. The TCLX Qignal is provided as the clock to several flip-flops located in the SCSI chip control PAL 114 to provide registered operation.
The SDREQ* signal is provided by the output of a two input NAND gate 116. One input to the NAND gate 116 is the DREQ signal provided from the SCSI chip 22 over the SCONT bus. The DREQ signal is also provided to ~ fourth D input of the flip-flop 106. The respective fourth output of the flip-flop 106 is provided to a fifth D input of the ~lip-flop 106. The fifth output of the flip-flop 106 is provided to the second input of the NAND gate 116, so that a data request from the SCSI chip 22 is synchronized and delayed, while a removal request happens immediately.
Preferably the SCSI control PAL 114 contains 4 D-type flip-flops. Two of the flip-flops produce signals referred to as FFWEN2 and FFREN2, which are used in developing the read and write enable signals provided to the FI~O 42. The preferred FIFO 42 operates such that when the particular enable signal is low, the data is clocked on the ri~ing edge of the clock signal, in the preferred embodiment the TCLK ~ignal, provided to 3Q that particular input ~et. The other two outputs of the flip-flops in the SCSI control PAL 114 are the DACK* and DBWR* ~ignals, which are provided to the SCSI
chip 22 to indicate acknowledgement of the data transfer request ~nd whether the transfer request will be a read or a write. The two remaining outputs of the ? .
PAL 114 are the FFWEN* and the FFREN* signals which ~re provided, respectively, to the write and read enable inputs of the FIFO 42. The eguations for the SCSI PAL
114 are as follows:
FFWEN2 :z DACK FFWEN2* CPYDIR* ALLOW
~ DACK FFWEN2~ CPYDIR* CPYMODE
FFREN2 := SDREQ DACX* FLSREL CPYDIR -FFREN2*
+ FFREN* DUMY CPYDIR* CPYMODE*
+ FFREN* DUMY LOOPBACK
+ SDREQ DACK* CPYMODE CPYDIR -FFREN2*
DACK := SDREQ DACK* ALLOW CPYDIR*
+ DACK FFWEN2* ALLOW CPYDIR*
~ SDREQ DACK* FLSREL ~ CPYDIR
+ DACK FFREN FLSREL CPYDIR
+ SDREQ DACK* CPYMODE
+ DACK FFWEN2* CPYMODE ^ CPYDIR~
+ DACR FFREN CPYMODE ~ CPYDIR
DBWR := SDREQ FLSREL CPYDIR ~ DACK 9 CPYDIR
+ SDREQ CPYMODE CPYDIR
FFWEN = FFWENl TREQ + FFWEN2 BITBUXT*
FFREN = FFREN1 TREQ + FFREN2 FLSREL ~ FLUSH + RELEASE
Thus the FFWEN2 signal toggles when the SCSI chip 22 has an acknowledged request, the direction indicates a write to the FIFO 42 and the FIFO 42 can receive data or loopback operations are occurring. The FFREN2 signal toggles on data ~eing requested by the SCSI chip 22, reads of the FIFO 42, and flushing, released or in loopback ~ode. The DACK ~ignal is 6et to toggle once per word transfer with the SCSI chip 22~ The DBWR
signal is high during reads. Th~ FFWEN signal tracks the FFWENl signal for BMIC 20 transfers and the FFWEN2 ~ign~l when the SC5I data i~ not being ignored. The FFREN signal tracks the FFREN1 signal for BMIC 20 transfers and the FFREN2 signal for SCSI chip 22 transfers.
A BMIC control PAL 118 is also contained in the S FIFO control logic 52. The BMIC control PAL 118 preferably c~ntains 4 D-type flip-flops and receives the TCLR signal as the clocking input to those flip-flops. The FLUSH*, ALLOW*, RELEASE*, LOOPBACK, TLD~, TREQ*, TCHAN, and TDIR signals are provided as inputs to the PAL 118. Two registered outputs from the BMIC control PAL 118 are the FFWENl* and FFRENl*
signals, which indicate that the BMIC 20 is desiring to do read or write ~perations respectively. The re~ai~ing two flip-flop outputs are the TACKl and TACK2 signals which are used to provide internal operation of the PAL 118. The TACR* signal is provided by the PAL
118 to the BMIC 20 to indicate an acknowledgement of a data transfer request. The tri-state control of the TACK* signal is provided by the TACK2 signal. The FF2BEN* signal is provided to the output enable input of the buffer 48 ~nd the B2FFEN~ ~ignal is provided to the output control of the buffer 44. The equations for the ~MIC control PAL 118 are as follows:
FFRENl := TREQ RELEASE . TDIR* . TCHAN .
LOOPBACK*
TREQ FLUSH o TDIR* ~ TCHAN . LOOPBACR*
+ TREQ RELEASE TDIR~ TCHAN
LOOPBACK
~ TREQ ~ FLUSH . TDIR~ o TCHAN . LOOPBACR
FFWENl := TREQ ^ ALLOW . TDIR TCHAN
TACXl := TREQ ~ RELEASE . TDIR* . TCHAN .
LOOPBA~K*
+ TREQ o FLUSH . TCHAN ~ LOOPBACK*
TREQ ~ ALLOW ~ TDIR . TC~AN
TREQ . RELEASE TDIR* . TCHAN~ .
LOOPBACK
~ TREQ . FLUSH . TDIR* . TCHAN* LOOPBACK
+ TLD . TCHAN . TACR~
+ TLD . TCHAN* . TACK* . LOOPBACX
TACK2 := LOOPBACK ~ TCHAN
B2FFEN - TCHAN TDIR . LOOPBACR~ TREQ
~ TDIR . LOOPBACK . TREQ
FF2BEN ~ TCHAN TDIR* . LOOPBACK* TREQ
~ TDIR* LOOP~ACK TREQ
TACK = TACKl . TREQ
~ TACK1 TLD
Thus the FFRENl signal is active when the BMIC 20 is requesting a transfer, the FIFO 42 is being read and is released or flushed and the data path channel is active for normal data transfers or the com~and path channel of the BMIC 20 is active for loopback operati~ns. The FFWENl signal is active when the BMIC
20 is reguesting a write transf~r, the FIFO 42 can receive data and the d~ta path channel is active. The transfer request i5 acknowledged by the TACK signal when proper and the buffers 44 and 48 are activated in the proper directions durinq the tr~nsfers, Operation ~f the data channel is generally as follows. The local microproce~sor 24 receives a transfer command from the host processor vi~ the BMIC
20 and the dual port RAM 36. The local micropro~essor ~4 resets the FIFO 42 and the FIFO control logic 52, ~ets the directio~ if necessary and set~ up the SCSI
chip 22. T~e first described oper~tion i5 ~ transfer from the BMIC 20 to tbe SCSI chip 22. When the local pr~cessor 24 notifies the BMIC 28 to initi~te the transfer, the BMIC ~0 begins pr~viding d~ta at a high r~te to the FI~O 42 after the BMIC 2Q gains ~ccess to the host bus. The SCSI chip 22 begins receiving the data at its rate. If the BMIC 20 is exceeding the reading rate of the SCSI chip 22, as generally occurs because the BMIC 20 is bursting data, the BMIC 20 halts operations when the FIF0 42 becomes almost full.
Preferably the almost full point allows several sectors of data to be transferred in a burst, improving host bus efficiency. The BMIC 20 restarts transmitting data when the FIF0 42 goes below half full. This process continues until the BMIC 20 has transferred all desired data. ~eanwhile, the SCSI chip 22 has been steadily removing data. When the BMIC 20 completed operations, the local microprocessor 24 was interrupted to set the FLUSH bit to allow the FIF0 42 to be emptied. The SCSI
chip 22 proceeds to read the FIF0 42 until its internal counters reach zero. The continued readinq would be stopped if the flush bit had not been set until the flush bit was set, because releasing stops at the ~lmost empty point. When complete, the SCSI chip 22 interrupts the local microprocessor 24 to inform it that flush can be released and the FIF0 is available for another transfer. The local microprocessor 24 informs the host system via the BMIC 20 that tne transfer is complete~
Another c~mmand is received by the local microprocessor 24. This is a read command to transfer data to the host cystem. Again the local microprocessor 24 resets the FIF0 42 and the FIF0 control logic 52 and ~e~s the direction. Additionally, the SCSI chip 22 and the BMIC 20 are programmed for the transfer. The transfer begins with the SCSI c~ip 22 providing data to the ~IF0 42. When the FIF0 42 reaches half full, the BMIC 20 is sllowed to read the data The BMIC 20 rapidly transfers the data until the almost empty level is reached, where operations pause until half full or flushing. Eventually the SCSI chip 22 completes its portion of the transfer and notifies the local microprocessor 24 by way of an interrupt.
The local microprocessor 24 6ets the flush mode and the BMIC 20 can complete transfer of the data. When complete the BMIC 20 notifies the local microprocessor 24 and a new operation can commence. Again the local microprocessor 24 then notifies the host system that the transfer is complete.
Thus the local microprocessor 24 only performs ~et up control operations and flush enablement and does not handle any data i~ the transfer, allowing the data to be transferred at the rate of the 610wer of the BMIC 20 or the SCSI chip 22. If these devices are designed to operate at their bus maximums, the transfer can be performed at a rate near the theoretical maximums.
Referring now to Figures 3A, 3B and 3C, the memory interface between the dual port RAM 36 and the local processor 24 is relatively straightforward. The address lines from the local processor 24, the LA bus, are provided to the address inputs of one side of the dual ported RAM 36, while the 16 bits of the local microprocessor data bus referred to as LD are provided to the data inputs of the port of the RAM 36. The various control lines fro~ the local processor 24 such as MWR*, BHE* and MRD* for writes/reads and high bytes are provided to the various control inputs of the port.
Additionally, a signal referred to as CLRAMCS0* or command channel RAM chip 6elect, which is developed by address decode from the local microprocessQr 24 and is not 6hown for clarity, is provided to the chip enable input of that p~rt o~ t~e RAM 36.
The interface to the BMIC 20 is ~lightly morc complicated because an address counter must be ~eveloped to allow proper addre~sing of the RAM 36 ~nd latches must be utilized to allow data ~ynchronization.
Four 4 bit synchronous counters 200, 202, 204 and 206 and three 3 input AND gates 208, 210 and 212 ~re combined to form a synchronous 16 bit counter. The data load inputs of the counters 200, 202, 204 and 206 receive values from the BNDAT or data bus from the BMIC
chip 20 and the counter or Q outputs of the counters 200, 202, 204 and 206 are provided to tAe address inputs of the second port of the RAM 36. The clocking signal of the counters 200, 202, 204 and 206 is provided by the TCK 6ignal, which is an output of a channel control PAL 214. Similarly, the inverted load input of the counters 200, 202, 204 and 206 receives the CLD* output of the channel control PAL 214. The inverted clear inputs of the counters 200-206 receive the RESETl* signal. One enable input of the counters 200-206 is connected to a logic high level, while the second enable inputs of the counters 200-204 are connected to the outputs of the AND qates 208-212. The second enable input of the counter 206, the least 6ignificant counter, is connected to the CLCE0 output of the PAL 214.
A pair of 8 bit D-type flip-flops 216 and 218 act ns ctorage registers for transfers of data from the B~IC 20 to the RAM 36. The D inputs of the flip-flops 216 and 218 are connected to the BMDAT bus, while the outputs are connected to the CLD or dual port RAM data bus for the BMIC port of the RAM 36. The TCK signal is provided to the clock inputs of the ~lip-flops 216 and 218, while a signal referred to as WE*, which is provided by the PAL 214, is provided to the output enable inputs of the flip-flops 216 and 218.
A pair of 8 bit flip-flops 220 and 222 are .provided for data transfers from the RAM 36 to the BMIC
20. To this end the data inpllts to the flip-flops 220 and 222 are connected to the CLD bus, while the outputs are connected to the BMDAT bus. The clocking 6ignal for the flip-flops 220 and 222 is provided by the CRD*
~ignal, which is provided as an output of the channel control PAL 214. The inverted output e~able inputs of the flip-flops 220 and 222 receives the RE* signal, which is provided as an output of a RAM control PAL
215. The read/write input for the BMIC port in the dual port RAM 36 is provided by a CWR* ~ignal provided by the PAL 214. The port or chip enable input is provided by a CLCE* signal, which is provided by the PAL 216, while the output enable input receives the CLOE* signal provided by the PAL 215. An additional signal provided by the PAL 214 is the TCLK signal, which is used as a transfer clock signal by the BMIC
20, the FIFO 42 and the FIFO control logic 52.
The channel control PAL 214 receives as inputs the CLKIN2 signal, which is a preferably a 20 MHz square wave signal produced by a free running oscillator on the SCSI bus controller S. Additional inputs to the PAL 214 are the CKDLY signal, which is a version of the CLKIN2 signal delayed 200 nanoseconds; the TLD* signal received from the BMIC 20; the TCHAN signal; the TDIR
~ign~l; the TREQ* signal; the C~DL5 signal, which is a 50 nanosecond delay of the CLKIN2 ~ignal; the LOOPBACK
sign~l and two signals referred to as TLDL* ~nd TRQL*
produced by the PAL 215.
The equations for the ~hannel control P~L 214 are as follows:
TCLK* = CLKIN2 + CKDL5 CLCE0* - TRQL* ~ TACK* ~ TRQL~ ~ TDR
~ TACK* ~ TDIR* + LOOPBACK
TCK* - CLXIN2 ~ CKDL5 CLD = TLDLA ~ TCHAN* ~ TLD ~ L~OPBAC~C* TACK*
CRD = TDIR* TCHAN* TREQ CKDL5 -LOOPBACK*
+ TLDL CLDL5 TACK TDIR* TCHAN* -LOOPBACK*
CWR = TDIR TCHAN* TRQL CKDL5 LOOPBACK*
+ TDIR TCHAN* TRQL CKDLY* -LOOPBACK*
TACK = TLDL TCHAN~ LOOPBACK*
+ TCHAN* LOOPBACK* TREQ
~ TACK TLD TCRAN* LOOPBACK*
WE - TDIR LOOPBACK* TCHAN* TRQL
~ TDIR LOOPBACK* TCHAN* TREQ
The RAM csntrol PAL 215 is preferably a PAL
containing 4 internal D-type flip-flops and the TCLK
lS signal is u~ed t~ clock these flip-flops. The inputs of the RAM control PAL 215 are the LOOPBACK signal, TREQ* signal, TDIR signal, the TCHAN signal, and the TLD* signal. Se~eral ~ignals are used internally by the RAM control PAL 215 and these are the TDL* signal, TWRL~ signal and the FLCNTE signal. Other signals provided by the RAM control PAL 215 have been previously mentioned. The equations for the RAM
co~tr~l PAL 215 are ~s follows~
CLOE = TDIR* TCHAN* LOOPBACK*
TRDL := TDIR* TCHANh TREQ LOOPBACK*
TWRL := TDIR ~ TCHAN* TREQ o LOOPBACK*
TRQL : = TCHAN* ^ TRE~ 4 LOOPBACK*
TLDL : = TCHAN* ~ TLD LOOPBACK* TLDL*
CLCE ~ TCHAN* TREQ L~VPBACK~ ~ TRQL
~ TCHAN* ~ TL~ LOOPBACX* ~ T~DL
RE - TDIR* TC~AN* LOC~BACX* T~D*
The TCLK and TCK 6ignals are ~imilar ~nd provided for fanout reasons. The operation of the dual port R~M
channel is disabled during loopback operations ~s indicated by the presenc~ of the LOOP~ACK* term. ~he IRQL signal is a latched version of a valid data transfer request by the BMIC 20. The TLDL is a toggled, latched version of the TLD signal for channel 0. The TRDL and TWRL signals are latched versions of the read and write str~bes produced by the BMIC 20 for channel 0. The CLOE signal is active during channel O
reads, while the CLCE signal is active during any channel 0 request or address load. The RE signal is active during data reads, while the WE signal is active during all write operations. The TACK signal is active when appropriate. The CLD signal is active when a channel 0 address is present. The CRD signal is active during reads, while the CWR is active during writes.
Therefore, this interface allows the BMIC 20 to read and write the dual port RAM 6 to allow command information to be passed to the local microprocessor 24 and status information to be received from the local microprocessor 24.
The foregoing disclosure and description of the invention are îllustrative and explanatory thereof, and various changes in the size, shape, materials, components, circuit elements, wiring connections and contacts, as well as in the details o the illustrated circuitry and con truction and method of operation may be made without departing from the spirit of the invention.
Claims (9)
1. A device controller for insertion in a host computer system having data lines and for communicating with a plurality of devices having data lines, the device controller comprising:
a local microprocessor having data lines for controlling operations for the device controller;
means coupled to said microprocessor and said microprocessor data lines and the host computer system and the host computer system data lines for exchanging command and status information between the host system and said local microprocessor;
means coupled to the plurality of devices and said local microprocessor, including said local microprocessor data lines, for providing a control interface between the plurality of devices and said local microprocessor;
first in, first out memory means for temporarily storing data between transferred between the host computer system and the plurality of devices;
means coupled to said first in, first out memory means and the host computer system data lines for transferring data between said memory means and the host system without data transfer by said local microprocessor; and means coupled to said first in, first out memory means and the plurality of devices data lines for transferring data between said first in, first out memory means and the plurality of devices without data transfer by said local microprocessor.
a local microprocessor having data lines for controlling operations for the device controller;
means coupled to said microprocessor and said microprocessor data lines and the host computer system and the host computer system data lines for exchanging command and status information between the host system and said local microprocessor;
means coupled to the plurality of devices and said local microprocessor, including said local microprocessor data lines, for providing a control interface between the plurality of devices and said local microprocessor;
first in, first out memory means for temporarily storing data between transferred between the host computer system and the plurality of devices;
means coupled to said first in, first out memory means and the host computer system data lines for transferring data between said memory means and the host system without data transfer by said local microprocessor; and means coupled to said first in, first out memory means and the plurality of devices data lines for transferring data between said first in, first out memory means and the plurality of devices without data transfer by said local microprocessor.
2. The device controller of claim 1, further comprising:
means coupled to said local microprocessor, said host data transfer means and said device data transfer means for preparing both said data transfer means for data transfer in a desired direction.
means coupled to said local microprocessor, said host data transfer means and said device data transfer means for preparing both said data transfer means for data transfer in a desired direction.
3. The device controller of claim 2, wherein said data transfer preparation means includes means for providing for transfer of all of said data from said first in, first out memory means.
4. The device controller of claim 3, wherein said data transfer means includes means for pausing transfer from said first in, first out memory means when said first in, first out means contains less than a predetermined amount of data.
5. The device controller of claim 4, wherein said data transfer means include means for allowing said data transfer means to transfer data from said first in, first out memory means when the final data to be transferred is contained in said first in, first out memory means.
6. The device controller of claim 3, wherein said data transfer means include means for pausing transfer to said first in, first out memory means when said first in, first out memory means contains more than a predetermined amount of data.
7. The device controller of claim 6, wherein said data transfer means includes means for pausing transfer from said first in, first out memory means when said first in, first out means contains less than a predetermined amount of data.
8. The device controller of claim 7, wherein said data transfer means include means for allowing said data transfer means to transfer data from said first in, first out means when the final data to be transferred is contained in said first in, first out means.
9. The device of controller of claim 1, wherein said command exchange means includes a dual ported random access memory, said dual ported memory being coupled to said local microprocessor data lines and the host computer system data lines.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/612,135 US5241630A (en) | 1990-11-13 | 1990-11-13 | Device controller with a separate command path between a host and the device and a separate data path including a first in, first out memory between the host and the device |
| US612,135 | 1990-11-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2054431A1 true CA2054431A1 (en) | 1992-05-14 |
Family
ID=24451876
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002054431A Abandoned CA2054431A1 (en) | 1990-11-13 | 1991-10-29 | Disk controller with separate data and command paths |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5241630A (en) |
| EP (1) | EP0486230A1 (en) |
| JP (1) | JPH05265929A (en) |
| CA (1) | CA2054431A1 (en) |
Families Citing this family (42)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5655147A (en) * | 1991-02-28 | 1997-08-05 | Adaptec, Inc. | SCSI host adapter integrated circuit utilizing a sequencer circuit to control at least one non-data SCSI phase without use of any processor |
| IL100127A0 (en) * | 1991-03-11 | 1992-08-18 | Future Domain Corp | Scsi controller |
| JPH04350737A (en) * | 1991-05-29 | 1992-12-04 | Nec Corp | Microcomputer |
| JPH05265947A (en) * | 1992-02-19 | 1993-10-15 | Nec Corp | Scsi controller |
| US5325401A (en) * | 1992-03-13 | 1994-06-28 | Comstream Corporation | L-band tuner with quadrature downconverter for PSK data applications |
| US5941964A (en) * | 1992-05-21 | 1999-08-24 | Intel Corporation | Bridge buffer management by bridge interception of synchronization events |
| US5371861A (en) * | 1992-09-15 | 1994-12-06 | International Business Machines Corp. | Personal computer with small computer system interface (SCSI) data flow storage controller capable of storing and processing multiple command descriptions ("threads") |
| US5463753A (en) * | 1992-10-02 | 1995-10-31 | Compaq Computer Corp. | Method and apparatus for reducing non-snoop window of a cache controller by delaying host bus grant signal to the cache controller |
| US5448709A (en) * | 1992-10-13 | 1995-09-05 | Compaq Computer Corporation | Disk array controller having command descriptor blocks utilized by bus master and bus slave for respectively performing data transfer operations |
| WO1994009436A1 (en) * | 1992-10-13 | 1994-04-28 | Compaq Computer Corporation | Disk array controller having advanced internal bus protocol |
| US5659690A (en) * | 1992-10-15 | 1997-08-19 | Adaptec, Inc. | Programmably configurable host adapter integrated circuit including a RISC processor |
| US5499384A (en) * | 1992-12-31 | 1996-03-12 | Seiko Epson Corporation | Input output control unit having dedicated paths for controlling the input and output of data between host processor and external device |
| US5897667A (en) * | 1993-11-16 | 1999-04-27 | Intel Corporation | Method and apparatus for transferring data received from a first bus in a non-burst manner to a second bus in a burst manner |
| US5455954A (en) * | 1993-12-22 | 1995-10-03 | Adaptec, Inc. | Host interrupt signal generation circuit for controlling an auto read operation in a disk drive controller |
| GB2286910B (en) * | 1994-02-24 | 1998-11-25 | Intel Corp | Apparatus and method for prefetching data to load buffers in a bridge between two buses in a computer |
| US5634081A (en) * | 1994-03-01 | 1997-05-27 | Adaptec, Inc. | System for starting and completing a data transfer for a subsequently received autotransfer command after receiving a first SCSI data transfer command that is not autotransfer |
| JP3474646B2 (en) * | 1994-09-01 | 2003-12-08 | 富士通株式会社 | Input / output control device and input / output control method |
| US5729719A (en) * | 1994-09-07 | 1998-03-17 | Adaptec, Inc. | Synchronization circuit for clocked signals of similar frequencies |
| US5434892A (en) * | 1994-09-16 | 1995-07-18 | Intel Corporation | Throttling circuit for a data transfer system |
| WO1996008773A2 (en) * | 1994-09-16 | 1996-03-21 | Cirrus Logic, Inc. | Pcmcia dma data bus mastering |
| US5548788A (en) * | 1994-10-27 | 1996-08-20 | Emc Corporation | Disk controller having host processor controls the time for transferring data to disk drive by modifying contents of the memory to indicate data is stored in the memory |
| US5717954A (en) * | 1995-10-13 | 1998-02-10 | Compaq Computer Corporation | Locked exchange FIFO |
| US6038620A (en) * | 1996-09-09 | 2000-03-14 | International Business Machines Corporation | Method and system for optimal high speed match in a high performance controller which ensures an input/output interface stays ahead of a host interface |
| US5961627A (en) * | 1997-06-18 | 1999-10-05 | Gigalabs, Inc | High speed switch for high speed connection between computers and peripheral devices |
| US6128686A (en) * | 1998-06-15 | 2000-10-03 | Compaq Computer Corporation | Hiding peripheral memory transactions on a local bus within a peripheral controller from a host system bus |
| US6816934B2 (en) | 2000-12-22 | 2004-11-09 | Hewlett-Packard Development Company, L.P. | Computer system with registered peripheral component interconnect device for processing extended commands and attributes according to a registered peripheral component interconnect protocol |
| KR100393983B1 (en) * | 1999-06-14 | 2003-08-06 | 엘지전자 주식회사 | Data Transmit Device For Improvement Processor Over Load |
| US6675253B1 (en) | 2000-04-04 | 2004-01-06 | Hewlett-Packard Development Company, L.P. | Dynamic routing of data across multiple data paths from a source controller to a destination controller |
| US6658520B1 (en) * | 2000-09-26 | 2003-12-02 | Intel Corporation | Method and system for keeping two independent busses coherent following a direct memory access |
| US6973524B1 (en) * | 2000-12-14 | 2005-12-06 | Lsi Logic Corporation | Interface for bus independent core |
| US6904481B1 (en) * | 2001-04-12 | 2005-06-07 | Lsi Logic Corporation | Bus sequence operation with automatic linking from current I/O information to subsequent I/O information |
| US6880033B1 (en) * | 2001-05-25 | 2005-04-12 | Adaptec, Inc. | Methods for configuring separate accessibility of each channel of a dual channel SCSI chip |
| US6941408B2 (en) | 2002-09-30 | 2005-09-06 | Lsi Logic Corporation | Bus interface system with two separate data transfer interfaces |
| US20040123027A1 (en) * | 2002-10-03 | 2004-06-24 | Workman Michael Lee | Systems and methods of multiple access paths to single ported storage devices |
| US20040068591A1 (en) * | 2002-10-03 | 2004-04-08 | Workman Michael Lee | Systems and methods of multiple access paths to single ported storage devices |
| US7007122B2 (en) | 2002-11-27 | 2006-02-28 | Lsi Logic Corporation | Method for pre-emptive arbitration |
| US20040193770A1 (en) * | 2003-03-13 | 2004-09-30 | Whiteman Jason W. | Communicating information in a computer system |
| US7085859B2 (en) | 2003-05-14 | 2006-08-01 | International Business Machines Corporation | Method, apparatus and program storage device for automatically presenting status from a host bus adapter until an error is detected |
| US8639866B2 (en) * | 2003-08-06 | 2014-01-28 | Hewlett-Packard Development Company, L.P. | Systems and methods for dividing a communications channel |
| US7421520B2 (en) * | 2003-08-29 | 2008-09-02 | Aristos Logic Corporation | High-speed I/O controller having separate control and data paths |
| US7213094B2 (en) * | 2004-02-17 | 2007-05-01 | Intel Corporation | Method and apparatus for managing buffers in PCI bridges |
| US20080070688A1 (en) * | 2006-09-20 | 2008-03-20 | John Loehrer | Real-time gaming system having scalable database |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2261567B1 (en) * | 1974-02-20 | 1977-09-23 | Honeywell Bull Soc Ind | |
| JPS5255446A (en) * | 1975-10-31 | 1977-05-06 | Toshiba Corp | Information transfer control system |
| US4417304A (en) * | 1979-07-30 | 1983-11-22 | International Business Machines Corporation | Synchronous cycle steal mechanism for transferring data between a processor storage unit and a separate data handling unit |
| US4825403A (en) * | 1983-05-16 | 1989-04-25 | Data General Corporation | Apparatus guaranteeing that a controller in a disk drive system receives at least some data from an invalid track sector |
| US4612613A (en) * | 1983-05-16 | 1986-09-16 | Data General Corporation | Digital data bus system for connecting a controller and disk drives |
| US4773004A (en) * | 1983-05-16 | 1988-09-20 | Data General Corporation | Disk drive apparatus with hierarchical control |
| US4591973A (en) * | 1983-06-06 | 1986-05-27 | Sperry Corporation | Input/output system and method for digital computers |
| US4860244A (en) * | 1983-11-07 | 1989-08-22 | Digital Equipment Corporation | Buffer system for input/output portion of digital data processing system |
| US4918597A (en) * | 1984-12-14 | 1990-04-17 | Alcatel Usa Corp. | Adaptive interface for transferring segmented message between device and microcomputer on line division multiplexed bus |
| US4918589A (en) * | 1985-10-31 | 1990-04-17 | Allen-Bradley Company, Inc. | Method and apparatus for linking processors in a hierarchical control system |
| JPS62138948A (en) * | 1985-12-13 | 1987-06-22 | Hitachi Ltd | Data transferring equipment |
| US4847812A (en) * | 1986-09-18 | 1989-07-11 | Advanced Micro Devices | FIFO memory device including circuit for generating flag signals |
| US4779190A (en) * | 1986-12-03 | 1988-10-18 | Ncr Corporation | Communication bus interface |
| US4775978A (en) * | 1987-01-12 | 1988-10-04 | Magnetic Peripherals Inc. | Data error correction system |
| US4843544A (en) * | 1987-09-25 | 1989-06-27 | Ncr Corporation | Method and apparatus for controlling data transfers through multiple buffers |
| US5065314A (en) * | 1988-09-23 | 1991-11-12 | Allen-Bradley Company, Inc. | Method and circuit for automatically communicating in two modes through a backplane |
| US5088025A (en) * | 1989-02-21 | 1992-02-11 | Unisys Corporation | Input/output processor control system with a plurality of staging buffers and data buffers |
| US5267191A (en) * | 1989-04-03 | 1993-11-30 | Ncr Corporation | FIFO memory system |
| US5056010A (en) * | 1989-10-30 | 1991-10-08 | Industrial Technology Research Institute | Pointer based DMA controller |
-
1990
- 1990-11-13 US US07/612,135 patent/US5241630A/en not_active Expired - Lifetime
-
1991
- 1991-10-29 CA CA002054431A patent/CA2054431A1/en not_active Abandoned
- 1991-11-08 EP EP91310354A patent/EP0486230A1/en not_active Withdrawn
- 1991-11-13 JP JP3325222A patent/JPH05265929A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05265929A (en) | 1993-10-15 |
| EP0486230A1 (en) | 1992-05-20 |
| US5241630A (en) | 1993-08-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Discontinued |