CA2043803A1 - Pattern synchronizing circuit - Google Patents
Pattern synchronizing circuitInfo
- Publication number
- CA2043803A1 CA2043803A1 CA002043803A CA2043803A CA2043803A1 CA 2043803 A1 CA2043803 A1 CA 2043803A1 CA 002043803 A CA002043803 A CA 002043803A CA 2043803 A CA2043803 A CA 2043803A CA 2043803 A1 CA2043803 A1 CA 2043803A1
- Authority
- CA
- Canada
- Prior art keywords
- clock
- low
- speed
- output
- speed data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0605—Special codes used as synchronising signal
- H04J3/0608—Detectors therefor, e.g. correlators, state machines
Abstract
ABSTRACT OF THE DISCLOSURE
An Nth one of N parallel sequences of low-speed data demultiplexed by a demultiplexer from high speed input data in synchronization with a high-speed clock is compared by N comparators with N parallel sequences of reference patterns. The N parallel sequences of reference patterns are each generated in synchronization with a frequency divided clock obtained by frequency dividing the high-speed clock into 1/N. When any of the comparators provides a disagreement output at least once, one clock pulse is eliminated by a post-clock eliminating circuit from the divided clock so that the N sequences of reference patterns are each delayed by one bit. When it is detected by a counter that any one of the comparators does not provide the disagreement signal for n consecutive bits, the sequence of reference pattern corresponding to this comparator and the Nth sequence of low-speed data are in synchronization with each other.
Clock pulses of the number corresponding to the line position of the synchronized sequence of reference pattern are eliminated by a pre-clock eliminating circuit from the high-speed clock which is applied to the demultiplexer. By this, line positions of the N parallel sequences of low-speed data are sequentially shifted so that the Nth sequence of low-speed data assumes the same line position as that of the synchronized reference pattern, and as a result, the N parallel sequences of low-speed data are synchronized with the N parallel sequences of reference patterns, respectively.
An Nth one of N parallel sequences of low-speed data demultiplexed by a demultiplexer from high speed input data in synchronization with a high-speed clock is compared by N comparators with N parallel sequences of reference patterns. The N parallel sequences of reference patterns are each generated in synchronization with a frequency divided clock obtained by frequency dividing the high-speed clock into 1/N. When any of the comparators provides a disagreement output at least once, one clock pulse is eliminated by a post-clock eliminating circuit from the divided clock so that the N sequences of reference patterns are each delayed by one bit. When it is detected by a counter that any one of the comparators does not provide the disagreement signal for n consecutive bits, the sequence of reference pattern corresponding to this comparator and the Nth sequence of low-speed data are in synchronization with each other.
Clock pulses of the number corresponding to the line position of the synchronized sequence of reference pattern are eliminated by a pre-clock eliminating circuit from the high-speed clock which is applied to the demultiplexer. By this, line positions of the N parallel sequences of low-speed data are sequentially shifted so that the Nth sequence of low-speed data assumes the same line position as that of the synchronized reference pattern, and as a result, the N parallel sequences of low-speed data are synchronized with the N parallel sequences of reference patterns, respectively.
Description
2~33~3 TITLE OF THE INVENTION
.
PATTE~N SYNCHRONIZING CIRCUIT
BACKGROUND OF THE INVENTION
The present invention relates to a pattern synchronizing circuit which is used~ for example, in measurement of the error rate of a digital signal transmission system, for synchronizing a reference pattern generator with input test data (a pseudo random pattern) prior to the measurement. More particularly, the invention pertains to a demultiplexed pattern synchronizing circuit whereby parallel sequences of input data obtained by demultiplexing a high-speed pseudo random pattern are synchronized with parallel sequences of reference patterns.
In the case of measuring the transmission error rate of a digital signal transmission system, a measurement pattern formed by a repetition of a certain pattern of a predetermined bit length is pro~ided from 2 pattern generator to the digital transmission system at the transmitting side thereof. At the receiving side of the digital transmission system the same pattern as the measurement pattern at the transmission side is 8enerated as a reference pattern and compared, bit by bit, with an input pattern provided through the transmission system and containing errors, by which the errors in the input pattern are detected, and the number of errors per unit bit is counted. It is customary to use, as the measurement pattern, a pseudo random pattern9 usuaLly a repetitive pattern of a maximum length linear shift register sequence of a (2n-1)-bit length. The bit length of a non-repetitive or random maximum length pattern9 obtainable with an n-stage shift register, is 2n-1, and such a pattern is called a - .
2 2~38~3 maximum length linear shift register sequences. It is well-known in the art that the pseudo random pattern, which is a repetition o~ such a pattern, has a feature in that a sequence of bits extracted therefrom every N =
2~ (where a is an integer equal to or greater than 1) bit positions starting at an arbitrary bit position cons~itutes the same pattern as the original pseudo random pattern.
In the case of measuring the error rate of a transmission system when a digital signal is provided thereto at a high speed, it is difficult to implement a high-speed comparator which is able to compare the input pattern with the reference pattern on a bitwise basis at the receiving side. A conventional solution to this problem, which takes advanta~e of the above-mentioned feature of the maximum length linear shift register sequence (hereinafter referred to as ML sequence), is to divide the inpu~ pattern, bit by bit, into N = 2~ parallel sequences on N lines, that is, demultiplex the input pattern into N parallel sequences of low-speed data at the receiving sideO In this instance, if the received pattern is error-free, the N = 20 parallel sequences of low-speed data each form the same pattern as the high-speed pseudo random pattern for measurement use generated at the transmitting side and they are sequentially displaced a ~ixed number of bits (about l/N of the pattern period) apart in phase. Accordingly, similar N
parallel sequences of low-speed patterns are generated as reference patterns at the receiving side and are respectively compared with the demultiplexed N parallel sequences o~ low-speed data, by which the error rate of the digital transmission system can be measured. For correct measurement of the error rate, however, it is 2~38~3 necessary to establish synchronization between the N
demultiplexed parallel sequences of low-speed data and the N parallel sequences of reference patterns so that they are in phase with each other.
Such a demultiplexed pattern synchronizing circuit is disclosed in U. S. Patent No. 4,878,233. This U. S.
patent shows the case where high-speed input data is demultiplexed, by use o~ a high-speed clock synchronized there~ith, into four parallel sequences of low-speed data on four output lines for comparison with four parallel se~uences of reference patterns by four comparators. The four parallel sequences of reference patterns are each eenerated in synchronization with a low-speed clock obtained by frequency dividing the above-said high-speed clock down to 1/4. The number of disagreements in the results of comparison by the four comparators is counted, and when the count value exceeds a predetermined value, it is decided that the four parallel sequences o~ low-speed data and the four parallel sequences of reference patterns are not synchronized with each other. Thereafter, upon each counting of a predetermined number of disagreements, one of the low-speed clocks for generating the reference patterns is eliminated, by which the four parallel sequences of reference patterns are all delayed by one bit relative to corresponding four parallel sequences of low-speed data. The one-bit delay of the reference patterns is repeated until the four parallel sequences of reference patterns are synchronized with the four parallel sequences of low-speed data.
WLth the demultiplexed pattern synchronizing circuit set forth in the above-mentioned ~. S. patent, however, no synchronization can be established, in the .. ~. ' ~ , ' ., ~
' 2~3~3 worst case, until the reference pa~tern is delayed for a period of time equal to the len~th of the ML sequence minus one blt, i. e. (2a l )~l bit (which is approximately one reference pattern period in practice, because n is selected equal to or ~reater than 4). In addition, the time length of 2~-1 bits in the reference pattern (or low-speed data) is equal to the time length of 4x (2-1 ) bits in the high-speed input data, and this corresponds to approximately f`our periods of the maximum len~th linear shift register sequence which is repeated in the high-speed input data. In other words, about four periods of the high-speed pattern for measurement are consumed merely for synchronization, not for measurement of the error rate--this impairs the efficiency of measurement of the error rate. Recently, in particular, a high-speed digital transmission in the gigahertz band for optical communication has come into -use, and the pattern for measuring the error rate o~ such a high-speed digital transmission system is required to be large in the bit length of one pattern period.
F'or example, in the case where the number of-bits o~ one period of the ML sequence of the high-speed pattern data for measurement is 223-1, the frequency f is 2 GHz and the number N of parallel sequences of low-speed data is 16s then one period of the reference pattern becomes around 67 milliseconds. In the case where the number of bits of one period o~ the ML sequence iS 23 1 -l, the frequency f is 2 GHz and the number N is 16, one period of the reference pattern becomes about 17 seconds. Thus, when the bit length of one period of the measurement pattern (high-speed input data) is as lar~e as 231-l (~ 2.15x 109) bits, the time for synchronization is 17 seconds at maximum and hence is 2~3~3 impractical.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a demultiplexed pattern synchronizing circuit with which it is possible to synchronize a reference pattern with input data in a short time.
According to the present invention, high-speed input data is demultiplexed by demultiplexer, in synchronization with a high-speed clock, into N parallel sequences of low-speed data on N output lines and N
parallel sequences of reference patterns are generated by a pattern generator in synchronization with frequency-divided clocks obtained by frequency dividing the high-speed clock down to 1/N. Then an Nth sequence of low-speed data, composed of data of every Nth bits of the N-bit data which is provided from the demultiplexer upon each occurrence of the divided clock, is compared by N comparators with the N parallel sequences of reference patterns from the reference pattern generator.
A control circuit skarts to detect disagreements in the comparator outputs and, when every one of the N
comparators has yielded the disagreement output at least once, generates a first clock pulse eliminating signal to eliminate one clock pulse from the divided clock input into the reference pattern generator and is reset to the disagreement detection starting state. When any one of the N parallel sequences of reference patterns agrees the low-speed data at least n times in succession, second clock pulse eliminatin~ signal is Benerated the number of times corresponding to the difference in output line position between the sequence of the matching reference pattern and the above-mentioned Nth sequence of low-speed data to eliminate, by the same number as , ' . ''`''' ..
.. ~. .
2 ~ c~
the second clock pulse eliminating signals, clock pulses of the high-speed clock which is applied to the demultiplexer. By this, the output line position of the Nth parallel sequence of low-speed data in the demultiplexer is shifted to the output line position of the sequence of matching reference patterns.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram illustrating an embodiment of the pattern synchronizing circuit according to the present invention;
Fig. 2A is a diagram for explaining demultiplexing;
Fi8. 2B is a diagram for explaining demultiplexing;
Fig. 3A is a circuit diagram showing a specific operative example of a portion of Fig. 1;
Fig. 3B is a circuit diagram showing a specific operative example of a control circuit in Fig. 1;
Fig. 4 is a timing chart showing the operation o~ the pattern synchronizing circuit of Fig. 1 in the case where n = 3 and N = 2; and Fig. 5 is a block diagram illustrating another embodi~ent of ~he present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
. . . _ Fig. 1 illustrates in block form an embodiment of the pattern synchronizing circui~ according to the present invention. High-speed data HD, which is a repetition of an ML sequence having a pattern length of t2n-1) bits, is provided via a digital transmission sys~em (not shown~ to a terminal 11 and is demultiplexed by a demultiplexer 15 into N parallel sequences of low-speed data on N output lines 1 to N. In this instance, the N may assume an arbitrary value which is N = 2 (where a is an integer equal to or greater than 1~.
High-speed clocks HCL are being applied to a terminal . - ..
2 ~ 3 12 in synchronization with the high-speed input data HD.
The high-speed clock HCL is applied to a pre-clock elimina~or 13, which normally outpu~s it intact but~
when supplied with one clock pulse eliminating signal CT2, eliminates one clock pulse as described later on.
The output clock FCL from the pre-clock eliminator 13 is divided by a divider 14 down to 1/N. The demultiplexer 15 operates as a serial-parallel converter and repeats operations of fetching the high-speed input data HD of N consecutive bits in synchronization with N clock pulses HCL and outputting them in parallel in synchroniæation with one divided clock DCL. Thus the high-speed input data HD is converted to N parallel sequences of low-speed data LDl to LD~ under control of the clock HCL from the terminal 12 and the clock DCL from the divider 14 as referred to above.
Fig. 2A shows the high-speed input data HD
(error-free) which is a repetition of an ML sequence "1001011" of a (23-1) = 7 bit length and the output line 20 number i (i = 1, 2, , N) to which is allocated each bit of the high-speed input data HD when it is demultiplexed to N = four parallel sequences of low-speed data LD1, LD2, LD3 and LD4, and Fig. 2B tabulates the demultiplexed low-speed data LD, through LD4. In the case where the allocation of the high-speed data bits is to the output lines is in the order of i = 1, 21 3i 4 the low-speed data LD1 through LD4 sequentially advance in phase by two bits as indicated by and asterisk~ put against the leading bit of each arbitrarily selected repetitive 7-bit pattern "1100101" in Fig. 2B. Now, assuming that the high-speed clock HCL is skipped one clock by the pre-clock eliminator 13 at the bit position indicated by a cross x in the hLgh-speed input data HD
2 ~
depicted in Fi~. 2A, the output clock DCL from the divider 14 is delayed for a quarter period (corresponding to one bit of the high-speed input data HD), accordingly the positions of the four consecutive bits, which are demultiple~ed, la~ one bit as indicated by the broken line frame ~F in Fig. 2~. As a result of this, thereafter, the sequences o~ low-speed data LD" LD2, LD3 and LD~
on the output lines 1, 2, 3 and 4 shown in Fig. 2B shift to the output lines 4, 1, 2 and 3, respectively, as indicated by the arrows. That is, the sequences of low-speed data on all the output lines shift by one line position upon each elimination of one clock pulse of the high-speed clock ~CL which is applied to the demultiplexer 15. The sequences of low-speed data on the output lines i = 1, 2, 3, 4 after shifting sequentially advance in phase by two bits as they were before shiftin~ and the sequence of low-speed data on the output line 4 is most adva~ced in phase. Incidentally, when the allocation of each consecutive four bits of the high-speed input data HD in Fi~. 2A to the output lines is in the order of i = 4, 3, 2, 1, opposite to the afore-mentioned order, the line positions of the sequences o~ low-speed data LDl, LD2, LD3 and LD~ shown in Fig. 2B would be on the line positions o~ i = 4, 3, 2 and 1 respectively, and the low-speed data LD4 on the output line 1 would become most advanced in phase. At any rate, the sequence of low-speed data of the most advanced phase is an Nth sequence of low-speed data which is composed of data of every Nth bits contained in each consecutive N-bit data which is demultlplexed by the demultiplexer 15 into N sequences and is output upon each occurrence of the divided clock DCL.
The clocks DCL from the divider 1LI are applied to Q post-clock ellminator 16, which normally outputs them 9 2~ 3 intact but, when supplied with one cloc~ eiliminating signal CTl, eliminates one of the divided clocks DCL.
Based on the divided clock RCL from the post-clock eliminator 16, a reference pattern generator 17 generates N parallel sequences of reference patterns RP1 through RP N' The reference patterns RPl to RP N sequentially advance in phase by a fixed number of bits and are common in frequency as is the case with the error-free low-speed data LDl to LDN. (N-1) selectors 18, to 18N l are provided for switching between the low-speed data LDN f the most advanced phase in the output of the de-multiplexer 15 and the other sequences of low-speed da~a LD1 through LDN l. The (N-1) parallel sequences of low-speed data DX1 to DXN_1 which are the outputs from the (N -1) selectors 181 to 18N_~ and the low-speed data ~DN
of the most advanced phase are provided to N comparators 191 to 1 9N for comparison with the N parallel sequences of reference patterns RP1 ~o RPN' A counter 21 counts the number of clocks RCL from the post-clock eliminator 16 and is reset by the clock pulse eliminating signal CT1 as described later on.
A synchronizing operation start signal SS to a terminal 22, the outputs of the comparators 191 to 1 9N~ :
the output of the counter ~1, ect. are applied to a control circuit ~3. The control circuit 23 outputs a select signal SC and, when predetermined conditions are satisfied, genera~es the clock pulse eliminating signals CT1 and CT2 and a synchronization completion signal S0.
The select sign~l SC is applied to the selectors 18 through 1 8N -1 to cause each of them to select the one or the other input thereto, depending on whether the - select signal SC is high- of low-level. When supplied with the clock pulse eliminating signal CTl, the post-:, . :
. . . .
.
~3~3 clock eliminator 16 eliminates one clock pulse from the input clock DCL, in consequence of` which the reference patterns RPI through RPN respectively iag in phase by one bi~. The clock pulse eliminating signal CTl is applied as a reset signal to the counter 21. When supp]ied with the second clock pulse eliminating signal CT2, the pre-clock eliminator 13 eliminates one clock pulse from the high-speed clock HCL, in consequence of which the output clock DCL of the divider 14 is delayed for the l/N period as mentioned previously; hence, the positions for demultiplexing to the N sequences thereafter shift one by one.
When supplied with the synchronizing operation start signal SS, the control circuit 23 controls, by the select signal SC, the selectors 1 al through 1 8N -1 to select the low-speed data LDN of the most advanced phase.
Accordingly? the N parallel sequences of reference patterns RPl through RPN from the reference pattern generator 17 are all compared with the low-speed data LDN of the most advanced phase. When supplied with the synchronizing operation start signal SS, the control circuit 23 outputs the first clock pulse eliminating signal CTl and~ at the same time, enters the disagreement detection starting state. A~ter this, whenever a disagreement has been detected by every one of the comparators 191 to 19N at least once, the control circuit 23 produces the clock pulse eliminating signal CTl and is reset itsel~ to the disagreement detection starting state. When supplied with the clock pulse eliminating signal CTl from the control circuit 23, the post-clock eliminator 16 eliminates one clock pulse from the divided clock DGL, accordingly the phases of generation of the reference patterns RP1 through RPN by 2~3~3 the reference generator 17 are delayed one bit behind the low-speed data LD~. The signal CTl also resets the counter 21.
When the high-speed input data HD to the terminal S ll is the ML sequence as mentioned previously, each of the N parallel sequences of low-speed data LDl to LDN
also becomes an ML sequence. These ~ parallel sequences of low-speed data LD1 to LDN are sequentially displaced nearly l/N of the pattern period apart in phase. For example, when the ML sequence "1001011" (23-1) = 7 bits long is demultiplexed to two parallel sequences tN = 2), the one is ahead of the other in phase by four bits (or the latter is ahead of the former by three bits). When the above-mentioned ML sequence is demultiplexed to four parallel sequences (N = 4) 7 the demultiplexed sequences sequentially advance in phase by two bits (2/7~ 1/4). The same is true of the reference pattern generator 17. The N parallel sequences of reference patterns RPl to RPN are ML sequences which sequentially advance in phase by approximately 1/N of the pattern period. Accordingly, the low-speed data LDN of the most advanced phase and the N parallel sequences of reference patterns RPl to RPN are compared by the comparators 19l to 19N~ respectively, and whenever a disagreement has been detected by every one of the comparators at least once, the operations of delayin~
the generation of each of the reference patterns RPl to RPN by one bit and resetting the control circuit 23 to the disagreement detection starting state are repeated~ by which any one of the N parallel sequences of reference patterns matches the low~speed data LDN of the most advanced phase within a period of time nearly equal to l/N of the re~erence pattern period at the longest.
; ~
' ' :
~3~
This decision of the pattern matching is made when the agreement is detected for n consecutive bits, if the number of bits of one period of the reference pattern is 2n-1 bits. When the pattern match is detected, the control circuit 23 applies the clock pulse eliminating signal CT2 to the pre-clock eliminator 13 a required number of times, by which the line position of the sequence of low-speed data which has been of the most advanced phase is moved to the same line position as that of the reference pattern found to match it. In other words, when the i-th sequence of reference pattern on the i-th output line is found to match the low-speed data of the most advanced phase on the N-th output line, (N-i) clock pulses are eliminated by the pre-clock eliminator 13 from the high-speed clock HCL, by which the N parallel sequences o~ low-speed data are brought into synchronization with the N parallel sequences of reference patterns. Following this~ the selectors 18 to 18~ 1 are controlled to select the low-speed data on the output lines 1 to N-1 corresponding to them, respectively, to count the numbers of disagreements (i.
e. errors) detected by the comparators 191 to 1 9N i by which the error rate of the transmission system is measured.
Fig. 3A illustrates in block form specific operative examples of the demultiplexer 15, the pre-clock eliminator 13 and the selector 181 in the case where N =
2. The demultiplexer 15 comprises four flip-flops 15A
to 15D and it fetches 1-bit data of the high-speed input data HD into the flip-flop 15A in synchronization with one clock pulse of the high-speed clock HCL and fetches the data from the flip-flop 15A into the flip-flop 15B
in synchronization with the next clock pulse of the clock ' ' : -'' 13 2~l~3~ ~3 HCL and, at the same time, fetches the next bit data of the high-speed input data HD into the flip-flop 15A.
The contents of the flip-flops 15A and 15B are fetched by the output clock DCL of the divider 14 into the flip-flops 15D and 15C, respectively. By repeating the above-said two-clock HCL operation, the high-speed lnput data HD is demultiplexed into two parallel sequences of low-speed data LD, and LDN. The selector 181 comprises gates 18A, 18B and 18C. When the select signal SC is high-level, the ga~e 18A is enabled, by which the output LDNof the flip-flop 15D is selected, and when the select signal SC is low-level, the gate 18B is enabled, by which the output LDl of the flip-flop 15C is selected.
The pre-clock eliminator 13 comprises a cascade connection of flip-flops 13A and 13B and gates 13C and 13D. Normally, the output of the gate 13C is high-level and the high-speed clock HCL passes through the gate 13D.
When the high-level of the clock pulse eliminating signal CT2 is applied to the flip-flop 13A, a high-level input is fetched khereinto by a clock pu].se of the high-speed clock HCL, its Q output goes hi~h on the trailing edge of the clock HCL 9 the high-level Q output is fetched by the next clock pulse of the clock HCL into the flip-~lop 13B, and its Q output goes high on the trailing edge of the clock HCL. Consequently, when the high-level of the clock pulse eliminating signal CT2 is rea~ by the first clock HCL into the flip-flop 13A, its q output goes low and, until the Q output of the ~lipflop 13B goes high on the trailing edge o~ the second clock HCL, the output of the gate 13C remains low and hence the gate 13D is held disabled and inhibits the passage therethrough of the : second clock HCL. The divider lLI is formed by a flip-flop and frequency-divides the output clock FCL from ' ' ' '' ., , ' ' ' ' ' :
2~3~3 the pre-clock eliminator 13 into one half the ~requency.
When one clock pulse is eliminated ~rom the output clock FCL, khe divided output DCL is delayed ~or a one-half period. The post-clock eliminator 16 in Fig. 1 is exactly identical in construction with the pre-clock eliminator 13, and hence is not shown.
Fig. 3B illustrates a specific operative example of the control circuit 23 in Fig. 1. The synchronizing operation start signal SS resets ~lip-flops 23A, 23B and 23C via a gate OR and, at the same time, it is output as the clock pulse eliminating signal CTl, which resets the counter 21 which forms a l/n divider. By this, the control circuit 23 is placed in the disagreement detection starting state. The flip-flop 23A reset by the signal SS
outputs, as the select signal SC, its q output having gone high and, at the same time, it enables a gate AND3 and resets an encoder 23D and a counter 23E. Consequently, gates ANDl and AND2 are enabled thereafter upon each occurrence of the clock RCL.
When supplied with a disagreement output (high-level) from the comparator 19N via the gate AND2, the flip-flop 23C is triggered and a high level H provided to its data terminal D is read khereinto, then its q output goes low. Next,~when supplied with a disagreement output from the comparator 191, the Plip-flop 23B is triggered and a high level is read thereinto and its q output also goes low. As a result of this, the output of a gate NOR goes high and this high-level output is provided as the clock pulse eliminating signal CTl via the gate OR. At the same time, the high-level output of the gate NOR is applied to the flip-flops 23A, 23B and 23C, thus resetting the control circuit 23 again to the ; disagreement detection starting state. The operations ;, .~, ~3~3 described above are also performed when the comparator 19~ produces the disagreement output earlier than the comparator 1 9N and when the both comparators 191 and 1 9N simultaneously produce the disagreement outputs.
The counter 21 starts counting of clock pulses of the clock RCL from zero each time it is reset. The count value of the counter 21 represents the number of bits for which either one of the comparators 191 and 1 9N iS not continuously providin3 disagreement outputs (i. e. providing agreement outputs), and when the count value reaches n = 3 bits, the counter 21 generates a high-level output. In an ML sequence of the (23-1) bit length, all sequences of three or more successi~e bits differ one another; so that the count value "3" of the counter 21 means establishment of synchronization between one of the reference patterns RP1 and RPN and the low-speed date LDN in either one of the comparators 191 and 1 9N . The hi~h-level output of the counter 2~ tri~gers the flip-flop 23A, making its q output low and its Q
output high. Accordingly, the gates AND1, AND2 and AND3 are disabled, the select signal SC goes low and a gate AND5 is enabled.
Since the one o~ the flip-flops 23B and 23C, which corresponds to the comparator 191 or 19N having provided the a~reement output (L-level) ~or three bits in succession, remains in the reset state, its Q output remains low and the Q output of the other flip-flop remains high (The two reference patterns RP1 and RPN
cannot simultaneously be synchronized with the low-speed da~a LDl). The Q outputs of the flip-flops 238 and 23C
are applied to input terminals Dl and D2 of the encoder 23D and encoded into the number of clock pulse eliminating signals CT2 to be output, depending upon which input ' ;; - . : ' , : . - . : ~
,:,;, ' - '. :
., ' ' ~ .
terminal is supplied with the high-level Q output. For instance, when the comparator 1 9N yields the agreement outpu-t for three successive bits, it means that the low-speed data LDN and the reference pattern RPN have been synchronized with each other. Consequently, the low-speed data LDl and the reference pattern RP, also ought to have been synchroni~ed with each other and no clock pulse eliminating signals CT2 need to be output. In other words, the encoder 23D is so designed as to output "OO"
when the pieces of data which are provided to the input terminals D1 and D2 are "l" and "O", respectively.
On the contrary, when the comparator 191 yields the agreement output for three successive bits, it means that the low-speed data LD~ and the reference pattern RP1 have been synchronized with each other, and consequently, the low-speed data LD1 and the reference pattern RP~ are not synchronized with each other.
Accordingly, the clock pulse eliminating signal CT2 needs to be Benerated once to move the line position of 20 low-speed data LD~ to the line position o~ low-speed data LD1. When the pieces of data to the input terminals D1 and D2 Of the encoder 23D are "O" and "l", respectively, the encoder 23D outputs "Ol". The clock RCL is provided via a gate AND4 to the counter 23~ for counting and at the same time it is out;put as the clock pulse eliminating signal CT2 from the gate AND4. The count value of the counter 23E and the output o~ the encoder 23D are applied to a match detector 23F. The match detector 23F generates a high-level output when the count value of the counter 30 23E and the output of the encoder 23D do not match each other and also generates a low-level output when they match each other. Accordingly, in the aboYe example1 when one clock pulse RCL passes through the gate AND4 17 2 ~ 3 and the c~unt value of the counter 23E goes to "01", the match detector 23F produces a low-level output, by which the gate ANDLI is disabled, and at the same time, the synchroniza~ion completion signal SO is provided from the gate AND5.
Fig. 4 shows an example of the operation o~ the pattern synchronizing circuit of the present invention in the case where N = 2 and one period oP the reference pattern is 23-1 (n=3) bits long as in the cases of Figs.
3A and 3B. When sùpplied with the synchronizing operation start signal SS from the terminal 22, the control circuit controls the selector 181 by the select signal SC, to set it so as to select the low-speed data LDN.
Consequently, the comparators 191 and 19~ are supplied at one input with the low-speed data LDN, which is compared with the reference patterns RP1 and RPN on a bitwise basis. In Fig. 4 the agreement between them is indicated by a small circle at the right-hand end of the bit of the reference pattern concerned and the mismatch by a small cross at the right-hand end of the bit of the reference pattern concerned. The control circuit 23 responds to the synchronizing operation start signal SS to output a first shot of the clock pulse eliminating signal CT1 and reset its internal circuits to the disagreement detection starting state. When either of the comparators 191 and 1 9N outputs a disagreement signal at least once, the control circuit , 23 outputs the clock pulse eliminating signal CT1, by which one clock pulse oP the input clock RCL of the reference pattern generator 17 is eliminated as indicated by the broken line. On this account, the reference patterns RP1 and RPN are caused to retain the same data for a two-clock time duration. That is, :
3 ~ ~ ~
the reference patterns RP1 and RP~ are each delayed in phase by one bit. In the example shown in Fig. 4, the one-bit delay by such a disagreement detection is shown to be repeated twice. Next, when either one of the comparators 191 and 19~ obtains an agreement output for three consecutive bits, the count value of the counter 21 goes to "3" at a time point tl; so that the clock pulse eliminating signal CT2 is provided from the control circuit 23, and immediately thereafter, one clock pulse is eliminated by the pre-clock eliminator 13 from the clock FCL which is supplied to the divider 14, as indicated by the broken line. As a result o~ this, the clock DCL from the divider 14 and the clock RCL from the post-clock eliminator 16 are each composed of two consecutive pulses. In the example of Fig. 4, the phases of the low-speed data LD1 and LDN are exchanged so that a bit HDa in the high-speed input data HD to be demultiplexed into the low-speed data LD1 is skipped over but instead the next bit HDb is demultiplexed thereinto as indicated by the arrows. In consequence, the low-speed data LD1 and LDN and the reference patterns RP1 and RPN are synchronized with each other, respectively7 and the control circuit 23 generates the synchroni~ation completion si~nal SO, af~er which the selector 181 is placed in a state in which to select the low-speed data LD1. The numbers of disa~reements in the compared outputs provided to output terminals 25~ and 25N of the comparators 191 and 19N are counted by a device (not shown~, by which the error rate can be obtained. If comparators for obtaining the error rate are provided separately of the comparators 191 through 1 9N depicted in Fig. 1, then the selectors 181 through 1 8N _ 1 will be unnecessary and the low-speed data LDN will be provided 19 2~3~3 direc~ly to the comparators 191 khrough 1 9N .
The embodiment,of the pat~,ern synchronizing circuit of the present invention depicted in ~ig. 1 is constructed so that during the synchronizing operation the low-speed data LDN is compared with each of the reference patterns RP1 through RPN~ In the Fig. 4 , example of the operation of the pattern synchronizing circuit, assuming that during the synchronizing operation the high-speed input data HD contains errors with a particular period and that errors are unevenly distributed in the low-speed data LDN from the demultiplexer 15; accordingly, it is dif~icult to synchronize the low-speed data LDN with either one of the re~erence patterns RPl and RP. N . In general, in the case where during the synchronizing operation the high-speed input data HD contains errors with a particular period and errors are unevenly distributed in that particular one of the low-speed data LD, through LDN
which is selected by the (N-1) selectors 181 through 1 8N - 1, it may sometimes be impossible to synchronize the selected one of'the low-speed data LD1 through LD~ with the reference patterns RP1 through RPN. Fig. 5 illustrates another embodiment of the present invention which obviates such a defect. ~' The FiB. 5 embodiment is identical in construction with the Fig. 1 embodiment except the provision o~ a counter 24 and an OR gate 26. The counter 24 is reset by the synchronizing operation start signal SS applied ` ' to the control circuit 23, and it counts the number of clock pulse eliminating signals CT1 which are applied to ,~
the post-clock eliminator'16 and generates a high~level ,' .
output when its count value reaches a predetermined value M. The high-level output is combined by the OR
,. .
.
~3~3~0~
gate 26 wi~h the output o~ the gate AND~ in Fig. 3B and applied as the clock pulse eliminatin6 signal CT2 to the pre-clock eliminator 13 via the OR gate 26. The value M
to be set in the counter 24 is selected to be the smallest inte~er greater than (2n-1)/N, for example, and in the case where n = 3 and N = 2, the value M is set to 4.
When the value n is large, it does not essentially matters even if the value M is set to an integer either above or below (2n~ N, but close thereto.
During the synchronizin~ operation the low-speed data LDN is output as low-speed output data DX1 to DXN-1 o~ the selectors 181 to 1 8N _ 1 and it is determined in the comparators 191 to 19N whether or not the low-speed data LDN matches the reference patterns RP1 to RPN, respectively. In the case where the high-speed input data HD contains errors with a particular period and errors are unevenly distributed in the low-speed data LDN, a state of generating the clock pulse eliminating signal CT1 at least once occurs in any n consecutive bits, and in this instance, no synchronization can be established as long as the errors are unevenly distributed.
The counter 24 counts the number of pulses of the clock pulse eliminating signal CT1, and when its count value goes to M, the control circuit 23 ~enerates the clock pulse eliminatin~ si~nal CT2. Immediately thereafter one clock pulse is eliminated by the pre-clock eliminator 13 from the clock FCL which is applied to the divider 14, by which the line positions o~ low-speed data LD1 to LDN are sequentially shifted by one line position in the demultiplexer 15. As a result of this, errors are une~enly distributed in the sequence of low-speed data LDN 1; SO that no error are evenly distrlbuted in the low-speed data LDN of the most , .
advanced phase after the line position shift selected by the selectors 181 to 18N-1. This ensures synchronization of the low-speed data LD1 to LDN and the reference patterns RP1 to RP~ by the synchronizin~
operation as is the case with the Fig. 1 embodiment.
As described above, according to the present invention, that one of N demultiplexed sequences of low-speed data which has the most advanced phase is compared with each of N parallel sequences of reference patterns and is synchronized with that one of the reference patterns whose phase is the closest thereto and line positions of the N parallel sequences of low-speed data are cyclically shifted in one direction so that the line position of the sequence of low-speed data of the most advanced phase is moved to the line position of the sequence of reference pattern of the closest phase.
Hence, the synchronization can be established within a time 1/N of the reference pattern period in the worst case.
It will be apparent that many modifications and variations may be effected without departing from the scope of the novel concepts of the present invention.
~:
.. . .
.
PATTE~N SYNCHRONIZING CIRCUIT
BACKGROUND OF THE INVENTION
The present invention relates to a pattern synchronizing circuit which is used~ for example, in measurement of the error rate of a digital signal transmission system, for synchronizing a reference pattern generator with input test data (a pseudo random pattern) prior to the measurement. More particularly, the invention pertains to a demultiplexed pattern synchronizing circuit whereby parallel sequences of input data obtained by demultiplexing a high-speed pseudo random pattern are synchronized with parallel sequences of reference patterns.
In the case of measuring the transmission error rate of a digital signal transmission system, a measurement pattern formed by a repetition of a certain pattern of a predetermined bit length is pro~ided from 2 pattern generator to the digital transmission system at the transmitting side thereof. At the receiving side of the digital transmission system the same pattern as the measurement pattern at the transmission side is 8enerated as a reference pattern and compared, bit by bit, with an input pattern provided through the transmission system and containing errors, by which the errors in the input pattern are detected, and the number of errors per unit bit is counted. It is customary to use, as the measurement pattern, a pseudo random pattern9 usuaLly a repetitive pattern of a maximum length linear shift register sequence of a (2n-1)-bit length. The bit length of a non-repetitive or random maximum length pattern9 obtainable with an n-stage shift register, is 2n-1, and such a pattern is called a - .
2 2~38~3 maximum length linear shift register sequences. It is well-known in the art that the pseudo random pattern, which is a repetition o~ such a pattern, has a feature in that a sequence of bits extracted therefrom every N =
2~ (where a is an integer equal to or greater than 1) bit positions starting at an arbitrary bit position cons~itutes the same pattern as the original pseudo random pattern.
In the case of measuring the error rate of a transmission system when a digital signal is provided thereto at a high speed, it is difficult to implement a high-speed comparator which is able to compare the input pattern with the reference pattern on a bitwise basis at the receiving side. A conventional solution to this problem, which takes advanta~e of the above-mentioned feature of the maximum length linear shift register sequence (hereinafter referred to as ML sequence), is to divide the inpu~ pattern, bit by bit, into N = 2~ parallel sequences on N lines, that is, demultiplex the input pattern into N parallel sequences of low-speed data at the receiving sideO In this instance, if the received pattern is error-free, the N = 20 parallel sequences of low-speed data each form the same pattern as the high-speed pseudo random pattern for measurement use generated at the transmitting side and they are sequentially displaced a ~ixed number of bits (about l/N of the pattern period) apart in phase. Accordingly, similar N
parallel sequences of low-speed patterns are generated as reference patterns at the receiving side and are respectively compared with the demultiplexed N parallel sequences o~ low-speed data, by which the error rate of the digital transmission system can be measured. For correct measurement of the error rate, however, it is 2~38~3 necessary to establish synchronization between the N
demultiplexed parallel sequences of low-speed data and the N parallel sequences of reference patterns so that they are in phase with each other.
Such a demultiplexed pattern synchronizing circuit is disclosed in U. S. Patent No. 4,878,233. This U. S.
patent shows the case where high-speed input data is demultiplexed, by use o~ a high-speed clock synchronized there~ith, into four parallel sequences of low-speed data on four output lines for comparison with four parallel se~uences of reference patterns by four comparators. The four parallel sequences of reference patterns are each eenerated in synchronization with a low-speed clock obtained by frequency dividing the above-said high-speed clock down to 1/4. The number of disagreements in the results of comparison by the four comparators is counted, and when the count value exceeds a predetermined value, it is decided that the four parallel sequences o~ low-speed data and the four parallel sequences of reference patterns are not synchronized with each other. Thereafter, upon each counting of a predetermined number of disagreements, one of the low-speed clocks for generating the reference patterns is eliminated, by which the four parallel sequences of reference patterns are all delayed by one bit relative to corresponding four parallel sequences of low-speed data. The one-bit delay of the reference patterns is repeated until the four parallel sequences of reference patterns are synchronized with the four parallel sequences of low-speed data.
WLth the demultiplexed pattern synchronizing circuit set forth in the above-mentioned ~. S. patent, however, no synchronization can be established, in the .. ~. ' ~ , ' ., ~
' 2~3~3 worst case, until the reference pa~tern is delayed for a period of time equal to the len~th of the ML sequence minus one blt, i. e. (2a l )~l bit (which is approximately one reference pattern period in practice, because n is selected equal to or ~reater than 4). In addition, the time length of 2~-1 bits in the reference pattern (or low-speed data) is equal to the time length of 4x (2-1 ) bits in the high-speed input data, and this corresponds to approximately f`our periods of the maximum len~th linear shift register sequence which is repeated in the high-speed input data. In other words, about four periods of the high-speed pattern for measurement are consumed merely for synchronization, not for measurement of the error rate--this impairs the efficiency of measurement of the error rate. Recently, in particular, a high-speed digital transmission in the gigahertz band for optical communication has come into -use, and the pattern for measuring the error rate o~ such a high-speed digital transmission system is required to be large in the bit length of one pattern period.
F'or example, in the case where the number of-bits o~ one period of the ML sequence of the high-speed pattern data for measurement is 223-1, the frequency f is 2 GHz and the number N of parallel sequences of low-speed data is 16s then one period of the reference pattern becomes around 67 milliseconds. In the case where the number of bits of one period o~ the ML sequence iS 23 1 -l, the frequency f is 2 GHz and the number N is 16, one period of the reference pattern becomes about 17 seconds. Thus, when the bit length of one period of the measurement pattern (high-speed input data) is as lar~e as 231-l (~ 2.15x 109) bits, the time for synchronization is 17 seconds at maximum and hence is 2~3~3 impractical.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a demultiplexed pattern synchronizing circuit with which it is possible to synchronize a reference pattern with input data in a short time.
According to the present invention, high-speed input data is demultiplexed by demultiplexer, in synchronization with a high-speed clock, into N parallel sequences of low-speed data on N output lines and N
parallel sequences of reference patterns are generated by a pattern generator in synchronization with frequency-divided clocks obtained by frequency dividing the high-speed clock down to 1/N. Then an Nth sequence of low-speed data, composed of data of every Nth bits of the N-bit data which is provided from the demultiplexer upon each occurrence of the divided clock, is compared by N comparators with the N parallel sequences of reference patterns from the reference pattern generator.
A control circuit skarts to detect disagreements in the comparator outputs and, when every one of the N
comparators has yielded the disagreement output at least once, generates a first clock pulse eliminating signal to eliminate one clock pulse from the divided clock input into the reference pattern generator and is reset to the disagreement detection starting state. When any one of the N parallel sequences of reference patterns agrees the low-speed data at least n times in succession, second clock pulse eliminatin~ signal is Benerated the number of times corresponding to the difference in output line position between the sequence of the matching reference pattern and the above-mentioned Nth sequence of low-speed data to eliminate, by the same number as , ' . ''`''' ..
.. ~. .
2 ~ c~
the second clock pulse eliminating signals, clock pulses of the high-speed clock which is applied to the demultiplexer. By this, the output line position of the Nth parallel sequence of low-speed data in the demultiplexer is shifted to the output line position of the sequence of matching reference patterns.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram illustrating an embodiment of the pattern synchronizing circuit according to the present invention;
Fig. 2A is a diagram for explaining demultiplexing;
Fi8. 2B is a diagram for explaining demultiplexing;
Fig. 3A is a circuit diagram showing a specific operative example of a portion of Fig. 1;
Fig. 3B is a circuit diagram showing a specific operative example of a control circuit in Fig. 1;
Fig. 4 is a timing chart showing the operation o~ the pattern synchronizing circuit of Fig. 1 in the case where n = 3 and N = 2; and Fig. 5 is a block diagram illustrating another embodi~ent of ~he present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
. . . _ Fig. 1 illustrates in block form an embodiment of the pattern synchronizing circui~ according to the present invention. High-speed data HD, which is a repetition of an ML sequence having a pattern length of t2n-1) bits, is provided via a digital transmission sys~em (not shown~ to a terminal 11 and is demultiplexed by a demultiplexer 15 into N parallel sequences of low-speed data on N output lines 1 to N. In this instance, the N may assume an arbitrary value which is N = 2 (where a is an integer equal to or greater than 1~.
High-speed clocks HCL are being applied to a terminal . - ..
2 ~ 3 12 in synchronization with the high-speed input data HD.
The high-speed clock HCL is applied to a pre-clock elimina~or 13, which normally outpu~s it intact but~
when supplied with one clock pulse eliminating signal CT2, eliminates one clock pulse as described later on.
The output clock FCL from the pre-clock eliminator 13 is divided by a divider 14 down to 1/N. The demultiplexer 15 operates as a serial-parallel converter and repeats operations of fetching the high-speed input data HD of N consecutive bits in synchronization with N clock pulses HCL and outputting them in parallel in synchroniæation with one divided clock DCL. Thus the high-speed input data HD is converted to N parallel sequences of low-speed data LDl to LD~ under control of the clock HCL from the terminal 12 and the clock DCL from the divider 14 as referred to above.
Fig. 2A shows the high-speed input data HD
(error-free) which is a repetition of an ML sequence "1001011" of a (23-1) = 7 bit length and the output line 20 number i (i = 1, 2, , N) to which is allocated each bit of the high-speed input data HD when it is demultiplexed to N = four parallel sequences of low-speed data LD1, LD2, LD3 and LD4, and Fig. 2B tabulates the demultiplexed low-speed data LD, through LD4. In the case where the allocation of the high-speed data bits is to the output lines is in the order of i = 1, 21 3i 4 the low-speed data LD1 through LD4 sequentially advance in phase by two bits as indicated by and asterisk~ put against the leading bit of each arbitrarily selected repetitive 7-bit pattern "1100101" in Fig. 2B. Now, assuming that the high-speed clock HCL is skipped one clock by the pre-clock eliminator 13 at the bit position indicated by a cross x in the hLgh-speed input data HD
2 ~
depicted in Fi~. 2A, the output clock DCL from the divider 14 is delayed for a quarter period (corresponding to one bit of the high-speed input data HD), accordingly the positions of the four consecutive bits, which are demultiple~ed, la~ one bit as indicated by the broken line frame ~F in Fig. 2~. As a result of this, thereafter, the sequences o~ low-speed data LD" LD2, LD3 and LD~
on the output lines 1, 2, 3 and 4 shown in Fig. 2B shift to the output lines 4, 1, 2 and 3, respectively, as indicated by the arrows. That is, the sequences of low-speed data on all the output lines shift by one line position upon each elimination of one clock pulse of the high-speed clock ~CL which is applied to the demultiplexer 15. The sequences of low-speed data on the output lines i = 1, 2, 3, 4 after shifting sequentially advance in phase by two bits as they were before shiftin~ and the sequence of low-speed data on the output line 4 is most adva~ced in phase. Incidentally, when the allocation of each consecutive four bits of the high-speed input data HD in Fi~. 2A to the output lines is in the order of i = 4, 3, 2, 1, opposite to the afore-mentioned order, the line positions of the sequences o~ low-speed data LDl, LD2, LD3 and LD~ shown in Fig. 2B would be on the line positions o~ i = 4, 3, 2 and 1 respectively, and the low-speed data LD4 on the output line 1 would become most advanced in phase. At any rate, the sequence of low-speed data of the most advanced phase is an Nth sequence of low-speed data which is composed of data of every Nth bits contained in each consecutive N-bit data which is demultlplexed by the demultiplexer 15 into N sequences and is output upon each occurrence of the divided clock DCL.
The clocks DCL from the divider 1LI are applied to Q post-clock ellminator 16, which normally outputs them 9 2~ 3 intact but, when supplied with one cloc~ eiliminating signal CTl, eliminates one of the divided clocks DCL.
Based on the divided clock RCL from the post-clock eliminator 16, a reference pattern generator 17 generates N parallel sequences of reference patterns RP1 through RP N' The reference patterns RPl to RP N sequentially advance in phase by a fixed number of bits and are common in frequency as is the case with the error-free low-speed data LDl to LDN. (N-1) selectors 18, to 18N l are provided for switching between the low-speed data LDN f the most advanced phase in the output of the de-multiplexer 15 and the other sequences of low-speed da~a LD1 through LDN l. The (N-1) parallel sequences of low-speed data DX1 to DXN_1 which are the outputs from the (N -1) selectors 181 to 18N_~ and the low-speed data ~DN
of the most advanced phase are provided to N comparators 191 to 1 9N for comparison with the N parallel sequences of reference patterns RP1 ~o RPN' A counter 21 counts the number of clocks RCL from the post-clock eliminator 16 and is reset by the clock pulse eliminating signal CT1 as described later on.
A synchronizing operation start signal SS to a terminal 22, the outputs of the comparators 191 to 1 9N~ :
the output of the counter ~1, ect. are applied to a control circuit ~3. The control circuit 23 outputs a select signal SC and, when predetermined conditions are satisfied, genera~es the clock pulse eliminating signals CT1 and CT2 and a synchronization completion signal S0.
The select sign~l SC is applied to the selectors 18 through 1 8N -1 to cause each of them to select the one or the other input thereto, depending on whether the - select signal SC is high- of low-level. When supplied with the clock pulse eliminating signal CTl, the post-:, . :
. . . .
.
~3~3 clock eliminator 16 eliminates one clock pulse from the input clock DCL, in consequence of` which the reference patterns RPI through RPN respectively iag in phase by one bi~. The clock pulse eliminating signal CTl is applied as a reset signal to the counter 21. When supp]ied with the second clock pulse eliminating signal CT2, the pre-clock eliminator 13 eliminates one clock pulse from the high-speed clock HCL, in consequence of which the output clock DCL of the divider 14 is delayed for the l/N period as mentioned previously; hence, the positions for demultiplexing to the N sequences thereafter shift one by one.
When supplied with the synchronizing operation start signal SS, the control circuit 23 controls, by the select signal SC, the selectors 1 al through 1 8N -1 to select the low-speed data LDN of the most advanced phase.
Accordingly? the N parallel sequences of reference patterns RPl through RPN from the reference pattern generator 17 are all compared with the low-speed data LDN of the most advanced phase. When supplied with the synchronizing operation start signal SS, the control circuit 23 outputs the first clock pulse eliminating signal CTl and~ at the same time, enters the disagreement detection starting state. A~ter this, whenever a disagreement has been detected by every one of the comparators 191 to 19N at least once, the control circuit 23 produces the clock pulse eliminating signal CTl and is reset itsel~ to the disagreement detection starting state. When supplied with the clock pulse eliminating signal CTl from the control circuit 23, the post-clock eliminator 16 eliminates one clock pulse from the divided clock DGL, accordingly the phases of generation of the reference patterns RP1 through RPN by 2~3~3 the reference generator 17 are delayed one bit behind the low-speed data LD~. The signal CTl also resets the counter 21.
When the high-speed input data HD to the terminal S ll is the ML sequence as mentioned previously, each of the N parallel sequences of low-speed data LDl to LDN
also becomes an ML sequence. These ~ parallel sequences of low-speed data LD1 to LDN are sequentially displaced nearly l/N of the pattern period apart in phase. For example, when the ML sequence "1001011" (23-1) = 7 bits long is demultiplexed to two parallel sequences tN = 2), the one is ahead of the other in phase by four bits (or the latter is ahead of the former by three bits). When the above-mentioned ML sequence is demultiplexed to four parallel sequences (N = 4) 7 the demultiplexed sequences sequentially advance in phase by two bits (2/7~ 1/4). The same is true of the reference pattern generator 17. The N parallel sequences of reference patterns RPl to RPN are ML sequences which sequentially advance in phase by approximately 1/N of the pattern period. Accordingly, the low-speed data LDN of the most advanced phase and the N parallel sequences of reference patterns RPl to RPN are compared by the comparators 19l to 19N~ respectively, and whenever a disagreement has been detected by every one of the comparators at least once, the operations of delayin~
the generation of each of the reference patterns RPl to RPN by one bit and resetting the control circuit 23 to the disagreement detection starting state are repeated~ by which any one of the N parallel sequences of reference patterns matches the low~speed data LDN of the most advanced phase within a period of time nearly equal to l/N of the re~erence pattern period at the longest.
; ~
' ' :
~3~
This decision of the pattern matching is made when the agreement is detected for n consecutive bits, if the number of bits of one period of the reference pattern is 2n-1 bits. When the pattern match is detected, the control circuit 23 applies the clock pulse eliminating signal CT2 to the pre-clock eliminator 13 a required number of times, by which the line position of the sequence of low-speed data which has been of the most advanced phase is moved to the same line position as that of the reference pattern found to match it. In other words, when the i-th sequence of reference pattern on the i-th output line is found to match the low-speed data of the most advanced phase on the N-th output line, (N-i) clock pulses are eliminated by the pre-clock eliminator 13 from the high-speed clock HCL, by which the N parallel sequences o~ low-speed data are brought into synchronization with the N parallel sequences of reference patterns. Following this~ the selectors 18 to 18~ 1 are controlled to select the low-speed data on the output lines 1 to N-1 corresponding to them, respectively, to count the numbers of disagreements (i.
e. errors) detected by the comparators 191 to 1 9N i by which the error rate of the transmission system is measured.
Fig. 3A illustrates in block form specific operative examples of the demultiplexer 15, the pre-clock eliminator 13 and the selector 181 in the case where N =
2. The demultiplexer 15 comprises four flip-flops 15A
to 15D and it fetches 1-bit data of the high-speed input data HD into the flip-flop 15A in synchronization with one clock pulse of the high-speed clock HCL and fetches the data from the flip-flop 15A into the flip-flop 15B
in synchronization with the next clock pulse of the clock ' ' : -'' 13 2~l~3~ ~3 HCL and, at the same time, fetches the next bit data of the high-speed input data HD into the flip-flop 15A.
The contents of the flip-flops 15A and 15B are fetched by the output clock DCL of the divider 14 into the flip-flops 15D and 15C, respectively. By repeating the above-said two-clock HCL operation, the high-speed lnput data HD is demultiplexed into two parallel sequences of low-speed data LD, and LDN. The selector 181 comprises gates 18A, 18B and 18C. When the select signal SC is high-level, the ga~e 18A is enabled, by which the output LDNof the flip-flop 15D is selected, and when the select signal SC is low-level, the gate 18B is enabled, by which the output LDl of the flip-flop 15C is selected.
The pre-clock eliminator 13 comprises a cascade connection of flip-flops 13A and 13B and gates 13C and 13D. Normally, the output of the gate 13C is high-level and the high-speed clock HCL passes through the gate 13D.
When the high-level of the clock pulse eliminating signal CT2 is applied to the flip-flop 13A, a high-level input is fetched khereinto by a clock pu].se of the high-speed clock HCL, its Q output goes hi~h on the trailing edge of the clock HCL 9 the high-level Q output is fetched by the next clock pulse of the clock HCL into the flip-~lop 13B, and its Q output goes high on the trailing edge of the clock HCL. Consequently, when the high-level of the clock pulse eliminating signal CT2 is rea~ by the first clock HCL into the flip-flop 13A, its q output goes low and, until the Q output of the ~lipflop 13B goes high on the trailing edge o~ the second clock HCL, the output of the gate 13C remains low and hence the gate 13D is held disabled and inhibits the passage therethrough of the : second clock HCL. The divider lLI is formed by a flip-flop and frequency-divides the output clock FCL from ' ' ' '' ., , ' ' ' ' ' :
2~3~3 the pre-clock eliminator 13 into one half the ~requency.
When one clock pulse is eliminated ~rom the output clock FCL, khe divided output DCL is delayed ~or a one-half period. The post-clock eliminator 16 in Fig. 1 is exactly identical in construction with the pre-clock eliminator 13, and hence is not shown.
Fig. 3B illustrates a specific operative example of the control circuit 23 in Fig. 1. The synchronizing operation start signal SS resets ~lip-flops 23A, 23B and 23C via a gate OR and, at the same time, it is output as the clock pulse eliminating signal CTl, which resets the counter 21 which forms a l/n divider. By this, the control circuit 23 is placed in the disagreement detection starting state. The flip-flop 23A reset by the signal SS
outputs, as the select signal SC, its q output having gone high and, at the same time, it enables a gate AND3 and resets an encoder 23D and a counter 23E. Consequently, gates ANDl and AND2 are enabled thereafter upon each occurrence of the clock RCL.
When supplied with a disagreement output (high-level) from the comparator 19N via the gate AND2, the flip-flop 23C is triggered and a high level H provided to its data terminal D is read khereinto, then its q output goes low. Next,~when supplied with a disagreement output from the comparator 191, the Plip-flop 23B is triggered and a high level is read thereinto and its q output also goes low. As a result of this, the output of a gate NOR goes high and this high-level output is provided as the clock pulse eliminating signal CTl via the gate OR. At the same time, the high-level output of the gate NOR is applied to the flip-flops 23A, 23B and 23C, thus resetting the control circuit 23 again to the ; disagreement detection starting state. The operations ;, .~, ~3~3 described above are also performed when the comparator 19~ produces the disagreement output earlier than the comparator 1 9N and when the both comparators 191 and 1 9N simultaneously produce the disagreement outputs.
The counter 21 starts counting of clock pulses of the clock RCL from zero each time it is reset. The count value of the counter 21 represents the number of bits for which either one of the comparators 191 and 1 9N iS not continuously providin3 disagreement outputs (i. e. providing agreement outputs), and when the count value reaches n = 3 bits, the counter 21 generates a high-level output. In an ML sequence of the (23-1) bit length, all sequences of three or more successi~e bits differ one another; so that the count value "3" of the counter 21 means establishment of synchronization between one of the reference patterns RP1 and RPN and the low-speed date LDN in either one of the comparators 191 and 1 9N . The hi~h-level output of the counter 2~ tri~gers the flip-flop 23A, making its q output low and its Q
output high. Accordingly, the gates AND1, AND2 and AND3 are disabled, the select signal SC goes low and a gate AND5 is enabled.
Since the one o~ the flip-flops 23B and 23C, which corresponds to the comparator 191 or 19N having provided the a~reement output (L-level) ~or three bits in succession, remains in the reset state, its Q output remains low and the Q output of the other flip-flop remains high (The two reference patterns RP1 and RPN
cannot simultaneously be synchronized with the low-speed da~a LDl). The Q outputs of the flip-flops 238 and 23C
are applied to input terminals Dl and D2 of the encoder 23D and encoded into the number of clock pulse eliminating signals CT2 to be output, depending upon which input ' ;; - . : ' , : . - . : ~
,:,;, ' - '. :
., ' ' ~ .
terminal is supplied with the high-level Q output. For instance, when the comparator 1 9N yields the agreement outpu-t for three successive bits, it means that the low-speed data LDN and the reference pattern RPN have been synchronized with each other. Consequently, the low-speed data LDl and the reference pattern RP, also ought to have been synchroni~ed with each other and no clock pulse eliminating signals CT2 need to be output. In other words, the encoder 23D is so designed as to output "OO"
when the pieces of data which are provided to the input terminals D1 and D2 are "l" and "O", respectively.
On the contrary, when the comparator 191 yields the agreement output for three successive bits, it means that the low-speed data LD~ and the reference pattern RP1 have been synchronized with each other, and consequently, the low-speed data LD1 and the reference pattern RP~ are not synchronized with each other.
Accordingly, the clock pulse eliminating signal CT2 needs to be Benerated once to move the line position of 20 low-speed data LD~ to the line position o~ low-speed data LD1. When the pieces of data to the input terminals D1 and D2 Of the encoder 23D are "O" and "l", respectively, the encoder 23D outputs "Ol". The clock RCL is provided via a gate AND4 to the counter 23~ for counting and at the same time it is out;put as the clock pulse eliminating signal CT2 from the gate AND4. The count value of the counter 23E and the output o~ the encoder 23D are applied to a match detector 23F. The match detector 23F generates a high-level output when the count value of the counter 30 23E and the output of the encoder 23D do not match each other and also generates a low-level output when they match each other. Accordingly, in the aboYe example1 when one clock pulse RCL passes through the gate AND4 17 2 ~ 3 and the c~unt value of the counter 23E goes to "01", the match detector 23F produces a low-level output, by which the gate ANDLI is disabled, and at the same time, the synchroniza~ion completion signal SO is provided from the gate AND5.
Fig. 4 shows an example of the operation o~ the pattern synchronizing circuit of the present invention in the case where N = 2 and one period oP the reference pattern is 23-1 (n=3) bits long as in the cases of Figs.
3A and 3B. When sùpplied with the synchronizing operation start signal SS from the terminal 22, the control circuit controls the selector 181 by the select signal SC, to set it so as to select the low-speed data LDN.
Consequently, the comparators 191 and 19~ are supplied at one input with the low-speed data LDN, which is compared with the reference patterns RP1 and RPN on a bitwise basis. In Fig. 4 the agreement between them is indicated by a small circle at the right-hand end of the bit of the reference pattern concerned and the mismatch by a small cross at the right-hand end of the bit of the reference pattern concerned. The control circuit 23 responds to the synchronizing operation start signal SS to output a first shot of the clock pulse eliminating signal CT1 and reset its internal circuits to the disagreement detection starting state. When either of the comparators 191 and 1 9N outputs a disagreement signal at least once, the control circuit , 23 outputs the clock pulse eliminating signal CT1, by which one clock pulse oP the input clock RCL of the reference pattern generator 17 is eliminated as indicated by the broken line. On this account, the reference patterns RP1 and RPN are caused to retain the same data for a two-clock time duration. That is, :
3 ~ ~ ~
the reference patterns RP1 and RP~ are each delayed in phase by one bit. In the example shown in Fig. 4, the one-bit delay by such a disagreement detection is shown to be repeated twice. Next, when either one of the comparators 191 and 19~ obtains an agreement output for three consecutive bits, the count value of the counter 21 goes to "3" at a time point tl; so that the clock pulse eliminating signal CT2 is provided from the control circuit 23, and immediately thereafter, one clock pulse is eliminated by the pre-clock eliminator 13 from the clock FCL which is supplied to the divider 14, as indicated by the broken line. As a result o~ this, the clock DCL from the divider 14 and the clock RCL from the post-clock eliminator 16 are each composed of two consecutive pulses. In the example of Fig. 4, the phases of the low-speed data LD1 and LDN are exchanged so that a bit HDa in the high-speed input data HD to be demultiplexed into the low-speed data LD1 is skipped over but instead the next bit HDb is demultiplexed thereinto as indicated by the arrows. In consequence, the low-speed data LD1 and LDN and the reference patterns RP1 and RPN are synchronized with each other, respectively7 and the control circuit 23 generates the synchroni~ation completion si~nal SO, af~er which the selector 181 is placed in a state in which to select the low-speed data LD1. The numbers of disa~reements in the compared outputs provided to output terminals 25~ and 25N of the comparators 191 and 19N are counted by a device (not shown~, by which the error rate can be obtained. If comparators for obtaining the error rate are provided separately of the comparators 191 through 1 9N depicted in Fig. 1, then the selectors 181 through 1 8N _ 1 will be unnecessary and the low-speed data LDN will be provided 19 2~3~3 direc~ly to the comparators 191 khrough 1 9N .
The embodiment,of the pat~,ern synchronizing circuit of the present invention depicted in ~ig. 1 is constructed so that during the synchronizing operation the low-speed data LDN is compared with each of the reference patterns RP1 through RPN~ In the Fig. 4 , example of the operation of the pattern synchronizing circuit, assuming that during the synchronizing operation the high-speed input data HD contains errors with a particular period and that errors are unevenly distributed in the low-speed data LDN from the demultiplexer 15; accordingly, it is dif~icult to synchronize the low-speed data LDN with either one of the re~erence patterns RPl and RP. N . In general, in the case where during the synchronizing operation the high-speed input data HD contains errors with a particular period and errors are unevenly distributed in that particular one of the low-speed data LD, through LDN
which is selected by the (N-1) selectors 181 through 1 8N - 1, it may sometimes be impossible to synchronize the selected one of'the low-speed data LD1 through LD~ with the reference patterns RP1 through RPN. Fig. 5 illustrates another embodiment of the present invention which obviates such a defect. ~' The FiB. 5 embodiment is identical in construction with the Fig. 1 embodiment except the provision o~ a counter 24 and an OR gate 26. The counter 24 is reset by the synchronizing operation start signal SS applied ` ' to the control circuit 23, and it counts the number of clock pulse eliminating signals CT1 which are applied to ,~
the post-clock eliminator'16 and generates a high~level ,' .
output when its count value reaches a predetermined value M. The high-level output is combined by the OR
,. .
.
~3~3~0~
gate 26 wi~h the output o~ the gate AND~ in Fig. 3B and applied as the clock pulse eliminatin6 signal CT2 to the pre-clock eliminator 13 via the OR gate 26. The value M
to be set in the counter 24 is selected to be the smallest inte~er greater than (2n-1)/N, for example, and in the case where n = 3 and N = 2, the value M is set to 4.
When the value n is large, it does not essentially matters even if the value M is set to an integer either above or below (2n~ N, but close thereto.
During the synchronizin~ operation the low-speed data LDN is output as low-speed output data DX1 to DXN-1 o~ the selectors 181 to 1 8N _ 1 and it is determined in the comparators 191 to 19N whether or not the low-speed data LDN matches the reference patterns RP1 to RPN, respectively. In the case where the high-speed input data HD contains errors with a particular period and errors are unevenly distributed in the low-speed data LDN, a state of generating the clock pulse eliminating signal CT1 at least once occurs in any n consecutive bits, and in this instance, no synchronization can be established as long as the errors are unevenly distributed.
The counter 24 counts the number of pulses of the clock pulse eliminating signal CT1, and when its count value goes to M, the control circuit 23 ~enerates the clock pulse eliminatin~ si~nal CT2. Immediately thereafter one clock pulse is eliminated by the pre-clock eliminator 13 from the clock FCL which is applied to the divider 14, by which the line positions o~ low-speed data LD1 to LDN are sequentially shifted by one line position in the demultiplexer 15. As a result of this, errors are une~enly distributed in the sequence of low-speed data LDN 1; SO that no error are evenly distrlbuted in the low-speed data LDN of the most , .
advanced phase after the line position shift selected by the selectors 181 to 18N-1. This ensures synchronization of the low-speed data LD1 to LDN and the reference patterns RP1 to RP~ by the synchronizin~
operation as is the case with the Fig. 1 embodiment.
As described above, according to the present invention, that one of N demultiplexed sequences of low-speed data which has the most advanced phase is compared with each of N parallel sequences of reference patterns and is synchronized with that one of the reference patterns whose phase is the closest thereto and line positions of the N parallel sequences of low-speed data are cyclically shifted in one direction so that the line position of the sequence of low-speed data of the most advanced phase is moved to the line position of the sequence of reference pattern of the closest phase.
Hence, the synchronization can be established within a time 1/N of the reference pattern period in the worst case.
It will be apparent that many modifications and variations may be effected without departing from the scope of the novel concepts of the present invention.
~:
.. . .
Claims (7)
1. A pattern synchronizing circuit comprising:
pre-clock eliminating means for eliminating one clock pulse from a high-speed clock input thereinto upon each application thereto of a pre-clock pulse eliminating signal;
clock dividing means for frequency dividing the high-speed clock output from said pre-clock eliminating means to 1/N;
demultiplexing means whereby consecutive bits of said high-speed input data are sequentially demultiplexed into N parallel sequences of low-speed on N output lines in synchronization with said high-speed clock and said N sequences of low-speed data are output in synchronization with said frequency divided clock, N being an integer equal to or greater than 2;
post-clock eliminating means supplied with said frequency divided clock, for eliminating one pulse from said frequency divided clock upon each application thereto of a post-clock pulse eliminating signal;
reference pattern generating means for generating N parallel sequences of reference patterns sequentially displaced apart in phase, in synchronization with the output clock of said post-clock pulse eliminating means;
N comparators whereby an Nth sequence of low-speed data, composed of data of every Nth bits of N-bit data sequentially demultiplexed by said demultiplexing means into N parallel sequences and output upon each occurrence of said frequency divided clock is compared with said N parallel sequences of reference patterns, each of said N comparators outputting an agreement or disagreement signal;
asynchronism detecting means which generates said post-clock pulse eliminating signal upon detecting that each of said N comparators has output said disagreement signal at least once in a disagreement detection starting state; and synchronization setting means for detecting that one of said N parallel sequences of reference patterns with which said Nth sequence of low-speed data has been synchronized and for generating said pre-clock pulse eliminating signals of the number corresponding to the line position of said sequence of reference pattern synchronized with said Nth sequence of low-speed, whereby line positions of said N parallel sequences of low-speed data are sequentially shifted by said corresponding number in said demultiplexing means so that said Nth sequence of low-speed data assumes the same line position as that of said synchronized reference pattern.
pre-clock eliminating means for eliminating one clock pulse from a high-speed clock input thereinto upon each application thereto of a pre-clock pulse eliminating signal;
clock dividing means for frequency dividing the high-speed clock output from said pre-clock eliminating means to 1/N;
demultiplexing means whereby consecutive bits of said high-speed input data are sequentially demultiplexed into N parallel sequences of low-speed on N output lines in synchronization with said high-speed clock and said N sequences of low-speed data are output in synchronization with said frequency divided clock, N being an integer equal to or greater than 2;
post-clock eliminating means supplied with said frequency divided clock, for eliminating one pulse from said frequency divided clock upon each application thereto of a post-clock pulse eliminating signal;
reference pattern generating means for generating N parallel sequences of reference patterns sequentially displaced apart in phase, in synchronization with the output clock of said post-clock pulse eliminating means;
N comparators whereby an Nth sequence of low-speed data, composed of data of every Nth bits of N-bit data sequentially demultiplexed by said demultiplexing means into N parallel sequences and output upon each occurrence of said frequency divided clock is compared with said N parallel sequences of reference patterns, each of said N comparators outputting an agreement or disagreement signal;
asynchronism detecting means which generates said post-clock pulse eliminating signal upon detecting that each of said N comparators has output said disagreement signal at least once in a disagreement detection starting state; and synchronization setting means for detecting that one of said N parallel sequences of reference patterns with which said Nth sequence of low-speed data has been synchronized and for generating said pre-clock pulse eliminating signals of the number corresponding to the line position of said sequence of reference pattern synchronized with said Nth sequence of low-speed, whereby line positions of said N parallel sequences of low-speed data are sequentially shifted by said corresponding number in said demultiplexing means so that said Nth sequence of low-speed data assumes the same line position as that of said synchronized reference pattern.
2. The pattern synchronizing circuit of claim 1, wherein said asynchronism detecting means includes: N
hold means for holding predetermined logical states in response to disagreement signals from said N comparators;
and post-clock pulse eliminating signal generating means for generating said post-clock pulse eliminating signal and for resetting said N hold means when all of said N hold means enter said predetermined logical states.
hold means for holding predetermined logical states in response to disagreement signals from said N comparators;
and post-clock pulse eliminating signal generating means for generating said post-clock pulse eliminating signal and for resetting said N hold means when all of said N hold means enter said predetermined logical states.
3. The pattern synchronizing circuit of claim 1, wherein said synchronization setting means includes:
synchronization detecting means which is reset upon each application of said post-clock pulse eliminating signal, counts the number of output clock pulses of said post-clock eliminating means and outputs a synchronization detecting signal when the count value reaches a predetermined value; and pre-clock pulse eliminating signal generating means which responds to said synchronization detecting signal to output, as said pre-clock pulse eliminating signal, said output clock pulses of said post-clock eliminating means by said corresponding number.
synchronization detecting means which is reset upon each application of said post-clock pulse eliminating signal, counts the number of output clock pulses of said post-clock eliminating means and outputs a synchronization detecting signal when the count value reaches a predetermined value; and pre-clock pulse eliminating signal generating means which responds to said synchronization detecting signal to output, as said pre-clock pulse eliminating signal, said output clock pulses of said post-clock eliminating means by said corresponding number.
4. The pattern synchronizing circuit of claim 1, 2, or 3, further including counter means for counting the number of said post-clock pulse eliminating signals and for applying said pre-clock pulse eliminating signal to said pre-clock eliminating means once when the count value of said counter means reaches a predetermined number.
5. The pattern synchronizing circuit of claim l, 2, or 3, which further includes N-1 select means for selecting said Nth sequence of low-speed data and the other N-l sequences of low-speed data, and wherein said N sequence of low-speed data and output data of said N-1 select means are provided to said N comparators and during a synchronizing operation all of said N-l select means select and output said Nth sequence of low-speed data to said N-l comparators corresponding to them for comparison with said N parallel sequences of reference patterns.
6. The pattern synchronizing circuit of claim 3, wherein each of said reference patterns is maximum length linear shift register sequence of a (2n-1) bit length and said predetermined value is equal to or greater than n, n being a positive integer.
7. The pattern synchronizing circuit of claim 4, wherein each of said reference patterns is a maximum length linear shift register sequence of a (2n-1) bit length and said predetermined number is an integer nearly equal to (2n-1)/N, n being a positive integer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP147629/90 | 1990-06-06 | ||
| JP2147629A JPH0440125A (en) | 1990-06-06 | 1990-06-06 | Pattern synchronizing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2043803A1 true CA2043803A1 (en) | 1991-12-07 |
Family
ID=15434652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002043803A Abandoned CA2043803A1 (en) | 1990-06-06 | 1991-06-04 | Pattern synchronizing circuit |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5210754A (en) |
| EP (1) | EP0460604A3 (en) |
| JP (1) | JPH0440125A (en) |
| CA (1) | CA2043803A1 (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05160825A (en) * | 1991-12-03 | 1993-06-25 | Fujitsu Ltd | Synchronizing circuit |
| US5448668A (en) * | 1993-07-08 | 1995-09-05 | Perelson; Alan S. | Method of detecting changes to a collection of digital signals |
| JP2694807B2 (en) * | 1993-12-16 | 1997-12-24 | 日本電気株式会社 | Data transmission method |
| CA2128587A1 (en) * | 1994-07-21 | 1996-01-22 | Ed Morson | Method and arrangement for recognition of a coded transmitted signal |
| US5661763A (en) * | 1995-07-28 | 1997-08-26 | Adtran, Inc. | Apparatus and method for detecting programmable length bit pattern in serial digital data stream |
| US6459393B1 (en) * | 1998-05-08 | 2002-10-01 | International Business Machines Corporation | Apparatus and method for optimized self-synchronizing serializer/deserializer/framer |
| FI108826B (en) | 1999-03-12 | 2002-03-28 | Nokia Corp | Monitoring method and monitoring arrangement |
| US7047196B2 (en) | 2000-06-08 | 2006-05-16 | Agiletv Corporation | System and method of voice recognition near a wireline node of a network supporting cable television and/or video delivery |
| US7039074B1 (en) * | 2000-09-14 | 2006-05-02 | Agiletv Corporation | N-way demultiplexer |
| US8095370B2 (en) | 2001-02-16 | 2012-01-10 | Agiletv Corporation | Dual compression voice recordation non-repudiation system |
| JP3597142B2 (en) * | 2001-04-20 | 2004-12-02 | 日本電気株式会社 | Center phase determination circuit and center phase determination method |
| US7352777B2 (en) * | 2001-10-31 | 2008-04-01 | Intel Corporation | Data framer |
| US7188290B2 (en) * | 2002-04-23 | 2007-03-06 | Intel Corporation | Data alignment for telecommunications networks |
| GB0525229D0 (en) | 2005-12-12 | 2006-01-18 | Qinetiq Ltd | Pattern matching apparatus |
| US11940836B2 (en) | 2022-03-31 | 2024-03-26 | International Business Machines Corporation | Dual chip clock synchronization |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3144515A (en) * | 1959-10-20 | 1964-08-11 | Nippon Electric Co | Synchronization system in timedivision code transmission |
| JPS5814103B2 (en) * | 1975-04-07 | 1983-03-17 | 日本電気株式会社 | frame synchronizer |
| JPS585056A (en) * | 1981-07-02 | 1983-01-12 | Nec Corp | Diffusion signal generating circuit |
| JPH0775343B2 (en) * | 1986-02-14 | 1995-08-09 | 株式会社日立製作所 | Synchronization detection circuit and method |
| JPH01165239A (en) * | 1987-12-21 | 1989-06-29 | Advantest Corp | Data pattern synchronizing device |
| JPH0828691B2 (en) * | 1988-03-14 | 1996-03-21 | 富士通株式会社 | Frame synchronization method |
| US4984249A (en) * | 1989-05-26 | 1991-01-08 | First Pacific Networks | Method and apparatus for synchronizing digital data symbols |
-
1990
- 1990-06-06 JP JP2147629A patent/JPH0440125A/en active Pending
-
1991
- 1991-06-04 US US07/710,522 patent/US5210754A/en not_active Expired - Fee Related
- 1991-06-04 CA CA002043803A patent/CA2043803A1/en not_active Abandoned
- 1991-06-04 EP EP19910109109 patent/EP0460604A3/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| EP0460604A2 (en) | 1991-12-11 |
| US5210754A (en) | 1993-05-11 |
| EP0460604A3 (en) | 1993-01-20 |
| JPH0440125A (en) | 1992-02-10 |
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| EEER | Examination request | ||
| FZDE | Discontinued |