CA2041507C - A high performance pipelined emulator - Google Patents
A high performance pipelined emulatorInfo
- Publication number
- CA2041507C CA2041507C CA002041507A CA2041507A CA2041507C CA 2041507 C CA2041507 C CA 2041507C CA 002041507 A CA002041507 A CA 002041507A CA 2041507 A CA2041507 A CA 2041507A CA 2041507 C CA2041507 C CA 2041507C
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- CA
- Canada
- Prior art keywords
- instruction
- emulation
- chip
- address
- emulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
- G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
- G06F9/3879—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
Abstract
The emulator includes first and second pipelined stages connected through a bidirectional bus for executing source instructions normally executed by a different/source computer in a highly overlapped manner. The first stage includes an emulator chip which performs the function of fetching and decoding each source instruction stored in cache memory resulting in the generation of a number of vector addresses required for executing the instruction by the second stage. The second stage includes a high performance microprocessor chip having on-chip instruction and data caches for storing a plurality of emulation subroutines and data fetched during subroutine execution. In pipelined fashion, the emulator chip fetches and decodes each source instruction which generates a vector branch address which is loaded into the branch vector register while the microprocessor chip fetches and executes emulation subroutines specified by the vector address transferred via the bus for each previously decoded source instruction.
Description
RELATE~ APPLICATION
l. The Unlted States patent appllcatlon of Richard P.
Brown, Thomas F. Joyce, and Steven S. Smlth entitled, "External Procedure Invocatlon Apparatus," filed June 29, lg90, bearing serial number 546,347, which ls asslgned to the same asslgnee as this patent appllcatlon and lssued as Unlted State~ Patent No.
5,287,522.
20~1507 BAC~GROUND OF THE INVENTION
Field of Use The present invention relates to systems which execute complex instruction sets and more particularly to computers which emulate the operations of other computers.
Prior Art There are a number of systems desiqned to simulate or emulate the operations of a different type of computer (source computer). In certain cases, this has involved the use of separate translating programs to convert the source computer programs into a form executable by the emulating or simulating computer.
This approach has proved time consuming and inefficient.
To overcome the above disadvantages, one solution has been to provide a general purpose computer which includes a simulative interpretative capability enabling the computer to reference subroutines for executing source computer instructions. This arrangement is disclosed in U.S. Patent No. 3,698,007 which issued on October 10, 1972.
Another proposed approach has been to design the architecture of a computer specifically for efficient execution of source program instructions. It has been recognized that this approach requires a substantial investment in terms of cost and resources. Moreover, with continued rapid improvements in computer technology, such investments must be ongoing in order to remain product competitive.
.,~
l. The Unlted States patent appllcatlon of Richard P.
Brown, Thomas F. Joyce, and Steven S. Smlth entitled, "External Procedure Invocatlon Apparatus," filed June 29, lg90, bearing serial number 546,347, which ls asslgned to the same asslgnee as this patent appllcatlon and lssued as Unlted State~ Patent No.
5,287,522.
20~1507 BAC~GROUND OF THE INVENTION
Field of Use The present invention relates to systems which execute complex instruction sets and more particularly to computers which emulate the operations of other computers.
Prior Art There are a number of systems desiqned to simulate or emulate the operations of a different type of computer (source computer). In certain cases, this has involved the use of separate translating programs to convert the source computer programs into a form executable by the emulating or simulating computer.
This approach has proved time consuming and inefficient.
To overcome the above disadvantages, one solution has been to provide a general purpose computer which includes a simulative interpretative capability enabling the computer to reference subroutines for executing source computer instructions. This arrangement is disclosed in U.S. Patent No. 3,698,007 which issued on October 10, 1972.
Another proposed approach has been to design the architecture of a computer specifically for efficient execution of source program instructions. It has been recognized that this approach requires a substantial investment in terms of cost and resources. Moreover, with continued rapid improvements in computer technology, such investments must be ongoing in order to remain product competitive.
.,~
Accordingly, it is primary object of the present invention to provide a high performance computer system which is capable of emulating the complex instruction set of a general purpose computer system.
It is a further ob~ect of the present invention to provide a high performance computer system which uses commercial or existing computer technology.
SUMMARY OF THE lNv~NllON
The above and other objects of the present invention are achieved in a preferred embodiment of an emulator which includes two pipelined stages interconnected for communication through a bidirectional bus. The first stage includes an emulation (E) chip which couples to an instruction cache unit. The E chip operates to fetch from the instruction cache, program instructions executable by a general purpose computer (source computer). The E chip decodes each source instruction and generates a number of vector branch addresses required by the secon~ pipeline stage for executing the source instruction.
The second stage includes a high performance microprocessor chip having on-chip instruction and data caches for storing a plurality of emulation subroutines and any data fetched during the execution of the subroutineS.
In accordance with the present invention, in a pipelined fashion, the E chip fetches, decodes source instructions and generates the required vector branch addresses in parallel with the microprocessor chip's execution of the emulation subroutines specified by the vector addresses transferred via the bus. In the preferred embodiment, the microprocessor chip further ~z ~
It is a further ob~ect of the present invention to provide a high performance computer system which uses commercial or existing computer technology.
SUMMARY OF THE lNv~NllON
The above and other objects of the present invention are achieved in a preferred embodiment of an emulator which includes two pipelined stages interconnected for communication through a bidirectional bus. The first stage includes an emulation (E) chip which couples to an instruction cache unit. The E chip operates to fetch from the instruction cache, program instructions executable by a general purpose computer (source computer). The E chip decodes each source instruction and generates a number of vector branch addresses required by the secon~ pipeline stage for executing the source instruction.
The second stage includes a high performance microprocessor chip having on-chip instruction and data caches for storing a plurality of emulation subroutines and any data fetched during the execution of the subroutineS.
In accordance with the present invention, in a pipelined fashion, the E chip fetches, decodes source instructions and generates the required vector branch addresses in parallel with the microprocessor chip's execution of the emulation subroutines specified by the vector addresses transferred via the bus. In the preferred embodiment, the microprocessor chip further ~z ~
lncludes a dedicated reglster whlch couples to the bu~ and is used to store each vector branch address generated by the E chlp and loaded thereln during mlcroprocessor operatlon. Each tlme the microprocessor chlp accesses or reads the address contents of the branch vector reglster ln response to a branch on vector register instructlon contained wlthin one of the emulatlon subroutlnes being executed, this ls si~nalled to the E chlp through the bus.
this causes the E chip to load a next vector address lnto the reglster whlle the mlcroprocessor executes the emulatlon subroutine designated by the previously loaded vector address.
Thls faclllty, whlch ls the referenced related patent application, reduces the need for having the microprocessor chlp make any off-chlp accesses ln fetchlng emulatlon subroutlnes whlch substantially lncreases performance. Thls ls particularly lmportant when the mlcroprocessor chlp ls a reduced instruction chlp (RI~C) whlch is the case for the preferred embodiment. For reasons of high performance and commerclal avallablllty, a RISC
chlp whlch lncludes a tightly coupled or on-chlp data and instruction caches was selected for lmplementlng the second pipeline stage.
In accordance wlth the present invention there is provlded a plpelined emulator for executlng a set of sollrce instructions executable by a general purpose cornputer having a speciflc architecture, said emulator comprlsin~: a first pipelined stage coupled to an instruction cache, said first pipelined stage includlng an emulation chlp for fetching, decoding each source instructlons stored in said lnstruction cache and for generatlng a number of vector addresses for identifylng a 4a 72434-116 corresponding number of emulatlon subrolltlnes re~uired for executing said each source instructlon; a second pipelined stage, - said second stage including a high performance microprocessor chip and instruction and data caches tightly coupled to said microprocessor chip, said instruction cache of said second stage storing a plurality of emulation subroutines for executing said set of source instructions and said data cache of said second stage for storing data fetched during execution of said emulation subroutines; and, a bldirectlonal bus interconnecting said first and second pipeline stages for tr-ansfer of sald number of vector addresses between said flrst and second plpellned stages, sald emulation chip decoding and generating sald number of vector addresses for each source lnstruction ln parallel wlth sald microprocessor chlp fetchlng and executing those emulator subroutlnes stored ln sald lnstructlon cache of sald second stage specified by the number of vector addresses generated for a previously decoded source lnstructlon by said emulator chip and transferred through said bldlrectlonal bus for emulating said general purpose computer in executing said each source instruction.
In accordance with a further aspect of the present lnventlon there is provided a plpellned emulator for e~ecutlng source lnstructions executable by a general purpose computer, said emulator comprlsing a mlcroprocessor chlp stage includlng on-chip instruction and data caches, said on-chip lnstructlon cac~le storlng a plurallty of emulatlon subroutlnes for sald source instructions; an emulation chip stage coupled to an instruction cache for storlng a plurallty of source lnstructlons of a program to be emulated by said emulator, said emulation chip stage , . ...
4~ 72434-116 lncludlng an lnstructlon unlt coupled to said lnstruction cache for fetching and decodlng each source instruction and a subroutlne address control store coupled to said lnstrl~ctlon unlt, said store lncludlng a plurallty of locatlons, each for storing a vector address identlfylng a different one of sald plurality of emulatlon subroutines; ar,d, a bldlrectional bus interconnecting said microprocessor and emulation chip stages for transferring information accordlng to a standard protocol, said emulatlon lnstruction unlt durlng a flrst phase of operatlon, decodlng each source lnstructlon fetched from sald lnstruction cache and ln accordance wlth sald decodlng causlng sald control store to read out said vector address for transfer to said mlcroprocessor chlp stage uslng sald standard protocol and durlng a second phase of operatlon, sald mlcroprocessor chip stage fetchlng sald vector address previously transferred to sald mlcroprocessor chlp stage durlng sald first phase and executing lnstructlons of a specified one of said emulation subroutines designated by said vector address, said executlng lnstructions overlapplng sald emulation chlp stage decoding of a next source instruction, said read out of said vector address and sald transfer to sald mlcroprocessor chip stage thereby enabllng the executlon of source lnstructlons ln a two-stage overlapped pipellned mode of operation.
In accordance with another aspect of the present invention there is provided a rrlethod of operating an emulator having first and second pipeline stages for executing source instructions executable by a general purpose computer ln a hlghly efficlent manner, sald method comprlslng the steps of ~a) fetching, decodlng and generatlng a branch vector address by an emulator chip of said first plpellne stage of sald emulator for ~ ~ ~ 7 ~ ~ ~
' ., 4c 72434-116 each source instructlon during a flrst phase of operatlon; (b) transferrlng the ~ranch vector address durlng sald first phase of operatlon to a microprocessor chip of said second pipellne stage of said emulator through a bidirectional bus interconnecting said chips; and, (c~ fetching and exesuting instructions of one of a plurallty of emulation subroutines stored in an on-chip lnstruction cache of sald mlcroprocessor chlp speclfled by the branch vector address transferred durlng step (b) durlng a second phase of operatlon for executing a next source instructlon upon completlon of t.he previous source instruction thereby enabling said first and second stages of said emulator to execute each said source instruction in a highly overlapped plpelined fashion.
In accordance wlth a stlll further aspect of the present inventlon there ls provlded a pipelined emulator for executlng ln a flrst computer system a set of computer program lnstructions executa~le in a different second computer system, said emulator belng characterized by: a flrst stage coupled to recelve sald instructions in sequence, said first stage decoding each one of said received instructions and, in response to said decoding, generating at least one address representation of a rnernory location holdlng an emulatlon subroutlne for carrylng out at least the partial execution of said one instruction in said first computer system; a second stage comprising a data processor, a first store for holding data and a second store for holding emulation subroutines, each of said subroutlnes provlding for carrying out at least the partial execution of one of said instructlons ln said first computer system, said second stage coupled to receive in succession address representations of the locations in said second store of respective ones of said .,."
4d 72434-116 emulatlon subroutines, and to fetch from said second store and execute the ones of said stored emulation subroutines whose ~ locations in said second store are identified by said received address representations; and an interconnection member coupling together sald flrst and second stages of transmltting said address representations generated by said first stage to said second stage; whereby, when (1) said first stage is decodlng a received instruction, generating a corresponding address representation and applylng said address representation to sald interconnectlon rnember for transmittal to said second stage, concurrently (ii) said second stage is fetchlng from sald second store and executlng the one of said stored emulation subroutines whose location in said second store is identified by the address representatlon previously transmitted from said first stage to said second stage.
The novel features which are belleved to be characteristic of the invention, both as to its organlzation and method of operatlon, together wlth further ob~ects and advantages of the present invention, will be better understood frorn the following detailed descriptlon taken in con~unctlon wlth the accompanying drawings.
.
20415~7 ~RIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram of a system which includes the two stage pipelined emulator of the preferred embodiment of the present invention.
S Figure 2 shows in greater detail, the different stages of the emulator of Figure 1.
Figure 3 is a flow diagram used to illustrate the branch vector mechanism which is included in the emulator of Figure 1.
Figures 4a and 4b are flow diagrams used to explain the operation of the emulator of Figure 1.
Figure 5 illustrates the overlapped pipelined operation of the emulator of Figure 1.
Figure 6 illustrates in greater detail the internal registers of one stage of the emulator of Eigure 2.
Figure 7 illustrates representative set of emulation subroutines used in describing the operation of the emulator of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Figure 1 shows in block diagràm form, a data processing system 10. As shown, the system 10 includes an emulator 12 which couples to a system bus 14 through a bus interface unit 16 and to an instruction cache 18.
The emulator 12 includes two pipeline stages which correspond to an emulation chip 12-2 and a microprocessor chip 12-4. The chips 12-2 and 12-4 are interconnected to communicate through a bidirectional bus 12-6 which also provides a main memory access path through bus interface unit 16 and system bus 14.
The E chip 12-2 performs three main functions. It fetches source instructions executable by a general purpose computer from instruction cache 18, crac~s or decodes each instructlon and, based upon the result of such decoding, generates a number of branch vector addresses whlch specify the correspondlng emulatlon subroutlnes for executlng each source instruction. Thus, the E chip 12-2 may lnclude hardware slmllar to an lnstructlon or I chlp [such as that descrlbed ln the copendlng patent application of Deborah K.
Staplin and Jian-Kuo Shen tltled, "Instruction Unit Loglc Management Apparatus Included ln a Plpellned Processing Unit, Serlal Number 07/374,881 filed on June 30, 1989 and asslgned to the same assignee as named herein.]
The mlcroprocessor 12-4 performs the main functlon of executlng the requlred emulatlon subroutlnes speclfled by the vector branch addresses generated by E chlp 12-2 and storlng the results and other lnformatlon whlch is the same as that stored by the general purpose computer belng emulated during lts executlon of source lnstructlons. In the preferred embodlment, the mlcroprocessor 12-4 takes the form of a hlgh performance reduced lnstructlon set (RISC) mlcroprocessor chlp whlch includes on-chlp lnstructlon and data caches for mlnlmlzlng access delays. For example, one such chlp ls the Intel 1860 mlcroprocessor.
In the preferred embodiment, the emulator 12 ls used to emulate the complex lnstructlon set of the DPS6000 computer system manufactured by Bull HN Informatlon Systems Inc. The source lnstructlon set has several categorles of lnstructlons.
These lnclude a general or baslc lnstructlon set; an extended lnteger (EII) instruction set; a commerclal lnstructlon set;
and a scientlflc instruction set. The DPS6000 computer has an archltecture which includes both 16, 32 and 64-bit reglsters, mode and indicator registers and trap handler facillties. For a further descrlptlon of the types of - 6a -~:;
,... ..
instructions and architecture, reference may be made to U.S. Patent No. 4,638,450, in addition to the referenced copending patent appl~cation.
Figure 2 shows in greater detail, the orgai.~zations of E chip 12-2 and microprocessor chip 12-4. As shown, the E chip 12-2 includes an instructlon decode unit 12-200 such as above mentioned I chip. It also includes a subroutine address control store 12-202 and subroutine and sequencer unit 12-204 which interconnect as shown.
As previously mentioned, the unit 12-200 operates to fetch and decode each source instruction which results in the development of a starting address which is applied as an input to subroutine address control store 12-202, as shown. In the simplest case, t~is starting address may correspond to the op-code bits of the source instruction. The store 12-202 includes locations for storing microinstructions required for performing the required functions of E chip 12-2. Each location contains a microinstruction word having op-code control store address and vector address fields. The different vector branch addresses identify the emulation subroutines for executing the different instructions of the complex instruction set of the general purpose computer being emulated. In certain instances, control store 12-202 uses pairs of locations for storing vector branch addresses specifying emulation subroutines for performing the address development and execution portions of certain source instructions The subroutine and control store sequencer 12-204 includes the logic circuits for generating the necessary control signals for conditioning or advancing control store 12-202 and instruction decode unit 12-200 as required for processing source instructions fetched from instruction cache 18. As seen from Figure 2, the ~_ -8 control store 12-202 and subroutine and control store sequencer 12-204 connect in common to the control, address and data lines of bidirectional bus 12-6.
The bus 12-6 is operated according to a predefined protocol or dialog for transferring commands, address and data between chips 12-2 and 12-4, in addition to system bus 14. Transfers are synchronized through the use of a common clock connected to the input/output interfaces of both chips. The bus 12-6 provides a facility by which E chip 12-2 can write and read the contents of internal registers of chip 12-4 which connect to bus 12-6. This i5 done through the use of read and write port commands. For an example of this type of bus arrangement, reference may be made to U.S.
Patent No. 4,910,666 which issued on March 20, 1990.
As seen from Figure 2, microprocessor chip 12-4 includes a 32-bit branch vector register 12-400 which connects to bus 12-6 so as to be capable of being read and written by E chip 12-2. Additionally, the register 12-400 operatively connects to an instruction cache 12-402. Register 12-400 has associated therewith read and write indicators which are set to appropriate states for signaling when a read or write has taken place within register 12-400.
As explained herein, the read indicator is set to an active state by the RISC chip 12-4 in the same way any conventional indicator bit is set in response to accessing the contents of a register or register file.
The output from the read indicator of register 12-400 is used to generate an external vector accessed signal which is applied via bus 12-6 as an input to the E chip subroutine and control store sequencer 12-204, as shown. The write indicator is set in response to a bus 2 0 ~ 7 g write strobe signal applied via bus 12-6 when the register is written into by the E chip.
Instruction cache 12-402 is of a size for storing the most frequently used emulation subroutines required for executing the instruction set of the emulated general purpose computer.
Microprocessor chip 12-4 also includes an 8 kbyte data cache 12-404 for storing data and other information fetched in response to the instructions of an emulation subroutine. Microprocessor chip 12-4 further includes a register file, an arithmetic and logic unit and an instruction decode and control unit connected as shown which form part of a RISC core block 12-406.
For further information regarding the constructlon of a microprocessor which is similar to the microprocessor chip 12-4, reference may be made to the article titled, "Introducing the Intel i860 64-Bit Microprocessor", published in the August, 1989 issue of IEEE MICRO.
DESCRIPTION OF OPERATION
With reference to Figures 1 and 2, the operation of the emulator 12 of the preferred embodiment will now be described in both general and specific terms. Figure S
illustrates in general the pipelined operation of the E
chip 12-2 and the RISC microprocessor chip 12-4 of emulator 12 in executing source instructions read from instruction cache 18.
As shown, the E chip 12-2 performs the instruction decode and develops the vector address which corresponds to the starting address of the emulation subroutine to be executed by RISC microprocessor chip 12-4. In parallel, the RISC chip 12-4 performs a fetch of the ...
emulation subroutine address such as by reading the contents of the vector branch register 12-400 and then executes the specified emulation subroutines fetched from instruction cache 12-402 emulating the functionality of the source computer in executing the corresponding source instruction.
Important to the above operations is that by including a minimum amount of additional hardware in chip 12-4, the above described operations are able to proceed without having the RISC chip 12-4 fetch vector addresses for the emulation subroutines from off-chip.
The additional hardware includes dedicated vector register 12-400 and a branch mechanism for executing a branch operation for determining if the contents of the register 12-400 have been updated. Figure 3 illustrates the operation of this mechanism in executing a branch vector instruction. This mechanism is subject of the referenced related patent application which describes the operation of mechanism in greater detail.
Referring to Fiqure 3, it is seen that each time RISC chip 12-4 fetches an instruction of an emulation subroutine, it decodes the instruction. When the instruction is not a branch vector instruction, chip 12-4 executes the instruction and increments its program counter by one for fetching the next instruction. When the instruction is a branch vector instruction, chip 12-4 tests the contents of the vector register to determine if it had been updated. As mentioned previously, this is done by testing the state of the associated write indicator to determine if the register has been written or updated by E chip 12-2.
If the register contents have not been updated (i.e., the write indicator is still a ZERO), chip 12-4 increments its program counter and fetches the next 2 0 ~ 7 instruction. If the register contents have been updated, chip 12-4 branches to the emulation subroutine specified by the contents of the vector register by loading the contents into its program counter as shown in Figure 3. In this manner, the chip 12-4 does not have to perform any off-chip accesses for vector branch values, thereby reducing the time of instruction processing.
Before describing the operation of the emulator 12 in more specific terms, reference will be made to Figure 6. As mentioned previously, the figure shows the usage of the different registers within the 32-bit register set of the RISC chip 12-4 to store data, indicator and mode information specific to the emulated general purpose computer.
As seen from Figure 6, register RO stores an all ZEROS value and is used for performing clearing operations. Registers $1-$7 are used for storing operand sign and data information in the format shown stored in registers Rl-R7 of the emulated computer.
Register $8 is used as working register w8.
Registers $9-S15 are used to store address values stored in the Bl-B7 registers of the emulated computer.
Register $16 is used as a working register W9. Data which is stored in the Kl-K7 registers of the emulated computer is stored in registers $17-$23. Registers $23-$27 are assigned to store information which is stored in working registers W1-W3. The register $28 is used for storing a constant value OOlOh for shifting 16 bits and serves as working register W4.
The registers $29 and $30 are used as working registers W5 and W6 for storing mode indicator, commercial, scientific and basic indicator information 20~1507 stored in the emulated computer. Register $31 is used as working register W7. The VR register 12-400 described previously is used for storing a 32-bit branch vector address value.
First, the emulator 12 is initialized. When initialized, the E chip 12-2 is set to store a starting address which points to the first emulated computer instruction to be fetched and executed by the emulator 12. Also, the emulation subroutines required to emulate the operation of the general purpose computer will have been loaded into the instruction cache 12-402. Included as part of the emulation subroutines, are the emulation subroutines for the Add R5,R2 instruction 8hown in Figure 7.
It is assumed that the emulator 12 has been executing instructions and at some point encounters the ADD R5,R2 instruction. The branch vector register 12-400 is loaded in response to the bvr.t instruction of Figure 7. At this point, the register 12-400 contains the vector address to the start of the ADD R5,R2 emulation subroutine.
It will be appreciated that at the point where the source instruction execution starts, the vector address may or may not have been loaded. That is, the bvr.t and subsequent instructions may cause chip 12-4 either to time-out or to continue in a loop until the vector register 12-400 has been loaded. This operation is illustrated by the flow diagram of Figure 4a. That i8, as shown in Figure 4a, if the vector address contents have been updated as indicated by the setting of the write indicator, then microprocessor chip 12-4 sequences through the yes path and begins executing the ADD R5 emulation subroutine, as shown. If it has not been updated, then the chip 12-4 continues to loop.
20~1507 For each source instruction, there may be two source addresses, one for address development and the other for execution. These vector addresses would be loaded into register 12-400 in sequence. The second address would be loaded from the next control store location upon receipt of a vector accessed slgnal specified from the prior decoding of the source instruction just as in the case of the first vector address as shown in Figure 4b.
For certain types of source instructions, such as a conditional branch instruction, it is desirable that the RISC chip 12-4 have the capability to interrogate/
request the E chip 12-2 to obtain the other vector address for the branch path. Every time the RISC chip 12-4 selects the emulation subroutine for a source branch instruction, it can calculate the taken branch address ahead of time and store it in a register within the E chip 12-2. The RISC chip 12-4 can then request the branch vector address value from E chip 12-2 via bus 12-6. It will then be used in conjunction with a normal branch vector instruction to fetch the specified emulation subroutine.
In each of the a~ove cases, when the contents of the branch vector register 12-400 is updated or written by either the E chip 12-2 or RISC chip 12-4, the write indicator will be set to an active or binary ONE state.
As mentioned, in the case of the ADD instruction, the RISC chip 12-4 executes the bvr.t instruction which results starting the execution of the emulation subroutine for carrying out the ADD source instruction.
The source ADD instruction being executed requires no address developmemt. However, if address development was required, the address development emulation subroutine would have loaded working register W2 prior to branching address ADDR5 (ADDR5 instruction subroutine entry point).
As seen from Figure 7, there are a substantial number of RISC instructions required to perform the addition. However, each of these instructions is rapidly executed within a single cycle of operation.
The ADD source instruction specifies adding the 16-bit contents of the register R5 to the contents of register R2 and storing the result and any overflow condition respectively into register R5 and an overflow indicator register. The RISC instructions cause chip 12-4 to perform the addition of a 16-bit register in a 32-bit register field and store any bits carried into the high order field of the register in the corresponding I section of register W6 of Figure 6. The majority of the RISC instructions are used for aligning, shifting, etc. register contents to match up the bits within the desired register sections.
In greater detail, first, the RISC chip 12-4 executes the OR instruction of Figure 7. This ORs the contents of register RO (i.e., ZEROS) with the contents of register R2 and store the result (i.e., contents of R2) in working location W2. The rest of the subroutine instructions acts on the contents of working register W2 to add the contents to the contents of working register W5 (i.e., unsigned add). The orh instruction uses a constant value of FF5F to move the result to the upper 16-bit positions and ORs it with the contents of register R0 (all ZEROS). This stores the mask for masking off the carry and overflow bits.
Next, the high order bits are shifted down so that they will mask off the appropriate bits. The shift right arithmetic instruction puts in the sign bits. The AND instruction clears out the bits in the indicator section of working register W6. That is, first it clears out the bits from the addition, takes the bits from the addition and masks them back into the I section of the register W6.
The remaining instructions of the emulation subroutine are used to fetch mask values re~uired for completing the operation. The btne instruction tests the state of the overflow bit position in the W1 register. If there is an overflow (W1/=RO), the microprocessor chip 12-4 branches to the OVERFO
emulation subroutine which is used to test if there is a trap on overflow condition specified. Also, chip 12-4 stores the state of the OVF bit in the I section of the register W6. This involves testing the state of a predetermined mode bit which corresponds to Ml(T5). If a trap condition is indicated by the state of the mode bit, chip 12-4 branches to the trap handler emulation subroutine TV06.
If there is branch to the TV06 subroutine, chip 12-4 saves the source computer location of the source instruction being executed which in this example is the address of the ADD R5 instruction. Also, the TV06 emulation subroutine will execute certain overhead tasks such as storing away the address of the source computer instruction trapped on and calculating what address the trap handler is at and save away these registers and indicators. The last instruction of the TV06 emulation subroutine executed by RISC chip 12-4 causes the E chip 12-2 to fetch the first instruction of the emulated computer overflow trap handler.
If no trap is indicated, chip 12-4 executes a br instruction branching it back to the DONE emulation subroutine for fetching the next instruction corresponding to the f part of the next RISC
microprocessor's execution cycle shown in Figure 5. If the branch vector register 12-400 has not been updated, the loop at DONE is executed until the register i8 updated.
From the above, it is seen how the emulator of the present inventlon is able to emulate the operation of a general purpose computer having specific architectural features in executing instructions. The emulator achieves high performance by using a two-stage pipeline and a state of the art high performance commercial RISC
microprocessor chip. Even though a substantial number of RISC instructions are required to execute one source instruction, it is possible to execute such instructions at a very high rate.
It will be appreciated that it is possible to modify the algorithm or type of RISC instructions included in the emulation subroutines to better optimize them specifically for the architecture of the microprocessor chip. While the i860 chip was indicated for implementing chip 12-4, it was selected because of it having on-chip instruction and data caches. It will be obvious that other high performance chips could also be used, such as the R3000 and successor chips manufactured by MIPS Corporation.
It will be obvious to those skilled in the art that many changes may be made to the preferred embodiment of the present invention without departing from its teachings. For example, different chips and different instruction sets may be used. Other changes will be readily apparent to those skilled in the art.
While in accordance with the provisions and statutes there has been illustrated and described the best form of the invention, certain changes may be made without departing from the ~pirit of the invention ac set forth in the appended claims and that in some cases, certain features of the invention may be used to advantage without a corresponding use of other features.
What is claimed is:
this causes the E chip to load a next vector address lnto the reglster whlle the mlcroprocessor executes the emulatlon subroutine designated by the previously loaded vector address.
Thls faclllty, whlch ls the referenced related patent application, reduces the need for having the microprocessor chlp make any off-chlp accesses ln fetchlng emulatlon subroutlnes whlch substantially lncreases performance. Thls ls particularly lmportant when the mlcroprocessor chlp ls a reduced instruction chlp (RI~C) whlch is the case for the preferred embodiment. For reasons of high performance and commerclal avallablllty, a RISC
chlp whlch lncludes a tightly coupled or on-chlp data and instruction caches was selected for lmplementlng the second pipeline stage.
In accordance wlth the present invention there is provlded a plpelined emulator for executlng a set of sollrce instructions executable by a general purpose cornputer having a speciflc architecture, said emulator comprlsin~: a first pipelined stage coupled to an instruction cache, said first pipelined stage includlng an emulation chlp for fetching, decoding each source instructlons stored in said lnstruction cache and for generatlng a number of vector addresses for identifylng a 4a 72434-116 corresponding number of emulatlon subrolltlnes re~uired for executing said each source instructlon; a second pipelined stage, - said second stage including a high performance microprocessor chip and instruction and data caches tightly coupled to said microprocessor chip, said instruction cache of said second stage storing a plurality of emulation subroutines for executing said set of source instructions and said data cache of said second stage for storing data fetched during execution of said emulation subroutines; and, a bldirectlonal bus interconnecting said first and second pipeline stages for tr-ansfer of sald number of vector addresses between said flrst and second plpellned stages, sald emulation chip decoding and generating sald number of vector addresses for each source lnstruction ln parallel wlth sald microprocessor chlp fetchlng and executing those emulator subroutlnes stored ln sald lnstructlon cache of sald second stage specified by the number of vector addresses generated for a previously decoded source lnstructlon by said emulator chip and transferred through said bldlrectlonal bus for emulating said general purpose computer in executing said each source instruction.
In accordance with a further aspect of the present lnventlon there is provided a plpellned emulator for e~ecutlng source lnstructions executable by a general purpose computer, said emulator comprlsing a mlcroprocessor chlp stage includlng on-chip instruction and data caches, said on-chip lnstructlon cac~le storlng a plurallty of emulatlon subroutlnes for sald source instructions; an emulation chip stage coupled to an instruction cache for storlng a plurallty of source lnstructlons of a program to be emulated by said emulator, said emulation chip stage , . ...
4~ 72434-116 lncludlng an lnstructlon unlt coupled to said lnstruction cache for fetching and decodlng each source instruction and a subroutlne address control store coupled to said lnstrl~ctlon unlt, said store lncludlng a plurallty of locatlons, each for storing a vector address identlfylng a different one of sald plurality of emulatlon subroutines; ar,d, a bldlrectional bus interconnecting said microprocessor and emulation chip stages for transferring information accordlng to a standard protocol, said emulatlon lnstruction unlt durlng a flrst phase of operatlon, decodlng each source lnstructlon fetched from sald lnstruction cache and ln accordance wlth sald decodlng causlng sald control store to read out said vector address for transfer to said mlcroprocessor chlp stage uslng sald standard protocol and durlng a second phase of operatlon, sald mlcroprocessor chip stage fetchlng sald vector address previously transferred to sald mlcroprocessor chlp stage durlng sald first phase and executing lnstructlons of a specified one of said emulation subroutines designated by said vector address, said executlng lnstructions overlapplng sald emulation chlp stage decoding of a next source instruction, said read out of said vector address and sald transfer to sald mlcroprocessor chip stage thereby enabllng the executlon of source lnstructlons ln a two-stage overlapped pipellned mode of operation.
In accordance with another aspect of the present invention there is provided a rrlethod of operating an emulator having first and second pipeline stages for executing source instructions executable by a general purpose computer ln a hlghly efficlent manner, sald method comprlslng the steps of ~a) fetching, decodlng and generatlng a branch vector address by an emulator chip of said first plpellne stage of sald emulator for ~ ~ ~ 7 ~ ~ ~
' ., 4c 72434-116 each source instructlon during a flrst phase of operatlon; (b) transferrlng the ~ranch vector address durlng sald first phase of operatlon to a microprocessor chip of said second pipellne stage of said emulator through a bidirectional bus interconnecting said chips; and, (c~ fetching and exesuting instructions of one of a plurallty of emulation subroutines stored in an on-chip lnstruction cache of sald mlcroprocessor chlp speclfled by the branch vector address transferred durlng step (b) durlng a second phase of operatlon for executing a next source instructlon upon completlon of t.he previous source instruction thereby enabling said first and second stages of said emulator to execute each said source instruction in a highly overlapped plpelined fashion.
In accordance wlth a stlll further aspect of the present inventlon there ls provlded a pipelined emulator for executlng ln a flrst computer system a set of computer program lnstructions executa~le in a different second computer system, said emulator belng characterized by: a flrst stage coupled to recelve sald instructions in sequence, said first stage decoding each one of said received instructions and, in response to said decoding, generating at least one address representation of a rnernory location holdlng an emulatlon subroutlne for carrylng out at least the partial execution of said one instruction in said first computer system; a second stage comprising a data processor, a first store for holding data and a second store for holding emulation subroutines, each of said subroutlnes provlding for carrying out at least the partial execution of one of said instructlons ln said first computer system, said second stage coupled to receive in succession address representations of the locations in said second store of respective ones of said .,."
4d 72434-116 emulatlon subroutines, and to fetch from said second store and execute the ones of said stored emulation subroutines whose ~ locations in said second store are identified by said received address representations; and an interconnection member coupling together sald flrst and second stages of transmltting said address representations generated by said first stage to said second stage; whereby, when (1) said first stage is decodlng a received instruction, generating a corresponding address representation and applylng said address representation to sald interconnectlon rnember for transmittal to said second stage, concurrently (ii) said second stage is fetchlng from sald second store and executlng the one of said stored emulation subroutines whose location in said second store is identified by the address representatlon previously transmitted from said first stage to said second stage.
The novel features which are belleved to be characteristic of the invention, both as to its organlzation and method of operatlon, together wlth further ob~ects and advantages of the present invention, will be better understood frorn the following detailed descriptlon taken in con~unctlon wlth the accompanying drawings.
.
20415~7 ~RIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram of a system which includes the two stage pipelined emulator of the preferred embodiment of the present invention.
S Figure 2 shows in greater detail, the different stages of the emulator of Figure 1.
Figure 3 is a flow diagram used to illustrate the branch vector mechanism which is included in the emulator of Figure 1.
Figures 4a and 4b are flow diagrams used to explain the operation of the emulator of Figure 1.
Figure 5 illustrates the overlapped pipelined operation of the emulator of Figure 1.
Figure 6 illustrates in greater detail the internal registers of one stage of the emulator of Eigure 2.
Figure 7 illustrates representative set of emulation subroutines used in describing the operation of the emulator of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Figure 1 shows in block diagràm form, a data processing system 10. As shown, the system 10 includes an emulator 12 which couples to a system bus 14 through a bus interface unit 16 and to an instruction cache 18.
The emulator 12 includes two pipeline stages which correspond to an emulation chip 12-2 and a microprocessor chip 12-4. The chips 12-2 and 12-4 are interconnected to communicate through a bidirectional bus 12-6 which also provides a main memory access path through bus interface unit 16 and system bus 14.
The E chip 12-2 performs three main functions. It fetches source instructions executable by a general purpose computer from instruction cache 18, crac~s or decodes each instructlon and, based upon the result of such decoding, generates a number of branch vector addresses whlch specify the correspondlng emulatlon subroutlnes for executlng each source instruction. Thus, the E chip 12-2 may lnclude hardware slmllar to an lnstructlon or I chlp [such as that descrlbed ln the copendlng patent application of Deborah K.
Staplin and Jian-Kuo Shen tltled, "Instruction Unit Loglc Management Apparatus Included ln a Plpellned Processing Unit, Serlal Number 07/374,881 filed on June 30, 1989 and asslgned to the same assignee as named herein.]
The mlcroprocessor 12-4 performs the main functlon of executlng the requlred emulatlon subroutlnes speclfled by the vector branch addresses generated by E chlp 12-2 and storlng the results and other lnformatlon whlch is the same as that stored by the general purpose computer belng emulated during lts executlon of source lnstructlons. In the preferred embodlment, the mlcroprocessor 12-4 takes the form of a hlgh performance reduced lnstructlon set (RISC) mlcroprocessor chlp whlch includes on-chlp lnstructlon and data caches for mlnlmlzlng access delays. For example, one such chlp ls the Intel 1860 mlcroprocessor.
In the preferred embodiment, the emulator 12 ls used to emulate the complex lnstructlon set of the DPS6000 computer system manufactured by Bull HN Informatlon Systems Inc. The source lnstructlon set has several categorles of lnstructlons.
These lnclude a general or baslc lnstructlon set; an extended lnteger (EII) instruction set; a commerclal lnstructlon set;
and a scientlflc instruction set. The DPS6000 computer has an archltecture which includes both 16, 32 and 64-bit reglsters, mode and indicator registers and trap handler facillties. For a further descrlptlon of the types of - 6a -~:;
,... ..
instructions and architecture, reference may be made to U.S. Patent No. 4,638,450, in addition to the referenced copending patent appl~cation.
Figure 2 shows in greater detail, the orgai.~zations of E chip 12-2 and microprocessor chip 12-4. As shown, the E chip 12-2 includes an instructlon decode unit 12-200 such as above mentioned I chip. It also includes a subroutine address control store 12-202 and subroutine and sequencer unit 12-204 which interconnect as shown.
As previously mentioned, the unit 12-200 operates to fetch and decode each source instruction which results in the development of a starting address which is applied as an input to subroutine address control store 12-202, as shown. In the simplest case, t~is starting address may correspond to the op-code bits of the source instruction. The store 12-202 includes locations for storing microinstructions required for performing the required functions of E chip 12-2. Each location contains a microinstruction word having op-code control store address and vector address fields. The different vector branch addresses identify the emulation subroutines for executing the different instructions of the complex instruction set of the general purpose computer being emulated. In certain instances, control store 12-202 uses pairs of locations for storing vector branch addresses specifying emulation subroutines for performing the address development and execution portions of certain source instructions The subroutine and control store sequencer 12-204 includes the logic circuits for generating the necessary control signals for conditioning or advancing control store 12-202 and instruction decode unit 12-200 as required for processing source instructions fetched from instruction cache 18. As seen from Figure 2, the ~_ -8 control store 12-202 and subroutine and control store sequencer 12-204 connect in common to the control, address and data lines of bidirectional bus 12-6.
The bus 12-6 is operated according to a predefined protocol or dialog for transferring commands, address and data between chips 12-2 and 12-4, in addition to system bus 14. Transfers are synchronized through the use of a common clock connected to the input/output interfaces of both chips. The bus 12-6 provides a facility by which E chip 12-2 can write and read the contents of internal registers of chip 12-4 which connect to bus 12-6. This i5 done through the use of read and write port commands. For an example of this type of bus arrangement, reference may be made to U.S.
Patent No. 4,910,666 which issued on March 20, 1990.
As seen from Figure 2, microprocessor chip 12-4 includes a 32-bit branch vector register 12-400 which connects to bus 12-6 so as to be capable of being read and written by E chip 12-2. Additionally, the register 12-400 operatively connects to an instruction cache 12-402. Register 12-400 has associated therewith read and write indicators which are set to appropriate states for signaling when a read or write has taken place within register 12-400.
As explained herein, the read indicator is set to an active state by the RISC chip 12-4 in the same way any conventional indicator bit is set in response to accessing the contents of a register or register file.
The output from the read indicator of register 12-400 is used to generate an external vector accessed signal which is applied via bus 12-6 as an input to the E chip subroutine and control store sequencer 12-204, as shown. The write indicator is set in response to a bus 2 0 ~ 7 g write strobe signal applied via bus 12-6 when the register is written into by the E chip.
Instruction cache 12-402 is of a size for storing the most frequently used emulation subroutines required for executing the instruction set of the emulated general purpose computer.
Microprocessor chip 12-4 also includes an 8 kbyte data cache 12-404 for storing data and other information fetched in response to the instructions of an emulation subroutine. Microprocessor chip 12-4 further includes a register file, an arithmetic and logic unit and an instruction decode and control unit connected as shown which form part of a RISC core block 12-406.
For further information regarding the constructlon of a microprocessor which is similar to the microprocessor chip 12-4, reference may be made to the article titled, "Introducing the Intel i860 64-Bit Microprocessor", published in the August, 1989 issue of IEEE MICRO.
DESCRIPTION OF OPERATION
With reference to Figures 1 and 2, the operation of the emulator 12 of the preferred embodiment will now be described in both general and specific terms. Figure S
illustrates in general the pipelined operation of the E
chip 12-2 and the RISC microprocessor chip 12-4 of emulator 12 in executing source instructions read from instruction cache 18.
As shown, the E chip 12-2 performs the instruction decode and develops the vector address which corresponds to the starting address of the emulation subroutine to be executed by RISC microprocessor chip 12-4. In parallel, the RISC chip 12-4 performs a fetch of the ...
emulation subroutine address such as by reading the contents of the vector branch register 12-400 and then executes the specified emulation subroutines fetched from instruction cache 12-402 emulating the functionality of the source computer in executing the corresponding source instruction.
Important to the above operations is that by including a minimum amount of additional hardware in chip 12-4, the above described operations are able to proceed without having the RISC chip 12-4 fetch vector addresses for the emulation subroutines from off-chip.
The additional hardware includes dedicated vector register 12-400 and a branch mechanism for executing a branch operation for determining if the contents of the register 12-400 have been updated. Figure 3 illustrates the operation of this mechanism in executing a branch vector instruction. This mechanism is subject of the referenced related patent application which describes the operation of mechanism in greater detail.
Referring to Fiqure 3, it is seen that each time RISC chip 12-4 fetches an instruction of an emulation subroutine, it decodes the instruction. When the instruction is not a branch vector instruction, chip 12-4 executes the instruction and increments its program counter by one for fetching the next instruction. When the instruction is a branch vector instruction, chip 12-4 tests the contents of the vector register to determine if it had been updated. As mentioned previously, this is done by testing the state of the associated write indicator to determine if the register has been written or updated by E chip 12-2.
If the register contents have not been updated (i.e., the write indicator is still a ZERO), chip 12-4 increments its program counter and fetches the next 2 0 ~ 7 instruction. If the register contents have been updated, chip 12-4 branches to the emulation subroutine specified by the contents of the vector register by loading the contents into its program counter as shown in Figure 3. In this manner, the chip 12-4 does not have to perform any off-chip accesses for vector branch values, thereby reducing the time of instruction processing.
Before describing the operation of the emulator 12 in more specific terms, reference will be made to Figure 6. As mentioned previously, the figure shows the usage of the different registers within the 32-bit register set of the RISC chip 12-4 to store data, indicator and mode information specific to the emulated general purpose computer.
As seen from Figure 6, register RO stores an all ZEROS value and is used for performing clearing operations. Registers $1-$7 are used for storing operand sign and data information in the format shown stored in registers Rl-R7 of the emulated computer.
Register $8 is used as working register w8.
Registers $9-S15 are used to store address values stored in the Bl-B7 registers of the emulated computer.
Register $16 is used as a working register W9. Data which is stored in the Kl-K7 registers of the emulated computer is stored in registers $17-$23. Registers $23-$27 are assigned to store information which is stored in working registers W1-W3. The register $28 is used for storing a constant value OOlOh for shifting 16 bits and serves as working register W4.
The registers $29 and $30 are used as working registers W5 and W6 for storing mode indicator, commercial, scientific and basic indicator information 20~1507 stored in the emulated computer. Register $31 is used as working register W7. The VR register 12-400 described previously is used for storing a 32-bit branch vector address value.
First, the emulator 12 is initialized. When initialized, the E chip 12-2 is set to store a starting address which points to the first emulated computer instruction to be fetched and executed by the emulator 12. Also, the emulation subroutines required to emulate the operation of the general purpose computer will have been loaded into the instruction cache 12-402. Included as part of the emulation subroutines, are the emulation subroutines for the Add R5,R2 instruction 8hown in Figure 7.
It is assumed that the emulator 12 has been executing instructions and at some point encounters the ADD R5,R2 instruction. The branch vector register 12-400 is loaded in response to the bvr.t instruction of Figure 7. At this point, the register 12-400 contains the vector address to the start of the ADD R5,R2 emulation subroutine.
It will be appreciated that at the point where the source instruction execution starts, the vector address may or may not have been loaded. That is, the bvr.t and subsequent instructions may cause chip 12-4 either to time-out or to continue in a loop until the vector register 12-400 has been loaded. This operation is illustrated by the flow diagram of Figure 4a. That i8, as shown in Figure 4a, if the vector address contents have been updated as indicated by the setting of the write indicator, then microprocessor chip 12-4 sequences through the yes path and begins executing the ADD R5 emulation subroutine, as shown. If it has not been updated, then the chip 12-4 continues to loop.
20~1507 For each source instruction, there may be two source addresses, one for address development and the other for execution. These vector addresses would be loaded into register 12-400 in sequence. The second address would be loaded from the next control store location upon receipt of a vector accessed slgnal specified from the prior decoding of the source instruction just as in the case of the first vector address as shown in Figure 4b.
For certain types of source instructions, such as a conditional branch instruction, it is desirable that the RISC chip 12-4 have the capability to interrogate/
request the E chip 12-2 to obtain the other vector address for the branch path. Every time the RISC chip 12-4 selects the emulation subroutine for a source branch instruction, it can calculate the taken branch address ahead of time and store it in a register within the E chip 12-2. The RISC chip 12-4 can then request the branch vector address value from E chip 12-2 via bus 12-6. It will then be used in conjunction with a normal branch vector instruction to fetch the specified emulation subroutine.
In each of the a~ove cases, when the contents of the branch vector register 12-400 is updated or written by either the E chip 12-2 or RISC chip 12-4, the write indicator will be set to an active or binary ONE state.
As mentioned, in the case of the ADD instruction, the RISC chip 12-4 executes the bvr.t instruction which results starting the execution of the emulation subroutine for carrying out the ADD source instruction.
The source ADD instruction being executed requires no address developmemt. However, if address development was required, the address development emulation subroutine would have loaded working register W2 prior to branching address ADDR5 (ADDR5 instruction subroutine entry point).
As seen from Figure 7, there are a substantial number of RISC instructions required to perform the addition. However, each of these instructions is rapidly executed within a single cycle of operation.
The ADD source instruction specifies adding the 16-bit contents of the register R5 to the contents of register R2 and storing the result and any overflow condition respectively into register R5 and an overflow indicator register. The RISC instructions cause chip 12-4 to perform the addition of a 16-bit register in a 32-bit register field and store any bits carried into the high order field of the register in the corresponding I section of register W6 of Figure 6. The majority of the RISC instructions are used for aligning, shifting, etc. register contents to match up the bits within the desired register sections.
In greater detail, first, the RISC chip 12-4 executes the OR instruction of Figure 7. This ORs the contents of register RO (i.e., ZEROS) with the contents of register R2 and store the result (i.e., contents of R2) in working location W2. The rest of the subroutine instructions acts on the contents of working register W2 to add the contents to the contents of working register W5 (i.e., unsigned add). The orh instruction uses a constant value of FF5F to move the result to the upper 16-bit positions and ORs it with the contents of register R0 (all ZEROS). This stores the mask for masking off the carry and overflow bits.
Next, the high order bits are shifted down so that they will mask off the appropriate bits. The shift right arithmetic instruction puts in the sign bits. The AND instruction clears out the bits in the indicator section of working register W6. That is, first it clears out the bits from the addition, takes the bits from the addition and masks them back into the I section of the register W6.
The remaining instructions of the emulation subroutine are used to fetch mask values re~uired for completing the operation. The btne instruction tests the state of the overflow bit position in the W1 register. If there is an overflow (W1/=RO), the microprocessor chip 12-4 branches to the OVERFO
emulation subroutine which is used to test if there is a trap on overflow condition specified. Also, chip 12-4 stores the state of the OVF bit in the I section of the register W6. This involves testing the state of a predetermined mode bit which corresponds to Ml(T5). If a trap condition is indicated by the state of the mode bit, chip 12-4 branches to the trap handler emulation subroutine TV06.
If there is branch to the TV06 subroutine, chip 12-4 saves the source computer location of the source instruction being executed which in this example is the address of the ADD R5 instruction. Also, the TV06 emulation subroutine will execute certain overhead tasks such as storing away the address of the source computer instruction trapped on and calculating what address the trap handler is at and save away these registers and indicators. The last instruction of the TV06 emulation subroutine executed by RISC chip 12-4 causes the E chip 12-2 to fetch the first instruction of the emulated computer overflow trap handler.
If no trap is indicated, chip 12-4 executes a br instruction branching it back to the DONE emulation subroutine for fetching the next instruction corresponding to the f part of the next RISC
microprocessor's execution cycle shown in Figure 5. If the branch vector register 12-400 has not been updated, the loop at DONE is executed until the register i8 updated.
From the above, it is seen how the emulator of the present inventlon is able to emulate the operation of a general purpose computer having specific architectural features in executing instructions. The emulator achieves high performance by using a two-stage pipeline and a state of the art high performance commercial RISC
microprocessor chip. Even though a substantial number of RISC instructions are required to execute one source instruction, it is possible to execute such instructions at a very high rate.
It will be appreciated that it is possible to modify the algorithm or type of RISC instructions included in the emulation subroutines to better optimize them specifically for the architecture of the microprocessor chip. While the i860 chip was indicated for implementing chip 12-4, it was selected because of it having on-chip instruction and data caches. It will be obvious that other high performance chips could also be used, such as the R3000 and successor chips manufactured by MIPS Corporation.
It will be obvious to those skilled in the art that many changes may be made to the preferred embodiment of the present invention without departing from its teachings. For example, different chips and different instruction sets may be used. Other changes will be readily apparent to those skilled in the art.
While in accordance with the provisions and statutes there has been illustrated and described the best form of the invention, certain changes may be made without departing from the ~pirit of the invention ac set forth in the appended claims and that in some cases, certain features of the invention may be used to advantage without a corresponding use of other features.
What is claimed is:
Claims (21)
1. A pipelined emulator for executing a set of source instructions executable by a general purpose computer having a specific architecture, said emulator comprising:
a first pipelined stage coupled to an instruction cache, said first pipelined stage including an emulation chip for fetching, decoding each source instructions stored in said instruction cache and for generating a number of vector addresses for identifying a corresponding number of emulation subroutines required for executing said each source instruction;
a second pipelined stage, said second stage including a high performance microprocessor chip and instruction and data caches tightly coupled to said microprocessor chip, said instruction cache of said second stage storing a plurality of emulation subroutines for executing said set of source instructions and said data cache of said second stage for storing date fetched during execution of said emulation subroutines; and, a bidirectional bus interconnecting said first and second pipeline stages for transfer of said number of vector addresses between said first and second pipelined stages, said emulation chip decoding each source instruction and generating said number of vector addresses for each source instruction in parallel with said microprocessor chip fetching and executing those emulator subroutines stored in said instruction cache of said second stage specified by the number of vector addresses generated for a previously decoded source instruction by said emulator chip and transferred through said bidirectional bus for emulating said general purpose computer in executing said each source instruction.
-18a-
a first pipelined stage coupled to an instruction cache, said first pipelined stage including an emulation chip for fetching, decoding each source instructions stored in said instruction cache and for generating a number of vector addresses for identifying a corresponding number of emulation subroutines required for executing said each source instruction;
a second pipelined stage, said second stage including a high performance microprocessor chip and instruction and data caches tightly coupled to said microprocessor chip, said instruction cache of said second stage storing a plurality of emulation subroutines for executing said set of source instructions and said data cache of said second stage for storing date fetched during execution of said emulation subroutines; and, a bidirectional bus interconnecting said first and second pipeline stages for transfer of said number of vector addresses between said first and second pipelined stages, said emulation chip decoding each source instruction and generating said number of vector addresses for each source instruction in parallel with said microprocessor chip fetching and executing those emulator subroutines stored in said instruction cache of said second stage specified by the number of vector addresses generated for a previously decoded source instruction by said emulator chip and transferred through said bidirectional bus for emulating said general purpose computer in executing said each source instruction.
-18a-
2. The emulator of claim 1 wherein said microprocessor chip includes branch vector apparatus, said apparatus being connected to said bidirectional bus for receiving and storing each vector address generated and transferred by said emulation chip and said apparatus including output means for generating an external signal on said bus signaling each time said microprocessor chip accesses said each vector address to fetch one of said emulation subroutines from said instruction cache, enabling said emulation chip to transfer a next vector address to said branch vector apparatus thereby eliminating said second pipeline stage having to make off chip accesses.
3. The emulator of claim 2 wherein said branch vector apparatus further includes a branch vector register connected to said bus for receiving and storing said each vector address, read and write indicator means for storing signals received from said microprocessor and emulation chips indicating when said branch vector register has been accessed and updated respectively; and means for connecting said read indicator means to said output means for causing said output means to generate said external signal on said bus each time said read indicator means is set to an active state.
4. The emulator of claim 3 wherein said microprocessor chip includes a branch vector instruction facility for testing said write indicator means for determining when said write indicator means is set to an active state enabling said microprocessor chip to branch to one of said plurality of emulator subroutines stored in said instruction cache.
5. The emulator of claim 4 wherein each of said plurality of emulation subroutines includes a plurality of reduced instruction set (RISC) type of instructions and a branch vector instruction as a last one of said plurality of RISC type of instructions coded for fetching a next emulation subroutine.
6. The emulator of claim 1 wherein said instruction and data caches are located on said microprocessor chip and said microprocessor chip is a standard reduced instruction set (RISC) type chip.
7. The emulator of claim 3 wherein said emulation chip includes a subroutine and control store sequencer coupled to a subroutine address control store and an instruction decode unit, said instruction decode unit being coupled to said instruction cache and in response to fetching and decoding said each source instruction, said unit generating a starting address for accessing said subroutine address control store, said subroutine control store having a plurality of addressable storage locations for storing microinstructions for controlling emulation chip operations, each of a number of said microinstructions containing a vector address for specifying a starting address of a different one of said plurality of emulation subroutines and said control store being connected to said bus, said control store in response to said starting address reading out a specified one of said number of said microinstructions for generating one of said number of vector addresses for transfer to said microprocessor chip.
8. The emulator of claim 7 wherein said subroutine and control store sequencer is connected to said output means of said microprocessor chip, said sequencer in response to each said external signal advancing said subroutine address control store to access a microinstruction for reading out another one of said number of said microinstructions for generating a next one of said number of vector addresses for transfer to said microprocessor chip.
9. The emulator of claim 8 wherein said number of said microinstructions include vector addresses for specifying emulation subroutines for performing address development and execution operation phases required for emulating execution of source instructions by said general purpose computer.
10. A pipelined emulator for executing source instructions executable by a general purpose computer, said emulator comprising:
a microprocessor chip stage including on-chip instruction and data caches, said on-chip instruction cache storing a plurality of emulation subroutines for said source instructions;
an emulation chip stage coupled to an instruction cache for storing a plurality of source instructions of a program to be emulated by said emulator, said emulation chip stage including:
an instruction unit coupled to said instruction cache for fetching and decoding each source instruction and a subroutine address control store coupled to said instruction unit, said store including a plurality of locations, each for storing a vector address identifying a different one of said plurality of emulation subroutines; and, a bidirectional bus interconnecting said microprocessor and emulation chip stages for transferring information according to a standard protocol, said emulation instruction unit during a first phase of operation, decoding each source instruction fetched from said instruction cache and in accordance with said decoding causing said control store to read out said vector address for transfer to said microprocessor chip stage using said standard protocol and during a second phase of operation, said microprocessor chip stage fetching said vector address previously transferred to said microprocessor chip stage during said first phase and executing instructions of a specified one of said emulation subroutines designated by said vector address, said executing instructions overlapping said emulation chip stage 22a decoding of a next source instruction, said read out of said vector address and said transfer to said microprocessor chip stage thereby enabling the execution of source instructions in a two-stage overlapped pipelined mode of operation.
a microprocessor chip stage including on-chip instruction and data caches, said on-chip instruction cache storing a plurality of emulation subroutines for said source instructions;
an emulation chip stage coupled to an instruction cache for storing a plurality of source instructions of a program to be emulated by said emulator, said emulation chip stage including:
an instruction unit coupled to said instruction cache for fetching and decoding each source instruction and a subroutine address control store coupled to said instruction unit, said store including a plurality of locations, each for storing a vector address identifying a different one of said plurality of emulation subroutines; and, a bidirectional bus interconnecting said microprocessor and emulation chip stages for transferring information according to a standard protocol, said emulation instruction unit during a first phase of operation, decoding each source instruction fetched from said instruction cache and in accordance with said decoding causing said control store to read out said vector address for transfer to said microprocessor chip stage using said standard protocol and during a second phase of operation, said microprocessor chip stage fetching said vector address previously transferred to said microprocessor chip stage during said first phase and executing instructions of a specified one of said emulation subroutines designated by said vector address, said executing instructions overlapping said emulation chip stage 22a decoding of a next source instruction, said read out of said vector address and said transfer to said microprocessor chip stage thereby enabling the execution of source instructions in a two-stage overlapped pipelined mode of operation.
11. The emulator of claim 10 wherein said microprocessor chip includes branch vector apparatus, said apparatus being connected to said bidirectional bus for receiving and storing each vector address generated and transferred by said emulation chip and said apparatus including output means for generating an external signal on said bus signaling each time said microprocessor chip accesses said each vector address to fetch one of said emulation subroutines from said instruction cache, enabling said emulation chip to transfer a next vector address to said branch vector apparatus thereby eliminating said microprocessor chip having to make off chip accesses.
12. The emulator of claim 1 wherein said branch vector apparatus further includes a branch vector register connected to said bus for receiving and storing said each vector address, read and write indicator means for storing signals received from said microprocessor and emulation chips indicating when said branch vector register has been accessed and updated respectively; and means for connecting said read indicator means to said output means for causing said output means to generate said external signal each time said read indicator means is set to an active state.
13. The emulator of claim 12 wherein said microprocessor chip includes a branch vector instruction facility for testing said write indicator means for determining when said write indicator means is set to an active state enabling said microprocessor chip to branch to one of said plurality of emulator subroutines stored in said instruction cache.
14. The emulator of claim 13 wherein each of said plurality of emulation subroutines includes a plurality of reduced instruction set (RISC) type of instructions and a branch vector instruction as a last one of said plurality of RISC type of instructions coded for fetching a next emulation subroutine.
15. The emulator of claim 3 wherein said emulation chip further includes a subroutine and control store sequencer coupled to a subroutine address control store and instruction decode unit, said instruction decode unit in response to fetching and decoding said each source instruction, generating a starting address for accessing said subroutine address control store, said subroutine control store having a plurality of addressable storage locations for storing microinstructions for controlling emulation chip operations, each of a number of said microinstructions containing said vector address for specifying a starting address of (said) different one of said plurality of emulation subroutines and said control store being connected to said bus, said control store in response to said staring address reading out a specified one of said number of said microinstructions for (applying) one of said number of vector addresses to said bus for transfer to said microprocessor chip (using said standard protocol.)
16. The emulator of claim 15 wherein said subroutine and control store sequencer is connected to receive said external signal from said output means of said microprocessor chip, said sequencer in response to each said external signal advancing said subroutine address control store to access a microinstruction for reading out another one of said number of said microinstructions for generating a next one of said number of vector addresses for transfer to said microprocessor chip during said first phase of operation.
17. The emulator of claim 16 wherein said number of said microinstructions include vector addresses for specifying emulation subroutines for performing address development and execution operation phases required for emulating execution of source instructions by said general purpose computer.
18. A method of operating an emulator having first and second pipeline stages for executing source instructions executable by a general purpose computer in a highly efficient manner, said method comprising the steps of:
(a) fetching, decoding and generating a branch vector address by an emulator chip of said first pipeline stage of said emulator for each source instruction during a first phase of operation;
(b) transferring the branch vector address during said first phase of operation to a microprocessor chip of said second pipeline stage of said emulator through a bidirectional bus interconnecting said chips; and, (c) fetching and executing instructions of one of a plurality of emulation subroutines stored in an on-chip instruction cache of said microprocessor chip specified by the branch vector address transferred during step (b) during a second phase of operation for executing a next source instruction upon completion of the previous source instruction thereby enabling said first and second stages of said emulator to execute each said source instruction in a highly overlapped pipelined fashion.
(a) fetching, decoding and generating a branch vector address by an emulator chip of said first pipeline stage of said emulator for each source instruction during a first phase of operation;
(b) transferring the branch vector address during said first phase of operation to a microprocessor chip of said second pipeline stage of said emulator through a bidirectional bus interconnecting said chips; and, (c) fetching and executing instructions of one of a plurality of emulation subroutines stored in an on-chip instruction cache of said microprocessor chip specified by the branch vector address transferred during step (b) during a second phase of operation for executing a next source instruction upon completion of the previous source instruction thereby enabling said first and second stages of said emulator to execute each said source instruction in a highly overlapped pipelined fashion.
19. The method of claim 18 wherein step c further includes the step of executing a plurality of reduced instruction set (RISC) instructions of said one of said plurality of emulation subroutines for emulating said general purpose computer in executing said each source instruction.
20. A pipelined emulator for executing in a first computer system a set of computer program instructions executable in a different second computer system, said emulator being characterized by a first stage coupled to receive said instructions in sequence, said first stage decoding each one of said received instructions and, in response to said decoding, generating at least one address representation of a memory location holding an emulation subroutine for carrying out at least the partial execution of said one instruction in said first computer system;
a second stage comprising a data processor, a first store for holding data and a second store for holding emulation subroutines, each of said subroutines providing for carrying out at least the partial execution of one of said instructions in said first computer system, said second stage coupled to receive in succession address representations of the locations in said second store of respective ones of said emulation subroutines, and to fetch from said second store and execute the ones of said stored emulation subroutines whose locations in said second store are identified by said received address representations; and an interconnection member coupling together said first and second stages of transmitting said address representations generated by said first stage to said second stage;
whereby, when (i) said first stage is decoding a received instruction, generating a corresponding address representation and applying said address representation to said interconnection member for transmittal to said second stage, concurrently (ii) said second stage is fetching from said second store and executing the one of said stored emulation subroutines whose location in said second store is identified by the address representation previously transmitted from said first stage to said second stage.
a second stage comprising a data processor, a first store for holding data and a second store for holding emulation subroutines, each of said subroutines providing for carrying out at least the partial execution of one of said instructions in said first computer system, said second stage coupled to receive in succession address representations of the locations in said second store of respective ones of said emulation subroutines, and to fetch from said second store and execute the ones of said stored emulation subroutines whose locations in said second store are identified by said received address representations; and an interconnection member coupling together said first and second stages of transmitting said address representations generated by said first stage to said second stage;
whereby, when (i) said first stage is decoding a received instruction, generating a corresponding address representation and applying said address representation to said interconnection member for transmittal to said second stage, concurrently (ii) said second stage is fetching from said second store and executing the one of said stored emulation subroutines whose location in said second store is identified by the address representation previously transmitted from said first stage to said second stage.
21. The emulator of claim 20, further characterized by:
a register coupled to said interconnection means for receiving and holding address representations transmitted over said interconnection means; and means for sensing the fetching of an emulation subroutine held in said second store in response to an address representation held in said register for transmitting a signal over said interconnection means to notify said first stage to transmit the next-succeeding address representation.
a register coupled to said interconnection means for receiving and holding address representations transmitted over said interconnection means; and means for sensing the fetching of an emulation subroutine held in said second store in response to an address representation held in said register for transmitting a signal over said interconnection means to notify said first stage to transmit the next-succeeding address representation.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/546,348 US5430862A (en) | 1990-06-29 | 1990-06-29 | Emulation of CISC instructions by RISC instructions using two pipelined stages for overlapped CISC decoding and RISC execution |
| US546,348 | 1990-06-29 |
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| CA2041507A1 CA2041507A1 (en) | 1991-12-30 |
| CA2041507C true CA2041507C (en) | 1999-04-06 |
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| EP (1) | EP0464494B1 (en) |
| CA (1) | CA2041507C (en) |
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- 1991-06-20 EP EP91110177A patent/EP0464494B1/en not_active Expired - Lifetime
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| US5430862A (en) | 1995-07-04 |
| CA2041507A1 (en) | 1991-12-30 |
| DE69129565D1 (en) | 1998-07-16 |
| EP0464494B1 (en) | 1998-06-10 |
| DE69129565T2 (en) | 1999-03-18 |
| EP0464494A3 (en) | 1993-12-08 |
| EP0464494A2 (en) | 1992-01-08 |
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