CA2030621C - Method and an arrangement for accurate digital determination of the time or phase position of a signal pulse train - Google Patents
Method and an arrangement for accurate digital determination of the time or phase position of a signal pulse trainInfo
- Publication number
- CA2030621C CA2030621C CA002030621A CA2030621A CA2030621C CA 2030621 C CA2030621 C CA 2030621C CA 002030621 A CA002030621 A CA 002030621A CA 2030621 A CA2030621 A CA 2030621A CA 2030621 C CA2030621 C CA 2030621C
- Authority
- CA
- Canada
- Prior art keywords
- signals
- signal
- train
- pulse
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
Abstract
The invention relates to a method and an apparatus for accurate digital determination of the time or phase position of a signal pulse train in relation to a fixed time or frequency reference.
The arrangement generates and produces directly on the output a digital word corresponding to the measuring value current at that time.
The pulse train is compared in a plurality of EXCLUSIVE-OR gates (OR0-OR3) with a number of reference clock signals (RCL0-RCL3) which are mutually displaced in time. There is produced on the output of each gate a signal (MS0-MS3) which is dependent on the input signals of the gates with respect to frequency and pulse ratio. The output signals from the gates are sent to a comparison circuit (CO) in which a MIN of MAX operation is carried out, the pulse ratio of the output signals (MSO-MS3) being compared and the output signal which lies nearest to a predetermined pulse-ratio value being subjected to analogue/digital conversion in a converter (AD). The pulse train, in digital form, is thereafter code-converted in a code converter (CC) together with the three most significant bits taken from the pulse train prior to the AD-conversion process. The thus produced binary code can be corrected for systematic deviations resulting from frequency differences between the frequency, reference frequency and/or sampling frequency of the pulse train, by the addition/subtraction of a predetermined numeric sequence.
The arrangement generates and produces directly on the output a digital word corresponding to the measuring value current at that time.
The pulse train is compared in a plurality of EXCLUSIVE-OR gates (OR0-OR3) with a number of reference clock signals (RCL0-RCL3) which are mutually displaced in time. There is produced on the output of each gate a signal (MS0-MS3) which is dependent on the input signals of the gates with respect to frequency and pulse ratio. The output signals from the gates are sent to a comparison circuit (CO) in which a MIN of MAX operation is carried out, the pulse ratio of the output signals (MSO-MS3) being compared and the output signal which lies nearest to a predetermined pulse-ratio value being subjected to analogue/digital conversion in a converter (AD). The pulse train, in digital form, is thereafter code-converted in a code converter (CC) together with the three most significant bits taken from the pulse train prior to the AD-conversion process. The thus produced binary code can be corrected for systematic deviations resulting from frequency differences between the frequency, reference frequency and/or sampling frequency of the pulse train, by the addition/subtraction of a predetermined numeric sequence.
Description
~3~2:~
A MET}IOD AND AN ~RRANGEMENT FOR ACCUR~TE DIGI'I'~L DETERMININA~rloM
OF THE TIME OR PIIASE POSITION OF A SIGNAL PULSE TR~IN
TECHNICAL FIEI.D
The present invention relates to a method and an arrangement for accurate digital determination of the time or phase position of a signal pulse train relative to a fixed time or frequency referen-ce. The arrangement is operative to generate a digital word which corresponds to the measurement value which is current at that time and produces said value directly on its output.
BACKGROUND ART
Two main methods for determining the time or phase position of a signal pulse train are known to the art. These methods are known respectively as the zero-crossing timing method and the complex vector method.
When practising the zero-crossing method, the desired time information is obtained by registering the position in a referen-ce-divider chain at those moments when the pulse train changes sign.
The time resolution obtained with this method is quite simply one period of the highest reference frequency signal produc~d on the input of the reference frequency-divider chain~ For example, in order to determine the phase position oE a pulse train having a repetition frequency of 1 MHZ with a resolution of 1 degree, it would be necessary to apply a frequency of 360 MHZ to the input of the frequency-divider chain. Consequently, the logic used to determine the phase would need to be very fast, even in the case of low-frequency pulse trains of moderate resolution.
Whenpractising the complexvectormethod, the information desired is assumed to be included in the fundamental sine component of the pulse train. This sine component is filtered-out and resolved into two quadrature components, by correlation with sine and cosine 2~3~2 ~
reference-Erequencies in balanced mixers. Consequently, it i5 then necessary to digitize the two results and to process the arc-tangent of their ratio in a computer in order to determine the phase.
DISCLOSURE OF THE INVENTION
The problem with the first of these methods is that it rec~uires the use of highly advanced loyic, even when carrying out relatively simple phase measurements.
The problem with the second method is that imperfections in the 10 analogue correlators introduce serious limitations into the method in practice, and the need to process the arc-tan in a computer adds greatly to the complexity oE the method.
The inventive arrangement is characterized by the inventive features set forth in the claims and solves the aforesaid pro-15 blems, by being operative to apply the pulse train to a pulseformer (limiter) which generates a square wave having a mark/-space ratio of approximately 50/50. The square wave is applied to N-number of EXCLUSXVE-OR circuits (e.g. 4) together with N-number of reference-frequency signals in the form of square waves, which 20 signals differ in timing progressively by l/Nth of a cycle. The requisite progressive time difference can be obtained, either by commencing with a high fre~uency and dividing said frequency down, or by utilizing delay lines. It is unimportant to the process which of these methods is used. The mark/space ratio between the 25 N-output signals from the EXCLUSIVE-OR circuits are mutually compared in comparison circuits in order to establish in which of N-rough phase-sectors the signal phase lies. The signal which lies nearest the pulse ratio 50/50 is then selected, filtered in a low-pass filter and digitized in an analogue/digital converter to form 30 a binary code which provides finer phase information within the rough sector that has already been determined. The advantages afforded by the inventive arrangement over known techniques are that time measurements or determinations can be made with an accuracy greater than one period of the highest possible frequency . ~ .
A MET}IOD AND AN ~RRANGEMENT FOR ACCUR~TE DIGI'I'~L DETERMININA~rloM
OF THE TIME OR PIIASE POSITION OF A SIGNAL PULSE TR~IN
TECHNICAL FIEI.D
The present invention relates to a method and an arrangement for accurate digital determination of the time or phase position of a signal pulse train relative to a fixed time or frequency referen-ce. The arrangement is operative to generate a digital word which corresponds to the measurement value which is current at that time and produces said value directly on its output.
BACKGROUND ART
Two main methods for determining the time or phase position of a signal pulse train are known to the art. These methods are known respectively as the zero-crossing timing method and the complex vector method.
When practising the zero-crossing method, the desired time information is obtained by registering the position in a referen-ce-divider chain at those moments when the pulse train changes sign.
The time resolution obtained with this method is quite simply one period of the highest reference frequency signal produc~d on the input of the reference frequency-divider chain~ For example, in order to determine the phase position oE a pulse train having a repetition frequency of 1 MHZ with a resolution of 1 degree, it would be necessary to apply a frequency of 360 MHZ to the input of the frequency-divider chain. Consequently, the logic used to determine the phase would need to be very fast, even in the case of low-frequency pulse trains of moderate resolution.
Whenpractising the complexvectormethod, the information desired is assumed to be included in the fundamental sine component of the pulse train. This sine component is filtered-out and resolved into two quadrature components, by correlation with sine and cosine 2~3~2 ~
reference-Erequencies in balanced mixers. Consequently, it i5 then necessary to digitize the two results and to process the arc-tangent of their ratio in a computer in order to determine the phase.
DISCLOSURE OF THE INVENTION
The problem with the first of these methods is that it rec~uires the use of highly advanced loyic, even when carrying out relatively simple phase measurements.
The problem with the second method is that imperfections in the 10 analogue correlators introduce serious limitations into the method in practice, and the need to process the arc-tan in a computer adds greatly to the complexity oE the method.
The inventive arrangement is characterized by the inventive features set forth in the claims and solves the aforesaid pro-15 blems, by being operative to apply the pulse train to a pulseformer (limiter) which generates a square wave having a mark/-space ratio of approximately 50/50. The square wave is applied to N-number of EXCLUSXVE-OR circuits (e.g. 4) together with N-number of reference-frequency signals in the form of square waves, which 20 signals differ in timing progressively by l/Nth of a cycle. The requisite progressive time difference can be obtained, either by commencing with a high fre~uency and dividing said frequency down, or by utilizing delay lines. It is unimportant to the process which of these methods is used. The mark/space ratio between the 25 N-output signals from the EXCLUSIVE-OR circuits are mutually compared in comparison circuits in order to establish in which of N-rough phase-sectors the signal phase lies. The signal which lies nearest the pulse ratio 50/50 is then selected, filtered in a low-pass filter and digitized in an analogue/digital converter to form 30 a binary code which provides finer phase information within the rough sector that has already been determined. The advantages afforded by the inventive arrangement over known techniques are that time measurements or determinations can be made with an accuracy greater than one period of the highest possible frequency . ~ .
3 2 ~
ofthe reference clock, therewithenabling the operating frequency ofthe arrangemerlt to be increased without requiring the provision of very high-speed logic. Furthermore, i-t is not necessary for the reference clock to be related precisely to the frequency of the pulse train to be measured.
BRIEF DESCRIPTION OF THE DRAWINGS
The inventive arrangement will now be described in more detail with reference to an exemplifying embodiment thereoE and with reference to the accompanying drawings, in which Figure 1 illustrates pulse-forming and time-displacement of the signals;
Figure 2 illustrates how the pulse ratio (mark/space) varies on the outputs of the EXCLUSIVE-OR circuits;
Figure 3 is a circuit diagram of an inventive comparison circuit;
and Figure 4 is a block schematic of an inventive arrangement.
BEST MODE OF CARRYING OUT THE INVENTION
As evident from Figure 1, a pulse train WT in analogue form is applied to the input of a limiter L. The limiter pulse-Eorms the signal so as to produce on the output of the limiter a square wave having the pulse ratio (mark/space) 50/50 ~ The square wave is applied to a first input of each of N number of EXCLUSIVE-OR
gates, in the illustrated embodiment four gates. A reference clock signal RCLO-RCL3 is applied to a second input of each of said gates, said gates being referenced ORO-OR3. Each of these reference-clock signals are square wave signals and are mutually displaced in time and in sequence by l/N of a cycle. The output signal from each EXCL~SIVE-OR gate is a square wave signal MSO-MS3 having twice the frequency of the input-signal frequency of respective gates and having a mark/space ratio depending on the mutual clocking of the two input signals of the gates, as evident from the diagram o~ Figure 2. The diagram shows variations in the mark/space ratio for the output signals MSO-MS3 from the gates s~ ~ 3 ~
ORO-OR3 as a function o e pUlSQ train clocking in rela-tion to reference-clock-timing.
Efforts to derive the mutual clocking of the two input signals from the outpu-t signal of one single EXCLUSIVE-OR gate will introduce some element of doubt, sin~e it is impossible to ascer-tain positively which 180 degree ranye contains the phase, but this problem is solved by mutually c~mparing the output signals ~rom a plurality of EXCLUSIVE OR gates. For instance, when N e-quals 4, in accordance with the illustrated embodiment, it is possible to determine immediately within which 1/8th of the reference-clock period the transitions of the input signal fall.
This is effected by comparison between the mark/space ratio of the output signals of the gates ORO-OR3 in accordance with the following MIN of MAX operation:
Table 1 If MSO > MS2 then let B1 = 0 else Bl = 1 If MS1 > MS3 then let B2 = 0 else B2 = 1 If MAX (MSO,MS2)> MAX (MSl,MS3) let B3 = O else B3=1.
Bl, B2 and B3 determine the three most significant bits in the desired time measuring process subsequent to appropriate code conversion from Gray to Binary form or some other output-signal code.
The 3-bit word B1, B2, B3 now has a 1:1 agreement with the octant within which the zero-crossing clocking of the signal lies The aforesaid described Min of Max-operation can be implemented, for instance, with the aid of a combination of NPN and PNP emitter-followers, as illustrated in Figure 3, although it canl alterna-tively, be realized with the aid of comparison circuits tcompara-tors), switches and logic circuits. Figure 3 thus illustrates one method o~ determining the three most significant bits of the prevailing measurement value in accordance with Table 1.
In order to be able to determine the three least significant bits LSB when measuring time, it is necessary to determine the mark/sp-ace ratio of the signal on the output of at least one of the 20~3~ A
EXCLUSIVE-OR gates OR0-OR3 more accurately. In prac-tice, it is beneficial to choose the gate whose mark/space ratio lies closest to 50/50, since this pulse-form is less sensitive ko distortion as a result of the restricted rise times of slow hardware logic. In this case, the three most significant bits Bl, B2, B3 determined in accordance with the aforegoing are used to select for finer an-alysis the pulse which has this property. This is the pulse which remains subsequent to the MIN of MAX operation.
i As will be seen from Figure 4, this finer measurement of the mark/space ratio can be effected with the aid of low~pass filters LP0-LP3 for extraction of the mean value of the signal, followed by analogue /digital conversion in an A/D-converter AD. In the case of a high-speed application, a 4-bit A/D-converter of the "FL~SH"-type can be used for instance. ~he inputs of respective low~pass filters are connected to corresponding outputs of the EXCLUSIVE-OR circuits OR0-OR3. The filter outputs are connected to inputs of a comparison circuit CO and to the inputs of a multiplexor M. The outputs from the comparison circuit, i.e. the most significant bits Bl, B2 and B3, are applied to inputs on the multiplexor M for the purpose of controlling the selection of that gate output-signal (MS0-MS3) whose pulse ratio lies closest to 50/50. The most significant bits are also applied to inputs on a code converter CC. The code converter is constructed either of discrete logic gates or can be a look-up table in an ROM-memory.
The memory address consists of the three bits ~l,B2,B3 and the bits (four or more) which constitute the result of said A/D-conversion. The memory content consists of the desired output code corresponding to each possible input bit-pattern. The output signal from the multiplexor M is applied to the input of said A/D-converter AD, the outputs of which are connected to correspondinginputs on said code converter CC, the outputs of which, in turn, deliver binary coded signals. When a 4-bit A/D-converter is combined, in this way, with the three most significant bits Bl,B2,B3 an accuracy of 7 bits i5 obtained during the phase-measuring process. Consequently, clocking, e.g., of a pulse trainwhose repetition frequency is 1 MHZ can be determined with a 2 0 3 ~ 'L
resolution of 1/128 ~s (8 ns) without needing to utili~e more than 1 MHZ reference clock-Erequency.
IE it is desired that a conventional binary code shall represent the timing measurement, it is necessa;ry-to convert the three most significant bits from the Gray code to binary code and to comple-ment the three least significant bits LSB in alternating octants.
This can be effected with conventiona:L logic, tables or software.
Binary code-representation will facilitate correction of the output value for any difference whatsoever between the reference clock and the expected Erequency of the pulse train. Assume that the expected nominal frequency of the pulse train is 1 000 003 HZ
but that the frequency of the available reference clocks is precisely 1 000 000 HZ. Assume ~or the sake of simplicity that the measuring accuracy is 7 bits and that 128 measurements are made each second. The sequence of hinary values prior to correc-tion will then have the following configuration for instance:
...... 59,62,65, ...... ,122,125,0,3,6,9, which illustrates a stepwise increase of 3, modulo 128, depending on said 3 HZ frequency difference. This can be corrected with the aid of a 7-bit external memory whose content is increased with 3, modulo 128, on each sampling occasion, this value being subtracted from the measurement value prior to transmitting an output signal.
A similar technique can also be used when the relationship between sampling period and reference-frequency deviation is more complex and can, for instance, involve increasing the word length of the memory with part quantities, or involve storing a full cycle of correction values in the memory.
This shows that arithmetic configured in software or hardware logic can be utilized for compensating non-integer relationships between the midfrequency, reference clocks and measurement frequency (sampling rate~ of the pulse train.
' :;
~. ~
2~3~
As will be evident from the aforegoing, the inventive arrangement enables a significant improvement in measuring accuracy to be achievedwithoutrequiring theprovision ofvery high-speed logic.
, ~ .
ofthe reference clock, therewithenabling the operating frequency ofthe arrangemerlt to be increased without requiring the provision of very high-speed logic. Furthermore, i-t is not necessary for the reference clock to be related precisely to the frequency of the pulse train to be measured.
BRIEF DESCRIPTION OF THE DRAWINGS
The inventive arrangement will now be described in more detail with reference to an exemplifying embodiment thereoE and with reference to the accompanying drawings, in which Figure 1 illustrates pulse-forming and time-displacement of the signals;
Figure 2 illustrates how the pulse ratio (mark/space) varies on the outputs of the EXCLUSIVE-OR circuits;
Figure 3 is a circuit diagram of an inventive comparison circuit;
and Figure 4 is a block schematic of an inventive arrangement.
BEST MODE OF CARRYING OUT THE INVENTION
As evident from Figure 1, a pulse train WT in analogue form is applied to the input of a limiter L. The limiter pulse-Eorms the signal so as to produce on the output of the limiter a square wave having the pulse ratio (mark/space) 50/50 ~ The square wave is applied to a first input of each of N number of EXCLUSIVE-OR
gates, in the illustrated embodiment four gates. A reference clock signal RCLO-RCL3 is applied to a second input of each of said gates, said gates being referenced ORO-OR3. Each of these reference-clock signals are square wave signals and are mutually displaced in time and in sequence by l/N of a cycle. The output signal from each EXCL~SIVE-OR gate is a square wave signal MSO-MS3 having twice the frequency of the input-signal frequency of respective gates and having a mark/space ratio depending on the mutual clocking of the two input signals of the gates, as evident from the diagram o~ Figure 2. The diagram shows variations in the mark/space ratio for the output signals MSO-MS3 from the gates s~ ~ 3 ~
ORO-OR3 as a function o e pUlSQ train clocking in rela-tion to reference-clock-timing.
Efforts to derive the mutual clocking of the two input signals from the outpu-t signal of one single EXCLUSIVE-OR gate will introduce some element of doubt, sin~e it is impossible to ascer-tain positively which 180 degree ranye contains the phase, but this problem is solved by mutually c~mparing the output signals ~rom a plurality of EXCLUSIVE OR gates. For instance, when N e-quals 4, in accordance with the illustrated embodiment, it is possible to determine immediately within which 1/8th of the reference-clock period the transitions of the input signal fall.
This is effected by comparison between the mark/space ratio of the output signals of the gates ORO-OR3 in accordance with the following MIN of MAX operation:
Table 1 If MSO > MS2 then let B1 = 0 else Bl = 1 If MS1 > MS3 then let B2 = 0 else B2 = 1 If MAX (MSO,MS2)> MAX (MSl,MS3) let B3 = O else B3=1.
Bl, B2 and B3 determine the three most significant bits in the desired time measuring process subsequent to appropriate code conversion from Gray to Binary form or some other output-signal code.
The 3-bit word B1, B2, B3 now has a 1:1 agreement with the octant within which the zero-crossing clocking of the signal lies The aforesaid described Min of Max-operation can be implemented, for instance, with the aid of a combination of NPN and PNP emitter-followers, as illustrated in Figure 3, although it canl alterna-tively, be realized with the aid of comparison circuits tcompara-tors), switches and logic circuits. Figure 3 thus illustrates one method o~ determining the three most significant bits of the prevailing measurement value in accordance with Table 1.
In order to be able to determine the three least significant bits LSB when measuring time, it is necessary to determine the mark/sp-ace ratio of the signal on the output of at least one of the 20~3~ A
EXCLUSIVE-OR gates OR0-OR3 more accurately. In prac-tice, it is beneficial to choose the gate whose mark/space ratio lies closest to 50/50, since this pulse-form is less sensitive ko distortion as a result of the restricted rise times of slow hardware logic. In this case, the three most significant bits Bl, B2, B3 determined in accordance with the aforegoing are used to select for finer an-alysis the pulse which has this property. This is the pulse which remains subsequent to the MIN of MAX operation.
i As will be seen from Figure 4, this finer measurement of the mark/space ratio can be effected with the aid of low~pass filters LP0-LP3 for extraction of the mean value of the signal, followed by analogue /digital conversion in an A/D-converter AD. In the case of a high-speed application, a 4-bit A/D-converter of the "FL~SH"-type can be used for instance. ~he inputs of respective low~pass filters are connected to corresponding outputs of the EXCLUSIVE-OR circuits OR0-OR3. The filter outputs are connected to inputs of a comparison circuit CO and to the inputs of a multiplexor M. The outputs from the comparison circuit, i.e. the most significant bits Bl, B2 and B3, are applied to inputs on the multiplexor M for the purpose of controlling the selection of that gate output-signal (MS0-MS3) whose pulse ratio lies closest to 50/50. The most significant bits are also applied to inputs on a code converter CC. The code converter is constructed either of discrete logic gates or can be a look-up table in an ROM-memory.
The memory address consists of the three bits ~l,B2,B3 and the bits (four or more) which constitute the result of said A/D-conversion. The memory content consists of the desired output code corresponding to each possible input bit-pattern. The output signal from the multiplexor M is applied to the input of said A/D-converter AD, the outputs of which are connected to correspondinginputs on said code converter CC, the outputs of which, in turn, deliver binary coded signals. When a 4-bit A/D-converter is combined, in this way, with the three most significant bits Bl,B2,B3 an accuracy of 7 bits i5 obtained during the phase-measuring process. Consequently, clocking, e.g., of a pulse trainwhose repetition frequency is 1 MHZ can be determined with a 2 0 3 ~ 'L
resolution of 1/128 ~s (8 ns) without needing to utili~e more than 1 MHZ reference clock-Erequency.
IE it is desired that a conventional binary code shall represent the timing measurement, it is necessa;ry-to convert the three most significant bits from the Gray code to binary code and to comple-ment the three least significant bits LSB in alternating octants.
This can be effected with conventiona:L logic, tables or software.
Binary code-representation will facilitate correction of the output value for any difference whatsoever between the reference clock and the expected Erequency of the pulse train. Assume that the expected nominal frequency of the pulse train is 1 000 003 HZ
but that the frequency of the available reference clocks is precisely 1 000 000 HZ. Assume ~or the sake of simplicity that the measuring accuracy is 7 bits and that 128 measurements are made each second. The sequence of hinary values prior to correc-tion will then have the following configuration for instance:
...... 59,62,65, ...... ,122,125,0,3,6,9, which illustrates a stepwise increase of 3, modulo 128, depending on said 3 HZ frequency difference. This can be corrected with the aid of a 7-bit external memory whose content is increased with 3, modulo 128, on each sampling occasion, this value being subtracted from the measurement value prior to transmitting an output signal.
A similar technique can also be used when the relationship between sampling period and reference-frequency deviation is more complex and can, for instance, involve increasing the word length of the memory with part quantities, or involve storing a full cycle of correction values in the memory.
This shows that arithmetic configured in software or hardware logic can be utilized for compensating non-integer relationships between the midfrequency, reference clocks and measurement frequency (sampling rate~ of the pulse train.
' :;
~. ~
2~3~
As will be evident from the aforegoing, the inventive arrangement enables a significant improvement in measuring accuracy to be achievedwithoutrequiring theprovision ofvery high-speed logic.
, ~ .
Claims (9)
1. A method for accurate digital determination of the time or phase position of a signal pulse-train in a telecommunication system, including the steps of:
forming a square-wave pulse-train from the signal pulse-train;
comparing the square-wave pulse-train with a plurality of mutually time-displaced square-wave reference signals to form a plurality of new signals having mark/space ratios in dependence on said comparisons;
mutually comparing the plurality of new signals in a MIN of MAX operation to coarsely determine the time or phase position of the signal pulse-train;
selecting the new signal whose mark/space ratio lies nearest to a predetermined mark/space ratio;
converting the selected new signal to digital form; and applying the coarsely determined time or phase position of the signal pulse-train and the digitized selected new signal to a code converter for producing a binary code value representing the time or phase position of the signal pulse-train;
wherein the binary code value can be corrected in respect of systematic deviations resulting from frequency differences among the pulse-train's frequency, the reference signals' frequency and/or a sampling frequency of the pulse-train, by addition/subtraction of a predetermined numerical sequence.
forming a square-wave pulse-train from the signal pulse-train;
comparing the square-wave pulse-train with a plurality of mutually time-displaced square-wave reference signals to form a plurality of new signals having mark/space ratios in dependence on said comparisons;
mutually comparing the plurality of new signals in a MIN of MAX operation to coarsely determine the time or phase position of the signal pulse-train;
selecting the new signal whose mark/space ratio lies nearest to a predetermined mark/space ratio;
converting the selected new signal to digital form; and applying the coarsely determined time or phase position of the signal pulse-train and the digitized selected new signal to a code converter for producing a binary code value representing the time or phase position of the signal pulse-train;
wherein the binary code value can be corrected in respect of systematic deviations resulting from frequency differences among the pulse-train's frequency, the reference signals' frequency and/or a sampling frequency of the pulse-train, by addition/subtraction of a predetermined numerical sequence.
2. The method of claim 1, wherein the step of mutually comparing the plurality of new signals in a MIN of MAX
operation includes the steps of low-pass filtering the plurality of new signals and mutually comparing the low-pass filtered new signals.
operation includes the steps of low-pass filtering the plurality of new signals and mutually comparing the low-pass filtered new signals.
3. The method of claim 1 or 2, wherein the predetermined mark/space ratio is 50:50, and the step of selecting the new signal whose mark/space ratio lies nearest to the predetermined mark/space ratio is based on the MIN of MAX operation.
4. The method of claim 3, wherein the selecting step includes the steps of applying low-pass filtered new signals to a multiplexer and causing the multiplexer to select one of the low-pass filtered new signals based on the coarsely determined time or phase position of the signal pulse-train produced by the MIN of MAX operation, and the selected new signal is converted to digital form by applying the selected new signal to an analog-to-digital converter.
5. An arrangement for accurately digitally determining the time or phase position of a signal pulse-train in a telecommunications system including:
a limiter for forming a square-wave pulse-train from the signal pulse-train;
a plurality of EXCLUSIVE-OR gates, one input of each gate receiving the square-wave pulse-train;
means for generating a plurality of reference clock signals, a respective one of the reference clock signals being applied to a second input of each of the gates, said reference clock signals being displaced sequentially in time in relation to one another, each of the gates producing an output signal having a frequency and a mark/space ratio which is contingent on the ratio between the signals on its first and second inputs;
a multiplexor for selecting one of the output signals;
a comparison circuit in which a MIN of MAX operation is carried out on the output signals, whereby the mark/space ratios of the output signals are mutually compared and that one of said output signals having a mark/space ratio value which lies closest to a predetermined mark/space ratio value is determined, that one output signal being selected by said multiplexor and applied to an input of an analogue/digital converter; and a code converter, wherein the code converter receives on a first number of inputs a signal from the analogue/digital converter and on a second number of inputs a signal from the comparison circuit, and the code converter converts the signals on said first and second number of inputs to signals in binary form which are produced on outputs of the converter and which represent the time or phase position of the signal pulse-train.
a limiter for forming a square-wave pulse-train from the signal pulse-train;
a plurality of EXCLUSIVE-OR gates, one input of each gate receiving the square-wave pulse-train;
means for generating a plurality of reference clock signals, a respective one of the reference clock signals being applied to a second input of each of the gates, said reference clock signals being displaced sequentially in time in relation to one another, each of the gates producing an output signal having a frequency and a mark/space ratio which is contingent on the ratio between the signals on its first and second inputs;
a multiplexor for selecting one of the output signals;
a comparison circuit in which a MIN of MAX operation is carried out on the output signals, whereby the mark/space ratios of the output signals are mutually compared and that one of said output signals having a mark/space ratio value which lies closest to a predetermined mark/space ratio value is determined, that one output signal being selected by said multiplexor and applied to an input of an analogue/digital converter; and a code converter, wherein the code converter receives on a first number of inputs a signal from the analogue/digital converter and on a second number of inputs a signal from the comparison circuit, and the code converter converts the signals on said first and second number of inputs to signals in binary form which are produced on outputs of the converter and which represent the time or phase position of the signal pulse-train.
6. An arrangement according to claim 5, wherein the signal from the comparison circuit constitutes the three most significant bits of the time or phase position of the signal pulse-train.
7. An arrangement according to claim 5 or 6, wherein said predetermined mark/space ratio value is 50/50.
8. An arrangement according to claim 5, 6 or 7, wherein the time-displacement between the reference clock signals is 1/Nth of a clock period when the number of reference clock signals is N.
9. An arrangement according to any one of claims 5 to 8, wherein the gates' output signals are connected to corresponding inputs of a plurality of low-pass filters and outputs from the filters are connected to the comparison circuit and the multiplexor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE8901441A SE463584B (en) | 1989-04-20 | 1989-04-20 | SET AND DEVICE PROVIDES ANY DIGITAL SEATING OF THE TIME OR PHASES OF A SIGNAL PULSE TAG |
| SE8901441-9 | 1989-04-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2030621A1 CA2030621A1 (en) | 1990-10-21 |
| CA2030621C true CA2030621C (en) | 1998-07-07 |
Family
ID=20375741
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002030621A Expired - Fee Related CA2030621C (en) | 1989-04-20 | 1990-03-28 | Method and an arrangement for accurate digital determination of the time or phase position of a signal pulse train |
Country Status (16)
| Country | Link |
|---|---|
| US (1) | US5148373A (en) |
| EP (1) | EP0394206B1 (en) |
| JP (1) | JP3286844B2 (en) |
| KR (1) | KR960011533B1 (en) |
| CN (1) | CN1046607A (en) |
| AT (1) | ATE120012T1 (en) |
| AU (1) | AU622552B2 (en) |
| CA (1) | CA2030621C (en) |
| DE (1) | DE69017741T2 (en) |
| DK (1) | DK0394206T3 (en) |
| ES (1) | ES2069058T3 (en) |
| HK (1) | HK84595A (en) |
| NZ (1) | NZ233118A (en) |
| PT (1) | PT93817A (en) |
| SE (1) | SE463584B (en) |
| WO (1) | WO1990013040A1 (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5351016A (en) * | 1993-05-28 | 1994-09-27 | Ericsson Ge Mobile Communications Inc. | Adaptively self-correcting modulation system and method |
| AU678626B2 (en) * | 1993-10-14 | 1997-06-05 | Ericsson Ge Mobile Communications Inc. | Adaptive bandwidth receiver |
| US5668837A (en) * | 1993-10-14 | 1997-09-16 | Ericsson Inc. | Dual-mode radio receiver for receiving narrowband and wideband signals |
| US5751762A (en) * | 1996-02-15 | 1998-05-12 | Ericsson Inc. | Multichannel receiver using analysis by synthesis |
| US6205183B1 (en) | 1998-05-29 | 2001-03-20 | Ericsson Inc. | Methods of suppressing reference oscillator harmonic interference and related receivers |
| US6101454A (en) * | 1998-11-23 | 2000-08-08 | The United States Of America As Represented By The Secretary Of The Navy | Apparatus to oscillograph single sub-nanosecond events |
| US6278867B1 (en) | 1998-11-25 | 2001-08-21 | Ericsson Inc. | Methods and systems for frequency generation for wireless devices |
| US6567475B1 (en) | 1998-12-29 | 2003-05-20 | Ericsson Inc. | Method and system for the transmission, reception and processing of 4-level and 8-level signaling symbols |
| US6310570B1 (en) * | 1999-06-04 | 2001-10-30 | Thomson Licensing S.A. | System with adjustable ADC clock phase |
| US7689639B2 (en) | 2004-06-04 | 2010-03-30 | Telefonaktiebolaget Lm Ericsson (Publ) | Complex logarithmic ALU |
| US7711764B2 (en) * | 2004-06-04 | 2010-05-04 | Telefonaktiebolaget Lm Ericsson (Publ) | Pipelined real or complex ALU |
| US8316068B2 (en) | 2004-06-04 | 2012-11-20 | Telefonaktiebolaget Lm Ericsson (Publ) | Memory compression |
| US20070133598A1 (en) * | 2005-12-12 | 2007-06-14 | Patrick Moran | System and method for determining position of communicating devices |
| FR2901911B1 (en) * | 2006-06-02 | 2008-08-01 | Schneider Electric Ind Sas | METHOD AND DEVICE FOR SAMPLING ELECTRIC SIGNALS OF A MULTIPHASED ELECTRICAL SYSTEM |
| CN105445552B (en) * | 2015-07-09 | 2018-07-27 | 深圳市科润宝实业有限公司 | The first phase position detecting method and system of sinusoidal signal |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1547360A (en) * | 1975-12-01 | 1979-06-13 | Gen Electric Co Ltd | Apparatus for indicating the sequence of alternating current signals |
| US4157500A (en) * | 1977-10-31 | 1979-06-05 | Societe d'Exploitation de Produits et de Techniques pour l'Aeronautique & l'Automatique | Multiperiodical phasemeter |
| US4178631A (en) * | 1978-02-13 | 1979-12-11 | Tractor, Inc. | Digital phase detector and method |
| US4183087A (en) * | 1978-03-07 | 1980-01-08 | Hughes Aircraft Company | Peak deviation sampling |
| JPS6046885B2 (en) * | 1978-05-17 | 1985-10-18 | 株式会社リコー | Phase detection method |
| US4318617A (en) * | 1979-12-14 | 1982-03-09 | Keuffel & Esser Company | DC Shift error correction for electro-optical measuring system |
| DE3153249C2 (en) * | 1981-06-03 | 1988-12-08 | Ant Nachrichtentechnik Gmbh, 7150 Backnang, De | Phase discriminator arrangement |
| US4800508A (en) * | 1986-06-30 | 1989-01-24 | Eaton Corporation | Frequency detector |
| EP0265080B1 (en) * | 1986-09-25 | 1991-11-27 | Nec Corporation | Device for detecting bit phase difference |
| FR2615626B1 (en) * | 1987-05-21 | 1989-07-28 | Alcatel Espace | METHOD FOR DIGITAL EVALUATION OF THE FREQUENCY AND PHASE OF SIGNALS AND DEVICES FOR CARRYING OUT SUCH A METHOD |
| AU606559B2 (en) * | 1987-12-24 | 1991-02-07 | Nec Corporation | Circuit for comparing a plurality of binary inputs |
| CA1298386C (en) * | 1988-05-25 | 1992-03-31 | Paul Langner | Intrapulse radar receiver |
| US4998219A (en) * | 1989-02-16 | 1991-03-05 | Ail Systems, Inc. | Method and apparatus for determining the greatest value of a binary number and for minimizing any uncertainty associated with the determination |
| US4996647A (en) * | 1989-03-27 | 1991-02-26 | Sperry Marine Inc. | Digital statistical processing for signal parameter determination |
-
1989
- 1989-04-20 SE SE8901441A patent/SE463584B/en not_active IP Right Cessation
-
1990
- 1990-03-28 DE DE69017741T patent/DE69017741T2/en not_active Expired - Lifetime
- 1990-03-28 KR KR1019900702489A patent/KR960011533B1/en not_active IP Right Cessation
- 1990-03-28 AU AU55544/90A patent/AU622552B2/en not_active Ceased
- 1990-03-28 WO PCT/SE1990/000200 patent/WO1990013040A1/en active Application Filing
- 1990-03-28 AT AT90850118T patent/ATE120012T1/en not_active IP Right Cessation
- 1990-03-28 CA CA002030621A patent/CA2030621C/en not_active Expired - Fee Related
- 1990-03-28 NZ NZ233118A patent/NZ233118A/en unknown
- 1990-03-28 JP JP50702490A patent/JP3286844B2/en not_active Expired - Lifetime
- 1990-03-28 DK DK90850118.2T patent/DK0394206T3/en active
- 1990-03-28 EP EP90850118A patent/EP0394206B1/en not_active Expired - Lifetime
- 1990-03-28 ES ES90850118T patent/ES2069058T3/en not_active Expired - Lifetime
- 1990-03-30 US US07/501,766 patent/US5148373A/en not_active Expired - Lifetime
- 1990-04-19 PT PT93817A patent/PT93817A/en not_active Application Discontinuation
- 1990-04-20 CN CN90102465A patent/CN1046607A/en active Pending
-
1995
- 1995-06-01 HK HK84595A patent/HK84595A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US5148373A (en) | 1992-09-15 |
| CN1046607A (en) | 1990-10-31 |
| JPH03505635A (en) | 1991-12-05 |
| DK0394206T3 (en) | 1995-07-10 |
| HK84595A (en) | 1995-06-09 |
| EP0394206A2 (en) | 1990-10-24 |
| ES2069058T3 (en) | 1995-05-01 |
| PT93817A (en) | 1990-11-20 |
| AU622552B2 (en) | 1992-04-09 |
| KR920700404A (en) | 1992-02-19 |
| KR960011533B1 (en) | 1996-08-23 |
| AU5554490A (en) | 1990-11-16 |
| JP3286844B2 (en) | 2002-05-27 |
| SE8901441L (en) | 1990-10-21 |
| SE463584B (en) | 1990-12-10 |
| EP0394206B1 (en) | 1995-03-15 |
| CA2030621A1 (en) | 1990-10-21 |
| DE69017741D1 (en) | 1995-04-20 |
| NZ233118A (en) | 1992-01-29 |
| ATE120012T1 (en) | 1995-04-15 |
| EP0394206A3 (en) | 1991-12-11 |
| SE8901441D0 (en) | 1989-04-20 |
| DE69017741T2 (en) | 1995-07-13 |
| WO1990013040A1 (en) | 1990-11-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2030621C (en) | Method and an arrangement for accurate digital determination of the time or phase position of a signal pulse train | |
| US3836908A (en) | Digital to analog converter | |
| US3656152A (en) | Improved a-d/d-a converter system | |
| US20030067354A1 (en) | Analog frequency locked loop with digital oversampling feedback control and filter | |
| EP0414953B1 (en) | Position detection device | |
| JPS61296843A (en) | Signal/noise ratio exponent generation apparatus and method for coding digital data | |
| US4071903A (en) | Autocorrelation function factor generating method and circuitry therefor | |
| US4974234A (en) | Method of and circuit for the measurement of jitter modulation of zero-related digital signals | |
| US4937579A (en) | Method of converting analog signals into digital signals and system for carrying out the method | |
| EP0191478B1 (en) | Measurement circuit for evaluating a digital-to-analog converter | |
| US5034977A (en) | Phase accumulation dual tone multiple frequency generator | |
| US4130799A (en) | Method and apparatus for continuous frequency measurement | |
| US6107890A (en) | Digital phase comparator and frequency synthesizer | |
| US3761916A (en) | Analog to digital converter | |
| US3678399A (en) | Method of and apparatus for electronically obtaining the argument of a complex function | |
| JPH01170221A (en) | Analog digital converter | |
| SU1272271A1 (en) | Digital spectrum analyzer | |
| JPH0267010A (en) | Analog-digital converter | |
| JPH0552882A (en) | Frequency measuring circuit | |
| SU1360550A1 (en) | Device for measuring errors of a-d converters | |
| JPH0125335Y2 (en) | ||
| SU1298679A1 (en) | Digital spectrum analyzer | |
| JPH01167677A (en) | Electric power detector | |
| US3665456A (en) | Method of and apparatus for analog-to-digital conversion of physical values and their ratios | |
| JPH0513404B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |