CA2022239A1 - Programmable fault insertion arrangement and method - Google Patents
Programmable fault insertion arrangement and methodInfo
- Publication number
- CA2022239A1 CA2022239A1 CA 2022239 CA2022239A CA2022239A1 CA 2022239 A1 CA2022239 A1 CA 2022239A1 CA 2022239 CA2022239 CA 2022239 CA 2022239 A CA2022239 A CA 2022239A CA 2022239 A1 CA2022239 A1 CA 2022239A1
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- fault
- command
- data
- data terminal
- circuit
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Abstract
A PROGRAMMABLE FAULT INSERTION ARRANGEMENT AND METHOD
ABSTRACT
A method for controlling a fault insertion circuit is disclosed that is arranged to generate and apply a fault signal to a digital circuit under test. First, a prompt request command is transmited to the fault insertion circuit from the data terminal. The fault insertion circuit receives the prompt request command and transmits to the data terminal a hardware fault response character if a hardware fault has been detect-ed, or a configuration status response character. An insertion command and fault instruction data is trans-mitted to the fault insertion circuit from the data terminal in response to the configuration status re-sponse character. The fault insertion circuit receives the insertion command and fault instruction data and ascertains if the insertion command and the data instruction are valid. If the command or the instruction are invalid, then an appropriate invalid command response character is transmitted to the data terminal. When the insertion command and instruction data are valid, the fault insertion circuit induces a fault to the digital circuit under test in accordance with the parameters of the data instruction. Finally, a completed response character is transmitted to the data terminal from the fault insertion circuit when the insertion command is successfully completed.
ABSTRACT
A method for controlling a fault insertion circuit is disclosed that is arranged to generate and apply a fault signal to a digital circuit under test. First, a prompt request command is transmited to the fault insertion circuit from the data terminal. The fault insertion circuit receives the prompt request command and transmits to the data terminal a hardware fault response character if a hardware fault has been detect-ed, or a configuration status response character. An insertion command and fault instruction data is trans-mitted to the fault insertion circuit from the data terminal in response to the configuration status re-sponse character. The fault insertion circuit receives the insertion command and fault instruction data and ascertains if the insertion command and the data instruction are valid. If the command or the instruction are invalid, then an appropriate invalid command response character is transmitted to the data terminal. When the insertion command and instruction data are valid, the fault insertion circuit induces a fault to the digital circuit under test in accordance with the parameters of the data instruction. Finally, a completed response character is transmitted to the data terminal from the fault insertion circuit when the insertion command is successfully completed.
Description
A PROGRAMMABLE FAULT INSERTION ARRANGEMENT AND METHOD
CROSS REFERENCE TQ RELATED APPLICATIONS
Cross Reference is made to the related U.S. Patent Applications entitled, IlA PROGRAMMABLE FAULT INSERTION
CIRCUIT," (Docket 88-7-017), filed on the same date, and by the same inventors as this Application.
FIELD OF THE INVENTION
The present invention relates to the field of electronic test devices, and more particularly, to a lo programmable device for insert.ing faults into an elec-tronic digital circuit.
~5~L~CC~C~ HE INVENTION
Fault insertion, is the means by which logic faults are introduced into an electronic digital circuit.~
Logic faults are operator induced logic signals such as ~ -a logic "high" or loyic "low" that are deliberately injected into a digital electronic circuit. The circuit is then monitored to ascertain if it responded correctly to the fault. For example, in a digital circuit having the capability to sense such failures and to send messages to a controller, an inserted fault should solicit a trouble message to the controller from the ;
circuit. A failure to send a trouble message would ~; indicate a problem with the maintenance functions of the ~ 25 circuit under test. Additionally, faults may be `~ inserted into a circuit under test to ascertain how the circuit operates under the faulted conditions.
- Presently, fault insertion is a tedious manual process carried out by a craftsperson or technician.
The technician using jumper wire, or a similar tool, attaches onè end of the ~umper to a connector pin of the device under test and grounds the other end. In a digital logic system this would simulate a logic ~Low"
; or "0" state. The technician would then monitor and interpret the operating conditions of the circuit under ;~
test using elther a test terminal and monitor, an :. .
oscilloscope or any other means commonly known for testing the performance of digital circuits. The process is then repeated for each fault inserted into the circuit under test.
Manual fault insertion has disadvantages in that it is extremely time consuming, and it is prone to human error. Additionally, without special equipment only logic "0" faults could be inserted into the circuit under test. The logic "0" only fault insertion, tends to be incomplete and therefore inefficient for the proper testing of digital circuits.
Accordingly, it is an object of the present inven-tion to provide a fault insertion arrangement and method which can be programmed by an operator to automatically apply fault signals to a digital circuit under test.
DISCLOSURE OF THE INVENTION
The above and other objects, advantages, and capabilities of the present invention are realized in a method for controlling a fault insertion circuit that is arranged to generate and apply a fault signal to a digital circuit under test. A data terminal is included for transmitting commands and instructions to the fault insertion circuit. The fault insertion circuit includes fault insertion hardware arranged to generate and apply a fault signal to a digital circuit under test and a controller. The controller is arranged to receive and interpxet commands and instructions transmitted from the data terminal and to transmit responses to the commands `` ~-to the data terminal. The controller is further arranged to poll the fault insertion hardware for its configuration iand for its proper operationi. The method for controlling the fault insertion circuit of the present invention comprises the following steps.
First, sending a prompt request command to the controller from the data terminal. The controller receives and interprets the prompt request command and 2~3~
transmits to the data terminal a hardware fault response character if a hardware fault has been detected. If no hardware fault has been dekected, a response character indicating the configuration status of the fault inser-tion circuit is transmitted to the data terminal.
Next, an insertion commancl and fault instructiondata are transmitted to the controller from the data terminal. The controller receives the insertion command and fault instruction data and interprets the insertion command to ascertain if the insertion command is valid.
If the command is invalid, the controller sends to the data terminal an invalid command response character. If the insertion command is valid, then the instruction data is interpreted.
The controller then checks the instruction data looking for a valid pin number. This is the connector pin which will be faulted on the digital circuit card under test. The pin number must be valid for the type of configuration that the fault insertion card is testing. If an invalid pin number is encountered, an invalid pin response character is sent to the data terminal.
Upon passing the above tests, the controller then sends to the fault insertion hardware control signals, which induces a fault to the digital circuit under test, in accordance with the parameters of the received data instruction.
Finally, the controller sends a completed response character to the data terminal, indicating that the last command was completed.
8RIEF DESCRIPTION OF THE DRAWINGS `
A better understanding of the invention may be had from the consideration of the following detailed de- ~
scription taken in conjunction with the accompanying ~ `
drawings in which~
., - ~
39~
Figure l is block diagram showing the programmable fault insertion arrangement connected to a digital circuit card under test in a digital system, in accor-dance with the principles of operation of the present invention;
Figure 2 is a block diagram showing the major functional areas of the progral~able fault insertion arrangement, in accordance with the principles of operation of the present inven1ion;
Figure 3 is a detailed block diagram of the fault insertion circuit of the programmable fault insertion arrangement, in accordance with the present invention;
and Figure 4 is a block diagram of the method used to program faults, in accordance with the operation of the present invention.
DESCRIPTION OF A PREFERRED EMBODIMENT
Directing attention first to Figure l, depicted therein, is the Programmable Fault Insertion Circuit (PFIC) in accordance to the principles of operation of the present invention. As can be seen, the PFIC l0 is connected between a Digital Circuit Card (DCC) 20, that is to be tested and a Digital System (DS) 30. The DCC
20 is a functional subsystem of DS 30. A data terminal 40 is connected to the PFIC l0. The data terminal 40 is used to issue commands to PFIC l0, in order to insert faults into the DCC 20. A maintenance data terminal 50, is connected to the DS 30 and is used to receive error or warning messages sent by DS 50 in response to the PFIC l0 inserted faults. It is contemplated that the PFIC l0 is connected betweèn the DCC 20 and the backplane Bus of the DS 50, via a pair of connectors (not shown) much in the same manner as a circuit card extender.
With xeference now to Figure 2, the major functional areas of PFIC l0 will now be explained. The 3~
, PFIC 10 is comprised of three functional areas, the communication port 11l the control hardware 12 and the fault insertion hardware 13.
The communication port is used to receive and send data from the data terminal 40. In the present embodi-ment the communication port 40 utilizes the EIA RS232C
specification for communication between the PFIC 10 and the data terminal 40. This provides for an industry standard data connection between the PFIC 10 and the data terminal 40 or a Personal Computer (PC). There-fore, any PC having a RS232C serial interface can act as the data terminal 40 to send and receive operating instructions to the PFIC 10.
It will be appreciated by those skilled in the art that other types of data communication standards or ::
protocols can be used to provide communication between the PFIC 10 and the data terminal 40 and the present invention is not limited thereto.
The control hardware 12 consists of the circuitry which interprets and executes the data instructions and commands sent to the PFIC 10 from the data terminal 40.
The commands perform diagnostics and induce or remove .
faults. In this embodiment the control hardware is comprised of a microcomputer of the type which includes in single device a microprocessor, read only memory, random access memory, timing, and I/0 capabilities.
The fault ins~rtion hardware is the functional ; circuitry which under control of the control hardware creates and applies to the selected connector pins of ~.
the DCC 20 the requested faults.
The fault ihsertion hardware is configured to : provide the following fault types~
Stuck at 1 (S-A-l), a signal having a logic "1' value;
Stuck at 0 (S-A-0), a signal having a logic "0"
value; and . ~.
~
; ~ ~
r~
2~-g Oscillation Fault, a signal which alternatively pulled to a logic "0" and logic "1" state, creating a square wave.
Referring now to Figure 3, a detailed explanation of the programmable fault insertion circuit in accor-dance with the present inventic)n will now be given.
The communication interfac:e 110 is comprised of a RS232 Transmitter/Receiver (TR) circuit, which connects the data terminal 40 to the serial communication ports of controller 12. The RS232 T~ circuit, uses an asynchronous serial link, including a handshaking protocol, for transferring information to/from the communication interface 110 and the data terminal 40.
The signals used by the TR circuit are: Data transmitted (DT), Data Received (DR), Clear to Send (CTS) and Data Terminal Ready (DTR). The interface is contemplated to transfer information along the serial link at 9600 Baud with each data byte composed of 7 bits of data, one even parity bit, one start bit and one stop bit.
The control hardware 12 includes a microcomputer 125, a system reset circuit 120, a configuration status circuit 121, and a I/O decoder 122. The microcomputer 125 includes Read Only Memory (ROM), were the PFIC's 10 operating program is stored, Random Access Memory (RAM), for the temporary storage of data, and a serial communi-cation interface. The serial communication interface connects the microcomputer 125 to the communications -interface 110.
The system reset circuit 120, powers up the the microcomputer 125 properly, by providing a reset signal that remains low for at least 20ms.
The configuration status circuit 121, is a hardwired circuit which provides data to the microcompu-ter 125 that identifies the type of PFIC 10 the micro-computer is controlling. Since there are a great ~
6 ~ ;
variety of circuit cards with different connector pin configurations, such as 98 pin upper/98 pin lower connector double height cards, or 98 pin connector single height cards more than one type of PFIC 10 must be produced and used. Therefore, instead of generating two or more operating programs to control each type of card, it is more efficient to write a single operating program which can control both types of PFICs. Thus, the microcomputer 125 checks which type of card it is installed on by reading the configuration status circuit 121 and uses the appropriate portions of the operating program for the proper operation of PFIC.
The I/O decoder 122 is a single 3/8 decoder device that is connected to the microcomputer's 12 address bus.
I/O decoder 122 decodes addresses generated by the microcomputer 125 into control signals for enables the fault insertion hardware within the I/O address space.
Signal IOS/ selects decoder 122 whenever a valid I/O
address appears on the address bus.
The fault insertion hardware consists of two groups of identical components. The first group generates and applies the S-A-l faults and the second group generates and applies the S-A-0 faults. The first group includes an S-A-l wrap around buffer 131, an S-A-1 data register 132, an S-A-l fault group select 133, S-A-l pin select logic 134, and S-A-l pullup hybrid devices 135. Simi-larly, the second group includes an S-A-0 wrap around buffer 136, an S-A-0 data register 137, an S-A-0 fault group select 138, S-A-l pin select logic 139, and S-A-0 pulldown hybrid devices 130. Additionally, the fault insertion hardware inciudes a diagnostic control flip flop (F/F) 150, used to allow diagnostics to be run on the fault insertion hardware.
The wrap around buffers 131 and 136 are connected to the microcomputer's 125 data bus and are used during diagnostics. When F/F 150 is set, the fault group -` 2022239 select decoders 133 and 138 are disabled allowing data written to the data registers 132 and 137 to be read back to the microcomputer via wrap around buPfers 131 and 136. The wrap around buffers 131 and 136 are enabled by signals generated by the I/O decoder 122.
The data registers 132 ancl 137 are eight bit register devices connected to t:he microcomputer's 12 data bus. Each register divides the stored data into an upper and lower nibble (4 bits). The lower nibble is used to select one o~ sixteen pins within the appropri-ate S-A-l or S-A-0 fault group. The upper nibble -selects one of six appropriate S-A-1 or S-A-0 fault groups. The data registers are written to by the micro-computer 125 by an enable signal generated by the I~O
decoder 122.
The fault group select decoders 133 and 138 receive the upper nibble from its associated data register 132, 137 and generate an enable signal to one of the six fault groups of the pin select logic devices 134, 139 respectively. The fault group select decoders 133, 138 are normally active unless deselected by gates 151 and 152 respectively, when diagnostics are run. Only one fault group can be active at any one time.
Each pin select logic 134, 139 consists of six 4/16 decoders. Each decoder corresponds to a one of six fault groups within the S-A-1 and S-A-0 fault type. The enabling signals generated by the group select decoders selects one of the six pin select decoders. One of the ~ `
sixteen pins of each decoder is then selected by the decoding of the lower nibble of data from the associated ~ ~-data register 132,!137. The pin select signal is then applied to the associated pullup hybrid 135 or pulldown ;~
hybrid 130.
The hybrid devices 135 and 130, are a plurality of discrete transistor and resistor combinations which apply the S-A-l or S-A-0 signals respectively, to the ~ 202~39 DCC 20. Each transistor resistor combination receives an enabling siynal from its associated pin select decoder and produces and applies the appropriate fault to the DCC 20.
With renewed reference to Figures 1, 3 and 4, an explanation of the operation oiE PFIC 10 will now be given. After the PFIC 10 is installed to the DCC 20 and powered up, an initialization and diagnostics routine is run by the microcomputer 125. The microcomputer 125 issues an address which is decoded by the I/O decoder 122. I/O decoder 122 generate~3 a set signal which is applied to the clock input of F/F 150. The Q output of the now set F/F 150, is applied to gates 151 and 152 which deselect the S-A-l and S-A-O fault group select decoders. The microcomputer then writes a byte of data into each of the data registers 132, 137. After the data has been written to the data registers 132, 137 the microcomputer 125 via the appropriate wrap around buffer 131, 136 reads the data back and checks that the data read back is correct. If the data read back is correct the I/O decoder 122 generates a reset signal which is applied to the C (clear~ input of F/F 150, resetting the fault insertion hardware for normal operation. The diagnostic routines also check the microcomputer 125 RAM -space, a checksum of the program ROM and the integrity of the communication link, by checking for even parity ;
on the incoming data. Any hardware failures are stored as data in the microcomputers 125 RAM and transmitted to the data terminal as a response to a prompt request.
The fault generation and insertion sequence between the data terminal 40 and the PFIC 10 begins when the -data terminal 40 issues a command to the PFIC 10. The valid commands are: ;~
P - prompt request;
R - reset command; and I - induce fault.
~' ~22~3~-The data terminal 40 then waits for a valid response character from the PFIC 10. The valid response characters are:
S - single height prompt;
D - double height prompt;
C - cable card prompt;
H - hardware problem with the PFIC;
C - command complete;
F - pin data was invalid: and I - command received was invalid.
The prompt command is the first command sent from data terminal 40. The microcomputer 125 receives and interprets the command. If all diagnostics were suc-cessfully completed, the PFIC 10 sends to the data terminal 40 the response character describing the PFIC
10 card type. This data is read by the microcomputer 125 from the configuration status circuit 121. If the PFIC 10 failed diagnostics the hardware problem response character is returned to the data terminal 40, indicating a hardware problem with the PFIC circuit.
If a valid prompt is returned to the data terminal 40, the data terminal 40 then transmits the induce fault command character to the PFIC 10. The induce fault commands character is accompanied by a data instruction ;~
detailing the type and duration of the fault to induce.
The data instruction has the following structure:
1 - Card number, refers to the number of card under ~
test addressed. ;
U - Sector, refers to the portion of the card under ~i test where the pin to be faulted is located. This could be U (upperj or !L ~lower) for a double height card, or S
(single) for a single height card.
00 - Pin number, refers to number of the pin to be faulted.
H - Fault type, refers to the type of fault to be inserted; H ~high), L (low) or O (oscillation).
'':
' ~ .
oooo - Duration time, refers to the length of time, in microseconds, a high or low fault is to be maintained.
oooo - High time, refers to the length of time, in microseconds, an oscillation fault is to remain high.
0000 - Low time, refers to the length of time, in microseconds t an oscillation fault is to remain low.
Using the command structure just described, a fault can be induced into the DCC 20 by transmitting to the PFIC 10 the following command alnd data instruction.
This command message will insert a S-A-1 signal on pin number ten of the DCC 20 having a duration of 25ms.
The transmitted command and data instruction is read and interpreted by the microcomputer 125. I~ the microcomputer 125 can not decode the received command, the invalid command response character is sent to the ;~
data terminal. Next the microcomputer 125 ascertains if the pin number contained in the data instruction received is valid for the card type the PFIC 10 is con- ;
nected to. If the pin number is invalid, the invalid pin response character is transmitted to the data terminal 40.
When these tests are successfully passed, the -microcomputer 125 sends an appropriate address to the I/O decoder 122. The decoder 122 enables the correct data register, in this example the S-A-1 data register 132 and the fault group select decoder 133.
The microcomputer 125 sends over the data bus a byte ~ ;
of data containing!the!fault group select and pin select data to the S-A-1 data register 132. After the data is read into the data register 132, the lower nibble of the data byte is transmitted to the S-A-1 pin select logic 134, and the higher nibble sent to the ,~..
20222~
,. .
. .
S-A-l fault group select 133. The higher nibble is decoded by fault yroup select 133 and the appropriate decoder of the pin select logic 134 is enabled. The enabled pin select logic decoder 134 reads the low order nibble and the pullup hybrid associated with the DCC 20 pin number 10 is activated to :induce a S-A-l fault for the commanded duration time.
When the time duration is completed the ~ault is removed and a command completed response character is transmitted to the data terminal 40 from the PFIC 10.
The PFIC 10 then assumes a standby state ready to accept another fault insertion command from the data terminal 40. The results of the fault induced into the DCC 20 can bs monitored via the DS 30 maintenance data terminal 50.
The PFIC 10 can also be reset from the data terminal 40, by issuing the reset command. When the reset command is received by microcomputer 125 any faults that are active are closed and the PFIC assumes the standby state. When the reset is complete a command completed response character is returned to the data terminal 40.
It is, however, useful to underscore some of the salient attributes of the subject invention. It will be well understood by those skilled in the art that the present invention provides for the ability to communicate with a data terminal or a PC to automatical-ly insert faults under the terminal's or PC's direction.
The insertion can be under the direction of an operator or under the direction of a program written to execute a specifi¢ sequence of faults into the digital system. `
The present invention easily allows a technician to write a test plan which would run on a PC, that would automatically insert faults into the digital system hardware and collect the test data to be analyzed at a later time or date.
Furthermorel it will be obvious to those skilled in the art that numerous modifications to the present invention can be made without departing from the scope of the invention as defined by the appended claims. In this context, it should be recognized that the essence of the invention resides in a fault insertion arrange-ment and method which can be programme.d by an operator, a data terminal or a personal computer to automatically apply a plurality of faults into a digital system, in order to ascertain if the digital system is operating properly.
. ' '' , ' .: ,. .
CROSS REFERENCE TQ RELATED APPLICATIONS
Cross Reference is made to the related U.S. Patent Applications entitled, IlA PROGRAMMABLE FAULT INSERTION
CIRCUIT," (Docket 88-7-017), filed on the same date, and by the same inventors as this Application.
FIELD OF THE INVENTION
The present invention relates to the field of electronic test devices, and more particularly, to a lo programmable device for insert.ing faults into an elec-tronic digital circuit.
~5~L~CC~C~ HE INVENTION
Fault insertion, is the means by which logic faults are introduced into an electronic digital circuit.~
Logic faults are operator induced logic signals such as ~ -a logic "high" or loyic "low" that are deliberately injected into a digital electronic circuit. The circuit is then monitored to ascertain if it responded correctly to the fault. For example, in a digital circuit having the capability to sense such failures and to send messages to a controller, an inserted fault should solicit a trouble message to the controller from the ;
circuit. A failure to send a trouble message would ~; indicate a problem with the maintenance functions of the ~ 25 circuit under test. Additionally, faults may be `~ inserted into a circuit under test to ascertain how the circuit operates under the faulted conditions.
- Presently, fault insertion is a tedious manual process carried out by a craftsperson or technician.
The technician using jumper wire, or a similar tool, attaches onè end of the ~umper to a connector pin of the device under test and grounds the other end. In a digital logic system this would simulate a logic ~Low"
; or "0" state. The technician would then monitor and interpret the operating conditions of the circuit under ;~
test using elther a test terminal and monitor, an :. .
oscilloscope or any other means commonly known for testing the performance of digital circuits. The process is then repeated for each fault inserted into the circuit under test.
Manual fault insertion has disadvantages in that it is extremely time consuming, and it is prone to human error. Additionally, without special equipment only logic "0" faults could be inserted into the circuit under test. The logic "0" only fault insertion, tends to be incomplete and therefore inefficient for the proper testing of digital circuits.
Accordingly, it is an object of the present inven-tion to provide a fault insertion arrangement and method which can be programmed by an operator to automatically apply fault signals to a digital circuit under test.
DISCLOSURE OF THE INVENTION
The above and other objects, advantages, and capabilities of the present invention are realized in a method for controlling a fault insertion circuit that is arranged to generate and apply a fault signal to a digital circuit under test. A data terminal is included for transmitting commands and instructions to the fault insertion circuit. The fault insertion circuit includes fault insertion hardware arranged to generate and apply a fault signal to a digital circuit under test and a controller. The controller is arranged to receive and interpxet commands and instructions transmitted from the data terminal and to transmit responses to the commands `` ~-to the data terminal. The controller is further arranged to poll the fault insertion hardware for its configuration iand for its proper operationi. The method for controlling the fault insertion circuit of the present invention comprises the following steps.
First, sending a prompt request command to the controller from the data terminal. The controller receives and interprets the prompt request command and 2~3~
transmits to the data terminal a hardware fault response character if a hardware fault has been detected. If no hardware fault has been dekected, a response character indicating the configuration status of the fault inser-tion circuit is transmitted to the data terminal.
Next, an insertion commancl and fault instructiondata are transmitted to the controller from the data terminal. The controller receives the insertion command and fault instruction data and interprets the insertion command to ascertain if the insertion command is valid.
If the command is invalid, the controller sends to the data terminal an invalid command response character. If the insertion command is valid, then the instruction data is interpreted.
The controller then checks the instruction data looking for a valid pin number. This is the connector pin which will be faulted on the digital circuit card under test. The pin number must be valid for the type of configuration that the fault insertion card is testing. If an invalid pin number is encountered, an invalid pin response character is sent to the data terminal.
Upon passing the above tests, the controller then sends to the fault insertion hardware control signals, which induces a fault to the digital circuit under test, in accordance with the parameters of the received data instruction.
Finally, the controller sends a completed response character to the data terminal, indicating that the last command was completed.
8RIEF DESCRIPTION OF THE DRAWINGS `
A better understanding of the invention may be had from the consideration of the following detailed de- ~
scription taken in conjunction with the accompanying ~ `
drawings in which~
., - ~
39~
Figure l is block diagram showing the programmable fault insertion arrangement connected to a digital circuit card under test in a digital system, in accor-dance with the principles of operation of the present invention;
Figure 2 is a block diagram showing the major functional areas of the progral~able fault insertion arrangement, in accordance with the principles of operation of the present inven1ion;
Figure 3 is a detailed block diagram of the fault insertion circuit of the programmable fault insertion arrangement, in accordance with the present invention;
and Figure 4 is a block diagram of the method used to program faults, in accordance with the operation of the present invention.
DESCRIPTION OF A PREFERRED EMBODIMENT
Directing attention first to Figure l, depicted therein, is the Programmable Fault Insertion Circuit (PFIC) in accordance to the principles of operation of the present invention. As can be seen, the PFIC l0 is connected between a Digital Circuit Card (DCC) 20, that is to be tested and a Digital System (DS) 30. The DCC
20 is a functional subsystem of DS 30. A data terminal 40 is connected to the PFIC l0. The data terminal 40 is used to issue commands to PFIC l0, in order to insert faults into the DCC 20. A maintenance data terminal 50, is connected to the DS 30 and is used to receive error or warning messages sent by DS 50 in response to the PFIC l0 inserted faults. It is contemplated that the PFIC l0 is connected betweèn the DCC 20 and the backplane Bus of the DS 50, via a pair of connectors (not shown) much in the same manner as a circuit card extender.
With xeference now to Figure 2, the major functional areas of PFIC l0 will now be explained. The 3~
, PFIC 10 is comprised of three functional areas, the communication port 11l the control hardware 12 and the fault insertion hardware 13.
The communication port is used to receive and send data from the data terminal 40. In the present embodi-ment the communication port 40 utilizes the EIA RS232C
specification for communication between the PFIC 10 and the data terminal 40. This provides for an industry standard data connection between the PFIC 10 and the data terminal 40 or a Personal Computer (PC). There-fore, any PC having a RS232C serial interface can act as the data terminal 40 to send and receive operating instructions to the PFIC 10.
It will be appreciated by those skilled in the art that other types of data communication standards or ::
protocols can be used to provide communication between the PFIC 10 and the data terminal 40 and the present invention is not limited thereto.
The control hardware 12 consists of the circuitry which interprets and executes the data instructions and commands sent to the PFIC 10 from the data terminal 40.
The commands perform diagnostics and induce or remove .
faults. In this embodiment the control hardware is comprised of a microcomputer of the type which includes in single device a microprocessor, read only memory, random access memory, timing, and I/0 capabilities.
The fault ins~rtion hardware is the functional ; circuitry which under control of the control hardware creates and applies to the selected connector pins of ~.
the DCC 20 the requested faults.
The fault ihsertion hardware is configured to : provide the following fault types~
Stuck at 1 (S-A-l), a signal having a logic "1' value;
Stuck at 0 (S-A-0), a signal having a logic "0"
value; and . ~.
~
; ~ ~
r~
2~-g Oscillation Fault, a signal which alternatively pulled to a logic "0" and logic "1" state, creating a square wave.
Referring now to Figure 3, a detailed explanation of the programmable fault insertion circuit in accor-dance with the present inventic)n will now be given.
The communication interfac:e 110 is comprised of a RS232 Transmitter/Receiver (TR) circuit, which connects the data terminal 40 to the serial communication ports of controller 12. The RS232 T~ circuit, uses an asynchronous serial link, including a handshaking protocol, for transferring information to/from the communication interface 110 and the data terminal 40.
The signals used by the TR circuit are: Data transmitted (DT), Data Received (DR), Clear to Send (CTS) and Data Terminal Ready (DTR). The interface is contemplated to transfer information along the serial link at 9600 Baud with each data byte composed of 7 bits of data, one even parity bit, one start bit and one stop bit.
The control hardware 12 includes a microcomputer 125, a system reset circuit 120, a configuration status circuit 121, and a I/O decoder 122. The microcomputer 125 includes Read Only Memory (ROM), were the PFIC's 10 operating program is stored, Random Access Memory (RAM), for the temporary storage of data, and a serial communi-cation interface. The serial communication interface connects the microcomputer 125 to the communications -interface 110.
The system reset circuit 120, powers up the the microcomputer 125 properly, by providing a reset signal that remains low for at least 20ms.
The configuration status circuit 121, is a hardwired circuit which provides data to the microcompu-ter 125 that identifies the type of PFIC 10 the micro-computer is controlling. Since there are a great ~
6 ~ ;
variety of circuit cards with different connector pin configurations, such as 98 pin upper/98 pin lower connector double height cards, or 98 pin connector single height cards more than one type of PFIC 10 must be produced and used. Therefore, instead of generating two or more operating programs to control each type of card, it is more efficient to write a single operating program which can control both types of PFICs. Thus, the microcomputer 125 checks which type of card it is installed on by reading the configuration status circuit 121 and uses the appropriate portions of the operating program for the proper operation of PFIC.
The I/O decoder 122 is a single 3/8 decoder device that is connected to the microcomputer's 12 address bus.
I/O decoder 122 decodes addresses generated by the microcomputer 125 into control signals for enables the fault insertion hardware within the I/O address space.
Signal IOS/ selects decoder 122 whenever a valid I/O
address appears on the address bus.
The fault insertion hardware consists of two groups of identical components. The first group generates and applies the S-A-l faults and the second group generates and applies the S-A-0 faults. The first group includes an S-A-l wrap around buffer 131, an S-A-1 data register 132, an S-A-l fault group select 133, S-A-l pin select logic 134, and S-A-l pullup hybrid devices 135. Simi-larly, the second group includes an S-A-0 wrap around buffer 136, an S-A-0 data register 137, an S-A-0 fault group select 138, S-A-l pin select logic 139, and S-A-0 pulldown hybrid devices 130. Additionally, the fault insertion hardware inciudes a diagnostic control flip flop (F/F) 150, used to allow diagnostics to be run on the fault insertion hardware.
The wrap around buffers 131 and 136 are connected to the microcomputer's 125 data bus and are used during diagnostics. When F/F 150 is set, the fault group -` 2022239 select decoders 133 and 138 are disabled allowing data written to the data registers 132 and 137 to be read back to the microcomputer via wrap around buPfers 131 and 136. The wrap around buffers 131 and 136 are enabled by signals generated by the I/O decoder 122.
The data registers 132 ancl 137 are eight bit register devices connected to t:he microcomputer's 12 data bus. Each register divides the stored data into an upper and lower nibble (4 bits). The lower nibble is used to select one o~ sixteen pins within the appropri-ate S-A-l or S-A-0 fault group. The upper nibble -selects one of six appropriate S-A-1 or S-A-0 fault groups. The data registers are written to by the micro-computer 125 by an enable signal generated by the I~O
decoder 122.
The fault group select decoders 133 and 138 receive the upper nibble from its associated data register 132, 137 and generate an enable signal to one of the six fault groups of the pin select logic devices 134, 139 respectively. The fault group select decoders 133, 138 are normally active unless deselected by gates 151 and 152 respectively, when diagnostics are run. Only one fault group can be active at any one time.
Each pin select logic 134, 139 consists of six 4/16 decoders. Each decoder corresponds to a one of six fault groups within the S-A-1 and S-A-0 fault type. The enabling signals generated by the group select decoders selects one of the six pin select decoders. One of the ~ `
sixteen pins of each decoder is then selected by the decoding of the lower nibble of data from the associated ~ ~-data register 132,!137. The pin select signal is then applied to the associated pullup hybrid 135 or pulldown ;~
hybrid 130.
The hybrid devices 135 and 130, are a plurality of discrete transistor and resistor combinations which apply the S-A-l or S-A-0 signals respectively, to the ~ 202~39 DCC 20. Each transistor resistor combination receives an enabling siynal from its associated pin select decoder and produces and applies the appropriate fault to the DCC 20.
With renewed reference to Figures 1, 3 and 4, an explanation of the operation oiE PFIC 10 will now be given. After the PFIC 10 is installed to the DCC 20 and powered up, an initialization and diagnostics routine is run by the microcomputer 125. The microcomputer 125 issues an address which is decoded by the I/O decoder 122. I/O decoder 122 generate~3 a set signal which is applied to the clock input of F/F 150. The Q output of the now set F/F 150, is applied to gates 151 and 152 which deselect the S-A-l and S-A-O fault group select decoders. The microcomputer then writes a byte of data into each of the data registers 132, 137. After the data has been written to the data registers 132, 137 the microcomputer 125 via the appropriate wrap around buffer 131, 136 reads the data back and checks that the data read back is correct. If the data read back is correct the I/O decoder 122 generates a reset signal which is applied to the C (clear~ input of F/F 150, resetting the fault insertion hardware for normal operation. The diagnostic routines also check the microcomputer 125 RAM -space, a checksum of the program ROM and the integrity of the communication link, by checking for even parity ;
on the incoming data. Any hardware failures are stored as data in the microcomputers 125 RAM and transmitted to the data terminal as a response to a prompt request.
The fault generation and insertion sequence between the data terminal 40 and the PFIC 10 begins when the -data terminal 40 issues a command to the PFIC 10. The valid commands are: ;~
P - prompt request;
R - reset command; and I - induce fault.
~' ~22~3~-The data terminal 40 then waits for a valid response character from the PFIC 10. The valid response characters are:
S - single height prompt;
D - double height prompt;
C - cable card prompt;
H - hardware problem with the PFIC;
C - command complete;
F - pin data was invalid: and I - command received was invalid.
The prompt command is the first command sent from data terminal 40. The microcomputer 125 receives and interprets the command. If all diagnostics were suc-cessfully completed, the PFIC 10 sends to the data terminal 40 the response character describing the PFIC
10 card type. This data is read by the microcomputer 125 from the configuration status circuit 121. If the PFIC 10 failed diagnostics the hardware problem response character is returned to the data terminal 40, indicating a hardware problem with the PFIC circuit.
If a valid prompt is returned to the data terminal 40, the data terminal 40 then transmits the induce fault command character to the PFIC 10. The induce fault commands character is accompanied by a data instruction ;~
detailing the type and duration of the fault to induce.
The data instruction has the following structure:
1 - Card number, refers to the number of card under ~
test addressed. ;
U - Sector, refers to the portion of the card under ~i test where the pin to be faulted is located. This could be U (upperj or !L ~lower) for a double height card, or S
(single) for a single height card.
00 - Pin number, refers to number of the pin to be faulted.
H - Fault type, refers to the type of fault to be inserted; H ~high), L (low) or O (oscillation).
'':
' ~ .
oooo - Duration time, refers to the length of time, in microseconds, a high or low fault is to be maintained.
oooo - High time, refers to the length of time, in microseconds, an oscillation fault is to remain high.
0000 - Low time, refers to the length of time, in microseconds t an oscillation fault is to remain low.
Using the command structure just described, a fault can be induced into the DCC 20 by transmitting to the PFIC 10 the following command alnd data instruction.
This command message will insert a S-A-1 signal on pin number ten of the DCC 20 having a duration of 25ms.
The transmitted command and data instruction is read and interpreted by the microcomputer 125. I~ the microcomputer 125 can not decode the received command, the invalid command response character is sent to the ;~
data terminal. Next the microcomputer 125 ascertains if the pin number contained in the data instruction received is valid for the card type the PFIC 10 is con- ;
nected to. If the pin number is invalid, the invalid pin response character is transmitted to the data terminal 40.
When these tests are successfully passed, the -microcomputer 125 sends an appropriate address to the I/O decoder 122. The decoder 122 enables the correct data register, in this example the S-A-1 data register 132 and the fault group select decoder 133.
The microcomputer 125 sends over the data bus a byte ~ ;
of data containing!the!fault group select and pin select data to the S-A-1 data register 132. After the data is read into the data register 132, the lower nibble of the data byte is transmitted to the S-A-1 pin select logic 134, and the higher nibble sent to the ,~..
20222~
,. .
. .
S-A-l fault group select 133. The higher nibble is decoded by fault yroup select 133 and the appropriate decoder of the pin select logic 134 is enabled. The enabled pin select logic decoder 134 reads the low order nibble and the pullup hybrid associated with the DCC 20 pin number 10 is activated to :induce a S-A-l fault for the commanded duration time.
When the time duration is completed the ~ault is removed and a command completed response character is transmitted to the data terminal 40 from the PFIC 10.
The PFIC 10 then assumes a standby state ready to accept another fault insertion command from the data terminal 40. The results of the fault induced into the DCC 20 can bs monitored via the DS 30 maintenance data terminal 50.
The PFIC 10 can also be reset from the data terminal 40, by issuing the reset command. When the reset command is received by microcomputer 125 any faults that are active are closed and the PFIC assumes the standby state. When the reset is complete a command completed response character is returned to the data terminal 40.
It is, however, useful to underscore some of the salient attributes of the subject invention. It will be well understood by those skilled in the art that the present invention provides for the ability to communicate with a data terminal or a PC to automatical-ly insert faults under the terminal's or PC's direction.
The insertion can be under the direction of an operator or under the direction of a program written to execute a specifi¢ sequence of faults into the digital system. `
The present invention easily allows a technician to write a test plan which would run on a PC, that would automatically insert faults into the digital system hardware and collect the test data to be analyzed at a later time or date.
Furthermorel it will be obvious to those skilled in the art that numerous modifications to the present invention can be made without departing from the scope of the invention as defined by the appended claims. In this context, it should be recognized that the essence of the invention resides in a fault insertion arrange-ment and method which can be programme.d by an operator, a data terminal or a personal computer to automatically apply a plurality of faults into a digital system, in order to ascertain if the digital system is operating properly.
. ' '' , ' .: ,. .
Claims (3)
1. A method for controlling a fault insertion circuit, said fault insertion circuit including fault insertion hardware arranged to generate and apply a fault signal to a digital circuit under test, said method further including a data terminal for transmit-ting commands and instructions to said fault insertion circuit, and said fault insertion circuit further including a controller for controlling said fault insertion hardware, polling the fault insertion hardware for its configuration and for the proper operation of said fault insertion hardware, and for receiving and interpreting said commands and instructions and for transmitting responses to said data terminal, said method comprising the steps of;
sending a prompt request command to said controller from said data terminal, said controller receiving and interpreting said prompt request command and transmit-ting to said data terminal a hardware fault response character if a hardware fault has been detected, or alternatively, a response character indicating the configuration status of said fault insertion circuit;
sending an insertion command and fault instruction data to said controller from said data terminal in response to said configuration status response charac-ter;
said controller receiving said insertion command and fault instruction data and;
interpreting said insertion command to ascertain if the insertion command is valid, and responsive to an invalid command said, controller sends to said data terminal an invalid command response character;
interpreting said instruction data, and responsive to an invalid pin number, sending to said data terminal an invalid pin response character;
interpreting said fault instruction data and sending control data to said fault insertion hardware to induce a fault to said digital circuit under test; and, sending a command completed response character to said data terminal, indicating that the last command was completed.
sending a prompt request command to said controller from said data terminal, said controller receiving and interpreting said prompt request command and transmit-ting to said data terminal a hardware fault response character if a hardware fault has been detected, or alternatively, a response character indicating the configuration status of said fault insertion circuit;
sending an insertion command and fault instruction data to said controller from said data terminal in response to said configuration status response charac-ter;
said controller receiving said insertion command and fault instruction data and;
interpreting said insertion command to ascertain if the insertion command is valid, and responsive to an invalid command said, controller sends to said data terminal an invalid command response character;
interpreting said instruction data, and responsive to an invalid pin number, sending to said data terminal an invalid pin response character;
interpreting said fault instruction data and sending control data to said fault insertion hardware to induce a fault to said digital circuit under test; and, sending a command completed response character to said data terminal, indicating that the last command was completed.
2. The method as claimed in claim 1 wherein said method further includes the steps of;
sending a reset command to said controller from said data terminal, said controller receiving said reset command and transmiting to said fault insertion hardware control commands terminating any faults that are pres-ently active; and said controller sending to said data terminal said command completed response character indicating that the last command has been completed.
sending a reset command to said controller from said data terminal, said controller receiving said reset command and transmiting to said fault insertion hardware control commands terminating any faults that are pres-ently active; and said controller sending to said data terminal said command completed response character indicating that the last command has been completed.
3. A method for controlling a fault insertion circuit arranged to generate and apply a fault signal to a digital circuit under test, said method including a data terminal for transmitting commands and instructions to said fault insertion circuit, and said fault insertion circuit further arranged to poll said fault insertion circuit for its configuration, and if the fault insertion circuit is operating properly, said method comprising the steps of:
sending a prompt request command to said fault insertion circuit from said data terminal, said fault insertion circuit receiving said prompt request command and transmitting to said data terminal a hardware fault response character if a fault in the fault insertion circuit has been detected, or alternatively, a response character indicating the configuration status of said fault insertion circuit;
sending an insertion command and fault instruction data to said fault insertion circuit from said data terminal in response to said configuration status response character;
said fault insertion circuit receiving said inser-tion command and fault instruction data and:
ascertaining if the insertion command is valid, and responsive to an invalid command said fault insertion circuit sends to said data terminal an invalid command response character;
ascertaining if said instruction data is valid, and responsive to invalid instruction data sending to said data terminal an invalid instruction data response character;
inducing a fault to said digital circuit under test responsive to said instruction data; and, sending a command completed response character to said data terminal, indicating that the last command was completed.
sending a prompt request command to said fault insertion circuit from said data terminal, said fault insertion circuit receiving said prompt request command and transmitting to said data terminal a hardware fault response character if a fault in the fault insertion circuit has been detected, or alternatively, a response character indicating the configuration status of said fault insertion circuit;
sending an insertion command and fault instruction data to said fault insertion circuit from said data terminal in response to said configuration status response character;
said fault insertion circuit receiving said inser-tion command and fault instruction data and:
ascertaining if the insertion command is valid, and responsive to an invalid command said fault insertion circuit sends to said data terminal an invalid command response character;
ascertaining if said instruction data is valid, and responsive to invalid instruction data sending to said data terminal an invalid instruction data response character;
inducing a fault to said digital circuit under test responsive to said instruction data; and, sending a command completed response character to said data terminal, indicating that the last command was completed.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US38703889A | 1989-07-31 | 1989-07-31 | |
| US387,038 | 1989-07-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2022239A1 true CA2022239A1 (en) | 1991-02-01 |
Family
ID=23528183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2022239 Abandoned CA2022239A1 (en) | 1989-07-31 | 1990-07-30 | Programmable fault insertion arrangement and method |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2022239A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6304905B1 (en) * | 1998-09-16 | 2001-10-16 | Cisco Technology, Inc. | Detecting an active network node using an invalid protocol option |
-
1990
- 1990-07-30 CA CA 2022239 patent/CA2022239A1/en not_active Abandoned
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6304905B1 (en) * | 1998-09-16 | 2001-10-16 | Cisco Technology, Inc. | Detecting an active network node using an invalid protocol option |
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