CA2008669A1 - Multiple mode memory module - Google Patents

Multiple mode memory module

Info

Publication number
CA2008669A1
CA2008669A1 CA002008669A CA2008669A CA2008669A1 CA 2008669 A1 CA2008669 A1 CA 2008669A1 CA 002008669 A CA002008669 A CA 002008669A CA 2008669 A CA2008669 A CA 2008669A CA 2008669 A1 CA2008669 A1 CA 2008669A1
Authority
CA
Canada
Prior art keywords
memory
bus
unit
address
storing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002008669A
Other languages
French (fr)
Other versions
CA2008669C (en
Inventor
Edward D. Mann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Wang Laboratories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wang Laboratories Inc filed Critical Wang Laboratories Inc
Publication of CA2008669A1 publication Critical patent/CA2008669A1/en
Application granted granted Critical
Publication of CA2008669C publication Critical patent/CA2008669C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0684—Configuration or reconfiguration with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Bus Control (AREA)

Abstract

A memory unit 18 includes a bus 16 which couples the memory unit to a memory control unit 14. The memory unit includes a latch for receiving and storing an address from the bus, a first memory plane for storing information units associated with an odd address, a second memory plane far storing information units associated with an even address, an input latch for receiving from the bus an information unit associated with a received address and output latches for storing;
prior to transmission to the bus, a stored information unit associated with a received address. The memory unit further includes logic, responsive to a state of a first bus signal line, for enabling the output latches to (a) simultaneously transmit to the bus an information unit from both the first and the second memory planes, or (b) sequentially transmit to the bus an information unit from one of the memory planes followed by an information unit from the other one of the memory planes.
CA002008669A 1989-05-05 1990-01-26 Multiple mode memory module Expired - Lifetime CA2008669C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/348,318 1989-05-05
US07/348,318 US5307469A (en) 1989-05-05 1989-05-05 Multiple mode memory module

Publications (2)

Publication Number Publication Date
CA2008669A1 true CA2008669A1 (en) 1990-11-05
CA2008669C CA2008669C (en) 2001-03-06

Family

ID=23367482

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002008669A Expired - Lifetime CA2008669C (en) 1989-05-05 1990-01-26 Multiple mode memory module

Country Status (2)

Country Link
US (1) US5307469A (en)
CA (1) CA2008669C (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2271449A (en) * 1992-09-29 1994-04-13 Ricoh Kk Dram and controller

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DE69122520T2 (en) * 1990-01-31 1997-02-13 Hewlett Packard Co Multiple bus system memory architecture
EP0913777B1 (en) * 1991-03-01 2005-05-11 Advanced Micro Devices, Inc. Output buffer for microprocessor
US5485589A (en) * 1991-12-31 1996-01-16 Dell Usa, L.P. Predictive addressing architecture
JP3060812B2 (en) * 1993-12-27 2000-07-10 日本電気株式会社 Information processing device
US5477488A (en) * 1994-02-14 1995-12-19 Texas Instruments Incorporated System, a memory and a process having bit processing circuits associated with memory for pre-processing data read by a processor
US5678030A (en) * 1995-02-28 1997-10-14 Harris Corporation Modification of timing in an emulator circuit and method
US6061759A (en) * 1996-02-09 2000-05-09 Apex Semiconductor, Inc. Hidden precharge pseudo cache DRAM
US5950219A (en) * 1996-05-02 1999-09-07 Cirrus Logic, Inc. Memory banks with pipelined addressing and priority acknowledging and systems and methods using the same
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
US5734849A (en) * 1996-07-01 1998-03-31 Sun Microsystems, Inc. Dual bus memory transactions using address bus for data transfer
WO1999019874A1 (en) 1997-10-10 1999-04-22 Rambus Incorporated Power control system for synchronous memory device
JP3461290B2 (en) * 1998-07-30 2003-10-27 富士通株式会社 Buffer access control circuit
US6199118B1 (en) * 1998-08-18 2001-03-06 Compaq Computer Corporation System and method for aligning an initial cache line of data read from an input/output device by a central processing unit
US6477569B1 (en) 1998-11-20 2002-11-05 Eugene Sayan Method and apparatus for computer network management
US6404660B1 (en) * 1999-12-23 2002-06-11 Rambus, Inc. Semiconductor package with a controlled impedance bus and method of forming same
JP2001325148A (en) * 2000-05-18 2001-11-22 Denso Corp Method and device for controlling access
US6889304B2 (en) * 2001-02-28 2005-05-03 Rambus Inc. Memory device supporting a dynamically configurable core organization
US7610447B2 (en) * 2001-02-28 2009-10-27 Rambus Inc. Upgradable memory system with reconfigurable interconnect

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Publication number Priority date Publication date Assignee Title
US4514808A (en) * 1978-04-28 1985-04-30 Tokyo Shibaura Denki Kabushiki Kaisha Data transfer system for a data processing system provided with direct memory access units
US4467443A (en) * 1979-07-30 1984-08-21 Burroughs Corporation Bit addressable variable length memory system
US4309754A (en) * 1979-07-30 1982-01-05 International Business Machines Corp. Data interface mechanism for interfacing bit-parallel data buses of different bit width
US4371928A (en) * 1980-04-15 1983-02-01 Honeywell Information Systems Inc. Interface for controlling information transfers between main data processing systems units and a central subsystem
JPS5715271A (en) * 1980-06-30 1982-01-26 Toshiba Corp Memory device
JPS5892025A (en) * 1981-11-26 1983-06-01 Hitachi Ltd Data processing system
US4509113A (en) * 1982-02-02 1985-04-02 International Business Machines Corporation Peripheral interface adapter circuit for use in I/O controller card having multiple modes of operation
JPS58149548A (en) * 1982-03-02 1983-09-05 Hitachi Ltd Controlling system of memory
US4787060A (en) * 1983-03-31 1988-11-22 Honeywell Bull, Inc. Technique for determining maximum physical memory present in a system and for detecting attempts to access nonexistent memory
DE3543911A1 (en) * 1984-12-14 1986-06-26 Mitsubishi Denki K.K., Tokio/Tokyo DIGITAL DELAY UNIT
US4716545A (en) * 1985-03-19 1987-12-29 Wang Laboratories, Inc. Memory means with multiple word read and single word write
US4683534A (en) * 1985-06-17 1987-07-28 Motorola, Inc. Method and apparatus for interfacing buses of different sizes
JPS61294562A (en) * 1985-06-21 1986-12-25 Mitsubishi Electric Corp Semiconductor memory device
JPS6226561A (en) * 1985-07-26 1987-02-04 Toshiba Corp Personal computer
US4947366A (en) * 1987-10-02 1990-08-07 Advanced Micro Devices, Inc. Input/output controller incorporating address mapped input/output windows and read ahead/write behind capabilities
US5109332A (en) * 1988-09-09 1992-04-28 Compaq Computer Corporation System for controlling the transferring of different widths of data using two different sets of address control and state information signals

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2271449A (en) * 1992-09-29 1994-04-13 Ricoh Kk Dram and controller
GB2271449B (en) * 1992-09-29 1996-09-04 Ricoh Kk Method of processing data representative of a colour image
US5630106A (en) * 1992-09-29 1997-05-13 Ricoh Company, Ltd. DRAM controller including bus-width selection and data inversion

Also Published As

Publication number Publication date
CA2008669C (en) 2001-03-06
US5307469A (en) 1994-04-26

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Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed
MKEC Expiry (correction)

Effective date: 20121202