CA1332695C - Method of making an article comprising a heteroepitaxial structure, and article produced thereby - Google Patents
Method of making an article comprising a heteroepitaxial structure, and article produced therebyInfo
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- CA1332695C CA1332695C CA000552552A CA552552A CA1332695C CA 1332695 C CA1332695 C CA 1332695C CA 000552552 A CA000552552 A CA 000552552A CA 552552 A CA552552 A CA 552552A CA 1332695 C CA1332695 C CA 1332695C
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- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03B—MANUFACTURE, SHAPING, OR SUPPLEMENTARY PROCESSES
- C03B25/00—Annealing glass products
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
METHOD OF MAKING AN ARTICLE COMPRISING A
HETEROEPITAXIAL STRUCTURE, AND ARTICLE PRODUCED THEREBY
Abstract Disclosed is a technique, formed "mesotaxy", for producing a heteroepitaxial structure comprising a layer of single crystal second material embedded in, and epitaxial with, a single crystal first material matrix. Mesotaxy comprises implantation of at least one chemical species (e.g., Co, Ni, Cr, Y or Mg) into a single crystal body (typically a semiconductor, e.g., Si or Ge) such that a buried layer rich in the implanted species is formed, and heat treating the implanted body such that a buried stoichiometric compound layer (e.g., CoSi2) isformed. Exemplarily, 3 ? 1017/cm2 200 keV Co ions are implanted into (100) Si nominally at 350°C, followed by a heat treatment that consists of 1 hour at 600°C
and 30 minutes at 1000°C. The resulting buried CoSi2 layer is epitaxial with the Si matrix, has high conductivity and is of good crystalline quality. The Si overlayer is of device quality. The thus produced heteroepitaxial structure can then be used to produce semiconductor devices, e.g., MOSFETs with a buried ground plane.
HETEROEPITAXIAL STRUCTURE, AND ARTICLE PRODUCED THEREBY
Abstract Disclosed is a technique, formed "mesotaxy", for producing a heteroepitaxial structure comprising a layer of single crystal second material embedded in, and epitaxial with, a single crystal first material matrix. Mesotaxy comprises implantation of at least one chemical species (e.g., Co, Ni, Cr, Y or Mg) into a single crystal body (typically a semiconductor, e.g., Si or Ge) such that a buried layer rich in the implanted species is formed, and heat treating the implanted body such that a buried stoichiometric compound layer (e.g., CoSi2) isformed. Exemplarily, 3 ? 1017/cm2 200 keV Co ions are implanted into (100) Si nominally at 350°C, followed by a heat treatment that consists of 1 hour at 600°C
and 30 minutes at 1000°C. The resulting buried CoSi2 layer is epitaxial with the Si matrix, has high conductivity and is of good crystalline quality. The Si overlayer is of device quality. The thus produced heteroepitaxial structure can then be used to produce semiconductor devices, e.g., MOSFETs with a buried ground plane.
Description
- 1- 1 3~2695 METHOD OF MAKING AN ARTICLE COMPRISING A
HETEROEPITAXIAL STRUCI-URE, AND ARIICLE PRODUCED l~IEREBY
Field of the Invention This invention pertains to methods for forming heteroepitaxial structures, and to semiconductor devices and other articles incorporating such stmctures.
S Back~round of the Invention From the beginning of semiconductor device technology physicists have postulated a host of heterostructures, i.e., combinations of layers of different materials in a single composite crystal. The interest in this kind of structure is traceable to the wide variety of characteristics that can potentially be achieved in 10 devices inco~porating such s~uctures.
In the last few years, considerable progress has been made in this field, and techniques are now known that permit production of various combinations of materials. For instance, U.S. pa~ent 4,554,045 teaches a method for producing metal silicide/silicon heterostructures, such that the 15 silicide is essentially monocrystalline and epitaxial with the underlying silicon substrate.
The known techniques are not restricted to techniques for forming heterostructures comprising a metal silicide layer. For instance, Ishiwara et al, Applied Phvsics Letters, Vol. 40, pages 66-68 (1982), disclose a20 technique for growing an epitaxial dielectric layer, namely CaF2, on silicon.All of the prior art techniques for growing a heteroepitaxial structure have in common that they involve deposition of material onto the surface of the single crystal substrate. Obviously, once the epitaxial single crystal overlayer is formed it can become the substrate for formation of a 25 further heteroepitaxial layer. Thus, the prior art knows SUCoSiJSi and Si/CaF2/Si heterostructures formed by particular embodiments of the deposition technique.
The prior art also knows several techniques for forming a particular heterostructure, namely, SUSiOJSi also referred to as SOI).
30 Structurally, SOI differs fundamentally from the above referred to ' - la -heterostructures since the SiO2 layer is not a single crystal layer, and, in fact, typically is amorphous. Thus SOI structures are not heteroepitaxial structures in the way the term is used herein, although, through seeding techniques, the orientation of the silicon overlayer can be caused to be the same as that of 5 the silicon wafer upon which the combination .. . .
. . .~ . :
HETEROEPITAXIAL STRUCI-URE, AND ARIICLE PRODUCED l~IEREBY
Field of the Invention This invention pertains to methods for forming heteroepitaxial structures, and to semiconductor devices and other articles incorporating such stmctures.
S Back~round of the Invention From the beginning of semiconductor device technology physicists have postulated a host of heterostructures, i.e., combinations of layers of different materials in a single composite crystal. The interest in this kind of structure is traceable to the wide variety of characteristics that can potentially be achieved in 10 devices inco~porating such s~uctures.
In the last few years, considerable progress has been made in this field, and techniques are now known that permit production of various combinations of materials. For instance, U.S. pa~ent 4,554,045 teaches a method for producing metal silicide/silicon heterostructures, such that the 15 silicide is essentially monocrystalline and epitaxial with the underlying silicon substrate.
The known techniques are not restricted to techniques for forming heterostructures comprising a metal silicide layer. For instance, Ishiwara et al, Applied Phvsics Letters, Vol. 40, pages 66-68 (1982), disclose a20 technique for growing an epitaxial dielectric layer, namely CaF2, on silicon.All of the prior art techniques for growing a heteroepitaxial structure have in common that they involve deposition of material onto the surface of the single crystal substrate. Obviously, once the epitaxial single crystal overlayer is formed it can become the substrate for formation of a 25 further heteroepitaxial layer. Thus, the prior art knows SUCoSiJSi and Si/CaF2/Si heterostructures formed by particular embodiments of the deposition technique.
The prior art also knows several techniques for forming a particular heterostructure, namely, SUSiOJSi also referred to as SOI).
30 Structurally, SOI differs fundamentally from the above referred to ' - la -heterostructures since the SiO2 layer is not a single crystal layer, and, in fact, typically is amorphous. Thus SOI structures are not heteroepitaxial structures in the way the term is used herein, although, through seeding techniques, the orientation of the silicon overlayer can be caused to be the same as that of 5 the silicon wafer upon which the combination .. . .
. . .~ . :
- 2 - I 332f~ 95 was formed.
One particular technique for forming a SOI heterostructure involves implantation of oxygen ions into a silicon substrate. See U.S. Patent 3,855,009.After appropriate preparation of a major surface of a silicon wafer, oxygen ions5 are implanted into the wafer through the major surface. As is well known, suchions come to rest in a relatively narrow subsurface region of the matrix, with the mean depth of penetration (and thickness of the oxygen-rich layer) depending on the energy of the ions. The '009 patent teaches that, after heat treating of theimplanted wafer at a temperature between 1000 and 1200C to anneal out damage 10 in the Si overlayer and to cause formation of the SiO2 layer from the implant, the thickness of the Si overlayer is increased by deposition of Si. Semiconductor devices can then be formed in the epitaxial silicon overlayer in a known manner.The '009 patent also teaches that buried silicon carbide and silicon nitride layers can be formed in substantially the same manner, by implantation of, 15 respectively, carbon or nitrogen ions. This prior art technique for forming asilicon heterostructure thus comprises implantation of relatively light ions into a silicon wafer, with the resulting buried silicon compound layer being non singlecrystal and nonepitaxial with the silicon matrix.
Recendy some work has also been done that involves implantation of 20 relatively heavy ions into silicon. See M. N. Kozicki et al, Institute of Physics Conference Series, No. 67, Section 3, pages 137-142 (1983). Ihese authors reporton the implantation of cobalt and chromium ions into polycrystalline silicon. The use of relatively high implantation energies (350 keV) resulted in the formation of a buried region of average composition of one metal atom to two silicon atoms.
25 The implanted samples were subjected to a conventional furnace anneal (900, 950, or 1025C) or to an electron beam anneal. The technique did not result in the formation of a homogeneous epita~cial buried layer. F. H. Sanchez et al, roceedings of the Materials Research Society Symposium, Vol. 51, pages 439-444, (1986) discloses implantation of Cr, Fe, Co, and Ni ions into single crystal 30 silicon samples. No buried layer was formed.
The prior art thus does not know any implantation method that results in formation of a buried single crystal layer that is epitaxial with the matrix.Furthermore, silicide layers formed by the prior art implantation process typically have a relatively low conductivity, due to the presence of gain boundaries, line 35 and point defects, and possibly two or more phases. The relatively low , .:~. ` . ,, ~
One particular technique for forming a SOI heterostructure involves implantation of oxygen ions into a silicon substrate. See U.S. Patent 3,855,009.After appropriate preparation of a major surface of a silicon wafer, oxygen ions5 are implanted into the wafer through the major surface. As is well known, suchions come to rest in a relatively narrow subsurface region of the matrix, with the mean depth of penetration (and thickness of the oxygen-rich layer) depending on the energy of the ions. The '009 patent teaches that, after heat treating of theimplanted wafer at a temperature between 1000 and 1200C to anneal out damage 10 in the Si overlayer and to cause formation of the SiO2 layer from the implant, the thickness of the Si overlayer is increased by deposition of Si. Semiconductor devices can then be formed in the epitaxial silicon overlayer in a known manner.The '009 patent also teaches that buried silicon carbide and silicon nitride layers can be formed in substantially the same manner, by implantation of, 15 respectively, carbon or nitrogen ions. This prior art technique for forming asilicon heterostructure thus comprises implantation of relatively light ions into a silicon wafer, with the resulting buried silicon compound layer being non singlecrystal and nonepitaxial with the silicon matrix.
Recendy some work has also been done that involves implantation of 20 relatively heavy ions into silicon. See M. N. Kozicki et al, Institute of Physics Conference Series, No. 67, Section 3, pages 137-142 (1983). Ihese authors reporton the implantation of cobalt and chromium ions into polycrystalline silicon. The use of relatively high implantation energies (350 keV) resulted in the formation of a buried region of average composition of one metal atom to two silicon atoms.
25 The implanted samples were subjected to a conventional furnace anneal (900, 950, or 1025C) or to an electron beam anneal. The technique did not result in the formation of a homogeneous epita~cial buried layer. F. H. Sanchez et al, roceedings of the Materials Research Society Symposium, Vol. 51, pages 439-444, (1986) discloses implantation of Cr, Fe, Co, and Ni ions into single crystal 30 silicon samples. No buried layer was formed.
The prior art thus does not know any implantation method that results in formation of a buried single crystal layer that is epitaxial with the matrix.Furthermore, silicide layers formed by the prior art implantation process typically have a relatively low conductivity, due to the presence of gain boundaries, line 35 and point defects, and possibly two or more phases. The relatively low , .:~. ` . ,, ~
conducdvity and high defect density make such prior art buried silicide layers unacceptable for applicadons such as metal base transistors, and at least reducetheir usefulness as a conductor material in multilayer integrated devices. On the other hand, the prior art deposidon method can be used to produce epitaxial layers S of silicide or other materials on silicon, and to form epitaxial silicon thereon, resuldng in formadon of buried layers of epitaxial silicide or other materials.
However, these deposition processes are slow, can only be successfully practicedunder extremely clean high vacuum conditions (thus typically do not lend themselves readily to pracdce in a manufacturing environment), tend to result in10 structures with interfacial impurides, and lead to incorporation of substantially all of the impurities in the starting material into the silicide.
In view of the potential significance of alticles such as semiconductor devices comprising buried, high quality epitaxial single crystal layers of metalsilicides and possibly other materials, a method for forming such buried layers 15 that can be practiced in a manufacturing environment with commonly available apparatus that has the potential of high throughput, that inherently leads to substandally impurity-free interfaces and to the eliminadon of impurides that are present in at least one of the stardng materials, is of substandal interest. This applicadon discloses such a method.
20 Glossary and Definitions By "mesotaxy" we mean herein the process of direct formation of a substandally single crystal second material body (typically a thin layer) within a substandally single crystal first material matrix (with the first and second materials differing in their chemical composition), such that the second material body is 25 epitaxial with the first material matrix. Mesotaxy is thus fundamentally different from epitaxy, which refers to the formadon of a second material layer on a firstmaterial, with the layer being epitaxial with the substrate. '~A t A "single crystal" or "monocrystalline" body herein is a body of crystalline material that has essentially the same crystalline orientadon throughout 30 the body. In agreement with current usage, a body is considered to be a single crystal body even though it may contain defects such as dislocadons.
One crystalline body herein is "epitaxial" with another crystalline body in contact with the former if at least two crystal latdce direcdons are condnuous across the interface between the two bodies.
'. ' , .
.
-~ ~3~ 695 By a "heterostructure" we mean herein a structure (typically a multilayer structure) that comprises a multiplicity of compositonally distinct regions (typically compositionally distinct layers).
A "heteroepitaxial" structure herein is a heterostructure in which at 5 least one region is epitaxial with another, compositionally distinct, region.
Typically, one layer is epitaxial with a chemically distinct contacting layer.
Summary of the Invention We describe here a new approach (to be referred to as "mesotaxy") to the formation of a heteroepitaxial structure that comprises a second material layer 10 embedded in a first material matrix. It involves implantadon of ions into a single crystal body and appropriate heat treatment of the implanted body.
Although the new method is described helein largely in terms of the formation of a buried metal silicide (pAmarily CoSi2, CrSi2, TiSi2 and NiSi2) layer in a silicon matrix, we expect that other semiconductors (e.g., Ge), and 15 possible compound semiconductors such as m-v and II-VI serniconductor and even other classes of matrices (e.g., metals or insulators), and other atomic implantation species (e.g., Y or Mg into Si, and combinations of implantation species, e.g., Co and Ni) can be found that are thermodynamically and crystallographically suited for mesotaxy. Therefore, we present first a general 20 description of the technique.
The inventive method comprises providing a single crystal body (exemplarily a semiconductor wafer) having a major surface, and implanting ions of at least one (frequendy relatively heavy) chemical species at a predeterminedmean depdh below the major surface of the body, such that a buried layer that is25 relatively rich in the implanted species is formed. Subsequent to the implantation the irnplanted body is heat treated. The implantation and heat treatrnent conditions are chosen such dhat the buried species-rich layer is transformed into dle second material layer. The second material is a substantially stoichiometriccompound dhat differs from the first material and comprises the implanted species.
30 The conditions are also chosen such that the resulting buried second material layer is substantially single crystal and epitaxial with the first material matrix. The second material layer and the first materiaVsecond mat~rial interfaces are substantially free of impurities.
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;:
.
The thus produced heterostructure can then be processed in any appropriate way to form an article, exemplarily an electronic, optical or optoelectronic device or devices. Processing techniques are well known in the art. See, for instance, D.J. Elliot, "Integrated Circuit Fabrication Technology" McGraw-Hill, 1982.
In accordance with one aspect oE the invention there is provided a method of manufacturing a semiconductor device comprising a first material body and a second material layer embedded within the body, the method comprising a) providing a single crystal semiconductor first material body having a major surface; b) implanting at least one chemical species into the first material body at a predetermined mean depth below the major surface of the body such that a buried species-rich layer results; c) heat treating the implanted body such that the buried species-rich layer is transformed into the second material layer, the second material being a substantially stoichiometric compound different from the first material and comprising the implanted chemical species; and d) completing the manufacture of the semiconductor device; CHARACTERIZED IN THAT e) the chemical species, implant and heat treatment conditions are chosen such that the second material layer is a substantially single crystal layer epitaxial with the ~lrst material body in which the second material layer is embedded, with the lattice mismatch between first and second material being less than 5%, and with the first material body during implantation having a nominal temperature above room temperature.
We know of no existing technologically significant process that meets the above description. However general the method may be, we currently consider its application to heteroepitaxial Si/metal silicide/Si structures to be especially significant ~;
since, inter alia, it can result in buried silicide layers of exceptionally high crystalline and/or electronic quality that offer promise for high quality device applications. Furthermore, we know of nothing in the prior art to suggest that mesotaxy might be possible, and we consider our discovery of mesotaxy to be indeed surprising.
Brief Description of the Drawine FIG. 1 is a schematic representation of an exemplary three-layer heteroepitaxial structure according to the invention;
FIG. 2 shows as-implanted RBS yields for a Co-implanted Si matrix;
FIG. 3 shows RBS yields for the Co-implanted Si matrix after heat treatment; and FIG. 4 schematically depicts an exemplary device according to the invention.
B
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- Sa -~ 332~q5 - Detailed Description A feature of the inventive technique is the implantation of (frequently relatively heavy) ions into a substrate body such that a buried layer rich in the implanted species is formed. Although the prior art knows an exarnple of the high 5 energy (350 keV) implantation of Co and Cr into polycrystalline Si such that aburied metal-rich layer was formed (see Kozicki et al, op. cit.), those skilled in the art generally expect that sputtering of the semiconductor target by the ions will irnpose a relatively low limit on the achievable concentration of the irnplantedspecies. See, for instance, Z. L. Liau et al, Journal of Vacuum Science and 10 Technolo~ry, Vol. 15, pp. 1629-1635 (1978). Also, see FIG. 1 of Sanchez et al(op. cit.), which shows that a buIied layer was not formed under the conditions of the irnplantation. However, we have shown that, despite the widespread expectation to the contrary, buried layers rich in a relatively heavy (atomic nurnber > 8, typically > 20) element can indeed be formed by ion implantation t ~ S2S ~5 using commercially available implanters.
A further and very significant feature of the inventive technique is a solid state reaction be~ween the semiconductor and the implanted species under conditions that favor formation of the desired compound, and also favor formation 5 of the compound as a buried single crystal epitaxial with the matrix in which it is embedded. This typically requires, inter alia, that the lattice structure and lattice constant of the semiconductor and of the compound be substandally matched, with the lattice constants generally differing by less than about 5%.
FIG. I schematically represents an exemplary three-layer 10 heterostructure according to the invention. It shows essentially single crystal lower and upper Srst material (e.g., semiconductor) layers 10 and 12, with an essentially single crystal compound layer 11 therebetween. As discussed above, 11 is epitaxial with both 10 and 12.
As will be readily appreciated by those skilled in the art, devices can lS be formed directly in a semiconductor overlayer 12, or 12 can form the substrate for the formation of one or more further layers. For instance, the thickness of 12 ~ J
can be increased by a known method for the growth of an epitaxial semiconductor layer on a substrate of the same semiconductor, and subsequently, devices can beformed in the top layer. See, for instance, the '009 patent. On the other hand, a 20 heteroepitaxial layer of another semiconductor (e.g., GaAs) could be grown on, e.g., a Si layer 12 by a known technique, and devices formed in the top layer.
It will also be appreciated by those skilled in the art that a controlled dose of the ions can be implanted substandally uniformly into either all or a significant part of the major surface of a semiconductor substrate, or that the 25 implantation can be localized such as to yield a patterned implant layer (possibly using different doses in different regions). In the latter case a patterned masklayer on the substrate or a programmable focused ion beam can be used to produce the patterned implant. Furthermore, since the implant depth is directly related to the ion energy, it is possible to create buried compound regions of 30 varying distance from the surface. This ability may, for instance, be advantageously used to create a multilevel conductor arrangement in VLSI chips.
We now describe in detail a particular exemplary embodiment of the invention, namely, the formation by mesotaxy of a buried epitaxial layer of CoSi2 in a Si matrix. As is well known, Co and Si form a number of compounds, 35 Co2Si, CoSi, CoSi2, of which only the last has the requisite crystal structure and .. .
~ 332695 lattice constant to make epitaxy with Si possible. Thus, the implant conditions and the heat treatment have to be chosen such that CoSi2 is formed. Othe,r constraints will be discussed below.
Exemplarily, we used a 200 keV, æo IlA/cm2, scanned 59Co+ beam.
S Both (100) and (111) orientation Si wafers were used as substrates. The major surface was prepared in a convendonal manner, and the substrate typically was tighdy clamped to a stainless steel block typically maintained at a temperature in the range 300-500C. However, some beam heating of the substrate cannot be ruled out.
After implantadon, the sample is subjected to a heat treatment, as will be described in more detail below. Since the heat treatment causes essentdally all of the implanted Co to contribute to the formation of the buried CoSi2 layer, it is easy to deterrnine the dose required to result in a given thickness of buried layer.
For instance, a thickness of 0.1 ~m CoSi2 requires implantatdon of approximately15 2 5 . 1ol7/cm2 of Co FIG. 2 shows Rutherford Backscattering Spectroscopy (RBS) yields for a random and a channeled (100) direction in an as-implanted (100) Si substrate, with 20 and 21 indicadng the (100) channeled and random yields, respecdvely. Such RBS yields are a commonly accepted indicator of crystalline 20 quality. The implant condidons were: substrate nominally at 350C, 200 keV, 3 10 /cm Co. FIG. 2 shows that the implanted Co is buried beneath the Si surface, with the peak Co concentration of 27.5 atomic % appearing at a depth ofabout 115 nm. FIG. 2 also shows that the as-implanted Co-Iich region has some degree of crystalline order in registry with the Si matrix, (X~ about 55%) but 25 def~nitely is not device-grade material. Xlr"" is the minimum observed rado of RBS yield in the channeling direcdon to that in the random direction, and is a standard measure of crystalline quality. A low temperature anneal (1 hour at 600-C) resulted in only slight changes in the RBS Co profile, indicadng some redistribudon of the Co with little improvement in crystallinity.
A subsequent high temperature treatment (1/2 hour at 1000C), however, produced a dramatic transformadon, as can be seen from FIG. 3, wherein 30 and 31 refer to the channeled and random yields, respecdvely. The Co profile has abrupt edges, the characterisdc yield for stoichiometric CoSi2, and a greatly reduced channeling yield (the latter being indicadve of the high 35 crystalline quality of the buried layer), e.g., Xn"~, about 12%.
. : . . . :.
~ :. . . -:. ... . . . .
. . .
:- ~
. - .
- 8- l 332695 FIG. 3 also indicates that the buried layer is epitaxial with the Si matrix, and that the crystalline quality of the top Si layer is substantially improved, as compared to the as-implanted condition. The dashed line 31 was obtained by computer simulation of the random RBS spectrum for a 110 nm layer S of CoSi2 sandwiched between a 60 nm top layer of Si and a Si bottom layer of effectively infinite thickness, and is in excellent agreement with the measured spectrum. Buried layers according to the invention typically have a X~
substantially smaller (at least 50% smaller) than the as-implanted X~ " in the same sample.
In summary, FIGS. 2 and 3 show that under the indicated conditions, a heteroepitaxial structure (Si/CoSi2/Si) of high crystalline ~quality can be produced by mesotaxy. Other experimental results agree with and amplify this conclusion. For instance, cross-section transmission electron microscopy also shows that the CoSi2 region is single crystal material epitaxial with the matrix.
15 High resolution transmission electron microscopy of the Si/CoSi2 interfaces shows them to be abrupt, epitaxial, and essentially smooth. The relative smoothness ofthe interface in the (100) orientation is of particular interest, since CoSi2 (and other silicides) cannot be grown without substantial faceting on (100) Si by other solid state methods. Since devices are most commonly fabricated on (100) Si, the20 presence of faceted interfaces in prior art Si/CoSi2 heteroepitaxial structures is a considerable disadvantage. The inventive technique is essentially free of this shortcoming.
Another problem associated with prior art techniques is dhe difficulty of obtaining high purity buried layers and atomically clean interfaces. As will be 25 appreciated by those skilled in the art, dhe presence of impurities results in higher resistivity and/or interface states which can negatively affect the operating characteristics of devices formed in such material. This problem is not present in dhe inventive technique, since dhe implantation technique inherendy results in removal of all but the wanted atomic species from the beam, and since the 30 interfaces are never exposed.
RBS is not dhe only experimental technique to yield quantitative information on dhe quality of the buAed layer. The resistance ratio (RR, definedas R(T = 300-K)/R(T = 4.2K), where R is dle resistivity and T the absolute temperature) of a buried conductive layer can be determined and is known to be a35 sensitive indicator of dhe structural integrity, crystalline defect density, interface ;' :
.
, ~ 332695 g roughness, chemical purity and deviations from stoichiometry of the layer, with a large value of the RR being indicative of high quality material. In buried metallic layers produced according to the invention the RR typically is substantially greater than 1, preferably > 5. For instance, the RR of a CoSi2 layer embedded in Si and5 produced by mesotaxy substantially as described ab~ve was found to be 15.48, which is almost a factor of 2 greater than that of the best prior art epitaxial CoSi2 film.
Typically several process parameters have to be chosen properly in order to achieve mesotaxy. Among these parameters generally are the substrate 10 temperature during implantation, the ion energy and dose, and the annealing temperature and time. Since the proper parameter values are expected to be, at least to some extent, dependent on the nature of the substrate and of the implant species, no generally valid parameter values can be given. However, based in part on our experience in the mesotaxy of CoSi2 in Si, it appears that the substrate 15 advantageously is maintained above room temperature (e.g., 300-500C for Si) to avoid amorphization and/or to aid in the diffusion of the implanted species in the matrix. Furthermore, the ion energy has to be relatively high (e.g., above 100 keV) in order to form a buried layer and to avoid loss of the implanted species due to sputtering, and the ion dose has to be high enough such that 20 stoichiometry can be attained by annealing. Still further, the annealing temperature has to be high enough such that compound formation as well as atomic rearrangement in the matrix can take place, yet be low enough such that degradation of the buried compound layer (manifested, for instance, by an increase in resistivity) is avoided. For instance, in the Si/CoSi2/Si system we found that 25 annealing in the 600 850DC range generally results in some improvement of thequality of the buried layer (RR increases by about 3-4 from the as-implanted condition), but that annealing in the range 850-1100C (preferably about 1000C)results in much greater improvement. Annealing above about 1100C resulted in deterioration of the quality of the buried layer. However, at least in some cases it 30 may be advantageous to have a multi-step heat treatment, e.g., with a low temperature anneal followed by a high temperature anneal.
In mesotaxy the buried layer is protected at all times by the top semiconductor layer. As a consequence the annealing temperature can be higher ~ . . . . . . .
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1 33~'695 Some of these results are exemplified by the data contained in Table 1, which pertains to the SVCoSi2/Si system, with Co implantation at 200 keV. As can be seen from the data in Table 1, the detailed characteristics of the buried layer may depend on the substrate orientation. For instance, whereas S the (100) orientation yielded buried layers having Xm~n of about 12% and RR >10, the (111) orientation yielded layers with Xn~"~ of about 7% and RR -7.
We would like to further illustrate the above points by citing conditions which we found not to result in successful growth of a buried CoSi2 layer in Si. Implantation temperatures of 77K, room temperature, and 260C all 10 resulted in an amorphous Si surface and/or failure to form a buried Co-rich layer.
Frequently, when annealing such low temperature implant samples at 1000C, migration of the Co to the surface was also observed. Doses of 1 1016, 5 1016, and 1 1017/cm2 did not result in formation of a stoichiometric layerunder the annealing conditions used by us.
Various device applications based on the basic structure depicted in FIG. 1 are contemplated. An exemplary schematic device structure is shown in FIG. 3 of the ~009 patent and described in columns 4 and 5 of the patent.
Mesotaxy may also be advantageously used in optical and optoelectronic devices Other contemplated device applications of mesotaxy include a 20 MOSFET comprising a backside gate, and a MOSFET or other device comprising a buried ground plane. The laKer application is schematically illustrated in FIG. 4, wherein regions 40, 41, and 42 exemplarily are p, p+ and p+ conductivitytype, respectively, 43 refers to paKerned oxide, 44 refers to metallization regions, and 45 is a metallized via hole whereby contact is made to the buried ground 25 plane 11, formed by mesotaxy. Lndicated are also means for making electrical contact to the source and drain regions and the gate.
By means of mesotaxy it may also be possible to form a semiconductor layer within another semiconductor (e.g., CrSi2 within Si~, the two semiconductors having different bandgaps. Such combinations, which previously 30 have only been produced by MBE, are known to have interesting characteristicsthat make possible useful electronic devices such as heterojunction transistors. By means of a further implant (e.g., Co) a portion of the buried epitaxial semiconductor layer can be converted into a metal, opening up device design possibilities not previously available. Furthermore, more than one atomic species 35 can be implanted into the same region. For instance, implantation of Co and Ni - , - ~ . -.. . .. . . .
- 13- l 33~695 into Si is expected to result io formation of the epitaxial ternary silicide CoxNil xSi27 which is known to have advantageous conductive charac~eristics.
Example I: A (100) oriented Si wafer, cleaned by means of a conventional technique, was attached in a comrnercially available ion implanter to a stainless S steel block maintained at about 350C, with this temperature considered to be the nominal implant temperature. A mass analyzed beam (200keV, 40 ~lA, about 10 11A/cm2) of 59Co+ from a Freeman ion source was directed 7 off normal at the Si wafer. The implanted dose was 3 1017/cm2. After completion of the implant the wafer was maintained in vacuum (_10 Torr) for about 1 hour at 10 600C, followed by a 30 minute vacuum anneal at 1000C. The thus produced heterostructure contains an approximately 100 nm thick buried single crystal CoSi2 layer, with a 60 nm single crystal Si overlayer. The structure is heteroepitaxial, with the CoSi2 layer having X~ 12% and RR 15, and the Si overlayer having %.",1, - 15%.
15 Example II: A CoSi2 layer is formed by mesotaxy in a (lll)-oriented Si wafer substantially as described in Example I, except that the nominal implant temperature is about 300C, the ion energy is 400keV, the implant dose is 5 10 /cm, the thickness of the epitaxial CoSi2 layer is about 170 nm, and thatof the Si overlayer is about 130 nm.
20 Example III: A Co0 5Nio 5Si2 layer is formed by mesotaxy in a (100) oriented Si wafer substantially as described in Example I, except that substantially equal numbers of Co and Ni ions are implanted sequendally. The resulting epitaxial tertiary silicide layer has high conductivity and is of good crystalline quality.
Example IV: A buried epitaxial CoSi2 layer is formed by mesotaxy substantially 25 as described in Example I, except that the nominal implant temperature is about 500C, the ion energy is about 1.5 MeV and the ion dose is about 7.1017/cm2. In the Si overlayer of the resulting heteroepitaxial structure MOS devices are produced by conventional techniques, including providing electrical contact to the buried CoSi2 layer such that the buried layer serves as buried ground plane.
30 Example_: A Si/CoSi2/Si heteroepitaxial structure is formed substantially as described in Example I. On the Si overlayer a 0.5 ~m epitaxial layer of Si is grown by MBE.
Example VI: A heter~epitaxial structure is formed substantially as in Example V,except that on the Si overlayer a 0.5 ~m epitaxial layer of GaAs is grown by 35 MBE.
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i 1 3326q5 Example VII: A (100) oriented Ge wafer is cleaned by a conventional process and Co implanted therein substantially as descri'oed in Example I, except that the nominal implant temperature is 150C, the ion energy is 300 keV, and the implanted wafer is annealed at 750C. A buried epitaxial layer of CoGe2 is thus 5 foTmed.
As will be apparent to those skilled in the art, vaTious modifications and extensions of this invention are possible. All modifications and extensions which basically rely on the teachings through which this invention has advanced the art are properly considered to be within the SpiTit and scope of this invention.
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However, these deposition processes are slow, can only be successfully practicedunder extremely clean high vacuum conditions (thus typically do not lend themselves readily to pracdce in a manufacturing environment), tend to result in10 structures with interfacial impurides, and lead to incorporation of substantially all of the impurities in the starting material into the silicide.
In view of the potential significance of alticles such as semiconductor devices comprising buried, high quality epitaxial single crystal layers of metalsilicides and possibly other materials, a method for forming such buried layers 15 that can be practiced in a manufacturing environment with commonly available apparatus that has the potential of high throughput, that inherently leads to substandally impurity-free interfaces and to the eliminadon of impurides that are present in at least one of the stardng materials, is of substandal interest. This applicadon discloses such a method.
20 Glossary and Definitions By "mesotaxy" we mean herein the process of direct formation of a substandally single crystal second material body (typically a thin layer) within a substandally single crystal first material matrix (with the first and second materials differing in their chemical composition), such that the second material body is 25 epitaxial with the first material matrix. Mesotaxy is thus fundamentally different from epitaxy, which refers to the formadon of a second material layer on a firstmaterial, with the layer being epitaxial with the substrate. '~A t A "single crystal" or "monocrystalline" body herein is a body of crystalline material that has essentially the same crystalline orientadon throughout 30 the body. In agreement with current usage, a body is considered to be a single crystal body even though it may contain defects such as dislocadons.
One crystalline body herein is "epitaxial" with another crystalline body in contact with the former if at least two crystal latdce direcdons are condnuous across the interface between the two bodies.
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-~ ~3~ 695 By a "heterostructure" we mean herein a structure (typically a multilayer structure) that comprises a multiplicity of compositonally distinct regions (typically compositionally distinct layers).
A "heteroepitaxial" structure herein is a heterostructure in which at 5 least one region is epitaxial with another, compositionally distinct, region.
Typically, one layer is epitaxial with a chemically distinct contacting layer.
Summary of the Invention We describe here a new approach (to be referred to as "mesotaxy") to the formation of a heteroepitaxial structure that comprises a second material layer 10 embedded in a first material matrix. It involves implantadon of ions into a single crystal body and appropriate heat treatment of the implanted body.
Although the new method is described helein largely in terms of the formation of a buried metal silicide (pAmarily CoSi2, CrSi2, TiSi2 and NiSi2) layer in a silicon matrix, we expect that other semiconductors (e.g., Ge), and 15 possible compound semiconductors such as m-v and II-VI serniconductor and even other classes of matrices (e.g., metals or insulators), and other atomic implantation species (e.g., Y or Mg into Si, and combinations of implantation species, e.g., Co and Ni) can be found that are thermodynamically and crystallographically suited for mesotaxy. Therefore, we present first a general 20 description of the technique.
The inventive method comprises providing a single crystal body (exemplarily a semiconductor wafer) having a major surface, and implanting ions of at least one (frequendy relatively heavy) chemical species at a predeterminedmean depdh below the major surface of the body, such that a buried layer that is25 relatively rich in the implanted species is formed. Subsequent to the implantation the irnplanted body is heat treated. The implantation and heat treatrnent conditions are chosen such dhat the buried species-rich layer is transformed into dle second material layer. The second material is a substantially stoichiometriccompound dhat differs from the first material and comprises the implanted species.
30 The conditions are also chosen such that the resulting buried second material layer is substantially single crystal and epitaxial with the first material matrix. The second material layer and the first materiaVsecond mat~rial interfaces are substantially free of impurities.
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The thus produced heterostructure can then be processed in any appropriate way to form an article, exemplarily an electronic, optical or optoelectronic device or devices. Processing techniques are well known in the art. See, for instance, D.J. Elliot, "Integrated Circuit Fabrication Technology" McGraw-Hill, 1982.
In accordance with one aspect oE the invention there is provided a method of manufacturing a semiconductor device comprising a first material body and a second material layer embedded within the body, the method comprising a) providing a single crystal semiconductor first material body having a major surface; b) implanting at least one chemical species into the first material body at a predetermined mean depth below the major surface of the body such that a buried species-rich layer results; c) heat treating the implanted body such that the buried species-rich layer is transformed into the second material layer, the second material being a substantially stoichiometric compound different from the first material and comprising the implanted chemical species; and d) completing the manufacture of the semiconductor device; CHARACTERIZED IN THAT e) the chemical species, implant and heat treatment conditions are chosen such that the second material layer is a substantially single crystal layer epitaxial with the ~lrst material body in which the second material layer is embedded, with the lattice mismatch between first and second material being less than 5%, and with the first material body during implantation having a nominal temperature above room temperature.
We know of no existing technologically significant process that meets the above description. However general the method may be, we currently consider its application to heteroepitaxial Si/metal silicide/Si structures to be especially significant ~;
since, inter alia, it can result in buried silicide layers of exceptionally high crystalline and/or electronic quality that offer promise for high quality device applications. Furthermore, we know of nothing in the prior art to suggest that mesotaxy might be possible, and we consider our discovery of mesotaxy to be indeed surprising.
Brief Description of the Drawine FIG. 1 is a schematic representation of an exemplary three-layer heteroepitaxial structure according to the invention;
FIG. 2 shows as-implanted RBS yields for a Co-implanted Si matrix;
FIG. 3 shows RBS yields for the Co-implanted Si matrix after heat treatment; and FIG. 4 schematically depicts an exemplary device according to the invention.
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- Sa -~ 332~q5 - Detailed Description A feature of the inventive technique is the implantation of (frequently relatively heavy) ions into a substrate body such that a buried layer rich in the implanted species is formed. Although the prior art knows an exarnple of the high 5 energy (350 keV) implantation of Co and Cr into polycrystalline Si such that aburied metal-rich layer was formed (see Kozicki et al, op. cit.), those skilled in the art generally expect that sputtering of the semiconductor target by the ions will irnpose a relatively low limit on the achievable concentration of the irnplantedspecies. See, for instance, Z. L. Liau et al, Journal of Vacuum Science and 10 Technolo~ry, Vol. 15, pp. 1629-1635 (1978). Also, see FIG. 1 of Sanchez et al(op. cit.), which shows that a buIied layer was not formed under the conditions of the irnplantation. However, we have shown that, despite the widespread expectation to the contrary, buried layers rich in a relatively heavy (atomic nurnber > 8, typically > 20) element can indeed be formed by ion implantation t ~ S2S ~5 using commercially available implanters.
A further and very significant feature of the inventive technique is a solid state reaction be~ween the semiconductor and the implanted species under conditions that favor formation of the desired compound, and also favor formation 5 of the compound as a buried single crystal epitaxial with the matrix in which it is embedded. This typically requires, inter alia, that the lattice structure and lattice constant of the semiconductor and of the compound be substandally matched, with the lattice constants generally differing by less than about 5%.
FIG. I schematically represents an exemplary three-layer 10 heterostructure according to the invention. It shows essentially single crystal lower and upper Srst material (e.g., semiconductor) layers 10 and 12, with an essentially single crystal compound layer 11 therebetween. As discussed above, 11 is epitaxial with both 10 and 12.
As will be readily appreciated by those skilled in the art, devices can lS be formed directly in a semiconductor overlayer 12, or 12 can form the substrate for the formation of one or more further layers. For instance, the thickness of 12 ~ J
can be increased by a known method for the growth of an epitaxial semiconductor layer on a substrate of the same semiconductor, and subsequently, devices can beformed in the top layer. See, for instance, the '009 patent. On the other hand, a 20 heteroepitaxial layer of another semiconductor (e.g., GaAs) could be grown on, e.g., a Si layer 12 by a known technique, and devices formed in the top layer.
It will also be appreciated by those skilled in the art that a controlled dose of the ions can be implanted substandally uniformly into either all or a significant part of the major surface of a semiconductor substrate, or that the 25 implantation can be localized such as to yield a patterned implant layer (possibly using different doses in different regions). In the latter case a patterned masklayer on the substrate or a programmable focused ion beam can be used to produce the patterned implant. Furthermore, since the implant depth is directly related to the ion energy, it is possible to create buried compound regions of 30 varying distance from the surface. This ability may, for instance, be advantageously used to create a multilevel conductor arrangement in VLSI chips.
We now describe in detail a particular exemplary embodiment of the invention, namely, the formation by mesotaxy of a buried epitaxial layer of CoSi2 in a Si matrix. As is well known, Co and Si form a number of compounds, 35 Co2Si, CoSi, CoSi2, of which only the last has the requisite crystal structure and .. .
~ 332695 lattice constant to make epitaxy with Si possible. Thus, the implant conditions and the heat treatment have to be chosen such that CoSi2 is formed. Othe,r constraints will be discussed below.
Exemplarily, we used a 200 keV, æo IlA/cm2, scanned 59Co+ beam.
S Both (100) and (111) orientation Si wafers were used as substrates. The major surface was prepared in a convendonal manner, and the substrate typically was tighdy clamped to a stainless steel block typically maintained at a temperature in the range 300-500C. However, some beam heating of the substrate cannot be ruled out.
After implantadon, the sample is subjected to a heat treatment, as will be described in more detail below. Since the heat treatment causes essentdally all of the implanted Co to contribute to the formation of the buried CoSi2 layer, it is easy to deterrnine the dose required to result in a given thickness of buried layer.
For instance, a thickness of 0.1 ~m CoSi2 requires implantatdon of approximately15 2 5 . 1ol7/cm2 of Co FIG. 2 shows Rutherford Backscattering Spectroscopy (RBS) yields for a random and a channeled (100) direction in an as-implanted (100) Si substrate, with 20 and 21 indicadng the (100) channeled and random yields, respecdvely. Such RBS yields are a commonly accepted indicator of crystalline 20 quality. The implant condidons were: substrate nominally at 350C, 200 keV, 3 10 /cm Co. FIG. 2 shows that the implanted Co is buried beneath the Si surface, with the peak Co concentration of 27.5 atomic % appearing at a depth ofabout 115 nm. FIG. 2 also shows that the as-implanted Co-Iich region has some degree of crystalline order in registry with the Si matrix, (X~ about 55%) but 25 def~nitely is not device-grade material. Xlr"" is the minimum observed rado of RBS yield in the channeling direcdon to that in the random direction, and is a standard measure of crystalline quality. A low temperature anneal (1 hour at 600-C) resulted in only slight changes in the RBS Co profile, indicadng some redistribudon of the Co with little improvement in crystallinity.
A subsequent high temperature treatment (1/2 hour at 1000C), however, produced a dramatic transformadon, as can be seen from FIG. 3, wherein 30 and 31 refer to the channeled and random yields, respecdvely. The Co profile has abrupt edges, the characterisdc yield for stoichiometric CoSi2, and a greatly reduced channeling yield (the latter being indicadve of the high 35 crystalline quality of the buried layer), e.g., Xn"~, about 12%.
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- 8- l 332695 FIG. 3 also indicates that the buried layer is epitaxial with the Si matrix, and that the crystalline quality of the top Si layer is substantially improved, as compared to the as-implanted condition. The dashed line 31 was obtained by computer simulation of the random RBS spectrum for a 110 nm layer S of CoSi2 sandwiched between a 60 nm top layer of Si and a Si bottom layer of effectively infinite thickness, and is in excellent agreement with the measured spectrum. Buried layers according to the invention typically have a X~
substantially smaller (at least 50% smaller) than the as-implanted X~ " in the same sample.
In summary, FIGS. 2 and 3 show that under the indicated conditions, a heteroepitaxial structure (Si/CoSi2/Si) of high crystalline ~quality can be produced by mesotaxy. Other experimental results agree with and amplify this conclusion. For instance, cross-section transmission electron microscopy also shows that the CoSi2 region is single crystal material epitaxial with the matrix.
15 High resolution transmission electron microscopy of the Si/CoSi2 interfaces shows them to be abrupt, epitaxial, and essentially smooth. The relative smoothness ofthe interface in the (100) orientation is of particular interest, since CoSi2 (and other silicides) cannot be grown without substantial faceting on (100) Si by other solid state methods. Since devices are most commonly fabricated on (100) Si, the20 presence of faceted interfaces in prior art Si/CoSi2 heteroepitaxial structures is a considerable disadvantage. The inventive technique is essentially free of this shortcoming.
Another problem associated with prior art techniques is dhe difficulty of obtaining high purity buried layers and atomically clean interfaces. As will be 25 appreciated by those skilled in the art, dhe presence of impurities results in higher resistivity and/or interface states which can negatively affect the operating characteristics of devices formed in such material. This problem is not present in dhe inventive technique, since dhe implantation technique inherendy results in removal of all but the wanted atomic species from the beam, and since the 30 interfaces are never exposed.
RBS is not dhe only experimental technique to yield quantitative information on dhe quality of the buAed layer. The resistance ratio (RR, definedas R(T = 300-K)/R(T = 4.2K), where R is dle resistivity and T the absolute temperature) of a buried conductive layer can be determined and is known to be a35 sensitive indicator of dhe structural integrity, crystalline defect density, interface ;' :
.
, ~ 332695 g roughness, chemical purity and deviations from stoichiometry of the layer, with a large value of the RR being indicative of high quality material. In buried metallic layers produced according to the invention the RR typically is substantially greater than 1, preferably > 5. For instance, the RR of a CoSi2 layer embedded in Si and5 produced by mesotaxy substantially as described ab~ve was found to be 15.48, which is almost a factor of 2 greater than that of the best prior art epitaxial CoSi2 film.
Typically several process parameters have to be chosen properly in order to achieve mesotaxy. Among these parameters generally are the substrate 10 temperature during implantation, the ion energy and dose, and the annealing temperature and time. Since the proper parameter values are expected to be, at least to some extent, dependent on the nature of the substrate and of the implant species, no generally valid parameter values can be given. However, based in part on our experience in the mesotaxy of CoSi2 in Si, it appears that the substrate 15 advantageously is maintained above room temperature (e.g., 300-500C for Si) to avoid amorphization and/or to aid in the diffusion of the implanted species in the matrix. Furthermore, the ion energy has to be relatively high (e.g., above 100 keV) in order to form a buried layer and to avoid loss of the implanted species due to sputtering, and the ion dose has to be high enough such that 20 stoichiometry can be attained by annealing. Still further, the annealing temperature has to be high enough such that compound formation as well as atomic rearrangement in the matrix can take place, yet be low enough such that degradation of the buried compound layer (manifested, for instance, by an increase in resistivity) is avoided. For instance, in the Si/CoSi2/Si system we found that 25 annealing in the 600 850DC range generally results in some improvement of thequality of the buried layer (RR increases by about 3-4 from the as-implanted condition), but that annealing in the range 850-1100C (preferably about 1000C)results in much greater improvement. Annealing above about 1100C resulted in deterioration of the quality of the buried layer. However, at least in some cases it 30 may be advantageous to have a multi-step heat treatment, e.g., with a low temperature anneal followed by a high temperature anneal.
In mesotaxy the buried layer is protected at all times by the top semiconductor layer. As a consequence the annealing temperature can be higher ~ . . . . . . .
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1 33~'695 Some of these results are exemplified by the data contained in Table 1, which pertains to the SVCoSi2/Si system, with Co implantation at 200 keV. As can be seen from the data in Table 1, the detailed characteristics of the buried layer may depend on the substrate orientation. For instance, whereas S the (100) orientation yielded buried layers having Xm~n of about 12% and RR >10, the (111) orientation yielded layers with Xn~"~ of about 7% and RR -7.
We would like to further illustrate the above points by citing conditions which we found not to result in successful growth of a buried CoSi2 layer in Si. Implantation temperatures of 77K, room temperature, and 260C all 10 resulted in an amorphous Si surface and/or failure to form a buried Co-rich layer.
Frequently, when annealing such low temperature implant samples at 1000C, migration of the Co to the surface was also observed. Doses of 1 1016, 5 1016, and 1 1017/cm2 did not result in formation of a stoichiometric layerunder the annealing conditions used by us.
Various device applications based on the basic structure depicted in FIG. 1 are contemplated. An exemplary schematic device structure is shown in FIG. 3 of the ~009 patent and described in columns 4 and 5 of the patent.
Mesotaxy may also be advantageously used in optical and optoelectronic devices Other contemplated device applications of mesotaxy include a 20 MOSFET comprising a backside gate, and a MOSFET or other device comprising a buried ground plane. The laKer application is schematically illustrated in FIG. 4, wherein regions 40, 41, and 42 exemplarily are p, p+ and p+ conductivitytype, respectively, 43 refers to paKerned oxide, 44 refers to metallization regions, and 45 is a metallized via hole whereby contact is made to the buried ground 25 plane 11, formed by mesotaxy. Lndicated are also means for making electrical contact to the source and drain regions and the gate.
By means of mesotaxy it may also be possible to form a semiconductor layer within another semiconductor (e.g., CrSi2 within Si~, the two semiconductors having different bandgaps. Such combinations, which previously 30 have only been produced by MBE, are known to have interesting characteristicsthat make possible useful electronic devices such as heterojunction transistors. By means of a further implant (e.g., Co) a portion of the buried epitaxial semiconductor layer can be converted into a metal, opening up device design possibilities not previously available. Furthermore, more than one atomic species 35 can be implanted into the same region. For instance, implantation of Co and Ni - , - ~ . -.. . .. . . .
- 13- l 33~695 into Si is expected to result io formation of the epitaxial ternary silicide CoxNil xSi27 which is known to have advantageous conductive charac~eristics.
Example I: A (100) oriented Si wafer, cleaned by means of a conventional technique, was attached in a comrnercially available ion implanter to a stainless S steel block maintained at about 350C, with this temperature considered to be the nominal implant temperature. A mass analyzed beam (200keV, 40 ~lA, about 10 11A/cm2) of 59Co+ from a Freeman ion source was directed 7 off normal at the Si wafer. The implanted dose was 3 1017/cm2. After completion of the implant the wafer was maintained in vacuum (_10 Torr) for about 1 hour at 10 600C, followed by a 30 minute vacuum anneal at 1000C. The thus produced heterostructure contains an approximately 100 nm thick buried single crystal CoSi2 layer, with a 60 nm single crystal Si overlayer. The structure is heteroepitaxial, with the CoSi2 layer having X~ 12% and RR 15, and the Si overlayer having %.",1, - 15%.
15 Example II: A CoSi2 layer is formed by mesotaxy in a (lll)-oriented Si wafer substantially as described in Example I, except that the nominal implant temperature is about 300C, the ion energy is 400keV, the implant dose is 5 10 /cm, the thickness of the epitaxial CoSi2 layer is about 170 nm, and thatof the Si overlayer is about 130 nm.
20 Example III: A Co0 5Nio 5Si2 layer is formed by mesotaxy in a (100) oriented Si wafer substantially as described in Example I, except that substantially equal numbers of Co and Ni ions are implanted sequendally. The resulting epitaxial tertiary silicide layer has high conductivity and is of good crystalline quality.
Example IV: A buried epitaxial CoSi2 layer is formed by mesotaxy substantially 25 as described in Example I, except that the nominal implant temperature is about 500C, the ion energy is about 1.5 MeV and the ion dose is about 7.1017/cm2. In the Si overlayer of the resulting heteroepitaxial structure MOS devices are produced by conventional techniques, including providing electrical contact to the buried CoSi2 layer such that the buried layer serves as buried ground plane.
30 Example_: A Si/CoSi2/Si heteroepitaxial structure is formed substantially as described in Example I. On the Si overlayer a 0.5 ~m epitaxial layer of Si is grown by MBE.
Example VI: A heter~epitaxial structure is formed substantially as in Example V,except that on the Si overlayer a 0.5 ~m epitaxial layer of GaAs is grown by 35 MBE.
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i 1 3326q5 Example VII: A (100) oriented Ge wafer is cleaned by a conventional process and Co implanted therein substantially as descri'oed in Example I, except that the nominal implant temperature is 150C, the ion energy is 300 keV, and the implanted wafer is annealed at 750C. A buried epitaxial layer of CoGe2 is thus 5 foTmed.
As will be apparent to those skilled in the art, vaTious modifications and extensions of this invention are possible. All modifications and extensions which basically rely on the teachings through which this invention has advanced the art are properly considered to be within the SpiTit and scope of this invention.
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Claims (11)
1. A method of manufacturing a semiconductor device comprising a first material body and a second material layer embedded within the body, the method comprising a) providing a single crystal semiconductor first material body having a major surface;
b) implanting at least one chemical species into the first material body at a predetermined mean depth below the major surface of the body such that a buried species-rich layer results;
c) heat treating the implanted body such that the buried species-rich layer is transformed into the second material layer, the second material being asubstantially stoichiometric compound different from the first material and comprising the implanted chemical species; and d) completing the manufacture of the semiconductor device;
CHARACTERIZED IN THAT
e) the chemical species, implant and heat treatment conditions are chosen such that the second material layer is a substantially single crystal layer epitaxial with the first material body in which the second material layer is embedded, with the lattice mismatch between first and second material being less than 5%, and with the first material body during implantation having a nominal temperature above room temperature.
b) implanting at least one chemical species into the first material body at a predetermined mean depth below the major surface of the body such that a buried species-rich layer results;
c) heat treating the implanted body such that the buried species-rich layer is transformed into the second material layer, the second material being asubstantially stoichiometric compound different from the first material and comprising the implanted chemical species; and d) completing the manufacture of the semiconductor device;
CHARACTERIZED IN THAT
e) the chemical species, implant and heat treatment conditions are chosen such that the second material layer is a substantially single crystal layer epitaxial with the first material body in which the second material layer is embedded, with the lattice mismatch between first and second material being less than 5%, and with the first material body during implantation having a nominal temperature above room temperature.
2. The method of claim 1, wherein the chemical species is implanted with an energy of at least about 100keV, and wherein said chemical species is selected from the group of elements having atomic number greater than 8.
3. The method of claim 1, wherein the semiconductor is selected from the group consisting of Si and Ge.
4. The method of claim 3, wherein the semiconductor is silicon, and wherein the chemical species is selected from the group consisting of Co, Ni, Cr, Ti, Y, and Mg.
5. The method of claim 4, wherein during implantation the semiconductor body has a nominal temperature in the range from about 300°C to about 500°C, the chemical species is implanted with an energy of at least about 100keV, and step c) comprises heating the species-implanted substrate to a temperature in the range from about 800°C to about 1100°C.
6. The method of claim 4, wherein the second material is a member of the group consisting of CoSi2, NiSi2, CrSi2, TiSi2, and CoxNi1-xSi2, with 0<x<1Ø
7. The method of claim 1, wherein the semiconductor device is an electronic device, and step d) comprises providing means for making electrical contact with the second material layer.
8. The method of claim 4, wherein the major surface is at least approximately a (100) surface.
9. The method of claim 3, wherein the semiconductor body is a Ge body, and wherein the chemical species is Co.
10. The method of claim 1, wherein step d) comprises epitaxially depositing material on the major surface.
11. The method of claim 10, wherein the semiconductor body is a Si body, and wherein the epitaxially deposited material is chosen from the group consisting of Si and GaAs.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US934,160 | 1986-11-24 | ||
| US06/934,160 US4816421A (en) | 1986-11-24 | 1986-11-24 | Method of making a heteroepitaxial structure by mesotaxy induced by buried implantation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1332695C true CA1332695C (en) | 1994-10-25 |
Family
ID=25465066
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000552552A Expired - Fee Related CA1332695C (en) | 1986-11-24 | 1987-11-24 | Method of making an article comprising a heteroepitaxial structure, and article produced thereby |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4816421A (en) |
| EP (1) | EP0271232B1 (en) |
| JP (1) | JPH0654770B2 (en) |
| KR (1) | KR920007822B1 (en) |
| CA (1) | CA1332695C (en) |
| DE (1) | DE3789361T2 (en) |
| HK (1) | HK100594A (en) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4982263A (en) * | 1987-12-21 | 1991-01-01 | Texas Instruments Incorporated | Anodizable strain layer for SOI semiconductor structures |
| US5459346A (en) * | 1988-06-28 | 1995-10-17 | Ricoh Co., Ltd. | Semiconductor substrate with electrical contact in groove |
| JPH02170528A (en) * | 1988-12-23 | 1990-07-02 | Toshiba Corp | Manufacture of semiconductor device |
| US5075243A (en) * | 1989-08-10 | 1991-12-24 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Fabrication of nanometer single crystal metallic CoSi2 structures on Si |
| US5077228A (en) * | 1989-12-01 | 1991-12-31 | Texas Instruments Incorporated | Process for simultaneous formation of trench contact and vertical transistor gate and structure |
| DE4114162A1 (en) * | 1990-05-02 | 1991-11-07 | Nippon Sheet Glass Co Ltd | METHOD FOR PRODUCING A POLYCRYSTALLINE SEMICONDUCTOR FILM |
| US5236872A (en) * | 1991-03-21 | 1993-08-17 | U.S. Philips Corp. | Method of manufacturing a semiconductor device having a semiconductor body with a buried silicide layer |
| US5122479A (en) * | 1991-04-11 | 1992-06-16 | At&T Bell Laboratories | Semiconductor device comprising a silicide layer, and method of making the device |
| US5379712A (en) * | 1991-08-20 | 1995-01-10 | Implant Sciences Corporation | Method of epitaxially growing thin films using ion implantation |
| JP2914798B2 (en) * | 1991-10-09 | 1999-07-05 | 株式会社東芝 | Semiconductor device |
| DE4136511C2 (en) * | 1991-11-06 | 1995-06-08 | Forschungszentrum Juelich Gmbh | Process for the production of a Si / FeSi¶2¶ heterostructure |
| US5290715A (en) * | 1991-12-31 | 1994-03-01 | U.S. Philips Corporation | Method of making dielectrically isolated metal base transistors and permeable base transistors |
| EP0603461A3 (en) * | 1992-10-30 | 1996-09-25 | Ibm | Formation of 3-Dimensional silicon silicide structures. |
| US5666002A (en) * | 1993-06-22 | 1997-09-09 | Kabushiki Kaisha Toshiba | Semiconductor device with wiring layer in tunnel in semiconductor substrate |
| US5792679A (en) * | 1993-08-30 | 1998-08-11 | Sharp Microelectronics Technology, Inc. | Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant |
| US5563428A (en) * | 1995-01-30 | 1996-10-08 | Ek; Bruce A. | Layered structure of a substrate, a dielectric layer and a single crystal layer |
| US6686274B1 (en) * | 1998-09-22 | 2004-02-03 | Renesas Technology Corporation | Semiconductor device having cobalt silicide film in which diffusion of cobalt atoms is inhibited and its production process |
| TW541598B (en) * | 2002-05-30 | 2003-07-11 | Jiun-Hua Chen | Integrated chip diode |
| US7052939B2 (en) * | 2002-11-26 | 2006-05-30 | Freescale Semiconductor, Inc. | Structure to reduce signal cross-talk through semiconductor substrate for system on chip applications |
| FR2922360A1 (en) * | 2007-10-12 | 2009-04-17 | Soitec Silicon On Insulator | METHOD FOR MANUFACTURING SEMICONDUCTOR TYPE SUBSTRATE ON INTEGRATED GROUND PLAN INSULATOR. |
| FR2980636B1 (en) | 2011-09-22 | 2016-01-08 | St Microelectronics Rousset | PROTECTION OF AN ELECTRONIC DEVICE AGAINST REAR-BACK LASER ATTACK, AND CORRESPONDING SEMICONDUCTOR SUPPORT |
| US8889541B1 (en) | 2013-05-07 | 2014-11-18 | International Business Machines Corporation | Reduced short channel effect of III-V field effect transistor via oxidizing aluminum-rich underlayer |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3855009A (en) * | 1973-09-20 | 1974-12-17 | Texas Instruments Inc | Ion-implantation and conventional epitaxy to produce dielectrically isolated silicon layers |
| US4554045A (en) * | 1980-06-05 | 1985-11-19 | At&T Bell Laboratories | Method for producing metal silicide-silicon heterostructures |
| GB2078441A (en) * | 1980-06-17 | 1982-01-06 | Westinghouse Electric Corp | Forming impurity regions in semiconductor bodies by high energy ion irradiation |
| JPS59150419A (en) * | 1983-01-31 | 1984-08-28 | Toshiba Corp | Manufacture of compound semiconductor device |
| JPS59210642A (en) * | 1983-05-16 | 1984-11-29 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS60114122A (en) * | 1983-11-28 | 1985-06-20 | 松下精工株式会社 | Display apparatus of foliage plant |
| JPS63114122A (en) * | 1986-10-27 | 1988-05-19 | Yokogawa Hewlett Packard Ltd | Manufacture of conductive region in semiconductor substrate |
-
1986
- 1986-11-24 US US06/934,160 patent/US4816421A/en not_active Expired - Lifetime
-
1987
- 1987-11-16 DE DE3789361T patent/DE3789361T2/en not_active Expired - Fee Related
- 1987-11-16 EP EP87310087A patent/EP0271232B1/en not_active Expired - Lifetime
- 1987-11-23 KR KR1019870013173A patent/KR920007822B1/en not_active IP Right Cessation
- 1987-11-24 CA CA000552552A patent/CA1332695C/en not_active Expired - Fee Related
- 1987-11-24 JP JP62294293A patent/JPH0654770B2/en not_active Expired - Fee Related
-
1994
- 1994-09-22 HK HK100594A patent/HK100594A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR920007822B1 (en) | 1992-09-17 |
| DE3789361D1 (en) | 1994-04-21 |
| KR880006132A (en) | 1988-07-21 |
| EP0271232B1 (en) | 1994-03-16 |
| HK100594A (en) | 1994-09-30 |
| JPS63142631A (en) | 1988-06-15 |
| US4816421A (en) | 1989-03-28 |
| EP0271232A1 (en) | 1988-06-15 |
| JPH0654770B2 (en) | 1994-07-20 |
| DE3789361T2 (en) | 1994-06-23 |
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