CA1321836C - Apparatus and method for determining if a particular plug-in card is appropriate for use with an electronic processor - Google Patents
Apparatus and method for determining if a particular plug-in card is appropriate for use with an electronic processorInfo
- Publication number
- CA1321836C CA1321836C CA000614092A CA614092A CA1321836C CA 1321836 C CA1321836 C CA 1321836C CA 000614092 A CA000614092 A CA 000614092A CA 614092 A CA614092 A CA 614092A CA 1321836 C CA1321836 C CA 1321836C
- Authority
- CA
- Canada
- Prior art keywords
- error check
- card
- check code
- seed data
- retrieved
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2289—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by configuration test
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/006—Identification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/27—Built-in tests
Abstract
APPARATUS AND METHOD FOR DETERMINING
IF A PARTICULAR PLUG-IN CARD IS APPROPRIATE
FOR USE WITH AN ELECTRONIC PROCESSOR
ABSTRACT OF THE DISCLOSURE
An electronic processor based system is provided which is capable of receiving plug-in cards.
The plug-in card includes a memory which contains a first error check word which is a function of seed data words which are also stored in that memory. The first error check word is related to the seed data words by a predetermined algorithm. When the card is inserted in the processor system, the system reads the first error check word and the seed data words stored in the memory on the card. In one form, the processor system then performs its own independent calculation of a second error check word by using the same predetermined algorithm to operate on the seed data words retrieved from the card. The processor system compares the second error check word with the retrieved first error check word. If the second error check word is found to be the same as the retrieved first error check word, then the card is permitted to continue operation together with the system. However, if the second error check word is not found to be the same as the retrieved first error check word, then the card is not permitted to continue operating with the system.
IF A PARTICULAR PLUG-IN CARD IS APPROPRIATE
FOR USE WITH AN ELECTRONIC PROCESSOR
ABSTRACT OF THE DISCLOSURE
An electronic processor based system is provided which is capable of receiving plug-in cards.
The plug-in card includes a memory which contains a first error check word which is a function of seed data words which are also stored in that memory. The first error check word is related to the seed data words by a predetermined algorithm. When the card is inserted in the processor system, the system reads the first error check word and the seed data words stored in the memory on the card. In one form, the processor system then performs its own independent calculation of a second error check word by using the same predetermined algorithm to operate on the seed data words retrieved from the card. The processor system compares the second error check word with the retrieved first error check word. If the second error check word is found to be the same as the retrieved first error check word, then the card is permitted to continue operation together with the system. However, if the second error check word is not found to be the same as the retrieved first error check word, then the card is not permitted to continue operating with the system.
Description
1~2~ ~3~
30GF-lO03 APPARATUS AND METHOD FOR DETERMINING
IF A PARTICULAR PLUG-IN CARD IS APPROPRIATE
FOR USE UITH AN ELE.CTRONIC PROCESSOR
8ACKGROUND OF THE INyENTION
This invention relates in general to electronic data processors such as programmable lo~ic controllers and, more particularly, to electronic processors and controllers incorporating card slots for acceptin~ plug-in printed circuit cards.
Electronic data processors such as programmable logic controllers and computers are capable of IO accepting plug-in lo~ic cards to enhance the operation of the processor or to replace defective cards.
Typically, such plug-in cards include a multi-pin co~nector which may be plugged into a mating connector on the backplane of a programmable logic controller or into a matin8 connector which constitutes one slot on a motherboard bus. Unfortunately, with the relatively large number of different types of processors and potentially incompatible or inappropriate plug-in cards, 1:he number of possible processorlcard 1 32~83~
30CF-lO03 potentially incompatible or inappropriate plug-in cards, the number of possible processor/card combinations has become so large that it is often difficult for the user to know if a particular plug-in card is appropriate for use with a ~iven processor system. In some circumstances, dama8e to the processor, the plu~-in card or both can result if an improper plu~-in card is installed in a processor.
Accordingly, one object of the present invention is to provide an apparatus and method for determinin~
if a particular plug-in card is appropriate for use with a p'articular processor.
Another object of the present invention is to reduce the incidence of dama~e to electronic processors when inappropriate plu~-in cards are coupled to electronic processors.
In accordance with the present invention. an information processing system is provided which is capable of identifying an electronic circuit card prior to permitting operation of the electronic circuit on the card in the system. Each card to be plugged into the system has-a memory for storin~ a - first error check code and seed data. The first error check code is a function of the seed data stored on the card and is related to the seed data by a predetermined algorithm. The system further includes a microcomputer or other logic circuit capable of communicating with the card when the card is connected to the system. The microcomputer is programmed to ret'rieve the first error check code and the seed data from the oard and to calculate a second error check code from the retrieved sesd data using the predetermined algorithm. The microcomputer compares 132~ 83~
_ 3 30GF-lO03 the secord error chçck code with the retrieved first error check code. If the second error check code is idantical to the retrieved first error check code, the microcomputer reco~nizes the card and allows the system to operate usin~ the card. If the error check codes do not match, the microcomputer instructs the system to disregard the card, BRIEF DESCRIPTION OF THE DRAWINGS
The featurec of the invention believed to be novel are specifically set forth in the appended claims. However, the invention itself, both as to its structure and method of operation, may best be understood by referrin8 to the following description taken in conjunction with the accompanying drawings in which:
FIG. l is a block dia8ram of an electronic processor system ant a plug-in card which is ready for insertion into the processor system;
FIG. 2A is a representation of a memory map for the memory on the plug-in card;
FIG. 2B is a representation of the circular file map employed in the present invention: and FIG. 3 is- a flowchart of the operation of a control software program installed within memory in ths ~processor system to implement the present invention.
_,TAILED DESCRIPTION OF THE INVENTION_ FIG. l is a block dia~ram of an electronic ~321~3fi microprocèssor-based information processing system 100. System 100 includes an electronic processor unit 101 such as a programmable logic controller, a microprocessor-based compute!r or other computer. One processor unit which may be used as processor unit 101 is th0 Ser-ies 90-70 programmable logic controller, manufactured by GE Fanuc Aul:omation N.A., Inc. Those skilled in the art will appreciate, however, that the invention may be practiced in conjunction with other electronic processors as well. Processor unit 101 includes a main processor 102 such as a microprocessor, for example. Processor 102 is coupled via a bus 103 to a read only memory ~ROM) 104 and a random access memory ~RAM) 105. Read only memory 104 provides permanent storage for a selected operatin3 system which controls the general operation of processor unit 101 and further provides permanent stora~e for a control program which controls the specific operation of processor unit 101 in accordance with the present invention.
A multi-conductor connector 110 is coupled to processor unit 101 to permit processor unit 101 plug into a backplane 108. Plu3-in cards or printed circuit cards such as card 115 can be connected to backplane 108 which is connected to bus 103 of processor unit 110. 8ackplane 108 provides a convenient connection mechanism for interconnecting various types of plug-in cards or printed circuit boards. One end 115A of card 115 inclutes a plurality of conductive paths 120 for carrying electric signals from circuitry ~not shown) on card 115 throu~h backplane 108 and connector 110 to bus 103 of prscessor unit 101 and vice versa. Card end 115A is alternatively referred to as the mating portion 115A
~2~
of card 115. That is, card rnating portion llSA mates with connector 109 of backplane 108. The particular type of connector 110 shown in FIG. l is referred to as a VME connector while con1lector 115A is illustrated as an ed~e connector.
A memory 125, such as i~ read only memory (ROM), for example, is situated on card 115 for storing both seed data and first error check code, as explained subsequently. Seed data typically includes such information as the part number of card 115, the serial number of card 115, the manufacturing date of card 115 and other informa-tion specific to card 115. However-, seed ~ata may also include data which is not specifically related to the characteristics of card 115.
The first error check code stored in memory 115 is a function of the seed data stored in memory 115.
That is, the first error check cod~ is related to the seed data by a selected predetermined algorithm, an example of which is ~iven later. The first error check code is alternatively referred to as the first error check word.
In one embodiment of the invention, memory 125 is laid out as shown in the memory map of FIG. 2A which ~; depicts a memory segment or array 135. Memory lZ5 is shown as including M = 32 locations wherein each location is N=8 bits wide and exhibits its own unique address. In other words, each of these locations is capable of containin~ an 8 bit data word. A memory pointer 130 is defined to track the addresses of these M memory locations from i=O, i=l to i=M-l as shown in FIG. 2A, Locations i=0,1,2...M-2 are used for storing seed data. In other words, those memory locations of the memory segment 135 between adtresses i=l ant i=M-1 1321~3~
other than location ~= M-l itself are us~d for storing seed data. Memory location i=M-l Ithat is, location i=31 in this case) is used for storing the first check code, which as stated earlier, is a function of the seed data stored in the remainder of m~mory segment 135.
When a particular card 115 i5 plugged into backplane 108, processor 101 reads the seed data in memory locations i-0 through i=M-2 and thus retrieves that seed data. Also, when a card 115 is plugged into connector 110 of processor 101, processor 101 reads the first error check code in location i=M-l and thus retrieves the first error check code therein.
After retrievin8 the seed data ant the error check code as described above, processor 101 uses this same predetermined algorithm, which algorithm was previously stored in memory 104 of the processor, to operate on the seed data and to ~enerate an error check code which is referred to as the second error check code. Processor 101 then compares the retrieved first error code retrieved from memory 125 with the just calculated second error check code. If processor 101 determines that the second error check code is the same as the retrieved first error check code, this si~nifies that the particular card 115 has be~n verified as bein~ appropriate for processor 101 and processor 101 continues to operate and function with the card 115. That is, in this case, processor 101 continues to accept data from and send data and instructions to card 115 in the normal manner.
However, if processor 101 determines that the second error check code is not the same as the retrieved first error check code, thus signifying that the particular card 115 is improper, then processor 115 1 ~21835 ceases to operate iR conjunction with the particular card 115. That is, in this instance, processor 101 ceases to accept and proce!ss information from card 115.
The above described apparatus and procedure verifies that the particular card 115 is a proper card which is appropriate for use with processor 101.
Although for purposes of simplicity it has been stated that this verification occurs when the cart is plugget into backplane 108, more specifically, such 13 verification of the card will generally occur upon power-up of processor 101, that is, when the power to processor 101 is initially turned on after installation of card 115.
In thi 3 i nvention, any number of different algorithms may be selected as the above mentioned predetermined algorithm. Wh~t is important is that the error check code which is th~ output or result of the selected algorithm is a function of the seed data which is stored in memory 125 on card 115.
One such al~orithm is now described for purposes of example. It is noted that the p~rticular algorithm described below permits the calculating of error check codes in parallel over large amounts of seed data words in memory 125. Assuming the word length of the particular processor 101 is N ( N = 8 in this example) and that a cyclic redundancy code (CRC) polynomial is chosen which generates a code L bits long, then N CRC
codes are calculated in parallel over a memory array which is N bits wide by M bits long, for example, as in the memory array or segment 135 depicted in FIG.
2A.
More particularly, to accomplish this, a circular file 140 which is L bits long and N bits wide is created as depicted in FIG. 2B. This LxN circular file 140 is initialized with a value of zero (O).
Processor iOl gsnerates a file pointer 145 which counts in base L. As mentioned earlier, another pointer denoted as memory pointer 130 is 8enerated and kept by processor 101. such memory pointer 130 startin8 at i=O and ending at i=M-1. Memory pointer 130 points into memory array 135 as seen in FIG. 2A.
The value in memory array 135 pointet to by memory pointer 130 is placed into circular file 140 at the location pointed to by file pointer 145 and is exclusive OR'd at locations in circular file 140 pointed- to by file pointer-145 with relative offsets determined by all the terms in the original CRC poly-nomial except x.
An example will now be given to illustrate tha above point. If the CRC polynomial is selected to be x3~x2~1, then the value in memory array 135 ~ointed to by memory pointer 130 will be placed in the location in circular file 140 pointed to by file pointer 145 and exclusive OR'd to the locations pointed to by Modulo L (file pointer 145 +2) and Modulo L (file pointer 145 + 3). After this is done, both memory pointer 130 and file pointer 145 are incremented, and the above described operation is repeated until memory pointer 130 reaches a value of i=M.
After completion of the above described operations, N CRC codes exist in circular file 140.
Each of the N CRC codes in circular file 140 has been calculated oveF the N columns of memory array 135 and each of these N CRC codes carries the characteristics of the particular CRC polynomial employed to ~enerate the N CRC codes.
.
1~2~3~
_ g _ As explained subsequently, the N CRC codes are now combined in such a manner as to ~enerat~ one code which is N bits lon~. As a first step in ~enerating ono code which is N bits lon~, a zero vector of length S N is generated. As will be described subsequently, a series of operations will be performed on this vector, the final result of which will be designated the final vector. After each of these operations the resultant vector will for convenience still be designated a vector, althou~h the vector is chansed according to each operation performed thereon.
To reiterate, first, a zero vector of length N is generated. The first entry in circular file 140 is exclusive OR'd into the zero vector to 8enerate a resultant second vector. The second vector is then rotated left one bit to generate a third vector. The next (second) entry rin circular file 140 is then exclusive OR'd into the third vector to Benerate a fourth vector. The fourth vector is rotated left one bit. The above described procedure is repeated continuing with the fourth vector until all entries in circular file 140 are exclusive OR'd into the vector thus generating a final vector.
The final vector thus generated represents the first error check code which is stored in cart memory 125. It will now be seen that in this embodiment of the invention, the first error check code stored in memory location i=M-l is the final vector which is a function of the data stored in the remaining memory locations i=1,2...M-2.
Thus, in this particular embodiment of the invention, processor 101 verifies that card 115 is a proper card by retrieving the seed data in memory locations i-1,2...M-1, checking the model number, :, .. ~
132183~
vendor identifier,- and card characteristics and performing the same al~orithm operations just described on that seed data. to generate a resultant final vector which is the second error check code. As already explained in detail earlier, if the determined second error check code mat.ches the retriev~d first error check code, and all t,he seed data matches what the system can accept then card 115 is permitted to operate in conjunction with processor 101. Otherwise, if the card is of unknown type or the determined second error check code fails.to match the retrieved first error check code, the further.operation of card 115 in conjunction with processor 101 is not permitted.
The cessation of further interaction of processor 101 with the inappropriate card 115 may be accomplished in several different ways. For example, the operating system software within processor system 101 disables communications with the particular system port connector 110 into which the inappropriate card 115 is plug3ed. Alternatively, when the processor system operating system recognizes that an inappropriate card is plug~ed into port connector 115, power to card 115 may be switched off or an enable line coupled to card 115 is set to a disable state.
Whatever the particular manner selected, it is important that when card 115 is determined to be inappropriate, its operation in conjunction with processor system 101 is effectively discontinued.
FIG. 3 is a flowchart of a control software pro~ram stored in memory 104 within processor system 101 for execution to implement the present invention.
Power-up of processor system 101 occurs at block 200 at which initialization of system 101 also occurs.
132~83~
The seed data on card 115 is then retrieved at block ~05. The seed data is then compared with known acceptable data to determine of the board or card characteristics are acceptable to the processor system, block 206. If the characteristics, e.g., revision level, are not acceptable, the pro~ram jumps to block 230. If acceptable, the first error check code is retrieved at block-210. It will be recalled from the earlier discuseion that the first error check code stored in memory 125 is a function of the seed data stored therein and that the first error check code is related to the seed data by a predetermined al~orithm. The first error check code and the seed data were stored in card 115 at an earlier time.
Processor system 101 determines a second error check code at block 215 by employin~ the same predetermined algorithm as above to operate on the retrieved seed data to generate the second error check. The determined second error check code is compared with the retrieved first error check code at block 220. If the determined second error check code is found to be the same as the retrieved first error check code, ther.
~ as per block 225, system 101 is permitted to continue - operation with card 115. However, if the second error check code is determined to be different than the retrieved first error check code, then as per block 230, card 115 is not permitted to continue functionin~
together with processor system 101. That is, communications between card 115 and processor system 115 are caused to cease until th~ next power-on of processor system 101 or other appropriate time.
An apparatus for verifyin~ if a particular card is appropriate for operation ir, a selected processor system has been described in detail above, and a 132~8~
30GF-lO03 method for determi~in8 if a particular cart isappropriate for operating with a selected processor system has also been described. Such method is summarized in the flowchart of FIG. 3 and the foregoing discussion. The present invention may be advantageously used to reduce the incidence of dama~e to electronic processor systems when inappropriate plug-in cards are inserted into such electronic processor systems. Also, the invention advantageously avoids the corruption of data within processor system lOl which may otherwise result if an improper plug-in-c~rd were connected to processor lOl.
In addition, the invention will also screen cards which do not match the check algorithm and may be counterfit.
~ While only certain preferred features of the invention have been shown by way of illustration. many modifications and changes will occur to those skilled-in the art. For example, other error check algorithms may be employed or the processor system lOl may use an algorithm complementary to (rather than the same as) the algorithm used to generate the error check code for the card so that a predetermined value is produced when the error check codes are compared. In another form, the algorithm used to ~enerate the error check ~ code on the card may be different than the system ;~ algorithm. but complementary in the sense that a pr~determined value is 8enerated by the system algorithm when the seed data is combined with the error check code on the card. It is, therefore, to be - ~ understood that the present claims are intended to cover all such modifications and changes which fall within the true spirit of the invention.
30GF-lO03 APPARATUS AND METHOD FOR DETERMINING
IF A PARTICULAR PLUG-IN CARD IS APPROPRIATE
FOR USE UITH AN ELE.CTRONIC PROCESSOR
8ACKGROUND OF THE INyENTION
This invention relates in general to electronic data processors such as programmable lo~ic controllers and, more particularly, to electronic processors and controllers incorporating card slots for acceptin~ plug-in printed circuit cards.
Electronic data processors such as programmable logic controllers and computers are capable of IO accepting plug-in lo~ic cards to enhance the operation of the processor or to replace defective cards.
Typically, such plug-in cards include a multi-pin co~nector which may be plugged into a mating connector on the backplane of a programmable logic controller or into a matin8 connector which constitutes one slot on a motherboard bus. Unfortunately, with the relatively large number of different types of processors and potentially incompatible or inappropriate plug-in cards, 1:he number of possible processorlcard 1 32~83~
30CF-lO03 potentially incompatible or inappropriate plug-in cards, the number of possible processor/card combinations has become so large that it is often difficult for the user to know if a particular plug-in card is appropriate for use with a ~iven processor system. In some circumstances, dama8e to the processor, the plu~-in card or both can result if an improper plu~-in card is installed in a processor.
Accordingly, one object of the present invention is to provide an apparatus and method for determinin~
if a particular plug-in card is appropriate for use with a p'articular processor.
Another object of the present invention is to reduce the incidence of dama~e to electronic processors when inappropriate plu~-in cards are coupled to electronic processors.
In accordance with the present invention. an information processing system is provided which is capable of identifying an electronic circuit card prior to permitting operation of the electronic circuit on the card in the system. Each card to be plugged into the system has-a memory for storin~ a - first error check code and seed data. The first error check code is a function of the seed data stored on the card and is related to the seed data by a predetermined algorithm. The system further includes a microcomputer or other logic circuit capable of communicating with the card when the card is connected to the system. The microcomputer is programmed to ret'rieve the first error check code and the seed data from the oard and to calculate a second error check code from the retrieved sesd data using the predetermined algorithm. The microcomputer compares 132~ 83~
_ 3 30GF-lO03 the secord error chçck code with the retrieved first error check code. If the second error check code is idantical to the retrieved first error check code, the microcomputer reco~nizes the card and allows the system to operate usin~ the card. If the error check codes do not match, the microcomputer instructs the system to disregard the card, BRIEF DESCRIPTION OF THE DRAWINGS
The featurec of the invention believed to be novel are specifically set forth in the appended claims. However, the invention itself, both as to its structure and method of operation, may best be understood by referrin8 to the following description taken in conjunction with the accompanying drawings in which:
FIG. l is a block dia8ram of an electronic processor system ant a plug-in card which is ready for insertion into the processor system;
FIG. 2A is a representation of a memory map for the memory on the plug-in card;
FIG. 2B is a representation of the circular file map employed in the present invention: and FIG. 3 is- a flowchart of the operation of a control software program installed within memory in ths ~processor system to implement the present invention.
_,TAILED DESCRIPTION OF THE INVENTION_ FIG. l is a block dia~ram of an electronic ~321~3fi microprocèssor-based information processing system 100. System 100 includes an electronic processor unit 101 such as a programmable logic controller, a microprocessor-based compute!r or other computer. One processor unit which may be used as processor unit 101 is th0 Ser-ies 90-70 programmable logic controller, manufactured by GE Fanuc Aul:omation N.A., Inc. Those skilled in the art will appreciate, however, that the invention may be practiced in conjunction with other electronic processors as well. Processor unit 101 includes a main processor 102 such as a microprocessor, for example. Processor 102 is coupled via a bus 103 to a read only memory ~ROM) 104 and a random access memory ~RAM) 105. Read only memory 104 provides permanent storage for a selected operatin3 system which controls the general operation of processor unit 101 and further provides permanent stora~e for a control program which controls the specific operation of processor unit 101 in accordance with the present invention.
A multi-conductor connector 110 is coupled to processor unit 101 to permit processor unit 101 plug into a backplane 108. Plu3-in cards or printed circuit cards such as card 115 can be connected to backplane 108 which is connected to bus 103 of processor unit 110. 8ackplane 108 provides a convenient connection mechanism for interconnecting various types of plug-in cards or printed circuit boards. One end 115A of card 115 inclutes a plurality of conductive paths 120 for carrying electric signals from circuitry ~not shown) on card 115 throu~h backplane 108 and connector 110 to bus 103 of prscessor unit 101 and vice versa. Card end 115A is alternatively referred to as the mating portion 115A
~2~
of card 115. That is, card rnating portion llSA mates with connector 109 of backplane 108. The particular type of connector 110 shown in FIG. l is referred to as a VME connector while con1lector 115A is illustrated as an ed~e connector.
A memory 125, such as i~ read only memory (ROM), for example, is situated on card 115 for storing both seed data and first error check code, as explained subsequently. Seed data typically includes such information as the part number of card 115, the serial number of card 115, the manufacturing date of card 115 and other informa-tion specific to card 115. However-, seed ~ata may also include data which is not specifically related to the characteristics of card 115.
The first error check code stored in memory 115 is a function of the seed data stored in memory 115.
That is, the first error check cod~ is related to the seed data by a selected predetermined algorithm, an example of which is ~iven later. The first error check code is alternatively referred to as the first error check word.
In one embodiment of the invention, memory 125 is laid out as shown in the memory map of FIG. 2A which ~; depicts a memory segment or array 135. Memory lZ5 is shown as including M = 32 locations wherein each location is N=8 bits wide and exhibits its own unique address. In other words, each of these locations is capable of containin~ an 8 bit data word. A memory pointer 130 is defined to track the addresses of these M memory locations from i=O, i=l to i=M-l as shown in FIG. 2A, Locations i=0,1,2...M-2 are used for storing seed data. In other words, those memory locations of the memory segment 135 between adtresses i=l ant i=M-1 1321~3~
other than location ~= M-l itself are us~d for storing seed data. Memory location i=M-l Ithat is, location i=31 in this case) is used for storing the first check code, which as stated earlier, is a function of the seed data stored in the remainder of m~mory segment 135.
When a particular card 115 i5 plugged into backplane 108, processor 101 reads the seed data in memory locations i-0 through i=M-2 and thus retrieves that seed data. Also, when a card 115 is plugged into connector 110 of processor 101, processor 101 reads the first error check code in location i=M-l and thus retrieves the first error check code therein.
After retrievin8 the seed data ant the error check code as described above, processor 101 uses this same predetermined algorithm, which algorithm was previously stored in memory 104 of the processor, to operate on the seed data and to ~enerate an error check code which is referred to as the second error check code. Processor 101 then compares the retrieved first error code retrieved from memory 125 with the just calculated second error check code. If processor 101 determines that the second error check code is the same as the retrieved first error check code, this si~nifies that the particular card 115 has be~n verified as bein~ appropriate for processor 101 and processor 101 continues to operate and function with the card 115. That is, in this case, processor 101 continues to accept data from and send data and instructions to card 115 in the normal manner.
However, if processor 101 determines that the second error check code is not the same as the retrieved first error check code, thus signifying that the particular card 115 is improper, then processor 115 1 ~21835 ceases to operate iR conjunction with the particular card 115. That is, in this instance, processor 101 ceases to accept and proce!ss information from card 115.
The above described apparatus and procedure verifies that the particular card 115 is a proper card which is appropriate for use with processor 101.
Although for purposes of simplicity it has been stated that this verification occurs when the cart is plugget into backplane 108, more specifically, such 13 verification of the card will generally occur upon power-up of processor 101, that is, when the power to processor 101 is initially turned on after installation of card 115.
In thi 3 i nvention, any number of different algorithms may be selected as the above mentioned predetermined algorithm. Wh~t is important is that the error check code which is th~ output or result of the selected algorithm is a function of the seed data which is stored in memory 125 on card 115.
One such al~orithm is now described for purposes of example. It is noted that the p~rticular algorithm described below permits the calculating of error check codes in parallel over large amounts of seed data words in memory 125. Assuming the word length of the particular processor 101 is N ( N = 8 in this example) and that a cyclic redundancy code (CRC) polynomial is chosen which generates a code L bits long, then N CRC
codes are calculated in parallel over a memory array which is N bits wide by M bits long, for example, as in the memory array or segment 135 depicted in FIG.
2A.
More particularly, to accomplish this, a circular file 140 which is L bits long and N bits wide is created as depicted in FIG. 2B. This LxN circular file 140 is initialized with a value of zero (O).
Processor iOl gsnerates a file pointer 145 which counts in base L. As mentioned earlier, another pointer denoted as memory pointer 130 is 8enerated and kept by processor 101. such memory pointer 130 startin8 at i=O and ending at i=M-1. Memory pointer 130 points into memory array 135 as seen in FIG. 2A.
The value in memory array 135 pointet to by memory pointer 130 is placed into circular file 140 at the location pointed to by file pointer 145 and is exclusive OR'd at locations in circular file 140 pointed- to by file pointer-145 with relative offsets determined by all the terms in the original CRC poly-nomial except x.
An example will now be given to illustrate tha above point. If the CRC polynomial is selected to be x3~x2~1, then the value in memory array 135 ~ointed to by memory pointer 130 will be placed in the location in circular file 140 pointed to by file pointer 145 and exclusive OR'd to the locations pointed to by Modulo L (file pointer 145 +2) and Modulo L (file pointer 145 + 3). After this is done, both memory pointer 130 and file pointer 145 are incremented, and the above described operation is repeated until memory pointer 130 reaches a value of i=M.
After completion of the above described operations, N CRC codes exist in circular file 140.
Each of the N CRC codes in circular file 140 has been calculated oveF the N columns of memory array 135 and each of these N CRC codes carries the characteristics of the particular CRC polynomial employed to ~enerate the N CRC codes.
.
1~2~3~
_ g _ As explained subsequently, the N CRC codes are now combined in such a manner as to ~enerat~ one code which is N bits lon~. As a first step in ~enerating ono code which is N bits lon~, a zero vector of length S N is generated. As will be described subsequently, a series of operations will be performed on this vector, the final result of which will be designated the final vector. After each of these operations the resultant vector will for convenience still be designated a vector, althou~h the vector is chansed according to each operation performed thereon.
To reiterate, first, a zero vector of length N is generated. The first entry in circular file 140 is exclusive OR'd into the zero vector to 8enerate a resultant second vector. The second vector is then rotated left one bit to generate a third vector. The next (second) entry rin circular file 140 is then exclusive OR'd into the third vector to Benerate a fourth vector. The fourth vector is rotated left one bit. The above described procedure is repeated continuing with the fourth vector until all entries in circular file 140 are exclusive OR'd into the vector thus generating a final vector.
The final vector thus generated represents the first error check code which is stored in cart memory 125. It will now be seen that in this embodiment of the invention, the first error check code stored in memory location i=M-l is the final vector which is a function of the data stored in the remaining memory locations i=1,2...M-2.
Thus, in this particular embodiment of the invention, processor 101 verifies that card 115 is a proper card by retrieving the seed data in memory locations i-1,2...M-1, checking the model number, :, .. ~
132183~
vendor identifier,- and card characteristics and performing the same al~orithm operations just described on that seed data. to generate a resultant final vector which is the second error check code. As already explained in detail earlier, if the determined second error check code mat.ches the retriev~d first error check code, and all t,he seed data matches what the system can accept then card 115 is permitted to operate in conjunction with processor 101. Otherwise, if the card is of unknown type or the determined second error check code fails.to match the retrieved first error check code, the further.operation of card 115 in conjunction with processor 101 is not permitted.
The cessation of further interaction of processor 101 with the inappropriate card 115 may be accomplished in several different ways. For example, the operating system software within processor system 101 disables communications with the particular system port connector 110 into which the inappropriate card 115 is plug3ed. Alternatively, when the processor system operating system recognizes that an inappropriate card is plug~ed into port connector 115, power to card 115 may be switched off or an enable line coupled to card 115 is set to a disable state.
Whatever the particular manner selected, it is important that when card 115 is determined to be inappropriate, its operation in conjunction with processor system 101 is effectively discontinued.
FIG. 3 is a flowchart of a control software pro~ram stored in memory 104 within processor system 101 for execution to implement the present invention.
Power-up of processor system 101 occurs at block 200 at which initialization of system 101 also occurs.
132~83~
The seed data on card 115 is then retrieved at block ~05. The seed data is then compared with known acceptable data to determine of the board or card characteristics are acceptable to the processor system, block 206. If the characteristics, e.g., revision level, are not acceptable, the pro~ram jumps to block 230. If acceptable, the first error check code is retrieved at block-210. It will be recalled from the earlier discuseion that the first error check code stored in memory 125 is a function of the seed data stored therein and that the first error check code is related to the seed data by a predetermined al~orithm. The first error check code and the seed data were stored in card 115 at an earlier time.
Processor system 101 determines a second error check code at block 215 by employin~ the same predetermined algorithm as above to operate on the retrieved seed data to generate the second error check. The determined second error check code is compared with the retrieved first error check code at block 220. If the determined second error check code is found to be the same as the retrieved first error check code, ther.
~ as per block 225, system 101 is permitted to continue - operation with card 115. However, if the second error check code is determined to be different than the retrieved first error check code, then as per block 230, card 115 is not permitted to continue functionin~
together with processor system 101. That is, communications between card 115 and processor system 115 are caused to cease until th~ next power-on of processor system 101 or other appropriate time.
An apparatus for verifyin~ if a particular card is appropriate for operation ir, a selected processor system has been described in detail above, and a 132~8~
30GF-lO03 method for determi~in8 if a particular cart isappropriate for operating with a selected processor system has also been described. Such method is summarized in the flowchart of FIG. 3 and the foregoing discussion. The present invention may be advantageously used to reduce the incidence of dama~e to electronic processor systems when inappropriate plug-in cards are inserted into such electronic processor systems. Also, the invention advantageously avoids the corruption of data within processor system lOl which may otherwise result if an improper plug-in-c~rd were connected to processor lOl.
In addition, the invention will also screen cards which do not match the check algorithm and may be counterfit.
~ While only certain preferred features of the invention have been shown by way of illustration. many modifications and changes will occur to those skilled-in the art. For example, other error check algorithms may be employed or the processor system lOl may use an algorithm complementary to (rather than the same as) the algorithm used to generate the error check code for the card so that a predetermined value is produced when the error check codes are compared. In another form, the algorithm used to ~enerate the error check ~ code on the card may be different than the system ;~ algorithm. but complementary in the sense that a pr~determined value is 8enerated by the system algorithm when the seed data is combined with the error check code on the card. It is, therefore, to be - ~ understood that the present claims are intended to cover all such modifications and changes which fall within the true spirit of the invention.
Claims (9)
1. An information processing system comprising:
an electronic circuit card including a memory for storing a first error check code and seed data, said first error check code being a function of the seed data stored on said card, said first error check code being related to said seed data by a predetermined algorithm; and An electronic processor capable of communicating with said card when said card is connected to said processor, said electronic processor including:
retrieving means, for retrieving said first error check code and said seed data from said card, thus providing a retrieved first error check code and retrieved seed data;
means for calculating a second error check code from said retrieved seed data using said predetermined algorithm;
comparing means for comparing said second error check code with said retrieved first error check code; and means for permitting said electronic circuit card to function with said system if said comparing means produces a predetermined value upon comparing said second error code to said retrieved first error check code and otherwise not permitting said electronic circuit card to function with said system.
an electronic circuit card including a memory for storing a first error check code and seed data, said first error check code being a function of the seed data stored on said card, said first error check code being related to said seed data by a predetermined algorithm; and An electronic processor capable of communicating with said card when said card is connected to said processor, said electronic processor including:
retrieving means, for retrieving said first error check code and said seed data from said card, thus providing a retrieved first error check code and retrieved seed data;
means for calculating a second error check code from said retrieved seed data using said predetermined algorithm;
comparing means for comparing said second error check code with said retrieved first error check code; and means for permitting said electronic circuit card to function with said system if said comparing means produces a predetermined value upon comparing said second error code to said retrieved first error check code and otherwise not permitting said electronic circuit card to function with said system.
2. The information processing system of claim 1 wherein said comparing means produces said predetermined value when said second error check code is identical to said first error check code.
3. The information processing system of claim 1 and including means for comparing said seed data to preselected data stored in said processor and for disabling operation of said electronic circuit card if said seed data does not match said preselected data.
4. The information processing system of claim 3 wherein said seed data includes at least data representative of model number, vendor identifying number, and characteristics of said electronic circuit card.
5. The information processing system of claim 1 wherein said predetermined algorithm is of the form x3 + x2 + 1.
6. The information processing system of claim 1 wherein said means for calculating a second error check code comprises a circular file L bits long and N bits wide, where L is the desired number of bits in the second error check code and N is the bits per word used in said system, said calculating means being operative to repetitively exclusive OR
each entry in said file with an adjacent entry to produce a result, rotate said result by one bit and repeat the exclusive OR operation until all of the entries in the circular file are exclusive OR'd into the second error check code.
each entry in said file with an adjacent entry to produce a result, rotate said result by one bit and repeat the exclusive OR operation until all of the entries in the circular file are exclusive OR'd into the second error check code.
7. In an information processing system capable of accepting electronic circuit cards therein, a method of determining if a particular card is appropriate for use in said system, said method comprising the steps of:
storing a first error check code on said card, said first error check code being a function of seed data stored on said card, said first error check code being related to said seed data by a first predetermined algorithm;
retrieving said first error check code from said card and storing it in the system;
retrieving the seed data stored on said card and storing it in the system;
calculating a second error check code from said retrieved seed data using a second predetermined algorithm;
summing said second error check coda with said retrieved first error check code; and permitting said card to function with said system if said step of summing produces a predetermined value and otherwise not permitting said card to function with said system.
storing a first error check code on said card, said first error check code being a function of seed data stored on said card, said first error check code being related to said seed data by a first predetermined algorithm;
retrieving said first error check code from said card and storing it in the system;
retrieving the seed data stored on said card and storing it in the system;
calculating a second error check code from said retrieved seed data using a second predetermined algorithm;
summing said second error check coda with said retrieved first error check code; and permitting said card to function with said system if said step of summing produces a predetermined value and otherwise not permitting said card to function with said system.
8. The method of claim 7 and including the steps of:
storing in the system preselected values of acceptable seed data;
comparing the stored seed to the retrieved seed data; and disabling operation of the card if the stored seed data is outside the preselected values of acceptable seed data.
storing in the system preselected values of acceptable seed data;
comparing the stored seed to the retrieved seed data; and disabling operation of the card if the stored seed data is outside the preselected values of acceptable seed data.
9. The method of claim 7 wherein said first and said second predetermined algorithms are identical, said step of summing comprising the step of comparing the first error check code with the second error check code for determining identity therebetween.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US369,898 | 1989-06-22 | ||
| US07/369,898 US5018146A (en) | 1989-06-22 | 1989-06-22 | Apparatus and method for determining if a particular plug-in card is appropriate for use with an electronic processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1321836C true CA1321836C (en) | 1993-08-31 |
Family
ID=23457387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000614092A Expired - Lifetime CA1321836C (en) | 1989-06-22 | 1989-09-28 | Apparatus and method for determining if a particular plug-in card is appropriate for use with an electronic processor |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5018146A (en) |
| CA (1) | CA1321836C (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5528602A (en) * | 1992-12-30 | 1996-06-18 | International Business Machines Corporation | Method for determining computer subsystem property |
| US5892683A (en) * | 1993-03-31 | 1999-04-06 | Altera Coporation | Program compatibility recognition for a programmable logic device |
| US5715422A (en) * | 1994-03-01 | 1998-02-03 | New Media Corp. | Data-storage and processing card having on-board data, processing instructions, and processing memory |
| US5926642A (en) * | 1995-10-06 | 1999-07-20 | Advanced Micro Devices, Inc. | RISC86 instruction set |
| US5790814A (en) * | 1996-01-23 | 1998-08-04 | Dell U.S.A., L.P. | Technique for supporting semi-compliant PCI devices behind a PCI-to-PCI bridge |
| US6216186B1 (en) | 1998-06-15 | 2001-04-10 | Sun Microsystems, Inc. | Modular computer system including compatibility evaluation logic |
| US6549027B1 (en) * | 2000-02-01 | 2003-04-15 | Sun Microsystems, Inc. | Apparatus and method for testing for compatibility between circuit boards |
| DE10052620B4 (en) * | 2000-10-24 | 2008-07-10 | Abb Ag | Method for initialization of a pluggable electrical unit |
| JP4190789B2 (en) * | 2002-04-05 | 2008-12-03 | 日本電気株式会社 | Method and system for automatically concealing PCI expansion card in computer system |
| DE10340411B4 (en) * | 2003-09-02 | 2005-10-13 | Infineon Technologies Ag | Device and method for the safe execution of a program |
| JP2005157551A (en) * | 2003-11-21 | 2005-06-16 | Canon Inc | Electronic apparatus, and control method thereof |
| BE1021333B1 (en) * | 2014-06-30 | 2015-10-30 | eWON SA | MODULAR M2M COMMUNICATION DEVICE |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4523314A (en) * | 1983-02-07 | 1985-06-11 | Sperry Corporation | Read error occurrence detector for error checking and correcting system |
| JPS6191790A (en) * | 1984-10-12 | 1986-05-09 | カシオ計算機株式会社 | Card collator |
| US4720831A (en) * | 1985-12-02 | 1988-01-19 | Advanced Micro Devices, Inc. | CRC calculation machine with concurrent preset and CRC calculation function |
| US4709367A (en) * | 1986-03-31 | 1987-11-24 | International Business Machines Corporation | Method and apparatus for distinguishing between diskettes in a diskette drive |
| JP2514954B2 (en) * | 1987-03-13 | 1996-07-10 | 三菱電機株式会社 | IC card |
| US4907231A (en) * | 1987-05-06 | 1990-03-06 | Fuji Photo Film Co., Ltd. | Memory cartridge-connectable electronic device such as electronic still video camera |
-
1989
- 1989-06-22 US US07/369,898 patent/US5018146A/en not_active Expired - Lifetime
- 1989-09-28 CA CA000614092A patent/CA1321836C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5018146A (en) | 1991-05-21 |
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