CA1320271C - Computer memory back-up with automatic tape positioning - Google Patents

Abstract

COMPUTER MEMORY BACK-UP
WITH AUTOMATIC TAPE POSITIONING

ABSTRACT OF THE DISCLOSURE

The interface apparatus couples a video recording device to the parallel data channel of a computer system and also to the computer video output circuitry, so that both digital information (such as computer programs or data files) and analog information (such as video signals for displaying on a television monitor) may be stored on the same video recording medium. The apparatus permits storage of both digital information and human readable information in a convenient back-to-back relationship. The interface permits the computer video monitor to directly display stored or live video broadcasts, without computer intervention. The invention allows the display of graphic, photographic and motion picture information in analog format thereby eliminating information lost through digitizing. An automatic search mode permits the computer to direct the video recording device to search for a predetermined location on the recording medium at high speed without human intervention. The computer is capable of controlling the video recording device by means of the remote control port of the video recorder.

Description

~32~2~

COMPUTER MEMORY BACK-UP
WITH AUTOMATIC TAPE POSITIONING

BACXGROUND AND SUMMARY OF THE INVENTION

This invention relates generally to computer data storage and video display equipment. More particularly, the invention relates to an apparatus for effecting the storage of computer generated digital information and analog video information using a video recording device such as a video tape recorder, VCR, or the like. Further, the invention relates to an apparatus for displaying video and television signals on a computer CRT monitor.
Present day computer systems employ architectures which provide for the storage of digital information by a number of different mechanisms, each having certain advantages and disadvantages. At the center of most computer systems is the central processing unit or ÇPU
which interprets, processes and executes instructions (¢omputer programs). ~he CPU coordinates the cooperation of varlous othex elements of the computer system and also over~ee~ the lnput/output procedures whereby the computer ~yutem communlcates wlth peripheral devlces~ The instructions or computer programs which the central procesulng unlt executes are ~tored ln some form of memory device where they may be accessed by the CPU upon demand.
These instruction~ are digltal information usually comprising a plurality of binary digits or bits arranged into groups, commonly called bytes or words. In addition to executing instructions, the CPU aluo generates digital in~ormation also as groups o~ binary digits. The digital ln~ormatlon so generated may represent addltional computer instructlons to be executed by the CPU

-2- ~ ~2~271 or by some other processing unit, or the digital information may represent data to be stored, acted upon or displayed.
Text files produced by word processing programs and source code computer program listings written in higher level computer languages are two examples of such data.
In order to store digital information, whether it represents computer instructions or data, so that the CPU can access it, and process and manipulate it quickly, random access memory (RAM) is included as a part of the computer system. Random access memory comprises an array of individually addressable electronic data cells, each capable of storing one binary digit or bit. Ordinarily these data cells are arranged in groups corresponding to the byte or word format of the digital information to be stored therein. One advantage of RAM memory is that digital information can be stored or retrieved very rapidly.
One disadvantage of present day RAM is that it does not retain stored digital in~ormation when electrical power is interrupted. Because of this disadvantage with RAM
memory, most computer systems also employ an alternate rorm o~ data storage, usually some form of magnetic data ~torage (~loppy disks, fixed disks or hard disks, and the like). Such magnetic data storage media have the advantage o~ being able to ~tore digital in~ormation magnetically, so that a constant ~upply o~ electrical power is not required.
one disadvantage o~ magnetic data storage ~y~tems i5 that the magnetic media are vulnerable to contamination by dirt, dust and other ~oreign materials.
In the case o~ the hard disk or ~ixed disk system, this w lnerability to ~oreign contaminants is particularly acute ~ince ~uch systems employ rapidly rotating disks (3,000 rpm) and read/write heads positioned less than the thickness o~ a human hair above the sur~ace o~ the disk. Even minute ~oreign particles, such as a single human hair, can cause the read/write head to bounce and crash into the disk ~urface, causing permanent damage almost -3- ~3~2~

instantaneously. Because of such vulnerability to contaminants it is considered wise practice to make duplicate or back-up copies of the stored data. In the case of floppy disk systems, a second diskette may be recorded to serve as a back-up copy. With hard disks, on the other hand, it has not proven practical to make back-up copies using additional hard disk storage devices, due to the relatively high cost of additional hard disk devices.
Similarly, it has not proven practical to record back-up copies of a hard disk memory onto floppy diskettes, since a typical ten megabyte hard disk memory would require some thirty to forty or more individual floppy diskettes in order to provide a full back-up copy.
Due to the impracticality of using floppy diskettes to back-up hard disk memory systems, some hard disk systems include provisions for making back-up copies in serial ~ormat on cassette tapes, known as tape streamers. With such tape streamer 6ystems the digital information is stored directly, in serial form, as a continuous sequence or stream o~ bits. Such tape streamer systems are comparatively quite expensive. In addition to tape streamers, there have been proposed other systems for producing bacX-up copies using audio and video cassette tape recording systems.
A common problem with all tape back-up systems, digital tape 6treamers, audio cassettes and video cassettes alike, is that the digital in~ormation serially stored on such devices may not be randomly accessed and viewed by the human operator. ~he human operator cannot browse through the contents o~ the back-up copy as one might browse through chapter headings o~ a book, since these back-up systems do not provide any human readable in~ormation.
While most computer systems employ a video monitor ~or displaying human readable in~ormation, these back-up systems o~ the prior art cannot convey video in~ormation to _ ~4~ ~3 2 a 2~ 1 such video monitors directly while the back-up tape is being replayed.
The present invention overcomes these shortcomings by providing a computer memory back-up system which permits the storage of both digital information (computer instructions ; and digital data) as well as analog video information using a single video recording apparatus, such as a video tape recorder, VCR, or the like. Using the invention, the computer operator can back-up the entire computer memory, or only selected files or blocks of computer memory, while at the same time recording analog video information that may be played back directly by the computer's video monitor or an auxiliary monitor or television set without ~urther processing by the computer's central processing unit. The video analog information may, for example, comprise an informative header conveying human readable in~ormation about the digital data stored elsewhere in the video recording device.
The invention greatly simplifies producing back-up copies of computer data files or programs by permitting the operator to record a human readable file header describing the data file or program to follow. The computer operator i~ thus able to brow~e through the content~ Or the inrormation ~tored in the video recording d-vi¢-, to locate a particular rile or program or to make ¢hange~ to that rile or program without arre¢ting other data ~tored el~ewhere in the video recording device.
The invention supports the broad capability of r-¢ording and di~playing any type of analog video inrormation, not ~ust human readable text. For example, graphi¢ inrormation including both still and motion pictures may be integrated with digital information upon the ~a~e recording medium. Because the analog video information can be directly displayed using the computer's video monitor or an auxiliary monitor or televi~ion ~et w~thout manipulatlon by the ¢entral proce~sing unit, the video -5- 1 3 2 ~27 ~

information enjoys an inherently much higher resolution than computer generated graphics. Photographs, motion pictures, blueprints and other visual information can be read and stored in analog form using video television cameras or the like without the need to digitize the information to make it computer compatible. Furthermore, the invention also supports the capability to display video or television signals directly upon the computer CRT
monitor. This feature may be used, for example, to display prerecorded taped or broadcast television, or live television on the CRT monitor--for training sessions, lnteroffice communication or the like.
In accordance with the invention, an apparatus ~or storing and retrieving digital and analog information using a video recording device having a means for serially storing video information is provided. The invention is intended ~or use with a computer system having a central processing unit for processing digital information through a parallel data channel and further having a video output means responsive to the central processing unit for generating analog in~ormation and ~or generating video sync signals.
The lnvention comprises a parallel to serial conversion mean~ coupled to the parallel data channel to receive the digital ln~ormation and to provide the digital in~ormation in ~erial ~orm. A ~ignal pro¢essing ~eans is receptive o~ the analog information and video syna signals and is ~urther ¢oupled to the ¢onversion means to receive the digital information. The signal processing means selectively provides to the video recording device either a ~irst video signal or a second video signal. The ~irst video signal ¢omprises the composite o~ the analog in~ormation and the video sync signals while the second video signal comprises the composite of the digital in~ormation and the video syn¢ ~ignals. In this ~ashion, both analog in~ormation and digital in~ormation may be stored upon the serial storage medium o~ the video re¢ording device.

-6- ~3~2~1 When used in conjunction with a video monitor, such as a video monitor responsive to the analog information and video sync signals generated by the computer system, e.g., the computer video monitor, the invention has the capability of directing analog video information directly to the video monitor without further processing by the central processing unit. In accordance with the invention a signal directing means controlled by the central processing unit and receptive of the serially stored video information from the video recording device is provided. The signal directing means is further receptive of analog information and video sync signals from the video output means of the computer ~ystem. The signal directing means is coupled to the video monitor for selectively directing to the video monitor either the ~erially stored video information from the recording device or the analog information and video sync ~ignals from the computer system, thereby permitting the visual display o~ both sources of information upon the same video monitor.
In the preferred embodiment the invention is adapted to plug into one of the computer systems peripheral expansion ~lot~, ~o that it may be housed entiroly within the computer cabln-t. The invention thu~ takes up no valuable desk top ~pace and i~ capable o~ deriving electrical power directly ~rom the computer ~y~tem power supply through the expansion ~lot. The invention ~urther comprises ~irmware storage o~ all computer instruction~ needed to a~sist the central proc-ssing unit in interfacing with the invention automatically. Such instructions make it possible for the invention to determine what type of computer system it is connected to and also the computer memory address or addresses where programs or data to be ~aved presently reside.
The invention ~urther include~ means for extracting video sync ~ignals directly ~rom the video output circuit within the computer system to insure compatability -7- ~32~2~

and also to make most efficient use of existing hardware without duplication. A mixing circuit is receptive of the serialized digital information from the signal processing means and also receptive of the extracted video ~sync signals. The mixing circuit provides a data video signal comprising digital information and video sync signals in a predetermined relationship, providing data video signals which are compatable with the storage format of the video recording device.
The invention further provides automatic search capabilities, whereby digital information can be stored and retrieved at a predetermined location on the video recording medium. A means is provided for converting the digital information into video information so that the in~ormation may be stored on the video recording medium.
A means is also provided converting the serially stored video information into digital information, so that it may be processed by the computer system. In addition, a means ~or encoding a plurality of serially spaced markers on the recording medium is provided. Each marker corresponds to a different storage location on the medium. A
control means responsive to the central processing unit and also responsive to the markers controls the video recording devioe causing it to position the recording medium at a location prescribed by the computer system. When a video tape recorder is used as the video recording device, the markers may be encoded on the audio recording track of the video tape, ucing a self-clocking code such as the Manche~ter code or the equivalent. If necessary, a video tape recorder may require modi~ication to permit the audio read/write head to remain in contact with or in close proximity to the recording medium when the video recorder i~ operating in fast forward or ~ast reverse modes.
The automatic search function permits the computer, acting through the interface apparatus o~ the invention, to ~earch for a particular location on the tape or -8- ~2~27~

recording medium at fast forward or fast reverse speeds, and then to automatically commence recording or playback at normal recording and playback speeds. The automatic search feature thereby allows the computer to locate a desired data file quickly and automatically.
In accordance with the automatic tape positioning aspects of the invention, there is provided an apparatus for connecting the computer system bus of a computer system to the remote control clock and data terminals of a tape recording apparatus. The apparatus comprises a bus buffer circuit having an input and an output for coupling to the computer system bus. An isolation circuit having an input for coupling to the clock and data terminals of the tape recording apparatus is provided. The isolation circuit has an output coupled to the input o~ the bus buffer circuit. The invention further comprises a latch circuit having a clock terminal coupled to the isolation circuit output to receive the clock signal there~rom. The latch circuit has an input coupled to the bus bu~er circuit output. A driver circuit is coupled at its input to the output of the latch circuit and provides an output ~or coupling to the data terminal o~ the tape recording apparatus. In accordance with ~he invention, the apparatus is adapted to respond to tape position counter signals which are provided by the tape recording apparatus at periodic intervals on the data terminal ln synchroni~m with a clock signal on the clock terminal. The invention ~urther comprises a program m-ans ~or synchronizing the computer system with the clock lgnal and ~or causing the computer system to read the tape position counter signal. The invention ~urther comprises program means ~or causing the computer system to write remote control signals to the tape recording apparatus, to thereby control the apparatus. ~hese remote control signals include playback, stop, record, ~ast ~orward, rewind or reverse, search, and so ~orth.
In accordance wlth the automatic tape positioning method, the invention provides a method o~ using a computer 9 ~ 32~2~1 system to control the motion of the tape in a tape storage device relative to a desired tape position. The method is adapted for use with tape storage devices having a tape counter which is indexed by movement of a tape drive mechanism and thereby indicative of the tape position. The tape storage device has an incoder responsive to the tape counter for providing a counter data signal indicative of the tape position and further having a tape drive mechanism controllable by command signals issued through a remote control port. Accordingly, the method comprises causing the computer system to store a desired tape position in memory.
This may be accomplished ~y storing the desired tape position in computer system memory or in a microprocessor register.
The method further comprises causing the computer system to generate a first command signal and communicating the first command signal through the remote control port to cause the tape drive mechanism to co ence motion of the tape toward the desired tape position. The computer system is then caused to read the counter data signal and to determine from the counter data signal the instantaneous position of the tape. The computer system is caused to monitor the instantaneous position and to compare the instantaneous position with the de~ired tape position. In response to the comparison, the computor is caused to generate a second command signal. The ~econd command signal is communicated through the remote control port to cause the tape drive mechanism to alter the motion o2 the tape at a predetermined location relatlve to the de~ired tape position. In accordance with the lnventive method, the 2irst command signal may include fast forward, rewind, play, search and comparable command signals. The second command signal may include stop, play, record, pause and other comparable command signals. The method includes causing the computer system to search at high speed ~or the deslred tape posltlon and to then stop and/or return to normal playback/record speed when the desired tape positlon is reached. In accordance with the inventive method, the -lo- ~3~27 1 computer system can further be caused to anticipate when the desired tape position will be reached and to alter the motion of the tape.at a predetermined location prior to reaching the desired tape position, to thereby allow for momentum of the tape drive mechanism and tape in motion.
The invention further provides a method of using a computer to retrieve information stored at a predetermined position in such a tape storage device, including, in addition to the above steps, the step of causing the computer æystem to generate a playback command signal and communicating the playback command signal through the remote control port to cause the tape drive mechanism to enter the playback mode, whereby the stored information may be retrieved. Retrieval of the stored information may be in accordance with the foregoing computer memory back-up system or it may be retrieved by playback upon a video or television monitor.
These and other objects and advantages of the invention will become more apparent from a review of the following specification and with reference to the accompanying drawings.
~Fief Descri~tion of the Drawinas Figure 1 is a perspective view illustrating a typical computer system and video recording device with which the inventlon may be used;
Flgure 2 i5 a block diagram of the computer system of Figure lt Figure 3 is a block circuit diagram o~ the invention;
Figure 4 i5 a block diagram illustrating the timing logic block of the invention:
Flgure 5 is a block diagram illustrating the analog logic block of the invention;
Figure 6 is a wave form diagram illustrating a typical video signal:
Figure 7 i5 a wave ~orm diagram illustrating the manner in which digital data is encoded on a video wave ~orm;

11 ~ 32~2~
Figure 8 is a timing diagram illustrating the operation of the invention over one video line;
Figure 9 is a timing diagram illustrating the operation of the invention over one video frame;
Figure lo diagrammatically depicts a television screen or raster, showing the portion thereof which is utilized by the invention;
Figures 11-19 are flow chart diagrams illustrating the operation of the invention, Figure 18 appears on the sixth sheet of drawings;
Figure 20 is a block circuit diagram of the circuit used to implement the autoseek feature of the invention;
Figures 21-26 are flow chart diagrams illustrating the operation of the autoseek portion of the invention; and Figure 27, appearing on the fifteenth sheet of drawings, is a wave form diagram comparing the nonreturn-to-o code with the Manchester bipolar one code used to implement the autoseek tape position markers;
Figure 28 is a schematic block diagram of the automatic tape positioning apparatus of the invention;
Figure 29 i5 a s¢hematic diagram of an isolation circuit used in the invention;
Figure 30 i~ a wave form timing diagram illustrating the clock and data slgnals over one complete serial ¢ommuni¢ation ¢y¢le;
Figure 31 i~ a wave form timing diagram of the clock and data ~ignals over one data byte interval;
Figure~ 32 and 32a depi¢t a flow chart diagram of the remote ¢ontrol routine of the invention;
Figure 33 i5 a flow chart diagram illustrating the Wait For Transmi~ion Gap routine;
Figure 34, appearlng on the twenty fi~th sheet of drawing~ a flow chart diagram illustrating the time-out error handling routine;
Figure 35 is a flow chart diagram illustrating the read transmission routine; and Figure 36 ie a flow chart diagram illu~trating the write transmission routine.

rn/

-12- 13~271 Descri~tion of the Preferred Embodiment Referring first to Figure l, a computer system with which the invention may be operated is illustrated generally at 20. The computer system includes video monitor 22 and computer system board or mother board 24 housed within cabinet 26. Mother board 24 includes a plurality of expansion slots 28 into which peripheral devices may be inserted. In its presently preferred embodiment the invention is assembled on circuit board 30 which is adapted for plugging into one of the expansion slots 28. The computer system 20 may also include a keyboard terminal or some other data entry device permitting a human operator to run programs and execute commands.
In the usual fashion, computer system 20 also includes a video output circuit for providing analog video signals and sync signals to video monitor 22. The video output circuit may, for example, reside on mother board 24 and provide one or more video output ports, such as video output port 32 to which video monitor 22 would normally be attached The present invention in the preferred embodiment 1B adapted for coupling to video output port 32 to extract video sync signals as needed and also to route the analog video signal~ to various destinations as will be de~cribed more fully herein. Accordingly, circuit board o~ tho inventlon includes a video input port 34 for ¢oupling to vldeo output port 32 and also includes a video output port 36 ~or connection to the video monitor 22. It will thus be seen that the invention 1B interposed between the computer's video output port 32 and the video monitor 22.
While the invention i8 being described in a microcomputer environment, such as computer system 20, it will be understood that the principles of the invention may be readily adapted for use in other computer system architectures.
The invention may ~urther be used with a video recording apparatus 38 such as a video tape -13- ~3~2~

recorder, VCR or other comparable device. The invention may likewise be used with other sources of video, e.g., television tuners, video cameras, as well. For illustration purposes, a video recording apparatus will be ~shown. Such video recording apparatus includes video input port 40, video output port 42 and RF output port 44. The RF
output port 44 may be connected to a video monitor or television set 46 in the usual fashion. In addition, the VCR video input port 35 of the invention is connected to the video output port 42 of the video recording apparatus, while the VCR video output port 37 of the invention is coupled to the video input port 40 of the recording apparatus. It will be understood that while a video tape recorder is presently preferred for storing information using the invention, other equivalent video recording devices may be substituted therefor without departing from the ~cope of the invention. In the presently preferred embodiment the invention produces and receives video signals through the VCR video input and output ports 35 and 37. These signals are in conformance with the Electronic Industries Association (EIA) RS-170 Electrical Per~ormance Standards For Television Signals. While the mbodiment described herein implements monochrome t-levi~ion signal~, the principles of the invention may be extendod to color video as well.
Re~erring to Figure 2, a typical computer system i9 lllu~trated ln block d~agram in con~unction with a video recording device, auxiliary monitor, and the inter~ace clrcuit o~ the invention. Figure 2 illustrates central proces~ing unit ~CPU) 50 communicating with computer bus S2 which includes a parallel data bus, an address bus and a plurality o~ control lines. The computer ~ystem ~urther includes random access memory ~RAM) 54, read only memory (ROM) 56, and may al~o include a disk drive 58 which communicates with computer bus 52 through disk controller 60. Disk drive 58 may be either a ~loppy disk drive or a -14- 132~

hard disk or fixed disk drive. The computer system 20 may further include a keyboard 62 communicating through k~yboard interface 64 to the computer bus 52. In addition, a video output device 66 is coupled to computer bus 52 and is responsive to CPU 50 to provide analog information and video sync signals. The video output device 66 may, for example, be disposed on the computer mother board of Figure 1, or it may be disposed within a computer terminal also including keyboard and video monitor, or it may be disposed at some other location within the computer system. The video output device 66 may, for example, include hardware character generators ~or producing alphanumeric characters displayable on a video monitor, or the video output device may be under software control and capable of ~orming alphanumeric characters by selectively illuminating various pixels on a cathode ray tube (CRT). In general, video output device 66 interprets instructions 2rom the CPU 50 and produces a video signal capable o~ producing alphanumeric characters or graphics upon a computer video monitor such as monitor 22.
Normally the video output devi¢e 66 would be coupled to monitor 22, as illustrated by the dashed line, for this purpose.
When the invention is used wlthin computer system 20, video output device 6~ is no longer coupled dlrectly to monitor 22. Instead, vldeo output devlce 66 ls coupled to the intor~ace apparatus o~ the invention designated generally at 70. Apparatus 70 in turn is coupled to vldeo monitor 22. The inter~ace apparatus o~ the invention i5 ~urther coupled to computer bus 52 so that it may receive instructions and digital data via the parallel data bùs, address bus and control lines o~ the computer system. The interface apparatus 70 provides signals to and receives signals ~rom the video recording device 38. Communication between the inter~ace apparatus 70 and video recording apparatus 38 is done serially. If desired, -15- ~3 2 ~ 2 ~ ~

an auxiliary monitor or television set 46 may be connected to the video recording apparatus.
Turning now to Figures 3, 4 and 5, the interface apparatus 70 of the invention will be discussed in greater detail. Figure 3 is an ovèrall block diagram of the interface apparatus, while Figures 4 and 5 depict the write timing logic blocks and analog logic blocks, respectively. With specifie reference to Figure 3, apparatus 70 includes a bus interface logic block denoted generally by reference numeral 72. The bus interface logic bloc~ couples the apparatus of the invention to the computer data bus 74, eomputer address bus 76, and to the control signal lines 78.
More speeifically, computer data bus 74 is coupled to local data bus 80 o~ the invention through data bus transceiver eireuit 82. Data bus transeeiver 82 serves as a bidireetional bu~fer and may be implemented using a 74LS245 integrated eireuit or the equivalent. It will be reeognized that while the 74LS245 integrated eircuit provides an eight bit bidirectional bu~er, for use with eight bit eomputer systems, the principles of the invention may be extended to other eomputer arehiteetures as well, such as cixteen bit, twenty four bit, thirty two bit, and so forth.
The eomputer address bus 76 and eontrol signal lin-- 78 are eoupled to an input/output address decoder logic ¢lreult 84 whieh may be implomented using 74LS155 d-eoder int-grated eireuits, or the like, to provide a read data signal, a write data sign~l, a read status signal, and a write control slgnal. The invention ~urther includes a ~irmware ~torage apparatus sueh as an EPROM 88, or the liXe ~or storing the eomputer instruetions used to implement the invention. ~hese instruetions will be diseussed more fully below in eonneetion with the aeeompanying ~low chart drawings. I~ required, a memory address deeoder logic eireuit 86 ~ay be eoupled to eomputer address bus 76 and 'eontrol signal lines 78 in order to ~ully eouple EPROM 88 to eomputer address bus 76. EPROM 88 i~ eoupled to local data ~ -16- ~ 32~ 5J~

bus 80 in order to make the program instructions available to the computer system CPu 50. EPROM 88 may be implemented using a 2732 integrated circuit, or the like. It will, of course, be understood that the bus interface logic block 72 must be designed to interface with a particular make and model of computer, thus the specific details of the interface logic block are subject to modificàtion without departing from the scope of the invention as set forth in the appended claims.
The interface apparatus of the invention further includes a transmitting and re¢eiving circuit or UART block 90. UART block 90 includes a universal a~ynchronous receiver transmitter or UART 92, which may be implemented using an IM6402A integrated circuit. Coupled to the transmit data line of UART 92 is a data latch which ~erves as an external bu~er 94 to UART 92. External buffer 94 i~ coupled to receive ~ignals from local data bus 80.
UART 92 is coupled via its receive data line to local data bu~ 80. UART 92 also provides a pair of serial input and output leads 96 and 98, respectively, for receiving and tran~mitting digital in~ormation in serial format. In g-n-ral, UART 92 ~erve~ as the link between local data bus 80, a parall~l data channel, and leads 96 and 98 which ~orm a a-rial data channel. UART 92 i~ controlled by wrlte timing logic block 100, yet to be di wu~ed, and al~o by CPU 50 via the read data and wrlte data line5 o~ inpUt/output addr-~ decodor loglc circuit 84. UART 92 communicates through lnput and output line3 96 and 98 with analog logic block 102, which will be discu~sed more ~ully below in connection with Flgure 5.
Analog logic block 102 is controlled by ~wltching signals provided by latch circuit 104 coupled to local data bus 80. Latch 104 provides a Monitor Analog 8witch Control 8ignal on lead 106, and a VCR Analog Switch Control Signal on lead 108. The VCR Analog Switch Control Signal on lead 108 is used in con~unction with a -17- ~32~2~

frame delay signal from write timing logic block 100. These signals are input to AND gate 110 to provide the VCR
Analog Switch Control Signal. The frame delay signal gates the VCR Analog Switch Control Signal so that the VCR or other recording device is coupled to receive data after a predetermined frame delay time. As will be explained more fully below, the frame delay time is used to insure that data is stored well within the visible center region of the video raster so as not t,o conflict with sync pulses.
The invention further includes a circuit for detecting when data is absent on serial input line 96 BO that video frames may be distinguished from one another. As will be more fully explained below the invention writes data to the video recording device in blocks of 256 bytes at a density of one byte per video line. Only a portion of the video frame is used to store data and the invention utilizes two consecutive frames to store a given 256 byte block. The second frame has fewer lines of data than the first frame and includes a tail end portion con~isting o~ a plurality of blank lines (lines with no ~tored data). One shot multivibrator 112 is co~pled to line 96 ~o that any incoming data on line 96 will continually r~-~t the one shot multivibrator 112. When the blank line tail end portion of a 6econd ~rame iB encountered, on- ~hot multivibrator 112 times out and eet~ a no data ~lag which i~ latched ln bu~er 114. Bu~er 114 also receives a r-ceivor ~tatu~ ~ignal and error signals from UART 92 and a tran~mit ~tatus signal ~rom write timing logic block 00. AB will be explained below, bu~fer 114 provides an indication to the CPU that the transmit bu~fer has data.
Re~erring now to Figure 4 the write timing logic block 100 will now be described in detail, In order to fully under~tand the write timing logic block 100 reference may ~l~o be had to Figures 6 and 7, which depict typical video wave ~orm~ processed or generated by the invention, together with Figures 8, 9 and 10 which depict the ~ystem timing ..~ ,.

-18- ~32~2~

in relation to video sync timing and the video raster pattern. Write timing logic block 100 includes a line delay timer 116 which provides a ten microsecond output pulse upon detection of the composite sync pulse generated by the computer video output device 66. If not already provided by the video output device, the composite sync pulse may be extracted from the composite video signal as will be discussed in connection with the analog logic block shown in Figure 5. With reference to Figure 8, line A
thereof depicts the composite sync pulse. In accordance with EIA RS-170 standards, the intraline timing between sync pulses is 63 microseconds. As indicated, the composite sync pulse includes both vertical sync and horizontal sync components. The output of delay timer 116 is shown on line B of Figure 8. The falling edge of the line delay pulse indicated by the dashed line 118 begins the le~t boundary o~ usable video. Figure 10 illustrates the usable video area of a television display. The larger rectangle 120 represents the entire raster or frame, while the inner rectangle 122 represents the usable display area. The portion o~ rectangle 120 to the left o~ rectangle 122 represents the horizontal blanking area o~ the display, while the portions o~ rectangle 120 above and below 122 represent the vertical blanking areas. The invention ls adapted to write a byte of digital data in the usable video area depicted by inner rectangle 122. More speci~ically, the dashed rectangle 124 depicts the area actually used by the invention to store data in the ~irst ~rame o~ a two ~rame block. The dotted rectangle 126 deplcts the actual area used by the invention to store data in the ~econd frame of a two frame block. Falling edge 118 determines the le~t-hand edge o~ rectangular areas 124 and 126.
The output o~ line delay timer 116 is coupled to one shot multivibrator 128 which produces a 500 nanosecond trigger pulse or &tart pulse. The start pulse is 1~2~

depicted on line C of Figure 8. The falling edge of the start pulse signals the beginning of a serial data stream. The data stream is illustrated on line D of Figure 8. It begins with a start bit 130, followed by eight data ~bits 132 and one parity bit 134. Data bits 132 and parity bit 134 are shown as dotted lines since they may assume various logical high and low combinations.
AND gate 136 is receptive of the start pulse and also coupled ~hrough inverter 138 to receive the co~posite sync signal. AND gate 136 extracts the vertical sync signal from the composite sync signal which in turn activates one shot multivibrator 140. Multivibrator 140 provides a four millisecond ~rame delay pulse illustrated on line B of Figure 9. Line A of ,Figure 9 depicts one complete video ~rame 142 consisting of a plurality of individual video lines 144 spaced between composite sync pulses 145. The upper and lower limits of usable video area, corresponding to the upper and lower edges of inner rectangle 122, i8 illustrated at 146. As noted earlier, the lnvention writes data to the smaller rectangular areas 124 and 126 within the usable video area 122.
The ~rame delay pulse triggers one shot ~ultivibrator 148 which produces a 500 nanosecond pulse to commence writing data to the ~irst line within rectangular ar-a~ 124 and 126. ~ine C o~ Figure 9 depicts the 500 nano~econd ,pul~e which sets ~lip ~lop 150 to a ~irst bi~table ~tate, indicating that data may now be tran-mitted. The 500 nanosecond pulse ~rom one shot multivibrator 148 also resets counter circuit 152. Counter circuit counts 176 video lines and produces a reset pulse when 176 lines have occurred. The reset pulse of counter circuit 152 resets ~lip flop 150 to a ~econd bistable state indicating that data may not be transmitted.
Counter clrcuit 152 anticipate~ the occurrence o~ the next vertical ~ync pulse and insures that data is not transmittod during the vertical 6ync pulse interval. The -~o~ il 32~2~1 reset pulse produced by counter circuit 152 or the sync anticipator pulse is illustrated on line D of Figure 9.
Line E of Figure 9 depicts the time during which data may be transmitted. It will be understood while counter circuit 152 times out after 176 lines, in anticipation of the next vertical sync pulse, the invention may be implemented using larger or smaller counting sequences. The 176 line count is presently preferred although not critical. In general, counter 152 should insure that data will not be transmitted when the vertical sync pulse occurs. In addition, by breaking a 256 byte block of data into unequal portions, i.e., a first frame of 176 bytes and a second frame of 80 bytes, the data is stored in a staggered relationship which makes it easier to distinguish between first and second video ~rames.
Write timing logic block 100 also includes logic gate 154 for providing a UART Transmitter Load and Start pulse. Logic gate 154 receives the start pulse from one shot multivibrator 128 and also receives the transmit ~ignal from ~lip ~lop 150. Logic gate 154 is also coupled to UART 92 to receive a signal indicating that the internal register o~ the UART is empty and also to receive a signal indicating that the internal buffer of the UART is mpty. In addltion to logic gate 154, a flip ~lop 156 is also provided to monitor the status o~ external buffer 94.
When external bu~er 94 i8 ~ull 0~ data, flip ~lop 156 output~ a Transmit Bu~er Full pulse to logic gate 154.
When all ~ive inputs o~ logic gate 154 are ~imultaneously ~ati~ied, an output pulse is produced causing the UART to commence transmitting data. It will be seen that through the u~e o~ internal bu~er 94 in combination with gate 154 and ~lip flop 156, the internal bu~er within UART 92 is de~eated, thereby permitting data to be transmitted through UART 92 under control o~ CPU 50. CPU 50, it will be recalled, provides the write data signal via input/output ` -21- 32~2~

address decoder lo~ic circuit 84. This write data signal controls the set terminal of flip flop 156.
Referring now to Figure 5, the analog logic block 102 is illustrated in greater detail. Analog logic block 102 includes an analog switching block 158 comprising two double pole single throw, electrically controlled switches 160 and 162. Analog switching block 158 may be implemented using a CD4066BCN integrated circuit or, the like. Such integrated circuit provides a quad bilateral switch for the transmission or multiplexing of analog or digital signals. The output leads of switch 160 are tied together and coupled to output current amplifier 164 ~or interfacing with and supplying video signals to a video monitor such as monitor 22. The output leads of switch 162 are tied together and coupled to output current amplifier 166 for interfacing with and providing video signals to the video input port 40 o~ the video recording device. Switch 160 is operated under software control by the Monitor Analog Switch Control Signal on lead 106.
It will be recalled that the Monitor Analog Switch Control Slgnal is provided by latch circuit 104. Similarly, switch 162 1~ actuated under so~tware control by the VCR Analog Sw~t¢h Control Signal on léad 168. The VCR Analog Switch Control Slgnal is provided by the AND gate 110, which is in turn reopon~lve to latch circult 104.
Switch 160 ~electlvely couples elther a first vid-o algnal or a ~-cond vldeo signal to the output current amplirl-r 164 and ultimately to a video monitor such as monltor 22. The Sirst video signal is designated VCR video and is derlved Srom video sig'nals from the video recording apparatus. The second video signal, designated computer video, i5 derived Srom computer video output devlce 66. More ~peclSlcally, VCR vldeo 1B derived ~rom output port 42 o~ the vldeo recordlng device using gain and clamp circuit 170. Gain and clamp circuit 170 voltage clamps the video signal to a ~ixed level at approximately 4 , ~ -22- ~ ~ J2 ~-~

volts to eliminate the néed for precision components. The VCR ~ideo signal is also processed through filter 172 and compared against a reference voltage data level in comparator 174 to extract serial data from the VCR video signal. This serial data is provided to the serial data input port of UART 92. The computer video signal i9 derived ~rom the ~omputer video output signal through gain circuit 176. The computer video signal is similarly compared against a reference voltage sync level in comparator 178, to extract a composite sync signal from the computer video signal.
Switch 162 in a similar fashion selectively couples either a first video signal or a second video signal to current amplifier 166 and ultimately to the video input port 40 of the video recording device. The first video signal comprises the computer video signal described above. The computer video signal comprises analog information and sync signals which convey human readable alphanumeric characters, graphics, still or motion pictures or the llke. The second video signal comprises a data video signal on lead 180. The data video signal is derived from the composite sync signal extracted by comparator 178.
Mlxer 182 receives the composite 6ync signal and the serial data ~rom serial output port 98 o~ the UART and combines them into a data video ~ignal. The data video ~ignal is ampli~ied by gain circuit 184 and comprises computer genorated digital in~ormation in a serial format wlth lmbedded sync pulses, meeting the EIA standards ~or television or video recording.
Having thus described the inter~ace circuit o~ the lnv~ntlon, a description o~ the operatlon now follows.
In con~unction with this description re~erence may be had to the ~low chart diagrams comprising Figures 11 through 19. Flgure 11 deplcts the maln menu 210 o~ commands avallable ln the presently pre~erred firmware lmplementation o~ the invention. As illustrated, the ~32~

main menu provides two binary read and write commands, B
Load and B Save, for reading data from the video recording device and for writing data to the video recording device. The B Load and B ~ave commands may be used, for example, to store and retrieve assembly language object code programs or raw digital data. Main menu 210 also provides Save and Load commands for writing and reading files such as those produced by higher level languages like BASIC. The main menu also includes a View Tape command which, when selected, causes the information stored on the video recording device to be directed to the computer video monitor.
This allows the user to read file header information directly, without interpretation by the computer, in order to determine what has been stored on the video recording device or to select a particular file for loading or editing. Finally, the main menu includes an exit command which restores the state o~ the CPU machine and returns control of the computer to the computer operating system.
Reviewing Figure 11 it will be noticed that the ~low charted sequence for the B Save and Save commands both include an instruction to display a blank file header.
This instru¢tion is designated by re~erence numeral 212.
Th~ display blank header routine i5 illustrated more ¢ompletely in Pigure 12. Re~erring to Figure 12, when either B ~ave or Save commands are entered, a blank ~ile header re~embling ~ile header 214 i5 written to the video monitor.
Most computer systems reserve one or more memory locations in which to store identi~ying in~ormation about the hardware and operating system so~tware implemented on that particular computer. The present invention is provided with ~irmware instructions which cause the CPU to interrogate those reserved memory locations and return in~ormation identi~ying the particular hardware and so~tware. This in~ormat~on iB written automatically to the ~ile header (or the user may type the in~ormation into the space provided in the ~ield between delimiters 216). I~ the -24- ~ 3 ~

computer system is equipped with a system time clock, the date and time is read from the clock and displayed on file header 214. If a system time clock is not provided, the user may type the date and time in the fields as indicated.
~ eturning to the main menu of Figure 11, the system proceeds to step 218 wherein the file type is written to the file header 214. If a B Save command was selected, the file type is written as a memory image, thus denoting that the data to be stored following the file header is binary data. If the Save command has been selected, the file type is assumed to be a BASIC file and the word ~ASIC is written to the file header as indicated. In addition, if the Save command was executed, the program routine also interrogates predetermined memory locations to determine the starting address and length of the BASIC file. Such information is provided by most implementations o~ the BASIC language. When step 218 has been performed, control proceeds to point 2 in the main menu program.
At point 2 the user is next prompted in step 220 to ~ill in any blanks remaining in ~ile header 214. The details of 6tep 220 are illustrated more completely in FigurQ 13. Re~erring to Figure 13, the user is prompted to ~111 in blanks, to hit the return key, to go to the next ~iQld and to hlt the escapQ key (ESC) when ~inished ~illing in the ~ile header. Fir~t, the pointer or cursor ls set to the end o~ the ~irst ~ield and then the pointer or cursor is backed up over any blank characters and advanced one space, where the program waits ~or a key to be depressed. I~ the return key is depressed, the pointer or cursor is set to the end o~ the next ~ield and program control branches back to step 222. I~ a cursor right key is depres~ed, the program control branches to ~he advance pointer ~tep 224. If a cursor le~t key i8 depressed, the pointer is backed up and program control resumes with step 224. If an escape key ~ESC) is depressed the starting - -25- ~32~2~

address and length fields are checked for nonnumeric characters If a nonnumeric character is detected, an error condition results and the user is prompted to correct the error or return to the main menu If no error is detected, the subroutine returns control to the main menu at a point following step 220 If anything besides a return key, escape key or left and right cursor movement keys has been depressed, the character depressed is written at the cursor location upon the screen and program control continues with the step 224 Referring back to Figure ll, the user is next prompted in step 226 to position and start the tape This routine is illustrated more fully in Figure 14 The routine prompts the user to indicate whether the tape is positioned correctly or not If the escape key is depre~sed, the main menu selection is aborted and control returns to point 1 of Figure ll to display the main menu once again If a Y or yes is entered by the user, the ~ubroutine returns to its calling point in the main menu If an N or no is entered by the user, a message is displayed prompting the user to press any key to view the tape then any key when done The routine waits ~or a first key to be depre~ed, then it changes switch 160 to redirect th- output o~ the video recording device to the computer monitor The routine then waits ~or a next key to be depr-~ed, whereupon it ~witches swltch 160 back to its d-~ault po~ition wherein the video signal ~rom the computer vldeo output device is directed to the monitor Control then returns to the calling point within the main menu program Next a write ~ile header routine 228 is executed Thl~ routine 18 illustrated in Figure 15 It is through the u~e o~ this write ~ile header routine that the invention places human readable information at the beginning o~ a ~tored dlgital in~ormation ~ile, 80 that the user can review the contents o~ the video tape or other video recording medium on a monitor or television set, without the - -26- ~32~

intervention of the computer. The human readable file header information is computer system independent, thus the user can review the file headers which describe stored programs or data even if the programs or data have been produced by different or incompatible computer systems. It is therefore possible to store on a single video tape, or other video recording medium, computer information and digital data produced by several incompatible computers.
With reference to Figure 15 the write file routine first copies the file name or description to the top line or title line of the video monitor or television monitor.
This file name or description usually resides within a file control block or other preassigned memory location when the particular ~ile is loaded in the computer's RAM memory. The ~ile name or description remains on the top line or title line even while digital information is being sent ~rom the video recording device. This provides helpful reassurance to the user that the correct file is being written or read. Switch 162 is then set to direct computer video to the VCR or video recording device. The program then delays ~or 10 seconds to permit the viewer to see the complete file header on the video monitor. It will of course be understood that the 10 second delay i5 not critical, but i6 merely selected to provide most readers ample tlme to read the entire ~ile header. Following the lO second d-lay, switch 162 is set to direct data video to the VCR
or recording devlce. This step is ~ollowed by a non critical one-hal~ second delay. The program then calculates a checksum o~ the entire ~ile header written to the video recording device. This checksum is based on the ASCII
values o~ both prompts and replies which insures that the checksum will be computer independent.
Next the program interrogates the read status line coupled to bu~er 114 and waits ~or a sync signal. When the sync signal occurs, the checksum calculated earlier is written to the video recording device. Figure 15A more ~, ~32~27~

fully illustrates the presently preferred way in which data is written to the video recording device. As indicated, the read status line is interrogated and the program waits until the buffer is no longer full. Then the instruction is given causing data to be strobed through the UART. In the presently preferred embodiment the hardware determines when the buffer is empty so that data may be strobed through the UART. Alternatively, the same result may be accomplished in software using interrupts, for example.
After the checksum is written a flag byte is next written to indicate the beginning of the file header.
The flag byte is written using substantially the same routine as described above in connection with Figure 15A. After the flag byte is written, three "don't care"
bytes are written and the program then successively points to each character in the file header, reading the character pointed to, and writing it to the video recording apparatus.
In the presently preferred embodiment the file header comprises eight lines or fields, each field comprising space ~or up to thirty-two individual characters. Using a pair o~ nested loops, the program points or steps successively through each o~ the thirty-two spaces in the ~irst ~ield, and then advances to the next ~ield. Each of the eight ~ields are successively written in thls ~ashion.
To insure that no data is lost the preferred embodiment~ writes multiple copies of the ~ile header. This i~ implemented in software by using a number o~ tries counter 230. The number o~ tries counter is preloaded with a ~tartlng integer (2 ~or example). Each pass through the write ~ile header routine decrements the counter by one.
When the counter is zero the write ~ile header routine exits to the main menu program which, in turn, calls the write data routine 232. The write data routlne is depicted in Flgure 16.

-28- ~ ~ 2 ~

Referring to Figure 16, the write data routine begins by calculating a checksum of the first 256 byte block of data, for error checking. A number of tries counter is initialized to a preselected number which determines the number of iterations through the write data loop. The read status line is interrogated, waiting for a sync pulse, as more fully indicated in Figure 16A. The checksum is then written to the video recording medium, followed by a write flag byte, which indicates that data is to follow. The flag byte is also written in accordance with the routine illustrated at Figure 16A. Next, one or more "don't care" bytes are written to the recording medium in accordance with the routine of Figure 16A.
The write starting address (Hi and Lo bytes) is next written to the recording medium in accordance with the routine o~ Figure 16A. A data counter is then initialized to 256, the byte size o~ the data block being written. In this regard, all data blocks are assumed to be 256 bytes, even partial blocks which may contain a number of blank lines at the tail end thereof. Next, each byte of data is strobed through the UART one byte at a time, beginning at the ~tarting address.
As each byte is written, the data counter is decremented and tested to determine i~ the entire 256 byte block has been written to the recording medium. I~ it has, the number o~ trie3 counter is decremented and tested.
I~ the number of tries counter has not reached zero, the program branches back through the write data loop, as indicated in Flgure 16, thereby causing multiple copies o~
the data block to be written to the recording medium. This is done to insure that data can be recovered even i~ one or more bytes within a given block contain parity errors. Once the number o~ tries counter has been decremented to zero, program control branches to decrement the most signl~icant byte ~MSB) o~ the byte or word contalning the length o~ the data ~ile being written.

11 3~27~

When this file length value, so decremented, reaches negative one, the write data task is complete and a task complete message is displayed. Otherwise the program branches to the entry point of the write data routine, and the entire sequence is repeated. By decrementing the most significant byte of the length word, the write data routine insures that data is always written in full 256 byte blocks. This insures that there will always be a plurality of blank lines at the end of each second frame.
Usually there will be 102 blank lines at the end of each second video frame. These blank lines are detected by one shot multivibrator 112 which provides the No Data Flag to bu~er 114.
Having thus described the Save and B Save routines, the~ Load and B Load routines will now be described. Referring to Figure 11, both the Load and ~ Load routines begin by prompting the user to position and start the tape, step 226. This step was described above in connection with Figure 14. Next the ~i~e header is read, step 234. Step 234 is depicted in detail in Fiqure 17.
Referring to Figure 17, the read status line is lnterrogated waiting ~or the No Data Flag. When the No Data Flag i~ ~et, the program, in step 236, skips over the title line. The routine ~or skipping over the title line is shown in Figuro 18. With re~eren¢e to Figure 18, a time-out counter 1~ lnltlallzed to a predetermined number, such as 12, and the read status line is lnterrogated to determine i~ a character ha~ been received. I~ a character has been received, it is a~sumed to be one o~ the characters in the title llne and the UART is instructed to ignore or trash the character. I~ no character is received ~as will occur after the last character o~ the title line has been read) the time out counter i~ decremented and tested. I~ the counter has reached zero, control returns to the read ~ile header routine of Figure 17. I~ the counter has not reached zero, the program branches back to the read status _30_ ~32~2 ~1 in~errogation step and the loop continues as described above. By initializing the time-out countere to a significantly large value (a value of 8 is usable) time out will occur only if a gap in data occurs. To aacomplish this the counter is initialized to a value such that the execution time of the software loop is considerably greater than 63 microseconds (the duration of one video line and one byte of data).
Referring back to Figure 17, the read file header routine then reads and saves the checksum which was stored on the recording medium on the Save or B Save routines.
Figure 17A illustrates the read sequence in greater detail.
In accordance with the read sequence, a time-out counter is initialized and the read status line is interrogated to determine i~ a character is received. If a character has been received, it is read from the UART. If a character has not been received, the time-out counter is decremented and tested. If the counter is not zero, control branches to the read ~tatus interrogation step. If the time-out counter ha~ reached zero, a time out occurs and program control branches to the entry point of the read ~ile header routine.
Pre~erably the time out counter of Figure 17A is initlalized to a su~ficiently large value, so that time out occur~ atter a gap in data occurs which i8 considerably great-r than the duration o~ two byte~, auch as would occur at the nd o~ ach ~econd video ~rame.
Arter the checksum has been read and saved, th- ~lag byte indicative o~ the beginning of the file header i~ next read in accordance with the routine o~ Figure 17A. I~ the Flag byte is ~ound, indicating the beginning of the ~ile header, the next three "don't care" bytes are read and ignored. I~ the ~lag byte is not detected, control branches to the entry point of the read ~ile header routine.
A~ter the ~don't care" bytes have been detected and ignored, a pointer i5 set to the ~lrst character in the ~irst row of the ~ile header. The routine then attempts to read the -31- ~32~

pointed to character from the UART. If a time out occurs, control branches to the skip over title line step 236. If no time out occurs, the character read from the UART is tested to determine if it contains any errors, such as timing errors or parity errors. A timing error causes control to branch to the entry point of the read file header routine. A parity error causes the program to advance the data pointer to the next character.
If no errors are detected the character is written to computer memory at a location designated for the file header. The pointer is then advanced to the next character and tested to determine whether it is pointing beyond the limit of the 32 character header field. If the limit is detected, the pointer is advanced to the next row and tested to determine whether it is beyond the last line ~the eighth line) of the ~ile header. Once all 32 character locations for each of the eight lines of the file header field have been written to computer memory, the checksum of the file header is calculated and compared with the checksum read ~rom the recording medium. If the checksums match, the read file header routine exits and returns control to where it left of~ in the main menu program. I~ the checksums do not match, control branches to the entry point o~ the read ~ile header routine and the entire seguence is repeated.
In the case o~ the Load command, which i8 used to load BASIC programs or data ~iles, the file being loaded is checked to determine that it is the proper type of ~ile, i.e.
compatible with the BASIC interpreter. In the case o~ the B
Load command the ~ile type is assumed to be a memory image or binary ~ile. Under both Load and B Load commands, the starting address and length o~ the file are then determined ~rom the in~ormation recorded in the ~ile header and control branches to the read data step 236. The read data step 236 is illustrated in detail in Figure 19.

-32- ~3~?~

Referring to Figure 19, the read data routine begins by initializing a byte counter to 256 and the read status line is interrogated while the program waits for a No Data Flag. The routine then skips over the title line in accordance with step 236, described above in connection with Figure 18. The checksum is then read and saved in accordance with the routine illustrated in Figure lsA. The routine of Figure lsA follows substantially the same logical sequence as the routine for reading characters from the file header, shown in Figure 17A.
Having read and saved the checksum, the program then reads and determines whether a Flag byte follows the checksum. If the Flag byte indicates data is to follow, the "don't care" bytes are read and ignored and the starting address bytes (Hi, Lo) are read and stored in an address counter. Bytes o~ data are then read from the UART, tested ~or timing and parity errors and written into RAM memory.
The sequence o~ reading bytes of data from the UART and writing those bytes into successive RAM memory locations proceeds by incrementing the address counter while decrementing the byte counter and the length of file counter.
When the length o~ file counter or the byte counter reach zero, a checksum of the 256 byte data block is calculated and compared with the checksum read ~rom the recording medium. Control then resumes with additional block~ o~ data belng written to RAM memory until the length o~
~ile ¢ounter reaches ~ero, whereupon the program returns control to the calling point within the main menu program. I~
the program i5 following a Load command, control is tran~erred to the BASIC interpreter ~or per~orming hou~ekeeping ~unction~ in the usual fashion.
Should the user wish to browse through the contents o~ a given video recording medium, such as a video ca~sette tape, a view tape routine 240 is provided in the main menu progra~ o~ Figure 11. The view tape routine ~lrst di~plays a message instructing the user to press any -33- ~ 3 ~J~

key to view the tape and then to press any key when finished. The routine then waits for a key to be depressed, giving the user time to position and start the tape.
In step 242 the routine changes the setting of switch 160, causing VCR video to be directed to the computer monitor. The program then waits for a second key to be depressed, whereupon switch 160 is returned to its default state wherein computer video is directed to the computer monitor. The main menu program also includes an exit routine 244 which restores the CPU registers and machine status and returns control to the computer operating system.
Figure 6 depicts a typical video signal comprising one video frame. As indicated, each line of analog video information is embedded between horizontal sync pulses. Each video irame, comprising 256 video lines, is embedded between vertical sync pulses. The voltage levels indicated in Figure 6 are for illustration purposes only, wherein zero volts represents a video black and + V
volts represent~ a video white. It will be understood that these voltages may be referenced to other voltage levels, thus the wave form of Figure 6 may appear shifted relative to the zero voltage axis. Figure 7 depicts a typical data vldeo ~ignal comprising one video line. The video data ~lgnal ¢ompri~e~ a data ~lag and eight data bits, ~ollowed by one parity bit. ~his data video signal i8 mbedded between horizontal sync pulses a~ indicated. I~
color video i~ implemented, a color burst occurs be~ore the data ~lag in each video line, in accordance with industry ~tandards. It will again be recognized that the voltage levol~ indicated in Figure 7 are merely illustrative, as the data video ~ignal may be re~erenced to other voltage levels causing the illustrated wave ~orm to be shi~ted with re~pect to the zero voltage axis. In contrast to analog video in~ormation, the digital data video information a~umes only two video voltage states, corresponding to video black and video white voltage levels. In -34~

contrast, analog video information also includes a range of grey video levels, as well.
In the foregoing embodiment the human operator is responsible for positioning the recording medium and starting the recording device. In the Save and B Save modes this involves locating where on the cassette tape or other recording medium the program is to be stored and then depressing the record switch to place the recording device in a record m~de. With the Load and B Load commands the operator is similarly responsible for positioning the tape or recording medium (using the view tape command if necessary) and then placing the recording device in a playback mode. Video recording devices equipped with fast forward and fast reverse with preview or search capabilities are preferable since the operator can select "search ~orward" or "search reverse" modes to manually locate a file header and subsequent data file more quickly.
In conjunction with the manual operation described above, the invention also includes an automatic ~earch mode which permits the computer to search in fast ~orward and ~ast reverse modes to locate a particular ~lle ~or writing or reading. In the automatic mode the video rocordlng devlce may have prevlew or search capabilitie~ in ~ast forward and reverse modes, although this i~ not required. The presently pre~erred embodiment for ~mplementlng an automatlc search mode utllizes the audio recording track ~ound on most video recording devices. I~
necessary to provide sufficient signal strength and pulse de~inition, the recording device may be modified so that the audio read head is loaded onto the recording medium during ~ast 40rward and ~ast reverse modes~ In the alternative, electronic signal ampli~ying and compensation networks may be u~ed to enhance and re~ine the periodic tape location markers as they are read by the audio read head.
Figure 20 illustrates the electronic circuitry reguired to implement the automatic ~earch mode o~ the ~ -35-present invention. The audio signal from the read head of the video recording device is processed through amplifier 250 and filter 252 to provide the required signal strength and frequency content to provide a robust tape location signal. The tape location signal is detected by comparator 254 and latched in buffer 256 for placement on the data bus in response to an enable signal from the address decoder 84.
The tape location markers which are detected by the audio read head of the video recording device may be prerecorded at periodic intervals by the tape manu~acturer or they may be recorded by the invention.
In order to implement the latter a latch circuit 258 is coupled to the local data bus to provide digital pul~es in response to data signals on the data bus and in response to clock signals from the address decoder 84.
Tape location signals may be generated ucing one of the data bus lines. For purposes of illustration, bit 7 of the local data bus is used to provide these tape location markers.
The output o~ latch 258 is processed through amplifier 260 and current amplifier 262 to provide a signal of ~lgni~icant energy to drive the write head of the video r-cording device. Under computer control via the data bu~ and address decoder, the invention may record periodic and sequentially numbered tape location markers.
As an alternative to periodic and sequentially numbered markers, the invention may instead assign different numbers to each o~ the ~iles stored on the recording medium as a means o~ distinguishing between and locating individual files.
As a second alternative, the invention may record all of the characters in the title line of each ~ile header onto the audio track as a means of distinguishing between and locating individual riles.
The automatic search mode ~urther includes a latch circuit 264 through which the computer communicates with the remote control interface o~ the video recording device.

~32~7~

Latch 264 may be coupled via hard wire or radiant energy link to the function controller 266 of the video recording device. The function controller circuit 266 may be implemented usinq commercially available hardware which accompanies video tape recording devices with remote control capability. Latch 264 is coupled to the local data bus and receives clock signals from address decoder 84.
The fast forward and fast rewind modes of most video tape recorders do not employ capstans to maintain a constant tape speed during fast forward and fast rewind.
In general, the tape speed during fast forward and fast rewind will vary in accordance with the diameter of the tape wound upon the take-up reels at any given point in time. To eliminate inaccuracy due to nonuniform tape speed, the presently preferred embodiment of the invention uses a Manchester code to record the periodic tape position markers and ~ile location markers. The Manchester code has the advantage of being sel~-clocking, and therefore is immune to the inaccuracies induced by varying tape speeds.
Figure 27 compares the widely used nonreturn-to-zero code ~N~Z) with the Manchester code for the binary code sequence, 01100. Strictly speaking, the present invention utilizes the blpolar one component o~ the Nanchester II code, also known a~ Blpha~e-L code. Ae illustrated in Figure 27, the Manche~ter bipolar one code changes state in the middle o2 the bit period, wherein a transltion ~rom Lo to H~
represents a binary "0", and the transition ~rom Hi to Lo repr~ents a binary "1". When two like binary digits occur in seguence, as the binary 1' 8 in bit periods 2 and 3 or ~8 the binary O's in bit periods 4 and 5~ an intermediate return tran~ition is made between bit periods as indicated at 268 and 270. The mid bit transition in each data cell provides the Manchester code with an e~ective error detection ~cheme. I~ noise produces a logic inversion in the data cell such that there is no transition, an error _37_ ~32~27~

indication is given, and synchronization must be reestablished.
Furthermore, the Manchester code is a self-clocking code. The clock in serial data communication defines the position of each data cell. For example, the interval 272 between the transitions in bit periods 1 and 2 establishes the clock time for the data samples 274 and 276 immediately following. In the presently preferred embodiment transitions are detecte,d by sampling on both sides of the midpoint where data transitions are expected to occur.
In other words, each data transition is expected to occur at approximately the half way point between the beginning and ending of any bit period. Samples are taken at the one-quarter and three-quarter clock times within each bit period.
The algorithms for writing and reading the above Manchester code are illustrated in the flow charts of Figures 21 through 26. Figure 21 depicts the write sequence ~or writing a word to the VC~ audio track or the like in Manchester II Sormat. If the word to be written is the Sirst word in a sequence the program first writes eight "0" bits to the recording medium to provide a plurality of tranoltions Srom which a clock can be extracted upon playback. Next the parity oS the word to be written is det-rmined and a sync pattern ls written in accordance with the routine Or Figure 2la.
The write sync sequence begins by oetting the output bit ~bit 7 in Figure 20) Lo. Next a delay Sor a one and a halS blt time ls executed, whereupon the output bit is oet H1. Flnally, a second one and one halr bit time delay io executed whereupon the write sync routine returns to the main program of Figure 21. The word to be written is rotated 50 that the least signiricant bit (LSB) is rotated into the carry bit location. ~he carry bit location is then tested to determine whether it holds a 0 or a 1. In accordance with this determination either a 0 bit or a 1 bit is written as illustrated in Figures 21b and 21c. When all of the bits have been rotated into the carry bit location and written, the parity bit is then written and the write sequence is terminated. The routine for writing a "0" bit is indicated in Figure 21b. The output bit is first set Lo and a delay for a one-half bit time is executed. The output bit is then set Hi and another delay for a one-half bit time is executed. The sequence for writing a "1" bit begins by setting the output bit Hi followed by a delay for a one half bit time. Next the output bit is set Lo, followed by another one-half bit time delay.
The sequence for reading words form the VCR in Manchester II format is indicated in Figure 22. The routine begins by testing to determine whether the incoming word is the first word in the sequence. If it is, the clock rate is determined in step 280 and the error flag is tested for exiting from the routine if the error flag is set. If the incoming word is not the first word in the sequence the routine branches around the clock determination step 280 and the error flag test 282.
Figure 23 illustrates the sequence of steps for finding the clock rate, step 280. First the period between transitions is measured and assumed to represent N/2 (one half bit time). The counter containing the measured period is then shifted left, thereby multiplying its value by two. In the next step 284 the counter is shifted right three times to determine the values for N/2, N/4 and N/8.
Limits are then calculated as indicated in step 286. The period between transitions is then again measured at step 288 and the routine goes through a series of tests to determine whether the newly measured period in the counter is less than 3/8 N, 5/8 N, 7/8 N, or 1 1/8 N. If the new counter value is less than 3/8 N control loops back to step 283 where the new counter value is assumed to be N/2.
If the new counter value is 5/8 N the counter is determined to be within limits for N/2 and a counter ` -39- 1~ 2~2 ~

recording the number of averages is incremented. If the number of averages equal nine the clock rate has been determined and the routine returns to the read program of Figure 22. If the number of averages does not equal nine, the counter value is assumed to be N/2 and the program branches back to step 284. If the new counter is less than 7/8 N the value is rejected and the program branches back to the starting point of routine 280. If the new counter value is less than 1 1/8 N ,it is within the limits for N. In this instance the number of averages counter is incremented and tested to determine if nine averages have been made. If nine averages have been made the program returns to the calling point within the read routine of Figure 22. If the number o~ averages is not nine the value for N is added to ths new counter and ,shi~ted right (divided by two), whereupon the program loops back to step 284. In testing the number o~ averages counter the value nine is used to accommodate the case where a sixteen bit binary number of alternating ones and zeros occurs as an input word ~101010...). With this alternating sequence o~ ones and zeros there are eight transitions and thus nine averages are u~ed.
The routine ~or rindlng the clock rate several times call~ a routine ~or measuring the period between tran~itlon~. This routine is illustrated in Figure 24. It begins by initializing a counter and sampling the incoming data bit. The counter is then incremented and the data bit i~ again sampled, ~ollowed by a test to determine i~ the ~ampled bit has changed. If it has not changed, the counter is tested to determine i~ one second has elapsed. If one ~econd has not elapsed control loops back to the increment counter step 294 and a second iteration is made. I~ one second has elapsed an error flag is set and the measuring routine exits to the calllng point in the clock rate determining program o~ Figure 23. I~ the bit has changed between successive samples the counter i3 initialized, in ~tep ....

-40- ~ 2 ~ ~

296, and the actual time period between transitions is measured. This is accomplished by again sampling the data bit and testing to determine whether it has changed from the previous sample. If it has not changed the counter is incremented in step 298 and the counter is tested to determine whether one second has elapsed. If one second has not elapsed control returns to step 297 where another sample of the data bit stream is made. If one second has occurred an error condition is detected, an error flag is set, and control exits to the calling point of the clock rate determining routine of Figure 23. When a bit change has been detected between successive samples . control returns to the calling point with the counter containing a value representing the measured time period between transitions.
Once the clock rate has been determined and the error flag tested, steps 280 and 282, the program then waits for the sync pattern, step 300. The wait for sync pattern routine is shown in Figure 25. This routine ~amples the incoming data stream and waits for downward-going transition. When such a transition occurs a delay for N/4 is executed and the data stream is then again ~ampled (at bit time one-quarter). The bit is then tested to see i~ ~t is at a logical Lo "O" state. If it is not, an error flag ls set and the routine exits. If it is at a ~'0" ~tate a delay ~or N/2 is executed and another sample o~ the data ~tream i5 taken ~at bit time three-quarter). The blt i~ again tested to determine if it is at a logical Lo or "O" ~tate. If it is not at a logical Lo state control branches to the entry point of the wait for 6ync pattern routine. I~ the bit i5 at a logical Lo or "O" state another N/2 delay is executed and another sample of the data bit is taken ~at bit time one and one-quarter).
The bit is again tested to determine i~ it i5 still at a loglcal Lo state. I~ it i5 not, control branches to the starting point at the wait for sync pattern routine. If -41- ~32~2~

the bit is at a logical Lo or "0" state the program counts up to an additional N/2 time period while looking for an upgoing transition. If an upgoing transition is not detected control branches to the bit testing step 302. If an upgoing transition is detected a delay for N/4 is executed and a sample of the data bit is taken at bit time one and three-quarters. m e bit is tested to determine if it is at a logical Hi or "1" level. If it is not at a logical Hi level an error flag is set and the routine exits. If it is at a logical Hi level a delay for N/2 is executed and another sample of the data bit is taken (at bit time two and one-guarter). The bit is then again tested to determine if it remains at a logical Hi or nl" state. If it is not at a logical Hi state contro} branches to the entry point of the walt ~or sync pattern routine. If the bit is at a logical Hi or "1" 6tate a delay for N/2 is executed and another sample of the data bit is taken (at bit time two and one-quarter). The bit is again tested and if it is not at a logical Hi or "1" state control branches to the starting point Or the wait ~or sync pattern routine. If the bit is at a logical Hi or "1" state, the sync pattern has been d-tected and the wait for sync pattern exits to the calling routlne o~ Pigure 22.
Returning to Figure 22, following the wait for sync pattorn ~tep 300 the orror ~lag i~ tested, and if it is not aet ~ixt-en bit~ o~ data are read in ~tep 304. 8tep 304 is d-talled ln Flgure 26. Referring to Figure 26, the reading of alxtoon bits o~ data i5 accomplished by delaying for a time ogual to N/2 and then sampling the data bit stream. Due to the cumulative ef~ect o~ previous delays, this sample is taken at bit tlme three and one-quarter. The routine then counts ~or a time equal to N/2 while looking ~or a transition. If no transition i~ detected, an orror ~lag is set and the routine exit~ to the calllng polnt at step 304 ln Flgure 22. If a transitlon is detected, a counter 1~ lnltialized to zero and a delay o~ N/4 ls xecuted while incrementing the counter. The -42- ~3~7~

data bit stream is again sampled (at bit time three-quarter No and this sample is compared with the previous sample to determine if they are complements of one another. If the two samples are not complements, an error flag is set and the routine exits. If the two data samples are complements, the routine determines if the last sampled bit is bit number seventeen (the parity bit of a sixteen bit word). If the last sampled bit is bit seventeen, this parity bit is saved and the routine exits to the calling point, step 304 in Figure 22. If the last sampled bit is not bit seventeen, it is shifted into the data word. This data word may represent a location in memory (such as two eight bit bytes in memory) where the sixteen bits o~ data are returned via the operation of this routine. After shifting the bit into the data word, a delay o~ N/2 is executed while incrementing the time counter.
Another sample is then taken at bit time one-quarter N. The program counts up to N/2 while incrementing the time counter and while looking ~or a transition. If a transition is detected, the bit time N is set equal to the value in the time counter and control loops back to step 306 to sample and shift another bit into the data word.
Returning to Figure 22, once sixteen bits of data have been read in step 304 ~or once the program returns from ~tep 304 with orror ~lag~ set), the error ~lag is tested and i~ not ~et, the parity d~ the sixteen blt word ~ust read is calculated. I~ the parity is not correct, an error ~lag is ~et ~nd the routine exits. I~ the parity is correct, the routine exits without setting the error flag.
While the algorithm ~or reading Manchester code i8 presently implemented in so~tware, the automatic search ~eature may also be implemented using hardware to read the Manchester code. A hardware embodiment may, ~or example, be con~tructed using a UART ~or parallel to serial and serial to parallel conversion, and using a Manchester encoder-decoder integrated circuit such as an HD-15530 manu~actured by Harris Corporation.

~ _43_ ~3~2~

The invention also provides an automatic tape positioning apparatus and method illustrated in Figure 28 et seq. The automatic tape positioning apparatus and method may be combined with the foregoing computer memory back-up -apparatus. If desired, the automatic tape positioning apparatus can be constructed on a separate circuit board for spaced apart attachment to the circuit board 30 of the computer memory back-up apparatus in piggyback fashion. The automatic tape positioning apparatus and method of the invention are not necessarily limited to use in conjunction with the computer memory back-up apparatus described above.
In general, the automatic tape positioning apparatus and method may be used in other applications where it is desired to effect remote control of a tape storage device by computer.
Such uses might include computer control of video taped presentat~ons, ~or example. For purposes of illustrating the invention, however, the automatic tape positioning apparatus and method will be described in conjunction with the computer memory back-up system described above. ~n this application it is desirable to be able to locate a particular computer data ~ile ~tored on a video tape by a video recording device, so that tho ~ile may be read ~rom the tape and loaded into computer memory.
In order to understand the invention in the xemplary u~e o~ ¢ontrolling a video tape recorder or video ¢assette recorder, some preliminary understanding o~ presently available video ¢assette recorders will be helpful. Many of today's video cassette recorders have wireless remote ¢ontrols. Other video cassette recorders have wired remote control which ~all into two categories. One category is the wired remote ¢ontrol which has a plurality o~ dedicated switching wires which are hard wired to the drive mechanism ¢ontrol ~witches within the recorder itself. This type of wired remote control typically has one wire ~or each ~unction to be controlled remotely, e.g. record, play, ~ast ~orward, fast reverse, etc. The other type o~ wired remote control is , ~

_44_ ~ 3~2~

the encoded signal type which typically provides a single twisted pair of wires for time multiplexed communication of signals which are generated by the remote controller and decoded within the recording device in order to control the various recorder functions. This latter wired remote control system is characterized in that it has significantly fewer wires than it has remotely controlled functions and uses time-muitiplexed serial communication between the remote controller and the recorder.
Some video cassette recorders are provided with jac~s for plug connection to a video camera. Often the video camera is provided with buttons for remotely actuating the recorders functions. In such systems, the video camera is typically provided with wired remote control capabilities of the time-multiplexed serial communication type. If a separate television channel tuner is provided as part of the recorder or as a plug-in option, the tuner control functions, such as channel ~election, are also typically controlled by the same time-multiplexed ~erial communication technique.
Similarly, most video cassette recorders are provided with a tape position counter which is mechanically coupled to the tape drive mechanism and is indexed by movem~!nt Or th- tape driv- me¢hanism. O~ten the tape position coun"er i~ m-chanically coupled to the shaft o~ one o~ the tape ta~--up reel driv- ~pindlee. While mechanical odometer-type tap- position counters are ~till being used in some tape r-corders, most video cassette recorder manu~acturers have replaced the mechanical odometer-type counter with an el-ctronic dlgital readout. An encoder is coupled to the ~ha~t o~ the tape drive spindle and provides pulses or digital ~ignals indicative of the movement o~ the tape drive mechanism. These pulses are counted by dedicated electronic hardware counters or by microprocessor-controlled program routines in order to provide a binary coded decimal signal indicative o~ the tape position. This binary coded decimal ~ignal is then fed to the digital readout for display. In ~ _45_ ~ 3~271 video cassette recorders which are already provided with the time-multiplexed serial communication channel (used to communicate between remote control devices, cameras and the recorder) this binary coded decimal counter signal is sometimes placed in the communication stream, so that communication between the position encoder and the digital readout is by way of this serial transmission stream.
The present automatic tape positioning invention is perhaps best suited for use with tape storage devices which employ this time-multiplexed serial communication scheme, since little or no modification of the commercially available recorder is required. A partial list of video cassette recorders which employ a time-multiplexed serial communication scheme are: Panasonic Model PV9600, Panasonic Model PV8000, General Electric Model lCVD4020X, Quasar Model PV5747XE, Sylvania Model RLS362AX, and Canon Model VRVOA. Most of these recorders are the portable type which also have video camera connectors. In computer memory back-up applications or in computer-controlled video presentations, where the ability to tune television broadcasts in not important, these portable machines are pre~erable in that they do not have an integral tuner and are typically quite a bit smaller and, there~ore, tak- up le~s desk ~pace.
Rererring now to Figure 28, the automatic tape po~ltionlng apparatus will now be described. The automatic po~itlonlng apparatus 410 i9 adapted to be coupled to the re~ote control terminal, connector or port 412 o~ a video tape recorder or video cassette recorder of the type which employs tlme-multlplexed serial communication. Typically the remote control lnter~ace o~ commercially available video cassette recorders ls a ~ive-pln connector, wlth one pin being unused, one pin carrying the DC power (nominally ~ive volts), one pin beinq at ground, one pin carrying a clock signal and one pin carrylng a data signal. The power signal i~ used by the automatlc tape positioning apparatus, and optlonally by the computer memory back-up apparatus, as a ~lgnal to indicate -46- 1~2~1 that the video cassette recorder is turned on and connected.
The clock signal is generated by the video cassette recorder.
It is used internally in the video cassette recorder and is routed to other related devices such as a television tuner, video camera and remote controller. The clock is used to synchronize the transmission of each bit of the seven bytes of data that make up the system control signal. The data signal is made common to all devices (tuner, camera, remote control, etc.) attached to the video cassette recorder. The data signal is pulled high internally within the video cassette recorder and is driven low by open collector drivers in each device. Each device must monitor the clock and is allowed to drive the data signal in the time period reserved for it. A
more complete description of the cloc~ siqnal and the data signal and the data signal will be presented below.
The automatic tape positioning apparatus includes isolation circuit 414 which provides isolation for each of the three video cassette recorder signals coupled to it, namely power, clock and data. The automatic tape positioning apparatus is adapted for coupling to the host computer system 20. Although the signals of both the video cassette recorder and the computer system are TTL logic levels, isolation is nece~sary because TTL logic inputs will load the signal ~pull it to zero volts) when the power to the computer or video ca~ette recorder i~ o~. Without isolation, i~ either the vld-o ca~ette recorder or computer iB on and the other is o~, the unit wlth power would have it~ signals shorted to ground, potentially interfering with normal operation. The i~olation circuit 414 prevents this from happening. The l~olation clrcuit ~or a ~ingle video cassette recorder signal is illustrated in Figure 29. There are three such circuits in isolation circuit 414. As illustrated, the isolation circuit consists o~ a tran6istor 416 which is res~stor coupled and biased to couple the individual video cassette recorder ~ignals to parallel bits of the microprocessor input port of computer system 20. The reading o~ the input bits is -47- ~ ~29~7~

performed in software. In order to interface the isolation circ~it 414 with the computer system bus 52, specifically with ~icroprocessor data bus 74 and with the microprocessor control signal lines 78, a bus buffer circuit 417 is used. Bus buffer circuit 417 can be implemented using a programmable input/output integrated circuit, such as a Z80PI0 integrated circuit. The isolation circuit and bus buffer circuit thus provide the communication link to permit the power signal, clock signal and data signal to flow from the video cassette recorder remote control connector to the data bus and control signal lines 74 and 78 of the host computer system 20.
In order to establish a data signal flow path from the computer system 20 back to the video cassette recorder, 2~ome additional circuitry is utilized. An open collector driver 418 is coupled at its output to the data line of the remote control connector. The input o~ driver 418 is coupled to a latch circuit 420 which is in turn connected to the clock and write data lines of bus buffer 417. When the microprocessor of computer system 20 sends data to the video cassette recorder, open collector driver 418 supplies the data signal to the remote control connector. Because the data signal must change synchronously with the falling edge of the clock, ag wlll be discussed more ~ully below, latch 420 i8 provlded to couple the output bit ~rom the microprocessor output port to the open collector driver 418. The latch is clocked by the clock ~ignal ~rom the remote control connector lnter~ace 412.
Although the automatic tape positioning method of the lnventlon ~nay be implemented using discrete electronic hardware components, the presently pre~erred embodiment implements the method in software. The software algorithms to read the video cassette recorder tape counter and to write a command to control the video cassette recorder. In order to under~tand these algorithms, an understanding o~ the video cas~ette recorder clock signal and data signal will be helpful. Figures 30 and 31 illustrate these signals. The -48- 1~2~2 i ~

presently commercially availahle video cassette recorders which employ a time-multiplexed serial c~mmunication scheme use seven data bytes, each byte comprising eight bits. The seven data bytes are synchronized by a clock whose period is 44.7 microseconds. The cycle in which the clock synchronizes the seven control bytes is 17.16 milliseconds. The actual transmission of the seven bytes occurs in approximately five milliseconds, leaving the clock idle for the other 12 milliseconds. Figure 30 illustrates the clock signal and data signal over one complete clock cycle 422. At this resolution, the individual clock pulses 424 are represented by spaced apart vertical lines. The individual data bytes Tl-T7 are represented by dotted lines.
Figure 31 depicts the clock and data signals at a higher resolution. More specifically, Figure 31 is a time-expanded resolution of the first group of clock pulses and corresponding data byte Tl of Figure 30. As seen at this resolution, the clock signal comprises a plurality of clock pul~es 424 which define ~alling edges 426 and rising edges 428. The data byte, in this case T1, comprises seven bits, designated bit 0-bit 7. The transitions 430 between bits occur in synchronism with the ralling edge o~ the clock, thereby placing the ri~ing edge o~ the clock at approximately th- center o~ the individual bits, at which point they may be ~ampled. The present automatic tape positioning apparatus and method i~ designed to work with this existing time~multiplexed ~erial communication ~cheme. As will be explained below, the invention does this without inter~ering with the normal operations o~ the video cassette recorder or its associated components.
Table I sets ~orth the transmission ~unction de~inition ~or each of the seven bytes o~ data in the serial communication echeme. In this regard, the ~unctions illustrated are merely exemplary o~ one particular scheme ~ound in ~ome commercially available video cassette recorders.
Other schemes are, o~ course, possible; and the invention is, _49_ ~ ~2~2 1~

therefore, not to be limited to any particular data transmission scheme.
........................................................................
TABLE I
................................ ...........
TRANS~ISSION FUNCTION DEFINITION
Trsnsmission Function T1 Tuner to VCR
T2 Csmers to VCR
T3 Remote to VCR
T4 Internsl VCR to VCR
T5 VCR to Devices Status T6 VCR to Devices Counter ~SB
T7 VCR to Devices Counter LSB
.............................................................. ...... ...

As indicated in Table I, the first three data bytes T1, T2 and T3 relate to communication between the video cassette recorder (VCR) and a tuner, camera and remote control device. Table II describes exemplary bit definitions for Various video cassette recorder modes or controlled functions.
Table II gives the bit definitions in both binary and hexadecimal.

- ~ 3 2 ~

.............. ..........................................................

.........................................................................

BITS
76543210 HEX VCR ~ODE
00000000 00 Stop 00001 01 0 OA P I ~y OO000010 .02 Re~ind 00000011 03 Fast For~ard 00001000 08 Record 00000100 04 Revie~
00000101 05 Cu~
00000110 0~ StilltPause 00001100 0C Frame Advance 00001111 OF Slo~
00101110 2E Slo~ Speod Up 00101111 2F Slo~ Spood Do~n 10010111 97 Timor Sot 10011001 99 Timer On 00001101 OD Roc/Rovio~
,........................................................................

In addition to the video cassette recorder control ~unctions, the serial transmission scheme also includes device ~tatus ~unctions comprising byteE~ TS, T6 and ~r7~ Tables III
and IV describe the bit de~initions o~ these status ~unctions.

-51- ~2~2i ~

................................................................ ... .
TA~LE 111 ...............................................................
BIT DEFI~ITIO~ T5 BITS

01010000 50 T6 ~ T7 Is T~pe Counter ~ On Camer~ Qemote S~itch On 01010101 55 T6 & T7 Is Tnpe Counter ~ On Csmer~ ~emote S~itch On 00000000 00 T6 & T7 Is,T~pe Counter ~ Off C~mer~ Remote S~itch On 00000101 05 T6 & T7 Is T~pe Counter ~ Off C~mer~ Remote S~itch Off11110000 F0 T6 & T7 Is B~ttery Level C~mera Remote S~itch On 11110101 F5 T6 & T7 Is Bottery Level C~mer~ Remote S~itch Off ................................ .........................................
T~BLE IV
..........................................................................
BIT DEFI~ITIO~ T6 & T7 T~PE COUNTER VALUE

I~54321076543210 ~CD T~PE POSlTiON
~SBLSB ~NNN
0001001101010111 1357 ~EX~MPLE)-With rs~erence to Table III, it is noted that ~our o~ the ds~ignated bit patterns ~namely hexadecimal 50, 55, 00 and OS) are used as tape counter status bytes. As set ~orth ln Table IV, the bit patterns o~ bytes T6 and T7 convey the actual binary coded declmal digits o~ the most signi~icant digits (MSB) and least signi~icant digits (LSB) o~ the tape counter value. Table IV gives an example ~or the tape counter value 1357.
The so~tware algorithm to e~ect automatic tape po~itioning control over the tape recording device by the computer system 20 i5 set forth in Figure 32. The algorithm may be implemented by programming the computer system 20 to execute the steps set ~orth in Figure 32. The algorithm is a -52- ~ ~2~

time-critical routine. It must read and write data signals in synchronism with the clock signal generated within the video cassette recorder. Accordingly, the computer system interrupts are disabled upon entry of the remote control routine at step 432. With the computer system interrupts disabled, the remote control routine itself must periodically check to make sure the computer system has not inadvertently locked up. Accordingly, in step 432, a software time-out counter is initialized to a value representing a time significantly greater than the time normally needed to execute the remote control routine. This value may represent, for example, a time twice what would normally be used by the remote control routine. The computer system interrupts are also disabled at this point, to enable the remote control routine to run without interruption from other devices attached to the computer system.
Next, in step 434, the routine waits for a gap in the serial transmission. With reference back to Figure 30, it is seen that there is a gap 436 between the end of data byte T7 and the beginning of the subsequent data byte Tl. The routine ~or waiting ~or the gap in transmission is depicted in Figure 33. Re~erring to Figure 33, the routine begins by setting a software time counter (not to be confused with the time-out counter) to a value more than su~icient to measure the elapsed time o~ the transmisslon gap, as indicated in step 438. A time o~ 4 mllliseconds i5 suf~icient ~or this purpose.
Next, the time counter i8 decremented in step 440 and then in step 442, the time counter is tested to determine if the full time has elap~ed, i.e. whether the counter has reached zero.
I~ zero has been reached, the wait for transmission gap routine returns to the calling routine, the remote control routine o~ Figure 32. On the other hand, i~ the counter has not reached zero, control proceeds to step 444 where the time-out counter (not to be con~used with the time counter) is again decremented. At this point, control proceeds to step 446, where the time-out counter set in step 432 i5 tested to _53- ~ 32~271 see whether zero has been reached Recall that this time-out counter initially contains a value significantly larger than the expected time to complete the entire remote control routine of Figure 32 Hence, if the time-out counter has been decremented to zero by the previous step 444 (and other time-out decrement steps elsewhere in the program~, a time-out error has occurred, indicating possible computer lockup If such an error has occurred, program control jumps to an error handling routine which reinitializes the machine state and returns to the starting step 432 If the time-out counter has not reached zero, which it normally should not, the program proceeds to step 448 where the clock signal input through bus buffer 417 is read and tested to determine whether it is high or low In step 450, if the clock is low at this point, the routine determines that the serial transmission must have been in the middle o~ reading some data bits In this instance, control branches back to the beginning step 438, where the time counter is reset to 4 milliseconds on the other hand, i~ the clock is high at step 450, control branches to step 440, where the current time counter value is decremented Thus it will be seen that i~ the transmission gap routine determinee that the clock signal i5 quiet for at least 4 millie-conde, the eerial tranemiesion i5 in the gap 436 Knowing this, the program ie able to eynchronize with the next occurring clock eignal Returning now to Figure 32, program control resumes at st-p 452 which le anothor time-out teet Step 452 per~orms se-ntially the eame ~unction as etep 446 discussed above, nam-ly a ~ump to an error handling routine should the computer ~ail to complete the romote control routine in the expected amount o~ time As illustrated in Figure 34, this error handling routine at the minimum comprises a step 454 whereby the computer eystem lnterrupts are enabled, and a step 456 which eete a ~lag indicating that the remote control routine ie not ready Thi~ ~lag may be used by other eoftware algorithme to det-rmine the reaeon ~or time-out, e g a device ~ -54- ~ ~ O ~ ~

not ready, and to prompt the user with the appropriate message. This time-out checking ~outine is implemented at a plurality of points within the routines of the invention. For example, the time-out checking routine appears several times throughout the remote control routine of Figure 32, as at steps 460, 464, 472, 476, 480, 486 and 492.
It will be recalled that the serial transmission comprises seven data bytes which occur in sequence. Bytes TS, T6 and T7 convey the tape position counter information. In order to read this information, the routine stays synchronized with the serial transmission by reading all seven of the data bytes and ignoring those which are not important.
Accordingly, in steps 458 and 462, the first and second bytes T1 and T2 are read and ignored. Next, at step 466, the routine branches, depending upon whether the computer is attempting to read the tape position counter or attempting to write in~ormation to control the video cassette recorder.
Both the read and write routines will be discussed in greater detail below. I~ the computer is only reading the counter, the program branches to step 468. If the computer is writing a command to the VCR, the control branches to step 470.
Followlng this branching decision, control continues by reading and ignorlng the ~ourth byte T4 o~ the transmission.
A~ter reading the ~i~th transmission T5, the routine proceeds to read and save transmissions T5, T6 and T7, as these bytes contaln the tape position counter in~ormation. ~See continuation o~ ~low chart on Figure 32a.) After the ~inal tran~mi~ion T7 has been saved in step 494, the interrupts are enabled in ~tep 496, thereby allowing other devices attached to the computer system to gain access to the computer system.
Next, in ~tep 498, the ~i~th transmission ~5, previously stored, is tested to determine whether the subseguent bytes ~6 and T7 represent tape counter values or whether they represent the battery charge level. A~ indicated in Table III, if T5 contains either the hexadecimal value FO or F5, then the ~ubsequent bytes T6 and T7 represent battery level data. On _55_ ~32~27~

the other hand, if T5 contains hexadecimal values 50, 55, oo or 05, then the subsequent bytes T6 and T7 represent the most significant and least significant digits of a four-digit binary coded decimal. This binary coded decimal is the tape counter value. Once the tape counter value has been determined, control continues at step So0 by setting a flag indicating that the remote control routine is ready and that the values stored in response to transmissions T6 and T7 represent a valid tape counter value.
Referring now to Figure 35, the read transmission routine comprises steps 502 through 530. The read tran6mission routine te~porarily stores received data in a location designated as the "current byte". In step 502, the current byte is initialized to zero. Next, in step 504, a bit counter is ~et ~or eight bits (being the number of bits in a data byte--see Figure 31).
The read transmission routine is called by the remote control routine of Figure 32 seven times, corresponding to tran~mi~sions Tl-T7. Hence, the read transmission routine i~ part o~ the time-critical remote control routine of Figure 32. Accordingly, the read transmission routine also perlodically'per~orms the time-out check to determine whether lockup pa~ occurred (~tep~ 508 and 516).
Th- r~ad tran~mi~ion routine tests the clock signal blt ln ~tep S10 and e%ecutes a continuous loop between steps 506 and S12 until the clock goes low. A~ter thls has happenea, the routlne enters a second loop between ~tep6 514 and S20 in which the program remains until the clock goes high. When this has occurred, the routine next samples the data slgnal bit ln step 522 and that data bit i8 moved into the carry bit o~ the microprocessor register. The carry bit i~ then rotated into the current byte, and the bit counter is decremented. I~ the bit counter has reached zero, the routine 1~ ~lni~hed and control return~ to the remote control routine.
I~ the bit counter has not been decre~ented to zero, control returns to ~tep 506, whereupon the process repeats.

-56- ~32~2 1~

In essence, steps 522 through 528 sample the data bits of each data byte as they occur in serial fashion. The sampled bits are temporarily placed in the carry bit location of a register within the microprocessor of the computer system. The rotate instruction moves the temporarily stored bit from the carry bit location to the first bit location of the microprocessor's accumulator. The rotate operation also moves the bit previously stored in the first bit location to the second bit-location of the accumulator, the second bit to the third bit, the third bit to the fourth bit...and the seventh bit to the carry bit. The rotate operation in effect performs a serial to parallel conversion of the eight bits of any given data byte.
Figure 36 illustrates the write transmission routine comprising steps 532 through 562. The desired command to be sent to the video cassette recorder is first placed in the accumulator or other register of the computer system microprocessor where a rotate operation is performed to move the most signi~icant bit (bit 7) into the bit zero location, step 532. A bit counter is then initialized in step 534 for eight bits. ~he counter is then decremented in step 536 and a~ter the time-out check routine 538, the clock is sampled and tested to determine whether it is high. Program control remain~ in a loop between steps 536 and 542 until the clock goes high. As soon as this occurs, the bit in the bit zero location is sent as a data bit to the video cassette recorder via the bu~ bu~er 417, latch 420 and driver 418. Next, in step 546, the command byte is again rotated to move the most signi~icant bit ~bit seven, ~ormerly bit six) into the bit zero location. A~ter testing ~or time-out, the clock is again ~ampled and program control remains in a loop between steps 548 and S54 until the clock goes low. When this happens, the bit counter is decremented and tested to determine whether any more bits remain to be sent. I~ 50, then program control branches back to step 536. I~ not, then the routine executes a delay loop o~ approximately ~orty microseconds in step 560 _57_ ~32~

and thereafter returns the output data signal to a high level in step 562. This last step is necessary because the interface operates using an open collector circuit. If the final bit sent happened to be low, it must be reset to high, otherwise the output would remain locked up forever.
From the foregoing, it will be seen that the invention provides the capability of computerized retrieval of information stored on a tape storage device, giving the computer the ability to read the tape counter which is indexed by movement of the tape drive mechanism and also the ability to send control signals to effect remote control operation of the tape storage device. The invention does this without interfering with normal operation of the tape storage device by monitoring the clocX signal produced by the tape storage device and reading or writing data bits at the proper time to synchronize with the existing serial communication scheme. In order to stay synchronized, the routine reads all of the control bytes produced in accordance with the communication ~cheme and ignores those which are not important to the operation of the invention. Throughout the entire process of reading the clock, a software time-out counter is maintained to detect a malfunction or disconnection o~ the serial co~munlcation slgnals. Detecting a time-out condition thus avoids tho po6sibllity of the invention being held inde~n~tely in a so~tware loop.
In operatlon, the algorlthm monitors the communicatlon ~y~tem clock to determlne when it has been contlnuously ldle for at least 4 or 5 milliseconds. The algorithm then a~sumes synchronization and begins to wait for the ~irst transmission. $he first two transmissions are read and discarded. If the routine is writing a command to the tape storage device, the third transmission is written.
Otherwise, the third transmission is also read and discarded.
$he ~ourth transmission is similarly read and discarded, while the last three transmissions are read and saved. In order to read a transmission, the routine waits for the clock bit to go -- -58- ~ 32~2 ~
to low (the first bit is being placed on the data signal).
Then, the routine waits for the clock to return high. The clock returning high indicates that setup times have been met and that the tape storage device has taken the data bit. This being the case, the apparatus of the invention can also read the data bit at this time. Eight data bits are read to make up a data byte transmission.
To write a transmission, in order to send a control signal to the tape storage device, the invention outputs a first bit ~hile the clock is high. The hardware latch will transfer the logic level to the data signal on the falling edge of the clock signal. The tape storage device reads the data bit on the rising edge of the clock (the wait period allows for signal setup time). When the clock has gone low and then returned high, the next bit is output, until all eight bits have been transmitted. After the last bit has been transmitted, the output signal is returned high.
After all seven transmissions have been read, the routine checks the Slag bits of byte T5 to determine if bytes T6 and T7 were tape counter information, as opposed to battery level information. If battery level information was transmitted, the invention will reread the entire sequence.
~f bytes ~6 and T7 were tape counter information, the routine wlll return with thi~ information.
With the ability to read tape counter in~ormation ~rom the tape ~torage device and the ability to ~end commands to the tape ~torage device, the invention allows the computer cy~tem to ~earch ~or a particular location on a tape and then playback or record at this location. The invention also allow~ the computer to place the tape storage device in a ~ast ~orward or ~ast rewind mode, while monitoring the tape counter value, until the desired tape position is reached. Thereupon, 1~ desired, the computer system can in~truct the tape storage devlce to playback or record at the regular speed.
While the u~es o~ the invention are many, one lmportant use o~ the invention is in con~unction with a -59- ~32~

computer memory back-up system, such as that described above.
The automatic tape positioning invention permits computer data files to be conveniently stored on and retrieved from video cassette tapes. Using a portable video cassette recorder, for example, the video tape back-up system takes up little desk space. Because the invention is plug compatible with the remote control features of the video cassette recorder, no modifications to the recorder need to be made.
In performing backup of hard disk storage devices, the tape counter positions of each file being stored can be recorded at one or more convenient locations, so that the computer system can automatically recover the appropriate files should the need arise. These tape counter values might, for example, be stored on the hard disk itself in the form of a file or subdirectory allocation table. The same table might also be stored at the beginning of the video tape, or at periodic positions along the tape, so that the computer system can readily determine where the backed up files are stored should recovery be necessary.
While the preferred embodiments of this invention have been illustrated and described in detail, it will be apparent that various modifications as to the details of con~truction and design may be made without departing from the ~pirit of th- invention or the ~cope o~ the following claims.
What is claimed is:

Claims (14)

1. An apparatus for connecting the computer system bus of a computer system to the remote control clock and data terminals of a tape recording apparatus, comprising:
bus buffer circuit having an input and having an output for coupling to said computer system bus;
isolation circuit having an input for coupling to said clock and data terminals of said tape recording apparatus and having an output coupled to said input of said bus buffer circuit;
latch circuit having a clock terminal coupled to said isolation circuit output, having an input coupled to said bus buffer circuit output and having an output; and driver circuit having an input coupled to said latch circuit output and having an output for coupling to said data terminal of said tape recording apparatus.

2. The apparatus of Claim 1 wherein said tape recording apparatus provides a tape position counter signal at periodic intervals on said data terminal in synchronism with a clock signal on said clock terminal, and further comprising:
program means for synchronizing said computer system with said clock signal and for causing said computer system to read said tape position counter signal.

3. The apparatus of Claim 1 wherein said tape recording apparatus is responsive to remote control signals via said data terminal in synchronism with A clock signal on said clock terminal, and further comprising:
program means for synchronizing said computer system with said clock signal and for causing said computer system to write remote control signals to said tape recording apparatus.

4. The apparatus of Claim 3 wherein said program means causes said computer system to write remote control signals to said latch circuit and said clock signal causes said latch circuit to write said remote control signals to said data terminal of said tape recording apparatus.

5. The apparatus of Claim 1 wherein said tape recording apparatus further includes a remote control power terminal and wherein said isolation circuit includes input for coupling to said power terminal to said computer system bus.

6. The apparatus of Claim 1 wherein said bus buffer circuit includes data input for coupling to the data bus of said computer system and includes a control input for coupling to the read and write control lines of said computer system.

7. A method of using a computer system to control the motion of tape in a tape storage device relative to a desired tape position, the tape storage device having a tape counter which is indexed by movement of a tape drive mechanism and thereby indicative of tape position, the tape storage device further having an encoder responsive to the tape counter for providing a counter data signal indicative of the tape position and the tape storage device further having a tape drive mechanism controllable by command signals issued through a remote control port, comprising:
causing the computer system to store a desired tape position in memory;
causing the computer system to generate a first command signal and communicating said first command signal through said remote control port to cause the tape drive mechanism to commence motion of the tape toward said desired tape position;
causing said computer system to read said counter data signal and to determine from said counter data signal the instantaneous position of said tape;
causing said computer system to monitor said instantaneous position and to compare said instantaneous position with said desired tape position; and in response to said comparison, causing said computer system to generate a second command signal and communicating said second command signal through said remote control port to cause the tape drive mechanism to alter the motion of the tape at a predetermined location relative to said desired tape position.

8. The method of Claim 7 wherein said first command signal is a fast forward command signal.

9. The method of Claim 7 wherein said first command signal is a rewind command signal.

10. The method of Claim 7 wherein said first command signal is a play command signal.

11. The method of Claim 7 wherein said second command signal is a stop command signal.

12. The method of Claim 7 wherein said second command signal is a play command signal.

13. The method of Claim 7 wherein said second command signal is a record command signal.

14. A method of using a computer system to retrieve information stored at a predetermined position on a tape in a tape storage device, the tape storage device having a tape counter which is indexed by movement of a tape drive mechanism and thereby indicative of the tape position, the tape storage device having an encoder responsive to the tape counter for providing a counter data signal indicative of the tape position and the tape storage device further having a tape drive mechanism for placing the tape storage device in at least a search mode and a playback mode, the tape drive mechanism being controllable by command signals issued through a remote control port, comprising:
causing the computer system to store said predetermined position in memory;
causing the computer system to generate a search command signal and communicating said search command signal through said remote control port to cause said tape drive mechanism to enter the search mode;
causing said computer system to read said counter data signal and to determine from said counter data signal the instantaneous position of said tape;

causing said computer system to monitor said instantaneous position and to compare said instantaneous position with said predetermined position;
in response to said comparison, causing said computer system to generate a playback command signal and communicating said playback command signal through said remote control port to cause said tape drive mechanism to enter the playback mode, whereby said stored information may be retrieved.