CA1314329C - High-speed press control system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A high-speed press control system including a control processor and an associated scan processor for executing a press algorithm providing timed interrupts and consisting of identical programmable sub-algorithms to control output and input registers. The high-speed press control system has the capability of monitoring and reacting to press position every 2.5m?.

Description

3 ~ ~

E GH-SPEED PRESS_CONTROL SYSTEM

Technical FieId This inve~tion rel~te~ genere~.ly to programD~ble logie co~trollers that control the operation of machine tool~, ~nd in particular thi~ invention relste~ to B
p~ogramm~ble logic controller containing instruotions ~or controlliDg ~ high-~peed punch pre~s including m~terial ~upply a~
removal.
B~ckground Prior Art Programm~ble logic controller~
(PLCsj th~t oontrol the operation vR a punch pre ~ compri~e B micropro~e~sor- ~ ed controller that inoludes a microproces~or, : ~mory and in~truotions oontained Ln the me~ory for sensing the condition of the various pert~ of the ~ h pre8~ and affecting t ~ opening and closing of ~witohes and valve~ for proper operation of the punch press.
Punch pre33es are often require1 to operate with ~uxiliary funotions, sush as feeder~, lifters, extractors, etc. Auto~ation valve ~olenoids are required to operate at ~peci~ic position~ of each pre~s ~troke. ~ach automation Yalve solenoid mu~t be cap~ble of bein~ turned ON and OFF at programmable ~lide position~ (with or without an adjus~able time del~y) or b~sed on re~ote contact status (again with or without a kime deluy). Since A `:

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. , -" ~3~32~

these operations may have to occur within a degree of the programmed setpoint, scan and I/O update time are criticalO
PLCs have operated according to rung laader diagrams that substantially emulate the older relay logic previously used to control punch press operations. In the prior art, the fastest that a punch press could be operated would be substantially 30 strokes per minute in conjunction with turning on and off approximately 8 valves or switches. This substanti~lly inhibits high-speed punch press operation where the punch press itself could operate at more than twice that speed. Speeding up the cycle time of the microprocessor in the PLC achieves some increase in speed in operating the punch press r but fails to achieve the necessary punch press operational speed.

Summary of the Invention Tn accordance with the invention, a programmable logic controller (PLC) based system for controlling a high-speed machine operating in cycle-type modes comprising in combination:
at least one machine having a plurality o~ components having at least t~o status states; an execution memory, machine control algorithm in said executive memory, a control processor for coordinating operation of the system; a communications connection between the machine and said control processor; said control processor also perEorming communication between said control proces~or and said machine; and, a scan processor for performing computation of desired output states and data values based upon the inputs received from the machine.

13~329 The programmable logic controller (PLC) of the invention may achieve a punch press operation oE substantially 120 strokes per minute with operation of a maximum of 64 values or switches~ The invention substantially multiplies the punch press speed through a particular seguence of microprocessor instructions that may operate at multiples of 2.5 milliseconds.
As the specified number of strokes a press is called upon to execute per minute keep increasing, these speed requirements necessitate the development of a new approach. The most viable means of achieving the desired speed is to incorporate the automation algorithm itself in the executive software of the scan processor. When enabled, this algorithm can be executed as part of the control processor's regular 2.5 ms interrupt. Necessary set-up parameters, such as position, time and remote contact status, can be passed to the image memory of the processor by establishing a function block of registers in which the location of this information is specified by the user.
The start of such a function block may be established by enabling a SPECIAL LET statement in the user program. Output (valve) bits may be turned ON or OFF in the real world each time the algorithm is executed by the scan processor, effectively providing the PLC
with the ability to monitor and react to press position every 2.5 ms.

~, ~ 3~32g Bxief Description of Drawings E'IG, 1 is a block d.iagram indicating a punch press and material handling system controlled by a programmable logic controller (PLC) of the invention;
FIG. 2 is a circle diagram illustrating some of the timing involved in ~.

~3~3~

the pro~ramE~ble logic controller of the invention;
FIG. 3 i~ a block dia~ran ~howLng the press, algorithm fu~ction block S ~tructure; a~d, FIGS. 4A ~nd 4~ show a fla~ ch~rt of an, sub-algorithm flo~ ~LQgra~.

De~ailed Descri~tion FIG. 1 ~hows a high-speed punch press 11 of the type which is controlled by the control ~ystem 12 of the invention. As will be readily appreciated, punch press 11 requires a ~ultitude of controll~d valve closure~ and o ~ ~, limit switche~
actuations, etc. to perform required Punctions. Further, the e ~yriad of : oper~tions must be done quickly anl preci3ely, and often in very rapid sequance. The control system 12 of the invcntion provides a punch press control having a par~ioular microprocessor instructional ope~ation of a special timed interrupt al~orithm to achieve press operation of substantially I20 strokes per minute with a m~ximum of B4 valves or : switches.
FIG. 3 show~ a block diagra~ of the inventive control ~yste~ 12 inoluding a pre~
algorithm 10 for controlling a hi~h-speed press. The ~ystem 12 o~ FIG. 2 includes a control prooes~or 14. ~ontrol proces~or 14, : 35 ': ' ' ;

.

~3~329 which may be of suitable known de~ign, provide~ ~anage~ent functions for the ~y~te~
and ooordinate~ the operation of all the comp~nent~ of systen 12.
System 12 Lnclu~es an exec~ltive memory 16 ~which may be p~rt o~ the control proces~or 14) and executive me~ory 16 includes the press algorithm 10. Syste~ 12 fur~her inoludes a compiled u~er me~ory 18, a bus inter~ace 22 and an image me ry 24. The information to and from the ~yst~m bus 25 i~
provided through bus interf~ce 22. The syste~
12 al~o includes ~can proces~or 2B~ to be de~cri ~ .
A~ mentioned, ¢ontrDl proces~or 14 either perform~ or coordinates all pr wes~or ystem 12 operations. This inoludeq performi~g all communication via a systems bus 25, and handlin~ all interrupt~ and error ~ condition from the sGan procesYor, communications interface network bu~, and the rem~inder of She programmabIe controller sy~tem.
Compiled user memory 18 compri~e~ a RAM and Ln operatiGn contains a compiled ver~ion o~ the user ~rogram and pres~
algorithm to serve a~ executable i~struction~
for the ~can processor. The compiIed user : memory 18 i~ randomly acces~ible by the 3~ oontrol processor 14 for pu~poses oP loading and editing uQer pro~ram~. The scan proce~r .

;

~3~ ~2~

28 acce~es the compiled u~er memory 18 ~ aa executive memory of ~ucce~sive m~truction~.
The image ~emory 24 receive~ the input ~t~
Prom the control proce3sor 14 anl 3to~a it ~or aece~ by the ~can proce~or 28.
A~ ~entioned, the pre~s algori~hm 10 is included in the executive memory 16. On : power-up, the algorithm 10 is tran~ferred P~om the executive memory 16 to the compiled user memory 18.
FIG. 3 also indicates the high-8peed punch preqs 11 ~nd is co~nected through suitable input and output ports 30 and 31 to the network buY. The pre~s ~l provides control and position input information to the control proce~sor 14 through bu~ ~4 anl, as will be explained, control proces~or 14 provide~ control information to the pre ~ 1l.
A~ ~ill be explained in detail and as indicated in FIG. 4, the pre~s control, ; algorithm 10 allows the PLC to be Lnterrupted after a 3pecified:amount of time a~d respond to specified input~ and control 3peci~ied outputs and then return t~ the ta3~ that were interrupted. Thi8 interrupt method can be : u~eful in application~ where output~ need to respond to BCD data or di~ital inputs being sampled within a pRrticular ti~e limit or where input pul e~ need to be st~etch~d to perMit recognition during norm~l ~can ti~e of program.

~3~3~ -The algorith~ 10 (enabled ~uoh a~
by ~peci~l L~T in~truction 200) con~ists of up to 64 execution~ of the ~ub-algorithm to control four con~ecutive output re~i3ters (64 outpu~; from 8 con~ecutive Lnput registers ~128 input~) or one B~D re~ister, see FIG. 4 ~pecial LET inat~tion~ 201 disable~ the interrupt al~orithm).
Each of the executi~ns of the 8ub-al~orithm consi~t of a ba~ic retentive ON/OFF
(~tart/~top) function where outputs can ~e delayed either ON, OFF or both. TURN ON or TURN OFF selectibility i~ a~ follows:

Definition Turn On Remark~
On REM Digital input/ Output internal command on Transition of l'ON
: Re~ote"

., : 25 :

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~:' ~ 3 ~

. ' ON P~ition ~CD O~-O~f 3utput Setpoints commaNd on Tr~nsition of "CAM"
create~ by on-off' setpoints ooMpar~d wlth ~D
input ON Tim Either of above Del~y turn plus Time Delay ~n of output Definition Turn Off Remarks Off REM Di~ital input/ Set~
internal commQnd to turn off Off Pos BCD On-Of~ Sets : setpoints command to ~ turn of~
~en:c~m ~
created by on-of~ ::
` setpoint~
is not N present . .
Off TL~ Either of above Delay plus Time Delay turn off or time delay of output after turn on The interrupt algorith~ per~orms immediate l/O
update on speci~ic B~D input and digital I/O
every interrupt. A consecutive block o~
registers must be as igned to tbe algorith~
with the start register selected in ~peoial . , .
.

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.: -, .. . . .

13~ ~329 instruotion 200. The length of the block i~
in multiplea of 15 x nu~ber of execution~ of sub-algorithm.
The ladder pro~ram ~tructure for enablin~ ~nd dis~bling the press al~orithm is aQ follows:
; Algorithm Enable ~un~

lo ~nable SPEC
-]Z[- LET l~L=(B) 200 ;tc);(D);(E);~FLi ~L
where ~Z~ - enables Interrupt Algorithms when closed and al~orithm previously disabled. Ke~ainin~
closed or opening haa no ef~ect.
i (A~ - ~tatus register - a~y unuYed re~ister used only with associated Enable~Di~able Rungs. Bit 18 will come on if incorrect number or p~rameter programmed.
~B) - 1st register of block of parameter ,~ - registers as~igned to algorithm.
~C) - Po~ition l~pUt re~i~ter.
(D) - 1st register of 8 consecutive input registers.
(E~ - 1st re~ister of 4 consecutiYe output registers separate from input register~.
(F) - No. of executions of sub-algorithms u ed.
~G) - Interrupt rate ~ multiple~ of 2.6MS, ~1 x 2.6MS, 2 x 5MS eto.
. ~
, :

13~3~

Note: Algorithm requires th~t 13 ~Separate regi~ters be a~si~ned ~or I/0, one for pOQitiOn input t 8 input regi~ter~ and 4 output registers.

Algorithm Di~able Rung Disable ~iPEC
-]Xt- LET (A) = (B) 2C1 (X) - Disables al~orithm Enable Rung when closed and algorithm previously enabled.
(A) - Status regi3ter used in Enable Rung.

Enablin~ and Disablin~ Interrupt To enable the interruptl a let statement with special instruction 200 and 5 parameters musSt bse progr~mmed. The let ~`
statement:may be pro~ra~med and operates asS
standard except the para~eters are Qtored when first enabled and opening the rung will not disable the interrupt. The interrupt will be activated on 2nd soan of run~ (lst scan bein~
dummy 3can). Disabling the interrupt occurs when the proce~sor goes to halt or a special instruDtion 201 let ~tatement i~s pro~rammed and enabled. Control regi~Ster 8176 bit 25 iss on when interrupt operating while bit 26 come~S
on after 1st interrupt isS oomplete.

, . !.
' s '~ --` ~3~3~1 Cha~ing Parameter_ of InterruPt Enable Rin~
As indioated above, the parameter~
of the ~pecial instruction 200 let rung are stored when first enabled. The param~t2rs may be program-changed while the interrupt i~
5 operating but the interrupt w~ll continue to run on the old parameter~. The new parameters will take effect o~ly a~ter the interrupt i~
di~abled a~d reenabled.

lQ Interru~t Action When the interrupt occurs due to internal clock and repetitive rate pro~ra~med in enabling let ~tatement, the proces~ar interrupt~ the task being performed. The 15 processor does an immediate input update on the position regis*er and eight (8) consecuti~e di~ital regi ters ~inp~t3), Using the algorithm control parameters block of re~ister~, the sub-20 algorithm is execut~d with the output i~a~e table updated if required as directed b~
output pointers and mask3. The st~tus of the sub algorithm is reflected in the "Wor~"
re~ister of the block. This register is 25 retentive and only changed by program control.
After all ~ub-algorithm~ requested ha~e been exeouted, an immediate output update is performed from the four (4) consecutive register~ defined a~ output~.

, ' ~ 3 ~

Interrupt Time The len~th of the Interrupt t~kes time aw~y fro~ processing the lsdder program and therefore the interrupt rate parameter, which is a multiple of the 2.5MS interr~pt interval, should be as high a~ possible. This i5 neces8ary to allow time between interrupts to process ladder pro8ram and communication.
5ub-Algorithm Control Parameter Registers (~e~i~ter Blook Allo~ation) The first thirteen re~i~ters oP each group is used to pro~ide operation data to the algorithm while the last 2 provide output or status. Note: The D prefix on ~ollowing block of 15 regi~ter indic~tes relatiYe order within blook--not actual register number.
Each re~i~ter contain~ l6 ~its.
Eaoh o~ the re~i ters Dl-D7 will now : 20 be described starting with register D1.

Reg ster~ Definition Desoription D1 Control Selection of type of operation desired Bit On Po9 ~ 1 ) Turn on with : po~ition-priority 4 On ~em (2) Turn on with input-priority 5 ; 30 On Time ~3) Delay turn on .

~ 35 : . , .

3~

~4) Not used Off POBS ( 5 ) Turn o~ with po~ition-priority l Off ~em t6) Turn OIf with input-priority 2 Off Time (7) ~elay Turn Off-priority 3 ~8) Not used O~f Rem invert (9~ Invert Turn off input 0-normal input=0 to turn o~f l-invert input-l to turn off ~10) not used (l1) not used S~ip ~: ou~put (12) Hold output in present Qtate. Reset~
register Dl4 Bit 9 : Reset ~l3) Hold Time Delay reset and output in ~ : 25 Tim Dly present state `-~ : Di~able Output (14) Force Output off.
Register D15 retains : ~ state. Sub-algorith~
i~ aoti~e.

Skip (15) Skip sub-,, .

, g algorithm. ~esets Functn Register D15 Bit 9 while balance of D15 retain ~tate. Sub-al~orith~ state is retained.
Exit (16) ~xit interrupt Al~orithm operation until next interrupt.
Algorm All re~aining sub-algor~thms retain last state.

A description of re8ister~ D2 through D14 is as follows:
Register Def DesQri~tion ; 15 D2 On Pos Po~ition on setpoint ~ with range 0-9999 :
S . P
D3 On ~em "On Rem" (~e~oté) register Pointr pointer-valid register iB any as~igned internal register or within Input Regi~ter block of up to 8 ; Regi~ter assigned in Enable Algorithm Run~.
A zero in regi~ter defaults to "ON REM"
25~ open (o) condition D4 On REM "On REM" regi~ter Ma~k mask-points to ~pecific or combination o~ input bits required to be all "on" (1) to satiYfy the ~EM "on"
condition. I~ mask=0 , 3 ~ ~

the "C)N REM" i 8 oonsiclered to be open or oPf ~ol D5 Off Pos Position o~f ~etpoint Sp with ran8e 0-9~99 D6 O~f REM Off ~e~m regi~ter Pointer pointer va1id register is sa~e a~ ~or D3 D7 Off ~EM O~f REM re~ister mask Mask point~ to specific or combination of input bits required to be all one l1) ~Normal~
or off (O) linvertedl.
If not true or mask i~
zero, command to turn on is reset.
D8 REM Ebl REM enable regi3ter pointer-must be valid : register Point ~ame as regi~ter D3. I~ zero, :: Rem function i~
~: enabled, :: : D9 R~M Ebl ~EM enable register j;~ 20 ma~k points to peoific or combination o~ bits required to be all on : (1). If not true, te~t of "ON REM" and "OFF REM" is bypas~ed and command (CMD) : : remains a~ is--on or off. If zero, REM
function is enab1ed.
D10 Output Output re~ister point-:~ Point valid regi~ter ia any assi~ned internal prQ~essor register or :! within a~signed output ~. 35 ~ 3 ~

regi3ter blook in ~nable Algorithm Rung.
A zero pointer cau~es no output function.
D11 Output Outpoint register mask Mask pvints to ~peoific or several outputs to be controlled from Yub-algorithm. If zero, no output action take~
plaoe.
D12 On Tim On Time Delay 1 Sp Setpoint-zero to 32767 decim~l in interrupt rate parameter time~

2.6 M5EC incre~ents per count. Delay~, in turn on of Internal Output (OUT AUX~.
: : D13 Of~ Ti~ Off Time Dsla~ ;
Sp Setpoint-sams a~ ~D12 except delays Turn Of~
of internal output - ~out aux) D14 Curtim Current ON/OFF timer count reaaining statu~
D15 Work : Sub-algorith~ Qtatus re~i~ter :~ 25 A definition of each of the 16 bit~
in the ~15 ~tatus regi~ter i8 as follo~s:
Bit CAM ~1) C~m on (1~ or off ~O) 3 CAMT (2) CAM on transitional. "ON" ~1) For one interrupt on O to 1 chan~e .

:; . , ~3~29 of c8~ ~Bit 1~
~EM ~3) On Rem condition3 determined by Rem Pointer and ~a~h. are true ~1) or fal~e (O) REMT ~4) On Rem transitional. "0~
for one interrupt o~l O to 1 change of REM (Bit 3) CMD (5) Command On ll~ or Off (0~ to internal output auxiliar~ (outaux) either direotly or after time delay.
~: lO Turned on(1) with either CAMT ~Bit .
2) or ~EMT (Bit 4) and turned oEf t) with either OAM off (BIT 1), OFF
REM or delay a~ ~elected Off Tim (6) Off timer enable i8 on ~1) when timin~ or tlmed out and off (O) when ~ Enable timers held re~et ~D1-13=1~ or CMD
.~ 15 i8 on.
. ~ On Tim ( 7 ) On timer enable i8 on (1) when ~ timing or timed out and off (0~ when !: Enable ti~er~ held reset (D1 13=1) or CMD
o~f.
Outaux (8) Output auxili~ry follow~ the CMD
~: (bit 5) plu~ delay~ if used. Its tate i~ loaded into output~s) as directed by output pointer and mask unles~ skip outp~ts (D17-12) i8 ON(l) or 1 t scan (D15-9) i8 off tt or output di~able ~D1-14) is on (1).
l~t scan (9) 1st scan completed ~ i8 turned ON when~um algorith~ has been executed. Turned o~P ~0) if ~ub-algorithm ~kipped (D1-15-1~ or output skipped lD1-~2-1). Cau~es output to be held in pre~nt 3tate : until ~econd interrupt cycle after l~t scan ~lag turned off (O) (10-16) Not used.

; 35 .

~ 3 ~

.

There ~re two bits available in Control Re8ister D1 to either free~e the state of the sub-al~orith~ (Bit 15) or freez~ the stAte of the output only ~Bit 12~ while allowing the ~ub-alxorith~ to respond to condition~. After either o~ these bits have been enabled and then di~abled, the sub-algorithm will be active or one interrupt without affecting output. The control o~ the output by the sub-~lgorithm i8 disabled until the tatu~ re~i~ter D15 bit 9 (1st scan) is on.
:~
Sub-al~orith~ Operation Refer to the flow diagra~ o~
~ FIGS. 4A ~nd 4B to co~ ider the ~ub-algorithm : operation.~ The ~te~ are as follows:
: 1. Determine if aub-algorithm i~
to be skipped from atate of D1-15. Skip if "on".
2. Determine if CAM (D15-1) crested by ON snd OFF position Zs etpointa ~nd pC~itlOn input i~
~; "on" or -toff". Al~o whether CAM is transitionin~ Prom Of~
to On (DlS 2-1).
3. Determine if "on re~ote" input 3 is "on" or "off" tD15-3) and whether transition from t-off"

'. `

' ,~
. . . . .

~ 3 ~

to "on" ha~ oc~urred.
(D15-4=1) Assl~mes "on re~ote"
open if "on re~30te" pointer~
and/or mask is zero. Inpuk~
may be any prooe3~0r internal re~i~ter bit.

4. Determine if co~snd ~D15~5~ i8 "on" or "off" I~D1~-5) with off conditi on~ checked before lo pro¢eeding to on oondition~.
A~sume~ all enabling remote~-l if remote enable input pointer and/or ma~k i~ zero. A~3ume~
OF~ and ON conditions aB not true iP as~ociated input pointer and/or ma~k i8 ~ero cau~in~ turn off and not turn on oP command. Note th~t : com~and i8 turned on only with cam or on remote tran~ition.
. 5. Determine if output auxiliary (D15-8) is "on" vr "oPf"
directly or through time delay path. Ig used the time delay i8 enabled pre~et and decremented on fir~t pa~s ~: throu~h path and deore~ented on sub~equent interrupts until æero. Enable Ti~e Del~y Re~et (D1 13) will hold time pre~et.
Note: Gurrent ti~e ~D14) i~

3 ~ 9 only updated with re~aining time while decrementing which i~ disabled by time delay reset enabled.
6. Deter~ine i~ output iS "on", "of~" or byp~s~ed. No action : taken i~ either output pointer or ma~k i8 zero.

; : 10 l~orithm Execution Time Executing the SP1 ti~d interrupt algorithm i~ ths highe~t task of the processor. Once ~tarted, the al~orith~ canno~
be interrupted find all other proce~sor task~
are ~uspended.
- Accordingly~ to allow ~or proper operation of the proce~or, the algorithm ~u~t - be limited to allow for ~ufficient time during ~ each 2.5M~clock pulse to handle communication ~-':~ 20 ta~ks, proceY~or housekeepin~ ta~k~ and: execute ladder. The maximum penalty for u9e of the ~aximum algorithm time will be a scan delay of lo times nor~al for repetitive interrupts at 2.5MS rate~
2~ For example; the overall ta3k time table i~:
Co~munication~ - 200 U9 Hinimum ~ou~ekeepin~ - 100 U~ Mini~um :
hadder ~ 100 Us Minimu~
Algorithm - 100 U~ Maximu~
~:
~ ~ .

:' ,. '"' To deter~ine the length o~ th~
algorithm, the time ~or each cxeoution o~ the sub-~lgorith~ progr~mmed i8 multiplied by the nu~ber of each type u~ed and sum the totals.
S The ~sximum li~it is 2100 U~.

Al~orithm_Control P~rameter Regi ter Chan~s The~e re~i ters are not changed while interrupt and ~ub-al~orithm~ are : 10 actively controlling the output.There are two bit~ svailable in Control Register D1 to either freeze the state of the sub-al~orithm (bit 15~ or freeze the state of the output only (Bit 12) while allowing the ~ub-~lgorithm to respond to ~ condition~. After either of the~e bit~ have :~ been enabled and then di~abled, the sub-al~orithm wil} be active for one interrupt ~ without a~fecting output. The control of the : : 20 output by the Yub-algorithm i~ di abled until the ~tatus regi~ter D15 bit 9 ( 1Qt scan) i~
on.
~ The above method of removing the : : output from sub-algorithm control c~n al~o be used to provide manual control of the output to the ladder pro~ra~.
: ~ : :
The invention thu~ provide~ a PLC
oontrol syste~ for a h1gh-speed preB8 utilizing a pres~ algorithm, which algorithm : inoludes a number o~ executions of a 3ub-:

, . . ., ~
. .

., ~ 3 ~ 2 ~

orithm, which enables preoise, oo~trolled high-speed operation of the pre~, While this inventioll i8 ~uaceptible of embodiment in many di~ferent ~orms, there i~ ~hown in the dra~ings and will herein be described in detail a preferred em~odiment of the invention with the understanding that the present di~olosure is to be oonsidered as an exemplification o~ the principle~ o~ the : 10 in~ention and i8 not intended to limit the broad aspeot o~ the invention to embodiment illustrated.
While the ~peoific *mbodiment3 have been illustrated and desoribed, numerou~
: 15 modi~ications come to mind without ~ignificantly departin~ ~ro~ the ~pirit of the invention and the ~cope of proteotion is only limited by the soope o~ the ~coomp~nying ,~ ~ Claims.
` ~ 20 ~' ~ 25 ::

: 30 :

~ 35

Claims (10)

1. A programmable logic controller (PLC) based system for controlling a high-speed machine operating in cycle-type modes comprising in combination:
at lea t one machine having a plurality of components having at least two status states;
an execution memory, machine control algorithm in said executive memory, a control processor for coordinating operation of the system;
a communication connection between the machine and said control processor;
said control processor also performing communication between said control processor and said machine; and, a scan processor for performing computation of desired output states and data values based upon the inputs received from the machine.

2. A PLC as in Claim 1, wherein the algorithm is in the executive instructions of the scan processor.

3. A PLC as in Claim 1, wherein the algorithm furnctions to provide periodic interrupts.

4. A PLC as in Claim 1, wherein the algorithm comprises a multiple function block software.

5. A PLC as in claim 1, wherein the algorithm comprises multiple executions of substantially the same sub-algorithm.

6. A PLC as in Claim 1, further including an image memory for receiving and storing internal inputs from the control processor and external inputs and outputs and data, and said scan processor having direct access to said image memory and performing computation on the inputs and data in said image memory.

7. A PLC a in Claim 1, further including a user memory for containing the user program, and said user memory connecting directly to said scan processor to control the operation and sequence of said scan processor in accordance with the user program.

8. A PLC as in Claim 1, wherein the scan cycle is 2.5 milliseconds and wherein the image memory is updated every scan cycle.

9. A PLC as in Claim 1, wherein the control processor provides control commands to said scan processor and receive inputs from said scan processor for communicating with the machine.

10. A PLC as in Claim 1, enabling the operation of a punch press at 120 strokes per minute.