CA1310060C - Electrostatic discharge protection network for large area transducer arrays - Google Patents
Electrostatic discharge protection network for large area transducer arraysInfo
- Publication number
- CA1310060C CA1310060C CA000545137A CA545137A CA1310060C CA 1310060 C CA1310060 C CA 1310060C CA 000545137 A CA000545137 A CA 000545137A CA 545137 A CA545137 A CA 545137A CA 1310060 C CA1310060 C CA 1310060C
- Authority
- CA
- Canada
- Prior art keywords
- electrostatic discharge
- thin film
- protection network
- large area
- transducer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S345/00—Computer graphics processing and selective visual display systems
- Y10S345/904—Display with fail/safe testing feature
Abstract
ABSTRACT OF THE DISCLOSURE
An electrostatic discharge protection network for large area transducerarrays in which each transducer has associated therewith an addressing circuit for changing the state of the transducer element. Each addressing circuit includes at least one thin film transistor having a resistive path provided between the thin film transistor gate electrode and one or both of the transistor's other two terminal electrodes in order to provide current leakage paths for equalizing the potential between the gate electrode and the other two terminals during an electrostatic discharge.
An electrostatic discharge protection network for large area transducerarrays in which each transducer has associated therewith an addressing circuit for changing the state of the transducer element. Each addressing circuit includes at least one thin film transistor having a resistive path provided between the thin film transistor gate electrode and one or both of the transistor's other two terminal electrodes in order to provide current leakage paths for equalizing the potential between the gate electrode and the other two terminals during an electrostatic discharge.
Description
13~0~0 - ELEGTROSTATIC DISCHARGE PROTECTION NETWORK FOR
LARGE AREA TRANSDUCE~ ARRAYS
Field of the Invention This invention relates generally to techniques and devices for protecting large area transducer arrays, controlled by thin film transistor circuits, from undesired high voltage effects resulting from electrostatic discharges and, in 10 particular, to equalizing the potential over all elements of the array during an electrostatic discharge event.
Background of the Invention 15 It is well known in the electronics industry that static electricity can cause severe damage to IC devices. The generation of the electrostatic charge results from the transfer of electrons within a body (polarization) or the transfer of electrons from one body to another (conductive charging), and is usually due to the interaction of bodies. The magnitude of the charge is 20 primarily dependent upon the size, shape, composition and electrical properties of the substances which make up the bodies. The prime sources of electrostatic charge encountered in a manufacturing facility are essentially the interaction of personnel with insulators. Typically, walking across a carpet, or over a vinyl floor, or the handling, rubbing or separating 25 various materials generates electrostatic charges which are transmitted to the person and causes that person to be charged. When the charged person handles or comes close to a susceptible electronic part, that part can be damaged by direct discharge from the contact or by being subjected to the electrostatic field surrounding the charged person. The generation of 5 15,000 volts between unprotected workers and electronic parts is not unusual in a typical manufacturing facility.
In general, voltage sensitive parts fail due to dielectric breakdown of insulating layers. In a transistor (MOSFET or TE`T) dielectric breakdown 10 usually occurs across the gate insulator. As feature sizes are reduced, in order to increase the number of devices upon a single substrate, this scaling makes the transistor more vulnerable to damage by smaller electrostatic discharges. These discharges may cause catastrophic failure or may shift the transistor operating characteristics out of specification. Failure results 15 when the dielectric strength is exceeded, causing insulator punchthrough and leaving a low resistance short. The high potential difference across the gate dielectric, caùsed by the presence of static charge, results in charges being trapped in the dielectric and shielding the correct operational electric field from the gate.
Numerous electrostatic discharge protection circuits have been developed to protect the transistor gate dielectric against these high voltage effects.
These circuits usually are connected directly to the input contact pads and serve to shunt away or reduce high voltage pulses to a value below the 25 critically disruptive valùe, while not interfering with device electrical performance. Usually these protection networks include diodes and other elements for which IC chip real estate must be allocated.
It is an object of an aspect of the present invention to provide a simple, low cost, electrostatic discharge protection network for large area thin film transducer arrays wherein each transducer has associated therewith an addressing circuit including at least one thin film transistor.
It is an object of an aspect of the present invention to provide paths for potential equalization of all elements on the array in response to spurious electrostatic discharges.
SUN~aRY OF THE INVENTION
An aspect of the invention is as follows:
An electrostatic discharge protection network for a large area transducer array, said array including a substrate on which is formed a plurality of thin film transducer elements and a thin film addressing circuit associated with each transducer element for changing the state of said transducer element, each of said addressing circuits including at least one thin film amorphous silicon transistor having a source terminal electrode and a drain terminal electrode spaced from one another and contiguous to a semiconductor layer, a gate electrode spaced from said semiconductor layer by a gate dielectric layer and located so as to control the current flow from said source terminal electrode to said drain terminal electrode, through said semiconductor layer, and a plurality of input contact pads for .~..~
131~
receiving external signals, connected to said addressing circuit, for controlling the state of said transducer elements said protection network including a strip of n+ amorphous silicon resistive material extending across all of said input contact pads, and resistor means comprising inter contact pad portions of said strip of resistive material for providing current leakage paths to e~ualize the potential across all of said gate dielectrics during an electrostatic discharge and wherein said resistor means as connected to said circuits and functioning to provide current leakage paths does not affect the normal operation of said thin film transistors.
By way of added explanation, the foregoing objects may be achieved, in one form, by providing, upon an insulating substrate, a large area thin film transducer array in which each transducer has associated therewith an addressing circuit for changing the state of the transducer element, and wherein each addressing circuit includes at least one thin film transistor having a resistive path provided between the thin film transistor gate electrode and one or both of the transistor's other two terminal electrodes in order to provide current leakage paths for equalizing the potential between the gate electrode and the other two terminals during an electrostatic discharge. The ohmic value of the resistive path is selected to be large enough so that current leakage between the gate electrode and 131 B~
, the other two terminals does not affect the normal operation of the thin film transis~or.
Brief Description of Drawings The advantages of the present invention will be understood by those skilled in the art through the following detailed description when taken in conjunction with the accompanying drawingst in which:
10 Figure 1 shows a side elevation view of a thin fillm transistor, Figure 2a schematically illustrates a thin film transistor wherein the gate electrode is connected to both the source and drain terminal electrodes by resistors, Figure 2b schematically illustrates a thin film transistor wherein the gate electrode is connected to the drain terminal electrode by a resistor, Figure 2c schematically illustrates a thin film transistor wherein the gate 20 electrode is connected to the source terminal electrode by a resistor, Figure 3 illustrates one embodiment of this invention on a large area one dimensional transducer array, . " .
~3~6~
Figure~ illustrates another embodiment of this invention on a large area one dimensional transducer array, 5 Figure 5a illustrates this invention being practiced on a large area two dimensional transducer array, and Figure 5b illustrates the cross section of a liquid crystal display controlled by the transducer array of Figure 5a.
Detailed Description of the Illustrated Embodiments Turning now to the drawings there is illustrated the structure of a well known amorphous silicon (a-Si:H~ thin film transistor (TET) 10, the so-called 15 inverted structure. It comprises a substrate 12 made of glass, ceramic, or any other insulating material that remains adequately smooth and flat in the common amorphous silicon TFT processing temperature range (<350C); a gate electrode 14, typically 500 to 1000 angstroms thick formed by a thin layer of Cr, NiCr or other suitable material, located on the substrate; a gate 20 dielectric 16, typically a silicon nitride layer several thousand angstroms thick, overlying the gate electrode; an a-Si:H charge transport layer 18 a few hundred to a few thousand angstroms thick; terminal electrodes formed of a thin n~ a-Si:H layer 20 and an Al contact layer 22 about 1 micron thick formed as the source 24 and the drain 26; and a second silicon nitride layer 1 3 ~
28 deposited over the a-Si:H layer in the channel region for passivation purposes.
As between source 24 and drain 26, a current leakage path through the a-5 Si:H semiconductor layer 18 exists when the gate of the transistor is not connected to any voltage source, i.e., when the gate electrode is floating.
Therefore, during an electrostatic discharge to either the source electrode or the drain electrode, the leakage path would allow the charge to move to the other electrode, thus equalizing their potentials. Since virtually no current 10 can flow across the gate dielectric, electrostatic discharge to the gate electrode could cause a large amount of charge to accumulate on the gate electrode, thus generating an extremely large potential difference across the gate dielectric between the gate electrode and either or both of the source electrode and drain electrode. This is particularly true when the gate 16 electrode is floating and the accumulated electrostatic charges cannot be drained away. Then the extremely large potential difference appearing across the gate dielectric can cause the damage described.
To substantially minimize electrostatic discharge damage to the transistor 20 10, it is proposed to establish a high resistance current path connecting thegatel4 to the source 24 and/or the drain 26 by means of a resistor 30. The alternative configurations are illustrated in Figures 2a, 2b and 2c. These allow the potential to be equalized across the gate dielectric 16. In any of thethree cases care must be taken in selecting the proper value for the resistor.
25 By selecting a resistor whose value is too low the resistor pair (Figure 2a) " ~
could thwart the proper operation of the TFI by bypassing the semiconductor layer.-Alternatively, if the ohmic value is too high, the resistor will not dissipate the electrostatic discharge fast enough to prevent damage to the gate dielectric. As a general rule, the value of the resistor should be such 5 that the leakage current therethrough does not af~ect the proper operation of the transducer element. The proper choice of the resistance value depends upon the particular circuitry in each application.
Turning to Figure 3 there is illustrated a one dimensional transducer array 10 32 in the form of a marking head of the type fully disclosed and described inUS 4,584,492. It includes a large area glass substrate 34 which has been typically made eleven inches by three-quarters inch having thereon, along one edge, marking electrodes 36, and along the opposite edge, input contact pads 38 (more accurately illustrated in Figure 4, and only schematically 15 represented as bus lines in Figure 3). In use, the contact pads are connectedto receive marking information from external IC drivers 40. By means of a multiplexed addressing arrangement, 104 input contact pads comprising 64 data lines 42 and 40 gate address lines 44 are sufficient for controlling 2560 marking electodes. Each of the gate address lines controls a section of 64 20 l~ rs 10, of the type described above. All of the elements, i.e. marking elec'crodes, TFTsj address lines, data lines and input contact pads, are integrally formed on the insulating substrate by thin film fabricating techniques.
.
Whenthe array is not connected in a printing machine and is floating electrically, as when it is being handled during testing, sorting, inspecting, packaging and being installed in a printing machine, it is likely to make 5 contact with a body which carries an electrostatic charge. The electrostatic charge which unsuspectedly has accumulated on an operator may be released to the array and may destroy or damage one or more of the thin film transistors, in the manner described above.
10 In order to protect each TFT, a resistor 30 is shown connected between each gate electrode 14 and each source electrode 24. Depending upon the function and arrangement of the transducer array it may be more desirable to connect the gate electrode to either the drain electrode or to both the source electrodeand the drain electrode, as illustrated in Figure 2. By convention herein, the 16 terminal of the TFT which is connected directly to the transducer element is identified as the drain electrode. In the transducer array of Figure 3 wherein the transducers are marking electrodes 36 of the printer device described in U.S. 4,584,592 and each marking electrode must hold the charge deposited thereon for an entire line time, care must be taken to avoid establishing any 20 current leakage path between the drain electrode and the gate electrode.
Therefore, it would be undesirable to connect the drain electrode to the gate electrode with resistor 30.
Although the Figure 3 embodiment will operate satisfactorily to protect the 25 TFTs from electrostatic discharge damage, it is not the optimum solution.
1310~0 This is because the resistors 30 take up valuable real estate which will be at a premium when fabricating higher resolution marking head arrays. Also, as the marking head arrays comprise more complex drive circuits, such as those envisioned for multifunction operation, these drive circuits will include 5 several transistors associated with each marking electrode, and it would become burdensome to provide a resistor for each transistor.
Therefore, rather than practicing this invention as shown in the Figure 3 embodiment, a much simpler approach is shown in the embodiment of Figure 10 4. The same result may be achieved by connecting all of the input contact pads 38 extending along one edge of the marking head array 32 with a resistive stripe 46 coextensive with the line of pads and in electrical contact with them so as to form inter-contact pad resistors. This results in connecting all the data lines 42 and all the gate address lines 44 so that 15 electrostatic charge accumulating on any one, or more, of these lines will leak rapidly throughout the array and will equalize the potential on all elements thereon.
The two major advantages of this configuration are: first, the resistive stripe 20 46 may be fabricated simultaneously with the deposition of the n+ a-Si:H
source and drain layers; and, second, that the resistive stripe is located on the substrate at a location where it will not compete for real estate. It shouldbe understood that the resistive stripe may be fabricated of lightly doped or undoped a-Si:H if desired, in order to be consistent with, and to be deposited 25 simultaneously with, other device layers. N+ a-Si:H is particularly ~ 3 ~
appealing because its resistivity is approximately 102 ohm-cm and in thin film form it is not uncommon to make resistors in the range of 107 to 109 ohms.
Practical protective networks may be made with a resistive strip whose inter-contact pad resistance is in the range of 5 to 100 mega-ohms. The resistive value of the inter-contact pad resistors must be selected to be low enough to leak charge at a speed to prevent the undesirable electrostatic discharge effects and high enough so that during operation the voltage level on one contact pad will not be significantly affected by voltage levels on its neighboring contact pads. Since the external IC chips used to drive the marking array have a relatively low output impedance (on the order of several kilo-ohms), there will be no significant cross-talk between adjacent contact pads at different voltages when adjacent contact pads are connected together by these large inter-contact pad resistors (on the order of several mega-ohms). Typically, the resistance value should be greater than about ten times the output impedance of the external drive circuit.
In U.S. Patent No. 4,719,481, issued January 12, 1988 ~H.C. Tuan and M.J. Thompson) there is disclosed transducer arrays in which each marking electrode transducer element is controlled by an addressing circuit comprising two thin film transistors. The present invention, applied to that array, would protect both TFTs from electrical discharges.
`~
~ 3 ~
The same approach to a protective network may also be used in the two dimensional transducer array 48, shown in Figures 5a ant ~b. In this embodiment, an orthogonal arrangement of display electrodes 50 is 5 deposited upon a large insulating substrate 52 so as to control the orientation of liquid crystal material 64 in each pixel of a display panel 56. The state of each display electrode is controlled by a TE~ 58. Each transistor receives a data signal along a data line 60, connected to its source electrode 62, and an address signal along gate line 64 connected to its gate electrode 66. When 10 the gate voltage turns the transistor ON current flows from the source electrode 62 to the drain electrode 68 and then to the display electode 50. All the source lines (Sl to SN) and all the gates lines (G1 to GN) are shown connected together with suitable resistors, for example, n+ a-Si:H resistive stripes 70. E~y following the principles of resistive value selection set forth 15 above, a protective network will be effected which will protect the gate dielectrics of all the switching transistors from electrostatic discharge but will have no effect on normal operation.
It should be understood that the present disclosure has been made only by 20 W8y of example and that numerous changes in details of construction and the combination and arrangement of parts may be resorted to without departing from the true spirit and the scope of the invention as hereinafter claimed.
LARGE AREA TRANSDUCE~ ARRAYS
Field of the Invention This invention relates generally to techniques and devices for protecting large area transducer arrays, controlled by thin film transistor circuits, from undesired high voltage effects resulting from electrostatic discharges and, in 10 particular, to equalizing the potential over all elements of the array during an electrostatic discharge event.
Background of the Invention 15 It is well known in the electronics industry that static electricity can cause severe damage to IC devices. The generation of the electrostatic charge results from the transfer of electrons within a body (polarization) or the transfer of electrons from one body to another (conductive charging), and is usually due to the interaction of bodies. The magnitude of the charge is 20 primarily dependent upon the size, shape, composition and electrical properties of the substances which make up the bodies. The prime sources of electrostatic charge encountered in a manufacturing facility are essentially the interaction of personnel with insulators. Typically, walking across a carpet, or over a vinyl floor, or the handling, rubbing or separating 25 various materials generates electrostatic charges which are transmitted to the person and causes that person to be charged. When the charged person handles or comes close to a susceptible electronic part, that part can be damaged by direct discharge from the contact or by being subjected to the electrostatic field surrounding the charged person. The generation of 5 15,000 volts between unprotected workers and electronic parts is not unusual in a typical manufacturing facility.
In general, voltage sensitive parts fail due to dielectric breakdown of insulating layers. In a transistor (MOSFET or TE`T) dielectric breakdown 10 usually occurs across the gate insulator. As feature sizes are reduced, in order to increase the number of devices upon a single substrate, this scaling makes the transistor more vulnerable to damage by smaller electrostatic discharges. These discharges may cause catastrophic failure or may shift the transistor operating characteristics out of specification. Failure results 15 when the dielectric strength is exceeded, causing insulator punchthrough and leaving a low resistance short. The high potential difference across the gate dielectric, caùsed by the presence of static charge, results in charges being trapped in the dielectric and shielding the correct operational electric field from the gate.
Numerous electrostatic discharge protection circuits have been developed to protect the transistor gate dielectric against these high voltage effects.
These circuits usually are connected directly to the input contact pads and serve to shunt away or reduce high voltage pulses to a value below the 25 critically disruptive valùe, while not interfering with device electrical performance. Usually these protection networks include diodes and other elements for which IC chip real estate must be allocated.
It is an object of an aspect of the present invention to provide a simple, low cost, electrostatic discharge protection network for large area thin film transducer arrays wherein each transducer has associated therewith an addressing circuit including at least one thin film transistor.
It is an object of an aspect of the present invention to provide paths for potential equalization of all elements on the array in response to spurious electrostatic discharges.
SUN~aRY OF THE INVENTION
An aspect of the invention is as follows:
An electrostatic discharge protection network for a large area transducer array, said array including a substrate on which is formed a plurality of thin film transducer elements and a thin film addressing circuit associated with each transducer element for changing the state of said transducer element, each of said addressing circuits including at least one thin film amorphous silicon transistor having a source terminal electrode and a drain terminal electrode spaced from one another and contiguous to a semiconductor layer, a gate electrode spaced from said semiconductor layer by a gate dielectric layer and located so as to control the current flow from said source terminal electrode to said drain terminal electrode, through said semiconductor layer, and a plurality of input contact pads for .~..~
131~
receiving external signals, connected to said addressing circuit, for controlling the state of said transducer elements said protection network including a strip of n+ amorphous silicon resistive material extending across all of said input contact pads, and resistor means comprising inter contact pad portions of said strip of resistive material for providing current leakage paths to e~ualize the potential across all of said gate dielectrics during an electrostatic discharge and wherein said resistor means as connected to said circuits and functioning to provide current leakage paths does not affect the normal operation of said thin film transistors.
By way of added explanation, the foregoing objects may be achieved, in one form, by providing, upon an insulating substrate, a large area thin film transducer array in which each transducer has associated therewith an addressing circuit for changing the state of the transducer element, and wherein each addressing circuit includes at least one thin film transistor having a resistive path provided between the thin film transistor gate electrode and one or both of the transistor's other two terminal electrodes in order to provide current leakage paths for equalizing the potential between the gate electrode and the other two terminals during an electrostatic discharge. The ohmic value of the resistive path is selected to be large enough so that current leakage between the gate electrode and 131 B~
, the other two terminals does not affect the normal operation of the thin film transis~or.
Brief Description of Drawings The advantages of the present invention will be understood by those skilled in the art through the following detailed description when taken in conjunction with the accompanying drawingst in which:
10 Figure 1 shows a side elevation view of a thin fillm transistor, Figure 2a schematically illustrates a thin film transistor wherein the gate electrode is connected to both the source and drain terminal electrodes by resistors, Figure 2b schematically illustrates a thin film transistor wherein the gate electrode is connected to the drain terminal electrode by a resistor, Figure 2c schematically illustrates a thin film transistor wherein the gate 20 electrode is connected to the source terminal electrode by a resistor, Figure 3 illustrates one embodiment of this invention on a large area one dimensional transducer array, . " .
~3~6~
Figure~ illustrates another embodiment of this invention on a large area one dimensional transducer array, 5 Figure 5a illustrates this invention being practiced on a large area two dimensional transducer array, and Figure 5b illustrates the cross section of a liquid crystal display controlled by the transducer array of Figure 5a.
Detailed Description of the Illustrated Embodiments Turning now to the drawings there is illustrated the structure of a well known amorphous silicon (a-Si:H~ thin film transistor (TET) 10, the so-called 15 inverted structure. It comprises a substrate 12 made of glass, ceramic, or any other insulating material that remains adequately smooth and flat in the common amorphous silicon TFT processing temperature range (<350C); a gate electrode 14, typically 500 to 1000 angstroms thick formed by a thin layer of Cr, NiCr or other suitable material, located on the substrate; a gate 20 dielectric 16, typically a silicon nitride layer several thousand angstroms thick, overlying the gate electrode; an a-Si:H charge transport layer 18 a few hundred to a few thousand angstroms thick; terminal electrodes formed of a thin n~ a-Si:H layer 20 and an Al contact layer 22 about 1 micron thick formed as the source 24 and the drain 26; and a second silicon nitride layer 1 3 ~
28 deposited over the a-Si:H layer in the channel region for passivation purposes.
As between source 24 and drain 26, a current leakage path through the a-5 Si:H semiconductor layer 18 exists when the gate of the transistor is not connected to any voltage source, i.e., when the gate electrode is floating.
Therefore, during an electrostatic discharge to either the source electrode or the drain electrode, the leakage path would allow the charge to move to the other electrode, thus equalizing their potentials. Since virtually no current 10 can flow across the gate dielectric, electrostatic discharge to the gate electrode could cause a large amount of charge to accumulate on the gate electrode, thus generating an extremely large potential difference across the gate dielectric between the gate electrode and either or both of the source electrode and drain electrode. This is particularly true when the gate 16 electrode is floating and the accumulated electrostatic charges cannot be drained away. Then the extremely large potential difference appearing across the gate dielectric can cause the damage described.
To substantially minimize electrostatic discharge damage to the transistor 20 10, it is proposed to establish a high resistance current path connecting thegatel4 to the source 24 and/or the drain 26 by means of a resistor 30. The alternative configurations are illustrated in Figures 2a, 2b and 2c. These allow the potential to be equalized across the gate dielectric 16. In any of thethree cases care must be taken in selecting the proper value for the resistor.
25 By selecting a resistor whose value is too low the resistor pair (Figure 2a) " ~
could thwart the proper operation of the TFI by bypassing the semiconductor layer.-Alternatively, if the ohmic value is too high, the resistor will not dissipate the electrostatic discharge fast enough to prevent damage to the gate dielectric. As a general rule, the value of the resistor should be such 5 that the leakage current therethrough does not af~ect the proper operation of the transducer element. The proper choice of the resistance value depends upon the particular circuitry in each application.
Turning to Figure 3 there is illustrated a one dimensional transducer array 10 32 in the form of a marking head of the type fully disclosed and described inUS 4,584,492. It includes a large area glass substrate 34 which has been typically made eleven inches by three-quarters inch having thereon, along one edge, marking electrodes 36, and along the opposite edge, input contact pads 38 (more accurately illustrated in Figure 4, and only schematically 15 represented as bus lines in Figure 3). In use, the contact pads are connectedto receive marking information from external IC drivers 40. By means of a multiplexed addressing arrangement, 104 input contact pads comprising 64 data lines 42 and 40 gate address lines 44 are sufficient for controlling 2560 marking electodes. Each of the gate address lines controls a section of 64 20 l~ rs 10, of the type described above. All of the elements, i.e. marking elec'crodes, TFTsj address lines, data lines and input contact pads, are integrally formed on the insulating substrate by thin film fabricating techniques.
.
Whenthe array is not connected in a printing machine and is floating electrically, as when it is being handled during testing, sorting, inspecting, packaging and being installed in a printing machine, it is likely to make 5 contact with a body which carries an electrostatic charge. The electrostatic charge which unsuspectedly has accumulated on an operator may be released to the array and may destroy or damage one or more of the thin film transistors, in the manner described above.
10 In order to protect each TFT, a resistor 30 is shown connected between each gate electrode 14 and each source electrode 24. Depending upon the function and arrangement of the transducer array it may be more desirable to connect the gate electrode to either the drain electrode or to both the source electrodeand the drain electrode, as illustrated in Figure 2. By convention herein, the 16 terminal of the TFT which is connected directly to the transducer element is identified as the drain electrode. In the transducer array of Figure 3 wherein the transducers are marking electrodes 36 of the printer device described in U.S. 4,584,592 and each marking electrode must hold the charge deposited thereon for an entire line time, care must be taken to avoid establishing any 20 current leakage path between the drain electrode and the gate electrode.
Therefore, it would be undesirable to connect the drain electrode to the gate electrode with resistor 30.
Although the Figure 3 embodiment will operate satisfactorily to protect the 25 TFTs from electrostatic discharge damage, it is not the optimum solution.
1310~0 This is because the resistors 30 take up valuable real estate which will be at a premium when fabricating higher resolution marking head arrays. Also, as the marking head arrays comprise more complex drive circuits, such as those envisioned for multifunction operation, these drive circuits will include 5 several transistors associated with each marking electrode, and it would become burdensome to provide a resistor for each transistor.
Therefore, rather than practicing this invention as shown in the Figure 3 embodiment, a much simpler approach is shown in the embodiment of Figure 10 4. The same result may be achieved by connecting all of the input contact pads 38 extending along one edge of the marking head array 32 with a resistive stripe 46 coextensive with the line of pads and in electrical contact with them so as to form inter-contact pad resistors. This results in connecting all the data lines 42 and all the gate address lines 44 so that 15 electrostatic charge accumulating on any one, or more, of these lines will leak rapidly throughout the array and will equalize the potential on all elements thereon.
The two major advantages of this configuration are: first, the resistive stripe 20 46 may be fabricated simultaneously with the deposition of the n+ a-Si:H
source and drain layers; and, second, that the resistive stripe is located on the substrate at a location where it will not compete for real estate. It shouldbe understood that the resistive stripe may be fabricated of lightly doped or undoped a-Si:H if desired, in order to be consistent with, and to be deposited 25 simultaneously with, other device layers. N+ a-Si:H is particularly ~ 3 ~
appealing because its resistivity is approximately 102 ohm-cm and in thin film form it is not uncommon to make resistors in the range of 107 to 109 ohms.
Practical protective networks may be made with a resistive strip whose inter-contact pad resistance is in the range of 5 to 100 mega-ohms. The resistive value of the inter-contact pad resistors must be selected to be low enough to leak charge at a speed to prevent the undesirable electrostatic discharge effects and high enough so that during operation the voltage level on one contact pad will not be significantly affected by voltage levels on its neighboring contact pads. Since the external IC chips used to drive the marking array have a relatively low output impedance (on the order of several kilo-ohms), there will be no significant cross-talk between adjacent contact pads at different voltages when adjacent contact pads are connected together by these large inter-contact pad resistors (on the order of several mega-ohms). Typically, the resistance value should be greater than about ten times the output impedance of the external drive circuit.
In U.S. Patent No. 4,719,481, issued January 12, 1988 ~H.C. Tuan and M.J. Thompson) there is disclosed transducer arrays in which each marking electrode transducer element is controlled by an addressing circuit comprising two thin film transistors. The present invention, applied to that array, would protect both TFTs from electrical discharges.
`~
~ 3 ~
The same approach to a protective network may also be used in the two dimensional transducer array 48, shown in Figures 5a ant ~b. In this embodiment, an orthogonal arrangement of display electrodes 50 is 5 deposited upon a large insulating substrate 52 so as to control the orientation of liquid crystal material 64 in each pixel of a display panel 56. The state of each display electrode is controlled by a TE~ 58. Each transistor receives a data signal along a data line 60, connected to its source electrode 62, and an address signal along gate line 64 connected to its gate electrode 66. When 10 the gate voltage turns the transistor ON current flows from the source electrode 62 to the drain electrode 68 and then to the display electode 50. All the source lines (Sl to SN) and all the gates lines (G1 to GN) are shown connected together with suitable resistors, for example, n+ a-Si:H resistive stripes 70. E~y following the principles of resistive value selection set forth 15 above, a protective network will be effected which will protect the gate dielectrics of all the switching transistors from electrostatic discharge but will have no effect on normal operation.
It should be understood that the present disclosure has been made only by 20 W8y of example and that numerous changes in details of construction and the combination and arrangement of parts may be resorted to without departing from the true spirit and the scope of the invention as hereinafter claimed.
2~
Claims (3)
1. An electrostatic discharge protection network for a large area transducer array, said array including a substrate on which is formed a plurality of thin film transducer elements and a thin film addressing circuit associated with each transducer element for changing the state of said transducer element, each of said addressing circuits including at least one thin film amorphous silicon transistor having a source terminal electrode and a drain terminal electrode spaced from one another and contiguous to a semiconductor layer, a gate electrode spaced from said semiconductor layer by a gate dielectric layer and located so as to control the current flow from said source terminal electrode to said drain terminal electrode, through said semiconductor layer, and a plurality of input contact pads for receiving external signals, connected to said addressing circuit, for controlling the state of said transducer elements said protection network including a strip of n+ amorphous silicon resistive material extending across all of said input contact pads, and resistor means comprising inter contact pad portions of said strip of resistive material for providing current leakage paths to equalize the potential across all of said gate dielectrics during an electrostatic discharge and wherein said resistor means as connected to said circuits and functioning to provide current leakage paths does not affect the normal operation of said thin film transistors.
2. The electrostatic discharge protection network for a large area transducer array as defined in Claim 1 wherein said transducer elements extend in two directions and comprise display electrodes formed orthogonally over the surface of said substrate.
3. The electrostatic discharge protection network for a large area transducer array as defined in Claim 1 wherein the value of said resistor means is at least an order of magnitude greater than output impedance of an external driver circuit connected to said input contact pads.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/922,603 US4803536A (en) | 1986-10-24 | 1986-10-24 | Electrostatic discharge protection network for large area transducer arrays |
| US922,603 | 1986-10-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1310060C true CA1310060C (en) | 1992-11-10 |
Family
ID=25447304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000545137A Expired - Fee Related CA1310060C (en) | 1986-10-24 | 1987-08-24 | Electrostatic discharge protection network for large area transducer arrays |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4803536A (en) |
| EP (1) | EP0265290A3 (en) |
| JP (1) | JPS63133124A (en) |
| CN (1) | CN1014381B (en) |
| BR (1) | BR8705707A (en) |
| CA (1) | CA1310060C (en) |
| MX (1) | MX159965A (en) |
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| JP2569053B2 (en) * | 1987-06-26 | 1997-01-08 | キヤノン株式会社 | Image sensor |
| JP2786628B2 (en) * | 1987-10-15 | 1998-08-13 | シャープ株式会社 | Liquid crystal panel electrode structure |
| US4960719A (en) * | 1988-02-04 | 1990-10-02 | Seikosha Co., Ltd. | Method for producing amorphous silicon thin film transistor array substrate |
| JPH01217421A (en) * | 1988-02-26 | 1989-08-31 | Seikosha Co Ltd | Amorphous silicon thin film transistor array substrate and its production |
| US5219771A (en) * | 1988-07-30 | 1993-06-15 | Fuji Xerox Co., Ltd. | Method of producing a thin film transistor device |
| JPH02137828A (en) * | 1988-11-18 | 1990-05-28 | Seiko Instr Inc | Input protection device for electrooptical device |
| US5019002A (en) * | 1989-07-12 | 1991-05-28 | Honeywell, Inc. | Method of manufacturing flat panel backplanes including electrostatic discharge prevention and displays made thereby |
| JP2764139B2 (en) * | 1989-10-20 | 1998-06-11 | ホシデン・フィリップス・ディスプレイ株式会社 | Active matrix liquid crystal display |
| KR920008675Y1 (en) * | 1989-12-30 | 1992-12-12 | 삼성전자 주식회사 | Thin film transistor for plate display |
| US5225919A (en) * | 1990-06-21 | 1993-07-06 | Matsushita Electric Industrial Co., Ltd. | Optical modulation element including subelectrodes |
| JPH04120522A (en) * | 1990-09-11 | 1992-04-21 | Matsushita Electric Ind Co Ltd | Liquid crystal display device |
| JP3071851B2 (en) * | 1991-03-25 | 2000-07-31 | 株式会社半導体エネルギー研究所 | Electro-optical device |
| US5220443A (en) * | 1991-04-29 | 1993-06-15 | Nec Corporation | Matrix wiring substrate and active matrix display having non-linear resistance elements for electrostatic discharge protection |
| US6778231B1 (en) | 1991-06-14 | 2004-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical display device |
| US6975296B1 (en) | 1991-06-14 | 2005-12-13 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of driving the same |
| JP3255942B2 (en) * | 1991-06-19 | 2002-02-12 | 株式会社半導体エネルギー研究所 | Method for manufacturing inverted staggered thin film transistor |
| US5371395A (en) * | 1992-05-06 | 1994-12-06 | Xerox Corporation | High voltage input pad protection circuitry |
| US5313319A (en) * | 1992-06-17 | 1994-05-17 | General Electric Company | Active array static protection devices |
| CN1065051C (en) * | 1992-08-13 | 2001-04-25 | 卡西欧计算机公司 | Thin-film transistor array and liquid crystal display device using the thin-film transistor array |
| US5428498A (en) * | 1992-09-28 | 1995-06-27 | Xerox Corporation | Office environment level electrostatic discharge protection |
| JP2886066B2 (en) * | 1993-11-16 | 1999-04-26 | 株式会社フロンテック | Thin film transistor substrate and method of manufacturing the same |
| US5648296A (en) * | 1994-07-27 | 1997-07-15 | General Electric Company | Post-fabrication repair method for thin film imager devices |
| US6013923A (en) * | 1995-07-31 | 2000-01-11 | 1294339 Ontario, Inc. | Semiconductor switch array with electrostatic discharge protection and method of fabricating |
| JPH10268794A (en) * | 1997-03-26 | 1998-10-09 | Sharp Corp | Display panel |
| JP4057127B2 (en) * | 1998-02-19 | 2008-03-05 | セイコーエプソン株式会社 | Active matrix substrate, method of manufacturing active matrix substrate, and liquid crystal device |
| JP3186701B2 (en) * | 1998-07-13 | 2001-07-11 | 日本電気株式会社 | Semiconductor device |
| US8355015B2 (en) | 2004-05-21 | 2013-01-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, display device and electronic device including a diode electrically connected to a signal line |
| US7217591B2 (en) * | 2004-06-02 | 2007-05-15 | Perkinelmer, Inc. | Method and process intermediate for electrostatic discharge protection in flat panel imaging detectors |
| JP4845352B2 (en) * | 2004-06-15 | 2011-12-28 | キヤノン株式会社 | Radiation imaging apparatus, manufacturing method thereof, and radiation imaging system |
| US20080024427A1 (en) * | 2006-07-26 | 2008-01-31 | Prime View International Co., Ltd. | Electronic ink display panel |
| CN101339941B (en) * | 2008-05-08 | 2010-06-02 | 北京中星微电子有限公司 | Electrostatic discharging protection circuit |
| JP5439837B2 (en) | 2009-02-10 | 2014-03-12 | ソニー株式会社 | Display device |
| CN106569351A (en) * | 2016-10-20 | 2017-04-19 | 中国电子科技集团公司第二十六研究所 | Antistatic high-frequency acousto-optical device |
| CN109427764B (en) * | 2017-08-24 | 2021-06-01 | 华为终端有限公司 | Electrostatic discharge protection device and circuit |
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| US4070653A (en) * | 1976-06-29 | 1978-01-24 | Texas Instruments Incorporated | Random access memory cell with ion implanted resistor element |
| JPS54154289A (en) * | 1978-05-26 | 1979-12-05 | Matsushita Electric Ind Co Ltd | Manufacture of thin-film transistor array |
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| WO1984003992A1 (en) * | 1983-03-31 | 1984-10-11 | Matsushita Electric Ind Co Ltd | Thin-film integrated device |
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| JPS59224172A (en) * | 1983-06-03 | 1984-12-17 | Hitachi Ltd | Breakdown preventing circuit in semiconductor circuit device |
| JPS59232456A (en) * | 1983-06-16 | 1984-12-27 | Hitachi Ltd | Thin film circuit element |
| JPS6038858A (en) * | 1983-08-12 | 1985-02-28 | Hitachi Ltd | Semiconductor integrated circuit device |
| US4584592A (en) * | 1984-08-13 | 1986-04-22 | Xerox Corporation | Marking head for fluid jet assisted ion projection imaging systems |
| JPH0682839B2 (en) * | 1984-08-21 | 1994-10-19 | セイコー電子工業株式会社 | Manufacturing method of display panel |
| JPS6188557A (en) * | 1984-10-05 | 1986-05-06 | Nippon Soken Inc | Thin-film transistor matrix array |
-
1986
- 1986-10-24 US US06/922,603 patent/US4803536A/en not_active Expired - Lifetime
-
1987
- 1987-08-24 CA CA000545137A patent/CA1310060C/en not_active Expired - Fee Related
- 1987-09-24 MX MX8514A patent/MX159965A/en unknown
- 1987-10-16 JP JP62261524A patent/JPS63133124A/en active Pending
- 1987-10-23 BR BR8705707A patent/BR8705707A/en unknown
- 1987-10-24 CN CN87107179.7A patent/CN1014381B/en not_active Expired
- 1987-10-26 EP EP87309426A patent/EP0265290A3/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| CN87107179A (en) | 1988-05-04 |
| MX159965A (en) | 1989-10-17 |
| EP0265290A2 (en) | 1988-04-27 |
| BR8705707A (en) | 1988-05-31 |
| US4803536A (en) | 1989-02-07 |
| JPS63133124A (en) | 1988-06-04 |
| CN1014381B (en) | 1991-10-16 |
| EP0265290A3 (en) | 1988-09-21 |
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| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |