CA1309492C - Communication system for video information apparatus - Google Patents
Communication system for video information apparatusInfo
- Publication number
- CA1309492C CA1309492C CA000498264A CA498264A CA1309492C CA 1309492 C CA1309492 C CA 1309492C CA 000498264 A CA000498264 A CA 000498264A CA 498264 A CA498264 A CA 498264A CA 1309492 C CA1309492 C CA 1309492C
- Authority
- CA
- Canada
- Prior art keywords
- communication
- transmission
- areas
- peripheral apparatus
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B31/00—Arrangements for the associated working of recording or reproducing apparatus with related apparatus
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
- G11B27/02—Editing, e.g. varying the order of information signals recorded on, or reproduced from, record carriers
- G11B27/031—Electronic editing of digitised analogue information signals, e.g. audio or video signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
Abstract
ABSTRACT OF THE DISCLOSURE
A communication system for video information apparatus for carrying out a communication between a video information apparatus and a peripheral apparatus arranged so that a communication is repeatedly carried out at a period synchronized with a signal of a vertical period having a constant phase relation relative to a vertical synchronizing signal.
A communication system for video information apparatus for carrying out a communication between a video information apparatus and a peripheral apparatus arranged so that a communication is repeatedly carried out at a period synchronized with a signal of a vertical period having a constant phase relation relative to a vertical synchronizing signal.
Description
BACKGRO~JND O~ 91~NTION
Field of the Invention This invention relates to bidirectional communication between a single master apparatus and a plurality of slave apparatus and, more particularly but not exclusively, to a method and apparatus for communicat~on between video information apparatus, such as VTR (video tape recorder) or video disc player, and peripheral apparatus, such as a tuner, a timer, a video camera, editin~ apparatus, a computer and so on.
Description of the Prior Art .
Recently, in order to enhance the enjoyment of video equipment, a video information system has been developed, which comprises a VTR as master apparatus and a plurality of peripheral or slave apparatus, such as a video camera, a television tuner unit, a timer unit and editing apparatus. In such a system, the communication of control data, such as a mode signal and various other control signals, between the VTR and each peripheral apparatus becomes a significant problem.
In a system for bidirectional communication between a VTR used as master apparatus and a plurality of peripheral apparatus each used as a slave apparatus, it is important that the number of communication lines be reduced as much as possible. This becomes increasingly important as the number of slave apparatus is increased.
A bidirectional communication system having at the side of the master apparatus only two communication lines one of which is a transmission communication line and the other of which is a reception communication line has much to ~309492 recommend it. Altern~tively, a bidirectlonal communication system having only one communication line may be employed, The assignee of the present application has previously proposed a bid~rectional communication system using only one communication line.
In this previously propo~ed system, a communication interval formed of a plurality of master and slave transmission areas that are arranged in a time division manner is taken as one block, and this block is repeated cyclically. The time control for communication is provided exclusively by the master appar~tus. The number of slave apparatus transmission areas is equal to the number of slave apparatus.
Even when two communication lines (master apparatus transmission line and slave apparatus transmission linel are used, seen from the side of the slave apparatus the transmission lines appear as one. Accordingly, when the communication is carried out cyclically as described above, the transmissions from the several slave apparatus are effected in the respective transmission areas in a time division manner.
However, since transmission areas are provided for all of the plurality of slave apparatus in a time division manner, as the number of slave apparatus increases, the total transmission period bècomes very long.
Since each slave apparatus does not always request the master apparatus to transmit video information, if a transmission area is provided for each of the plurality of 4 ~ ~ .
slave apparatus as described above, an unoccupied or useless transmission area occurs, resulting in low time efficiency.
On the other hand, it ~requently happens that a mode signal, a control signal and a command signal are communicated between the video information apparatus and the peripheral apparatus, for example, between the VTR and the video camera and the editing apparatus, in order that the two apparatus may be operated in synchronlsm with each other.
In the prior art, a communication of this kind is performed regardless of its time relation to an input signal or a reproduced video signal. For example, when a mode is changed, commands such as "playback mode next", "stop mode next" and so on are transmitted and received.
Particularly, when a communication is carriGd out only in a necessary case, as when the mode is changed as described above, if a miscommunication or erroneous communication occurs, the present mode remains erroneous at least until the next communication is made for changing the mode.
Further, since it is not known in advance exactly when the transmission data will arrive at the peripheral apparatus, the peripheral apparatus must be always in an interruptible state and always in a communicable state, so that the software therefor is difficult to write.
As to the video information apparatus, since it is not known in advance exactlv when the command or the like will arrive from the peripheral apparatus, the software therefor is also difficult to writa.
For this reason, it may be concluded that the communication should be carried out cyclically. However, if the cycle or period is free-running and n~ 3s~ ized with a video si~nal or in a fi~ed time relation to the latter, various problems occur.
For example, it has recently been proposed that data such as a time code including a frame number, a field number and the like be multiplexed on a video slgnal and then recorded. In such case, when the time codes are communicated, if the communication between the VTR and the peripheral apparatus is carried out over a period longer than, for example, the vertical period, the communication surpasses the frame number or field number of the time code at a certain time, producing a dropout in the time code output.
Furthermore, if the period of the communication is not synchronized with the video signal, when the command (for example) "set recording mode two fields from now" is issued in a communication between the VTR and the editing apparatus, the time "two fields from now" cannot be determined uniquely. This makes the software therefor very difficult to write.
OBJECTS AND SUMMARY OF THE INVENTION
An object of this invention is to provide a bidirectional digital communication system for video information apparatus that overcomes the problems of conventional apparatus noted above.
Another object of the invention is to provide a communication system for video information apparatus in which time division multiplexing can be easily controlled ny an inexpensive microcomputer.
Another object of the invention is to provide a communication system in which the number of time division areas can be less than the number of slave apparatus and in which the number of unused time divi~ion areas can be reduced, thereby improving time ~fflciency.
Another object of the invention i8 to provide a communication system for video information apparatus in which, when communication is carried out during a constant period or vertical period, the communication interval can be prevented from becoming too long. This provides free time during a stop interval that can be employed to perform functions other than communication.
Another object of the invention is to provide a communication system for video information apparatus that can transmit communication data signals such as a frame number signal and so on corresponding to the frame number, field number or the like.
Another object of the invention is to provide a communication system for video information apparatus in which, since the time for starting a communication can be predicted, the hardware of the peripheral apparatus and of the master apparatus can be simplified.
Another object of the invention is to provide a communication system for video information in which, since the communication is carried out in synchronism with the vertical period, it can easily be determined whether or not noise is mixed into a picture by the communication, thereby reducing the debugging period.
The foregoing and other objects of the invention are attained, according to one aspect thereof, by the provision of a system for communicating between master video apparatus and peripheral apparatus wherein video signals organized into vertical periods are processed; the apparatus 13~9A~2 comprising: means for generating timing siqnals synchronously with the vertical periods; means for establishinq first communication intervals having a substantially constant phase relation with respect to the timing signals; and communication means for effecting communication between the master apparatus and the peripheral apparatus during the first communication intervals.
According to another aspect of the invention, there is provided a data communication method for communicating serial data between a master apparatus and a plurality of slave apparatus in a bidirectional manner comprising the steps of: repeating cyclically a communication interval formed of a plurality of separate communication areas, the number of areas being less than the number of the slave apparatus; reserving first selected ones of the areas for transmission by the master apparatus and second selected ones of the areas for transmission by the slave apparatus; and respectively allocating the second areas to individual ones of the slave apparatus on a first-come, first-served basis.
BRIEF DESCRIPTION OF T~IE DRAWINGS
A better understanding of these and other objects, features and advantages of the present invention will become apparent from the following detailed description of the preferred embodiment thereof in conjunction with the accompanying drawings, wherein like reference characters designate like elements and parts and wherein:
Fig. 1 is a block diagram of a communication system ~including a VTR used as master apparatus and a video camera used as a slave apparatus) to which an embodiment of a communication method and apparatus according to t~s in~Jention is applied;
Fig. 2 is a diagram use~ul for explaining a bidirectional communicatlon carried out between the VTR and video camera shown in Fig. l;
Fiqs. 3A (formed of Figs. 3A-I and 3A-II) to 3K
(formed of Figs. 3K-I and 3K-II) are diagrams used to explain the transmission and reception, respectively, in one communication interval;
Fig. 4 is a flow chart useful for expla~ning the operation carried out by slave apparatus to determine an unoccupied transmission area within which to transmit;
Fig. 5 is a diagram schematically illustrating the operation of the flow chart of Fig. 4;
Fig. 6 is a flow chart of a program used by the VTR;
Fiq. 7 is a flow chart of a program used by the video camera;
Figs. 8A and 8B are diagrams used to explain how to cope with the disorder of a vertical synchronizing signal;
Fig. 9 is a flow chart helpful for explaining the operations of Figs. 8A and 8B; and Figs. lOA and lOB are respectively diagrams used to explain examples of other communication modes, such as when a communication is carried out in the midst of one operation, so that other operations cannot be performed and when a time division multiplexing process can be controlled easily.
DESCRIPTIO~ OF THE PREFERRED EM~ODIMENT 1 ~0 S 4 9 Now, the present invention will hereinafter be described with refer~nce to ~he attached drawings.
Fiq. 1 19 a block diagram showing an example of a communication system to which an embodiment of a bidirectional data communication method and apparatu~
according to the present invention is applied. In thls example, the bidirectional serial data communication i9 made possible by a single communication line. A VTR 10 (video tape recorder) is used as the master apparatus, and more than three slave apparatus such as a video camera 20, a television tuner unit and an editing apparatus (neither of the latter two being shown) are used. S~nce the structure of the communication control sections at the various slave apparatus are all the same, only the video camera 20 is shown in the example of Fig. 1.
A data commun~cation line 30 transmits control data between the VTR 10 and the video camera 20 and other slave apparatus.
The VTR 10 comprises a control section 11 which incorporates therein a microcomputer 110 to carry out the communication control and other controls, a video circuit and mechanical deck section 12, a VTR function key section 13, a VTR mode display section 14, a remote control function key section 15 for the video camera 20 and so on.
The video camera 20 comprises a control section 21 which incorporates a microcomputer 210 to carry out a communication control and other controls, a camera function key section 22, a remote control function key section 23 for the VTR 10, a display section 24 which can display data within, for example, a finder of the video camera 20 and so on. Further, motors 25~ and 25~ for respecti~el~ ~o~a9t4~
a focusing ring and a zoom ring of an lm~qe pickup lens and an iris motor 25I ~or controllinq the opening and closing of the iris are respectively connected through motor drive circuits 26F, 26Z and 26I to the control section 21.
The function key section 13 of the VTR 10 includes function keys for placing the apparatus in any of various modes, such as a recording mode, playback mode, pause mode, fast forward mode, rewind mode, stop mode and so on. When one of these function keys is depressed, the microcomputer 110 of the control section 11 identifies the depression of the function key and displays it on the display section 14.
At the same time, the microcomputer 110 supplies a necessary control signal to the video circuit and mechanical deck section 12 so as to place the VTR in the mode corresponding to the mode of the operated func~ion key.
Also the remote control function key section 23 for the VTR 10 at the video camera 20 includes function keys corresponding to various modes, such as recording mode, playback mode, pause mode, fast forward mode, rewind mode, stop mode and so on. When one of these function keys is depressed, as described below, control data is transmitted to the VTR 10 from the video camera 20 through the communication line 30. Such control data is latched in the register of the microcomputer 110 in the control section 11 and then the mode of the VTR 10 is determined from the content of the control data and the state of the key input of the function key section 13 of the VTR 10 at that time.
The corresponding mode is displayed on the display section 14 and the appropriate control siqnal is supplied to the video circuit and the mechanical deck section 12, thus placing the VTR 10 in the correspond~n~ mode. The reasoQ 9 4 9 2 the mode of the VTR 10 is determined on the basis of the data transmitted from the vldeo aamera 20 and the state of the function key section 13 of the VTR 10 is to prevent any erroneous operation. For instance, the case wherein the vîdeo camera 20 is placed in the recording mode while the VTR 10 is placed in the fast forward mode is not normal; in such a case, therefore, a fast forward command would be neglected and the recording mode would be continued. The correct operation is realiæed since the manner in which the future mode of the VTR 10 is selected in accordance with the combination of the remote control signal and the function key mode is stored in the microcomputer 110.
The signal data indicating that the VTR 10 is placed in the corresponding mode is then transmitted from the VTR 10 to the video camera 20. The signal data is received by the video camera 20, and the mode of the VTR 10 is displayed on the display section 24 within the view finder.
The remote control function key section 15 for the video camera 20 of the VTR 10 includes keys such as a focus key, iris key, zoom key, pan key, tilt key and so on. For example, when the zoom is operated, as will be described later, zooming data is transmitted to the video camera 20 from the VTR 10 through the transmission line 30 and stored in the register of the microcomputer 210 of the control section 21 in the video camera 20. Then, the zooming data is supplied to the zoom motor 25Z through the motor drive circuit 26Z, so that the zooming operation is carried out.
If the function key section 22 in the video camera 2Q is operated, the camera 20 carries out the operation corresponding to the key operation in response to the signal from the microcomputer 210 of the control section 21. 1 ~ ~9~92 for instance, the zoom key of the video camera 20 is operated, the zooming operation will b~ carried out.
The control section 11 o the VTR 10 and the control section 21 of the video camera 20 are constructed as described below. The control section 21 is constructed in exactly the same way in the other slave apparatus.
The microcomputer 110 in the control section 11 of the VTR 10 and the microcomputer 210 in the control sect~on 21 of the video camera 20 include 8-bit shift registers 111 and 211, respectively. Each of the shift registers 111 and 211 includes a serial input terminal SI, a serial output terminal SO and a clock terminal CX. The writing and reading of data into and from the shift registers 111 and 211 are carried out in the form of parallel data for the data buses of the microcomputers.
The writing and reading of the serial data into and from the shift registers 111 and 211 are controlled by communication controllers 112 and 212, respectively. The communication controllers 112 and 212 generate signals Gl, G2 and Gl', G2' which control input gate switches 113, 213 and output gate switches 114, 214 to turn on and off and shift clocks CLK and CLK' (one cycle thereof is, for example, 104 ~ sec) for the shift registers 111 and 211.
The communication controller 112 provided in the VTR 10, which is used as the master apparatus, is adapted to generate a start bit on the basis of a communication start signal CS transmitted from the microcomputer 110; on the other hand, the communication controller 212 in the video camera 20, which is used as slave apparatus, does not produce the start bit. In other words, the time control for , the communication is carried out only by the VTR 10, which functions as the master apparatu9. 1 3 0 9 4 9 2 Microcomputers can be employed as the communication controllers 11~ and 212.
Transistors 115 and 215 are input transistors, while transistors 116 and 216 are output transistorq. The collectors of the output transistors 116 and 216 are connected through reslstors 117 and 217, respectively, to power supply terminals of +5V. The same collectors are further connected to the communication line 30. The emitters of the respective transistors 116 and 216 are grounaed. The serial data from the shift registers 111 and 211 are supplied through the output switches 114 and 214 to the bases of the output transistors 116 and 216, respectively.
The communication line 30 is connected through resistors 118 and 218 to the bases of the input transistors 115 and 215. The emitters of the input transistors 115 and 215 are grounded and the collectors thereof are connected through resistors 119 and 219, respectively, to the power terminals of +5V. The collectors of the input transistors 115 and 215 are further respectively connected through input switches 113 and 213 to the serial input terminals SI of the shift registers 111 and 211.
Accordingly, when data is not being transmitted through the communication line 30, the line 30, since connected to the power supply terminals (+5V) via the resistors 117 and 217, is maintained at a level as high as +5V~
In the arrangement described above, the bidirectional communication between the VTR lO as the master apparatus and the video camera 20 as the slave apparatu~ ~ 9~ 9 2 carried out in synchronism with the vertical synchronizing signal VD shown if Fig. 2.
More specif~cally, in the VTR 10 as the master apparatus, an interval formed of two receiving areas (transmitting areas of the slave apparatus) P1 and P2 and two transmitting areas (recei~ring areas of the slave apparatus) p3 and P4 is treated as one communication interval. This communication interval and a pause interval of a constant period are repeatedly transmitted in synchronism with the vertical synchronizing signal VD as shown in Fig. 2. There are thus two transmission areas P
and P2 for the slave apparatus, so that there are fewer slave apparatus transmission areas than thare are slave stations. The transmissions from the slave apparatus are carried out by using a vacant one of the areas P1 and P2 as described below.
One bit at the beginning of each of the areas P1, P2, P3 and P4 is reserved for a start bit, which is produced only by the VTR 10 that is used as the master apparatus and by which the reception and the transmission between the master apparatus and the slave apparatus can be carried out.
That is, the communication controller 112 produces four start bits SB in one communication interval during each cycle.
Serial data Do to D7 of 8 bits are transmitted in each of the transmission and receiving areas Pl to P4 and the data Do to D7 of 8 bits constitute one word. Since one communication interval is formed of four communication areas P1 to P4, four data words are received and transmitted during one vertical period TF. The word number and the bit number within the communication interval are made constant so that the length of the communication interval becomes constant. Thus the length o~ the pause interval is also constant.
The transmission and reception within one communication interval is carried out as follow~. First the transmission from the master apparatus will be described.
While in Fig. 2 transmission from the master apparatus is carried out after the transmission from the slave apparatus is carried out, the sequential order of the transmission and the reception does not cause any problems if it is determined in advance.
The microcomputer 110 of the master apparatus generates a communication start signal CS (shown in Fig. 3A) which is then supplied to the communication controller 112.
The communication start signal CS is normally n 1" and falls off to "0" when the communication start request is generated. In this embodiment, the communication start signal CS falls to n o n four times during one vertical period TF. When the communication start request is generated, the communication controller 112 produces the start bit SB
(shown in Fig. B) that becomes "1" during a period of one bit or predetermined duration of time equal, for example, to 104 ~sec. The period during which the start bit SB is high begins when the communication start signal becomes low.
This start bit S8 is supplied to the base of the output transistor 116 and then is supplied to the communication line 30 which is connected with the collector of the output transistor 116 as a signal "0`' whose polarity is inverted.
The communication controller 112 gènerates 8 clock pulses CLK (shown in Fig. 3C) having a clock cycle or pulse period eaual to 104 ~sec. The firstl~ ~ ulses commences at a time coincident with ~he falling edge of the start bit SB, These pulses CLK are supplied to the clock terminal CK o~ the shift register 111. ~he control signal Gl (shown in Fig. 3D) for the output switch 114 becomes "1"
during the period of 8 clock pulses CLK, and the output transistor 114 is turned on during this period of "1", Since transmission data DTl ~shown in Fig. 3F) is already stored in the shift register 111 by the microcomputer 110, the-~8-bit transmission data DTl is read out from the shift register 111 by the 8 clock pulses CLK and then is supplied through the output switch 11~ and the output transistor 116 to the communication line 30. Fig. 3G shows the state of the signal on the communication line 30.
When the 8-bit transmission data DTl is transmitted, the output witch 114iis turned off so that the communication line 30 is pulled up to "ln. The period of "1" lasts for a time equal to the duration of 2.5 to 5 bits, and the period of 2.5 to 5 bits constitutes an end bit (refer to Figs. 2 and 3G). Such end bits are usually selected to be about two normal bits in duration. In this embodiment, however, in order to afford sufficient time for the microcomputer to perform all operations specified by the software, including latching and/or storing the communication data in a RAM (random access memory) of the microcomputer, the stop bit is extended so that it is longer than a normal bit.
The data transmitted from the master apparatus in the transmission area as mentioned above is supplied to, for example, the base of the input transistor 215 provided in the slave apparatus such as the video camera 20. The input 1309~92 transistor 215 is turned off at the start bit SB so that the collector output rises to "1". The communicatlon controller 212 de~ects this condition, and the control signal G1' ~Fig.
3I) for the input switch 213 rises to "1" and ~ clock pulses CLK' (Fig. 3K) each having a cycle 104 ~sec in length are produced, whereby the input switch 213 i9 turned on and the clock pulse CLK' is supplied to the clock terminal CK o the shift register 211. As a result, the tran~mission data DT
from the VTR 10 is latched in the shift register 211. The data latched in the shift register 211 is then transmitted to and stored in the RAM (not shown) of the microcomputer 210 during the stop bit period, and data DT2, which is to be transmitted from the video camera 20 to the VTR 10, is set in the shift register 211.
Although the data DT1 is latched in other slave apparatus simultaneously, whether or not the other slave apparatus use the data DTl is determined by their microcomputers by interpreting the content of the data DTl.
The receiving area for the master apparatus, or the transmission from the slave apparatus will be described next.
When the video camera 20 issues the transmission command and a transm~ssion demand signal DM (Fig. 1) is supplied to the communication controller 212, the video camera 20 is set in a transmission standby mode and the transmission data DT2 (the right-hand side of Fig. 3H) is stored in the shift register 211.
Under this state, the start bit SB (Fig. 3B) is generated by the communication controller 112 of the VTR 10 at the beginning of the area P1 (Fig. 2) and the start bit SB is transmitted through the transistor 116 (Fig. l) and 1~
the communication line 30 to the video came ~ 32~9 4~n, as shown in the right-hand side of Fig. 3G, the data on the transmission line 30 becomes "0" durin~ one blt period. As a result, the input transistor 215 of the video camera 20 is turned off and the collector output thereof becomes "1".
Since the communication controller 212 detects this condition and the control signal G2' ~Fig. 3J) for the output switch 214 becomes "1", the output switch 214 is turned on and the 8 clock pulses CLK' are generated during the period in which the signal G2' is "1". The 8 clock pulses CLK' are fed to the clock terminal CR of the shift register 211. Consequently, the data DT2 is read out from the shift register 211 (refer to Fig. 3~) and is fed through the output transistor 216 to the communication line 30.
After the start bit Ss is generated by the communication controller 112 of the VTR 10, the control siqnal G2 (Fig. 3E) for the input switch 113 becomes "1" so that the input switch 113 is turned on and the 8 clock pulses CLK (Fig. 3C) are generated during the period in which the signal G2 becomes n 1 n .
Accordingly, the data DT2 transmitted from the video camera 20 is supplied through the input transistor 115 and the switch 113 to the shift register 111 and stored in the shift register 111 on the basis of the clock pulse CLK.
The data DT~ is then transferred to and stored in the RAM of the microcomputer 110 during the end bit period of the transmission area Pl.
In the case described above the first area Pl in the communication interval is not used as a transmission area by other slave apparatus. Interference between two slave apparatus competing to use the same transmission area -t~-is avoided by causing one of the slave apparat ~ ~ ~ ~smit in the next area P2. In other words, certain transmission areas are reserved for transmisslons made b~ the various slave apparatus, and these areas are respectively allocated to individual ones of the slave apparatus on a first-come, first-served basis.
Fig. 4 is a flow chart representing a program used for such purpose. The program routines conforming with the flow chart of Fig. 4 are executed by the microcomputer of the control section of each slave apparatus.
When the start bit SB is transmitted from the master apparatus to each slave apparatus at the beginning of the area Pl, the slave apparatus having the transmission request command transmits the transmission data to the communication line 30 (step 101) in the transmission area Pl. At that time, the state of the data transmitted to the communication line 30 and the state of the communication line 30 are compared at every bit (step 102). More specifically, if the transmission data is ~0", the output transistor 216 is in the off state so that the communication line 30 must be placed in the state of 5V, while if the transmitted data is "1", the output transistor 216 is turned on so that the communication line 30 must be placed in the state of OV.
However, when data are transmitted from a plurality of slave apparatus, if the data bit from any one of the slave apparatus becomes "1", since its output transistor 216 is turned on, the communication line 30 is lowered to OV regardless of the data of other slave apparatus. Accordingly, when the communication line 30 becomes oV while the bit of the transmitted data is "0~, an , --~0--inconsistency exists between the data as transmitted and the .. .
data as monitored on the communication line 30. This inconsistency is detected by tho microcomputer o~ the control section of the slave apparatus (step 1031 and signifies the simultaneous transmission by other slave apparatus through the same area Pl. From the preceding description, it is apparent that when two or more slave apparatus simultaneously transmit data through the same transmission area, the slave apparatus whose transmission data bit Do to D7 transmits "l" first is given priority and the corresponding area is assigned as the transmission area of that slave apparatus. Then, in the slave apparatus in which it is detected that the data as transmitted and the data on the communication line 30 are different from each other at a given bit, the succeeding bits are all set tonO", whereby to prevent the data of the slave apparatus preempting the area Pl from being transmitted incorrectly.
The slave apparatus which could not transmit data through the area Pl again transmits data on the basis of the start bit SB which occurs at the beginning of the area P2 (step 104). A determination whether or not the area P2 is vacant is made in the same way as earlier noted at steps lO5 and 106. If the area P2 is vacant, it is selected as the transmission area of that slave apparatus. If on the other hand it is occupied, a determination whether or not the area Pl is vacant described above is made again in the next cycle. The operation described above is repeatedly carried out until a vacant area is detected.
Fig. 5 schematically illustrates these operations.
In Fig. 5, a slave apparatus I (for example, a tuner) and another slave apparatus II (for example, an editing . . .
-apparatus) compete with each other with respect to the transmission demand in the area P1 and the editlng apparatus as the slave apparatus II transmi9sion switches into the area P2. The master apparatus (VTR) receives in areas P
and P2 and transmits in the areas P3 and P4. Both slave apparatus receive in areas P3 and P4. Both atte~pt to transmit in the area Pl ~left half of Fig. 5). The tuner preempts the area P1 and the editor then switches to the area P2 (right half of Fig. 5).
The checking of the area at every bit can be performed easily by the shift register 211, which is formed as a 9-bit shift register. In practice, since the shift register that the 4-bit microcomputer incorporates therein is of a 9-bit type, such shift register can be used without modification.
During the pause or stop interval next following the communication interval formed of the four areas P1 to P4, the data processing based on the content of the received data is carried out by the VTR 10, the video camera 20 and other slave apparatus, and other processing is carried out in a time division manner.
As described below, the communication interval including the transmission from the VTR 10 and the transmission from the slave apparatus such as the video camera 20 and the like into one block is repeated cyclically, the pause interval being interposed therein. In this embodiment, since the start bit SB is generated only by the master apparatus and the time control is carried out by the master apparatus, the areas Pl to P~ can be discriminated surely and the communication interval and the .. . .
pause interval can be reliablv distinguished from each -other .
These operations are execute~ i3n0~c4c~ance with the followlng pro~ram routines of the microcomputer of the VT~ 10 and the video camera 20.
Fig. 6 is a flow chart of the program steps for the VTR 10, in which steps 201 to 209 are executed sequentially and repeatedly. In steps 205 to 207, either the from the video camera 20 or the function key operation of the VTR 10 is ~iven priority, whereby the mode of the VTR
10 is determined. These steps 205 to 207 are used to prevent erroneous operation.
In step 209, data co~rrespondina to the key operation at the VTR 10 and data indicative of the mode of the VTR 10 designated by the remote control signal from the video camera 20 are generated; and data indicative of "no operation to be performed" is generated when there are no command and no mode to be transmitted to the video camera 20.
More particularly, step 201, the start SB is transmitted by the VTR 10 (master apparatus). At step 202, data is received. At step 203, the start bit SB is transmitted. At step 204, data is transmitted. At step 205, the received data is analyzed. At step 206, the operated function key of the VTR 10 is read. At step 207, the mode of the VTR 10 is determined. At step 208, the mode of the VTR 10 is displayed. At step 209, the data to be transmitted is generated. The program then recycles to step 201.
Fig. 7 is a flow chart of the program routine for the video camera 20, in which steps 301 to 308 are executed sequentially and repeatedly. In step 308, the tran ~ ~Q ~o~9 2 data is generated and stored in the register and the video camera 20 is set in the standby mode until the start bit i9 received. The transmission data is transmitted at step 304.
More particularly, step 301, the start SB is received by the video camera 20 (slave apparatus). At step 302, data is transmitted. At step 303, the start bit SB i9 received. At step 304, data is received. At step 305, the received data is analyzed. At step 306, the mode of the camera 20 is displayed. At step 307, the operated function key of the camera 20 is read. At step 308, the data to be transmitted is generated. The program then recycles to step 301.
The generation of the start bit and of the clock pulse in the communication controller 112 and the detection of the start bit and the generation of the clock pulse in the communication controller 212 may be carried out under the control of the microcomputers 110 and 210, respectively, or by other hardware, as those skilled in the art will understand.
The communication is carried out in synchronism with the vertical sync signal VD as described above. When an artificial sync signal is mixed into the vertical sync signal VD or the television channel is changed by the television tuner, the period of vertical sync signal is disordered temporarily. If the communication responds to the disorder of the vertical sync signal, the communication may be interrupted, or malfunctions may occur in processes or operations other than the communication.
_~4_ Therefore, the following operations arQ performed so as to cope with the disorder of the vertical synchronizin~ signal.
The follo~ing data processing is executed by the software program of the microcomputer 110 of the VTR 10 that is used as the master apparatus for communica~ion.
The VTR 10 is set ~n the standby mode, in which lt is momentarily inoperative, after a period S that begins at the leading edge of the vertical sync signal VD (Fig. 8A) and that is selected so that TF > S. The period S may be, for example, 15 msec (see Fig. 8B). More specifically, the communication interval begins at the leading edge of the vertical sync signal VD, and the pause or stop interval, in which operations other than communication are performed, begins at the end of the period S. These other operations are interrupted until the time S is passed from the leading edge of the vertical sync signal VD. The normal complete cycle is 16.7 msec.
The vertical sync signal VD is not disordered, the following vertical sync signal VD arrives at the end of the time TF, whereby the VTR 10 is released from its waiting mode and the communication begins (see Fig. 8B). This operation is repeated indefinitely.
Generally, if the maximum waiting interval is taken as 2 ~S, the waiting mode is released at the midpoint thereof. That is, TF = S + Q S is approximately established. Theoretically, TF is a constant (16.66... msec = 1/60 sec), but actually it contains a periodic error ~T, as discussed below.
If the period of the vertical sync signal VD is disordered by channel selection and the like as shown in _q~_ `
1309492 .i~
Fig. 8A, whe~ the constant waitinq period 2~ S passes (Fig.
8B), the waiting mode i9 released and hence the communication begins. If the vertical sync signal VD
arrives before 3 msec passes ~ollow~ng the end of period S), the waiting mode is released upon its arrival; i.e., the waiting mode is released without waiting for the full 3 msec. Thus the VTR 10 is designed to follow the disorder of the period of the vertical sync signal VD if the time displacement of the vertical sync signal VD does not exceed + ~S. However, when the disorder of the period of the vertical sync signal VD is such that the time displacement thereof exceeds + ~S, the VTR 10 is not synchronized with the vertical sync signal VD for a certain time duration and the free-running cycle of duration S + 2 ~S that is determined by the microcomputer 110 continues. Thereafter, when the vertical sync siqnal VD again enters into the waiting period of 2 ~S, communication is started in synchronism with the vertical sync signal VD.
That is, when the vertical sync signal VD is disordered, a window having a width of + ~S is provided for the vertical period TF. Accordingly, disorder of the synchronization is known to exist when the vertical sync signal VD is outside this window. Then, until the vertical sync signal enters into the window, the communication is carried out at the free-running cycle of S ~ 2 a s. The time required by the VTR 1 n to return to synchronization with the vertical sync signal VD is determined by the width 2 ~S of the window. In Fig. 8 two successive vertical sync signals VD are shown to occur with a period Xl that deviates considerably from the norm. If the periodic error of the vertical sync signal VD is taken as + ~T where ~S ~ ~T and the displacement between the vertical sync signal VD and the ~`~ communication cycle after the channeL is changed is taken as X2, the following equation ~e9ults:
1309~92 X2 = (Xl + TF + QT) - (S + 2 ~ S) = Xl - {S + 2 ~S - (TF + ~T)}
= Xl - { (S + l~ S) - TF + ( ~ S + ~ T)}
= X~ S + ~T) (thus S + ~S = TF) The displacement is thus reduced by (~S + ~T) at e~ery period and hence in the worst case the vertical sync signal VD again enters into the window after a period of = 1 , and the VTR 10 is locked to the vertical ~S - QT
sync signal VD. These operations are carried out in accordance with the flow chart of Fig. 9. At step 401, the timer is cleared. At step 402, communication and other processes are carried out. At at step 4Q3, a determination is made whether or not the value registered by the timer has reached the starting point of the window. The determination is made repeatedly until the answer is yes. At step 404 a determination is made whether or not the sync signal has arrived. If so the program loops back to step 401. If not a determination is made at step 405 whether or not the value registered by the timer has reached the end point of the window. As long as the end point of the window has not been reached, the program loops back to step 404; when the end point of the window is reached, the program loops back to step 401.
As described above, when a P~L circuit is constructed by the software of the microcomputer, the communication can be carried out in synchronism with the vertical sync siqnal VD. 1 3 0 9 ~ 9 2 Accordingl~ if the vertical sync signal VD i9 disordered rapidly or the sync signal is weakened to destroy the synchronization, free-running synchronization is established by the PLL circuit provided by the software of the microcomputer so that interruption of communication is prevented and the communication therefore follows the vertical sync signal VD.
Since the processing time for transmission and reception is provided by making the length of the end bit longer than the norm, the serial data can be read out and written easily by the software. In addition, with respect to the hardware, there is the advantage than an extra la~ch circuit is not required.
Further, this system is an excellent match for the RS-232C that is the communication interface standard widely used in apparatus of this kind. In the communication system of this embodiment, using the RS-232C system communication channel, the data can be read out only by voltage conversion.
Since the communication is carried out cyclically and can be free-running, the correct content of the communication is restored immediately in case of a dropout or inadvertent error in the communication.
Furthermore, only the transmission line is needed, an expensive interface is not used, the communication and related functions can all be carried out by a one-chip microcomputer, and bidirectional digital data communication can be realized by inexpensive home LSIs.
In addition, since synchronization of the 13 b 9 4 ~ 2 communicatlon is established by the master apparatus, even whan a plurallty of operations A, 3, C and D ~Figs. lOA and lOB) in addition to the communication must be performed in a time division manner, it is poss~ble to prevent a given operation from being interrupted while ln progress.
~ hat i5, synchronizat~on o~ the communication i9 not established and an expensive interface is not employed, the communication may be carried out in the midst of one operation as shown in Fig. lOA so that other operations cannot be carried out. In this embodiment, since the synchronization of the communication is established by the master apparatus and other operations are carried out in the pause or stop interval of constant length, the control of the time division multiplexing processing became easy as shown in Fig. lOB. As a result, there is the advantage that the signal processing can be carried out by an inexpensive microcomputer.
In the embodiment described above, the communication is started in synchronism with the vertical sync signal VD itself; alternatively, communication may be started in synchronism with a signal synchronized with the vertical sync signal: for example, a signal indicative of the rotary phase of a rotary head and a switching signal for two rotary heads.
While the embodiment described above is the special case where communication can be realized by a single communication line, the present invention can be applied also to a case where two lines for transmission and reception, respectively, extend from the master apparatus to a plurality of slave apparatus.
l~hile in the embodiment described abovle a check is made at intervals or one bit to determine whether or not the transmission area is vacant, a check may be ma~e at intervals of, for example, one word ~8 bits).
If in the embodiment of Fig. 2 the earlier areas Pl and P2 are assigned as transmission periods of the slave apparatus and the later areas P3 and P4 are assi~ned as transmission periods of the master apparatus, only the start bit of the first half can always be transmitted cyclically, while the start bit of the second half can be transmitted only when data is transmitted from the master apparatus.
Further, if the reception of incoming data is carried out before the transmission of outgoing data, it is possible to reduce considerably the buffer memories that store the data in the communication controller 212 and the microcomputer 210 of the slave apparatus.
In accordance with the present invention, since the transmission from the slave apparatus is carried out by using a selected unoccupied area of the plurality of time division areas, the number of time division areas can be smaller than the number of slave apparatus; in addition, the unused areas are reduced and the efficiencv of use is increased. Furthermore, when the communication is carried out at a constant period, for example the vertical period, it is possible to prevent the length of the communication interval from becoming too long. Accordingly, it is possible to preserve the time necessary for carrying out operations other than communication during the stop mode interval.
Further, according to the present invention, since the communication is carried out periodically, if the communication is carried out once erroneously, the ~ 9 2 data is transmitted on the next occasion, whereby the erron~ous communication is restored t~ the correct one. In addition, according to the present invention, since the communication is carried out ln synchronism with a signal synchronized with the vertical sync signal, it is possible to transmit as communication da~a signals corresponding to the frame number and field of the video signal.
Furthermore, since the communication timing can be predicted, the design of the hardware of the peripheral apparatus and the main body is simplified.
In addition, since the communication is carried out in synchronism with the vertical period, the mixing of noise into the picture due to the communication or the like can be detected easily and the debugging period is reduced.
Thus there is provided in accordance with the invention a novel and highly effective method and apparatus for communication between vîdeo information apparatus, such as a VTR or video disc player, and peripheral apparatus, such as a tuner, a timer, a video camera, editing apparatus, a computer and so on. Many modifications of the preferred embodiment of the invention described above will readily occur to those skilled in the art without departing from the spirit or scope of the invention. Accordingly, the invention is defined by the appended claims only.
.
Field of the Invention This invention relates to bidirectional communication between a single master apparatus and a plurality of slave apparatus and, more particularly but not exclusively, to a method and apparatus for communicat~on between video information apparatus, such as VTR (video tape recorder) or video disc player, and peripheral apparatus, such as a tuner, a timer, a video camera, editin~ apparatus, a computer and so on.
Description of the Prior Art .
Recently, in order to enhance the enjoyment of video equipment, a video information system has been developed, which comprises a VTR as master apparatus and a plurality of peripheral or slave apparatus, such as a video camera, a television tuner unit, a timer unit and editing apparatus. In such a system, the communication of control data, such as a mode signal and various other control signals, between the VTR and each peripheral apparatus becomes a significant problem.
In a system for bidirectional communication between a VTR used as master apparatus and a plurality of peripheral apparatus each used as a slave apparatus, it is important that the number of communication lines be reduced as much as possible. This becomes increasingly important as the number of slave apparatus is increased.
A bidirectional communication system having at the side of the master apparatus only two communication lines one of which is a transmission communication line and the other of which is a reception communication line has much to ~309492 recommend it. Altern~tively, a bidirectlonal communication system having only one communication line may be employed, The assignee of the present application has previously proposed a bid~rectional communication system using only one communication line.
In this previously propo~ed system, a communication interval formed of a plurality of master and slave transmission areas that are arranged in a time division manner is taken as one block, and this block is repeated cyclically. The time control for communication is provided exclusively by the master appar~tus. The number of slave apparatus transmission areas is equal to the number of slave apparatus.
Even when two communication lines (master apparatus transmission line and slave apparatus transmission linel are used, seen from the side of the slave apparatus the transmission lines appear as one. Accordingly, when the communication is carried out cyclically as described above, the transmissions from the several slave apparatus are effected in the respective transmission areas in a time division manner.
However, since transmission areas are provided for all of the plurality of slave apparatus in a time division manner, as the number of slave apparatus increases, the total transmission period bècomes very long.
Since each slave apparatus does not always request the master apparatus to transmit video information, if a transmission area is provided for each of the plurality of 4 ~ ~ .
slave apparatus as described above, an unoccupied or useless transmission area occurs, resulting in low time efficiency.
On the other hand, it ~requently happens that a mode signal, a control signal and a command signal are communicated between the video information apparatus and the peripheral apparatus, for example, between the VTR and the video camera and the editing apparatus, in order that the two apparatus may be operated in synchronlsm with each other.
In the prior art, a communication of this kind is performed regardless of its time relation to an input signal or a reproduced video signal. For example, when a mode is changed, commands such as "playback mode next", "stop mode next" and so on are transmitted and received.
Particularly, when a communication is carriGd out only in a necessary case, as when the mode is changed as described above, if a miscommunication or erroneous communication occurs, the present mode remains erroneous at least until the next communication is made for changing the mode.
Further, since it is not known in advance exactly when the transmission data will arrive at the peripheral apparatus, the peripheral apparatus must be always in an interruptible state and always in a communicable state, so that the software therefor is difficult to write.
As to the video information apparatus, since it is not known in advance exactlv when the command or the like will arrive from the peripheral apparatus, the software therefor is also difficult to writa.
For this reason, it may be concluded that the communication should be carried out cyclically. However, if the cycle or period is free-running and n~ 3s~ ized with a video si~nal or in a fi~ed time relation to the latter, various problems occur.
For example, it has recently been proposed that data such as a time code including a frame number, a field number and the like be multiplexed on a video slgnal and then recorded. In such case, when the time codes are communicated, if the communication between the VTR and the peripheral apparatus is carried out over a period longer than, for example, the vertical period, the communication surpasses the frame number or field number of the time code at a certain time, producing a dropout in the time code output.
Furthermore, if the period of the communication is not synchronized with the video signal, when the command (for example) "set recording mode two fields from now" is issued in a communication between the VTR and the editing apparatus, the time "two fields from now" cannot be determined uniquely. This makes the software therefor very difficult to write.
OBJECTS AND SUMMARY OF THE INVENTION
An object of this invention is to provide a bidirectional digital communication system for video information apparatus that overcomes the problems of conventional apparatus noted above.
Another object of the invention is to provide a communication system for video information apparatus in which time division multiplexing can be easily controlled ny an inexpensive microcomputer.
Another object of the invention is to provide a communication system in which the number of time division areas can be less than the number of slave apparatus and in which the number of unused time divi~ion areas can be reduced, thereby improving time ~fflciency.
Another object of the invention i8 to provide a communication system for video information apparatus in which, when communication is carried out during a constant period or vertical period, the communication interval can be prevented from becoming too long. This provides free time during a stop interval that can be employed to perform functions other than communication.
Another object of the invention is to provide a communication system for video information apparatus that can transmit communication data signals such as a frame number signal and so on corresponding to the frame number, field number or the like.
Another object of the invention is to provide a communication system for video information apparatus in which, since the time for starting a communication can be predicted, the hardware of the peripheral apparatus and of the master apparatus can be simplified.
Another object of the invention is to provide a communication system for video information in which, since the communication is carried out in synchronism with the vertical period, it can easily be determined whether or not noise is mixed into a picture by the communication, thereby reducing the debugging period.
The foregoing and other objects of the invention are attained, according to one aspect thereof, by the provision of a system for communicating between master video apparatus and peripheral apparatus wherein video signals organized into vertical periods are processed; the apparatus 13~9A~2 comprising: means for generating timing siqnals synchronously with the vertical periods; means for establishinq first communication intervals having a substantially constant phase relation with respect to the timing signals; and communication means for effecting communication between the master apparatus and the peripheral apparatus during the first communication intervals.
According to another aspect of the invention, there is provided a data communication method for communicating serial data between a master apparatus and a plurality of slave apparatus in a bidirectional manner comprising the steps of: repeating cyclically a communication interval formed of a plurality of separate communication areas, the number of areas being less than the number of the slave apparatus; reserving first selected ones of the areas for transmission by the master apparatus and second selected ones of the areas for transmission by the slave apparatus; and respectively allocating the second areas to individual ones of the slave apparatus on a first-come, first-served basis.
BRIEF DESCRIPTION OF T~IE DRAWINGS
A better understanding of these and other objects, features and advantages of the present invention will become apparent from the following detailed description of the preferred embodiment thereof in conjunction with the accompanying drawings, wherein like reference characters designate like elements and parts and wherein:
Fig. 1 is a block diagram of a communication system ~including a VTR used as master apparatus and a video camera used as a slave apparatus) to which an embodiment of a communication method and apparatus according to t~s in~Jention is applied;
Fig. 2 is a diagram use~ul for explaining a bidirectional communicatlon carried out between the VTR and video camera shown in Fig. l;
Fiqs. 3A (formed of Figs. 3A-I and 3A-II) to 3K
(formed of Figs. 3K-I and 3K-II) are diagrams used to explain the transmission and reception, respectively, in one communication interval;
Fig. 4 is a flow chart useful for expla~ning the operation carried out by slave apparatus to determine an unoccupied transmission area within which to transmit;
Fig. 5 is a diagram schematically illustrating the operation of the flow chart of Fig. 4;
Fig. 6 is a flow chart of a program used by the VTR;
Fiq. 7 is a flow chart of a program used by the video camera;
Figs. 8A and 8B are diagrams used to explain how to cope with the disorder of a vertical synchronizing signal;
Fig. 9 is a flow chart helpful for explaining the operations of Figs. 8A and 8B; and Figs. lOA and lOB are respectively diagrams used to explain examples of other communication modes, such as when a communication is carried out in the midst of one operation, so that other operations cannot be performed and when a time division multiplexing process can be controlled easily.
DESCRIPTIO~ OF THE PREFERRED EM~ODIMENT 1 ~0 S 4 9 Now, the present invention will hereinafter be described with refer~nce to ~he attached drawings.
Fiq. 1 19 a block diagram showing an example of a communication system to which an embodiment of a bidirectional data communication method and apparatu~
according to the present invention is applied. In thls example, the bidirectional serial data communication i9 made possible by a single communication line. A VTR 10 (video tape recorder) is used as the master apparatus, and more than three slave apparatus such as a video camera 20, a television tuner unit and an editing apparatus (neither of the latter two being shown) are used. S~nce the structure of the communication control sections at the various slave apparatus are all the same, only the video camera 20 is shown in the example of Fig. 1.
A data commun~cation line 30 transmits control data between the VTR 10 and the video camera 20 and other slave apparatus.
The VTR 10 comprises a control section 11 which incorporates therein a microcomputer 110 to carry out the communication control and other controls, a video circuit and mechanical deck section 12, a VTR function key section 13, a VTR mode display section 14, a remote control function key section 15 for the video camera 20 and so on.
The video camera 20 comprises a control section 21 which incorporates a microcomputer 210 to carry out a communication control and other controls, a camera function key section 22, a remote control function key section 23 for the VTR 10, a display section 24 which can display data within, for example, a finder of the video camera 20 and so on. Further, motors 25~ and 25~ for respecti~el~ ~o~a9t4~
a focusing ring and a zoom ring of an lm~qe pickup lens and an iris motor 25I ~or controllinq the opening and closing of the iris are respectively connected through motor drive circuits 26F, 26Z and 26I to the control section 21.
The function key section 13 of the VTR 10 includes function keys for placing the apparatus in any of various modes, such as a recording mode, playback mode, pause mode, fast forward mode, rewind mode, stop mode and so on. When one of these function keys is depressed, the microcomputer 110 of the control section 11 identifies the depression of the function key and displays it on the display section 14.
At the same time, the microcomputer 110 supplies a necessary control signal to the video circuit and mechanical deck section 12 so as to place the VTR in the mode corresponding to the mode of the operated func~ion key.
Also the remote control function key section 23 for the VTR 10 at the video camera 20 includes function keys corresponding to various modes, such as recording mode, playback mode, pause mode, fast forward mode, rewind mode, stop mode and so on. When one of these function keys is depressed, as described below, control data is transmitted to the VTR 10 from the video camera 20 through the communication line 30. Such control data is latched in the register of the microcomputer 110 in the control section 11 and then the mode of the VTR 10 is determined from the content of the control data and the state of the key input of the function key section 13 of the VTR 10 at that time.
The corresponding mode is displayed on the display section 14 and the appropriate control siqnal is supplied to the video circuit and the mechanical deck section 12, thus placing the VTR 10 in the correspond~n~ mode. The reasoQ 9 4 9 2 the mode of the VTR 10 is determined on the basis of the data transmitted from the vldeo aamera 20 and the state of the function key section 13 of the VTR 10 is to prevent any erroneous operation. For instance, the case wherein the vîdeo camera 20 is placed in the recording mode while the VTR 10 is placed in the fast forward mode is not normal; in such a case, therefore, a fast forward command would be neglected and the recording mode would be continued. The correct operation is realiæed since the manner in which the future mode of the VTR 10 is selected in accordance with the combination of the remote control signal and the function key mode is stored in the microcomputer 110.
The signal data indicating that the VTR 10 is placed in the corresponding mode is then transmitted from the VTR 10 to the video camera 20. The signal data is received by the video camera 20, and the mode of the VTR 10 is displayed on the display section 24 within the view finder.
The remote control function key section 15 for the video camera 20 of the VTR 10 includes keys such as a focus key, iris key, zoom key, pan key, tilt key and so on. For example, when the zoom is operated, as will be described later, zooming data is transmitted to the video camera 20 from the VTR 10 through the transmission line 30 and stored in the register of the microcomputer 210 of the control section 21 in the video camera 20. Then, the zooming data is supplied to the zoom motor 25Z through the motor drive circuit 26Z, so that the zooming operation is carried out.
If the function key section 22 in the video camera 2Q is operated, the camera 20 carries out the operation corresponding to the key operation in response to the signal from the microcomputer 210 of the control section 21. 1 ~ ~9~92 for instance, the zoom key of the video camera 20 is operated, the zooming operation will b~ carried out.
The control section 11 o the VTR 10 and the control section 21 of the video camera 20 are constructed as described below. The control section 21 is constructed in exactly the same way in the other slave apparatus.
The microcomputer 110 in the control section 11 of the VTR 10 and the microcomputer 210 in the control sect~on 21 of the video camera 20 include 8-bit shift registers 111 and 211, respectively. Each of the shift registers 111 and 211 includes a serial input terminal SI, a serial output terminal SO and a clock terminal CX. The writing and reading of data into and from the shift registers 111 and 211 are carried out in the form of parallel data for the data buses of the microcomputers.
The writing and reading of the serial data into and from the shift registers 111 and 211 are controlled by communication controllers 112 and 212, respectively. The communication controllers 112 and 212 generate signals Gl, G2 and Gl', G2' which control input gate switches 113, 213 and output gate switches 114, 214 to turn on and off and shift clocks CLK and CLK' (one cycle thereof is, for example, 104 ~ sec) for the shift registers 111 and 211.
The communication controller 112 provided in the VTR 10, which is used as the master apparatus, is adapted to generate a start bit on the basis of a communication start signal CS transmitted from the microcomputer 110; on the other hand, the communication controller 212 in the video camera 20, which is used as slave apparatus, does not produce the start bit. In other words, the time control for , the communication is carried out only by the VTR 10, which functions as the master apparatu9. 1 3 0 9 4 9 2 Microcomputers can be employed as the communication controllers 11~ and 212.
Transistors 115 and 215 are input transistors, while transistors 116 and 216 are output transistorq. The collectors of the output transistors 116 and 216 are connected through reslstors 117 and 217, respectively, to power supply terminals of +5V. The same collectors are further connected to the communication line 30. The emitters of the respective transistors 116 and 216 are grounaed. The serial data from the shift registers 111 and 211 are supplied through the output switches 114 and 214 to the bases of the output transistors 116 and 216, respectively.
The communication line 30 is connected through resistors 118 and 218 to the bases of the input transistors 115 and 215. The emitters of the input transistors 115 and 215 are grounded and the collectors thereof are connected through resistors 119 and 219, respectively, to the power terminals of +5V. The collectors of the input transistors 115 and 215 are further respectively connected through input switches 113 and 213 to the serial input terminals SI of the shift registers 111 and 211.
Accordingly, when data is not being transmitted through the communication line 30, the line 30, since connected to the power supply terminals (+5V) via the resistors 117 and 217, is maintained at a level as high as +5V~
In the arrangement described above, the bidirectional communication between the VTR lO as the master apparatus and the video camera 20 as the slave apparatu~ ~ 9~ 9 2 carried out in synchronism with the vertical synchronizing signal VD shown if Fig. 2.
More specif~cally, in the VTR 10 as the master apparatus, an interval formed of two receiving areas (transmitting areas of the slave apparatus) P1 and P2 and two transmitting areas (recei~ring areas of the slave apparatus) p3 and P4 is treated as one communication interval. This communication interval and a pause interval of a constant period are repeatedly transmitted in synchronism with the vertical synchronizing signal VD as shown in Fig. 2. There are thus two transmission areas P
and P2 for the slave apparatus, so that there are fewer slave apparatus transmission areas than thare are slave stations. The transmissions from the slave apparatus are carried out by using a vacant one of the areas P1 and P2 as described below.
One bit at the beginning of each of the areas P1, P2, P3 and P4 is reserved for a start bit, which is produced only by the VTR 10 that is used as the master apparatus and by which the reception and the transmission between the master apparatus and the slave apparatus can be carried out.
That is, the communication controller 112 produces four start bits SB in one communication interval during each cycle.
Serial data Do to D7 of 8 bits are transmitted in each of the transmission and receiving areas Pl to P4 and the data Do to D7 of 8 bits constitute one word. Since one communication interval is formed of four communication areas P1 to P4, four data words are received and transmitted during one vertical period TF. The word number and the bit number within the communication interval are made constant so that the length of the communication interval becomes constant. Thus the length o~ the pause interval is also constant.
The transmission and reception within one communication interval is carried out as follow~. First the transmission from the master apparatus will be described.
While in Fig. 2 transmission from the master apparatus is carried out after the transmission from the slave apparatus is carried out, the sequential order of the transmission and the reception does not cause any problems if it is determined in advance.
The microcomputer 110 of the master apparatus generates a communication start signal CS (shown in Fig. 3A) which is then supplied to the communication controller 112.
The communication start signal CS is normally n 1" and falls off to "0" when the communication start request is generated. In this embodiment, the communication start signal CS falls to n o n four times during one vertical period TF. When the communication start request is generated, the communication controller 112 produces the start bit SB
(shown in Fig. B) that becomes "1" during a period of one bit or predetermined duration of time equal, for example, to 104 ~sec. The period during which the start bit SB is high begins when the communication start signal becomes low.
This start bit S8 is supplied to the base of the output transistor 116 and then is supplied to the communication line 30 which is connected with the collector of the output transistor 116 as a signal "0`' whose polarity is inverted.
The communication controller 112 gènerates 8 clock pulses CLK (shown in Fig. 3C) having a clock cycle or pulse period eaual to 104 ~sec. The firstl~ ~ ulses commences at a time coincident with ~he falling edge of the start bit SB, These pulses CLK are supplied to the clock terminal CK o~ the shift register 111. ~he control signal Gl (shown in Fig. 3D) for the output switch 114 becomes "1"
during the period of 8 clock pulses CLK, and the output transistor 114 is turned on during this period of "1", Since transmission data DTl ~shown in Fig. 3F) is already stored in the shift register 111 by the microcomputer 110, the-~8-bit transmission data DTl is read out from the shift register 111 by the 8 clock pulses CLK and then is supplied through the output switch 11~ and the output transistor 116 to the communication line 30. Fig. 3G shows the state of the signal on the communication line 30.
When the 8-bit transmission data DTl is transmitted, the output witch 114iis turned off so that the communication line 30 is pulled up to "ln. The period of "1" lasts for a time equal to the duration of 2.5 to 5 bits, and the period of 2.5 to 5 bits constitutes an end bit (refer to Figs. 2 and 3G). Such end bits are usually selected to be about two normal bits in duration. In this embodiment, however, in order to afford sufficient time for the microcomputer to perform all operations specified by the software, including latching and/or storing the communication data in a RAM (random access memory) of the microcomputer, the stop bit is extended so that it is longer than a normal bit.
The data transmitted from the master apparatus in the transmission area as mentioned above is supplied to, for example, the base of the input transistor 215 provided in the slave apparatus such as the video camera 20. The input 1309~92 transistor 215 is turned off at the start bit SB so that the collector output rises to "1". The communicatlon controller 212 de~ects this condition, and the control signal G1' ~Fig.
3I) for the input switch 213 rises to "1" and ~ clock pulses CLK' (Fig. 3K) each having a cycle 104 ~sec in length are produced, whereby the input switch 213 i9 turned on and the clock pulse CLK' is supplied to the clock terminal CK o the shift register 211. As a result, the tran~mission data DT
from the VTR 10 is latched in the shift register 211. The data latched in the shift register 211 is then transmitted to and stored in the RAM (not shown) of the microcomputer 210 during the stop bit period, and data DT2, which is to be transmitted from the video camera 20 to the VTR 10, is set in the shift register 211.
Although the data DT1 is latched in other slave apparatus simultaneously, whether or not the other slave apparatus use the data DTl is determined by their microcomputers by interpreting the content of the data DTl.
The receiving area for the master apparatus, or the transmission from the slave apparatus will be described next.
When the video camera 20 issues the transmission command and a transm~ssion demand signal DM (Fig. 1) is supplied to the communication controller 212, the video camera 20 is set in a transmission standby mode and the transmission data DT2 (the right-hand side of Fig. 3H) is stored in the shift register 211.
Under this state, the start bit SB (Fig. 3B) is generated by the communication controller 112 of the VTR 10 at the beginning of the area P1 (Fig. 2) and the start bit SB is transmitted through the transistor 116 (Fig. l) and 1~
the communication line 30 to the video came ~ 32~9 4~n, as shown in the right-hand side of Fig. 3G, the data on the transmission line 30 becomes "0" durin~ one blt period. As a result, the input transistor 215 of the video camera 20 is turned off and the collector output thereof becomes "1".
Since the communication controller 212 detects this condition and the control signal G2' ~Fig. 3J) for the output switch 214 becomes "1", the output switch 214 is turned on and the 8 clock pulses CLK' are generated during the period in which the signal G2' is "1". The 8 clock pulses CLK' are fed to the clock terminal CR of the shift register 211. Consequently, the data DT2 is read out from the shift register 211 (refer to Fig. 3~) and is fed through the output transistor 216 to the communication line 30.
After the start bit Ss is generated by the communication controller 112 of the VTR 10, the control siqnal G2 (Fig. 3E) for the input switch 113 becomes "1" so that the input switch 113 is turned on and the 8 clock pulses CLK (Fig. 3C) are generated during the period in which the signal G2 becomes n 1 n .
Accordingly, the data DT2 transmitted from the video camera 20 is supplied through the input transistor 115 and the switch 113 to the shift register 111 and stored in the shift register 111 on the basis of the clock pulse CLK.
The data DT~ is then transferred to and stored in the RAM of the microcomputer 110 during the end bit period of the transmission area Pl.
In the case described above the first area Pl in the communication interval is not used as a transmission area by other slave apparatus. Interference between two slave apparatus competing to use the same transmission area -t~-is avoided by causing one of the slave apparat ~ ~ ~ ~smit in the next area P2. In other words, certain transmission areas are reserved for transmisslons made b~ the various slave apparatus, and these areas are respectively allocated to individual ones of the slave apparatus on a first-come, first-served basis.
Fig. 4 is a flow chart representing a program used for such purpose. The program routines conforming with the flow chart of Fig. 4 are executed by the microcomputer of the control section of each slave apparatus.
When the start bit SB is transmitted from the master apparatus to each slave apparatus at the beginning of the area Pl, the slave apparatus having the transmission request command transmits the transmission data to the communication line 30 (step 101) in the transmission area Pl. At that time, the state of the data transmitted to the communication line 30 and the state of the communication line 30 are compared at every bit (step 102). More specifically, if the transmission data is ~0", the output transistor 216 is in the off state so that the communication line 30 must be placed in the state of 5V, while if the transmitted data is "1", the output transistor 216 is turned on so that the communication line 30 must be placed in the state of OV.
However, when data are transmitted from a plurality of slave apparatus, if the data bit from any one of the slave apparatus becomes "1", since its output transistor 216 is turned on, the communication line 30 is lowered to OV regardless of the data of other slave apparatus. Accordingly, when the communication line 30 becomes oV while the bit of the transmitted data is "0~, an , --~0--inconsistency exists between the data as transmitted and the .. .
data as monitored on the communication line 30. This inconsistency is detected by tho microcomputer o~ the control section of the slave apparatus (step 1031 and signifies the simultaneous transmission by other slave apparatus through the same area Pl. From the preceding description, it is apparent that when two or more slave apparatus simultaneously transmit data through the same transmission area, the slave apparatus whose transmission data bit Do to D7 transmits "l" first is given priority and the corresponding area is assigned as the transmission area of that slave apparatus. Then, in the slave apparatus in which it is detected that the data as transmitted and the data on the communication line 30 are different from each other at a given bit, the succeeding bits are all set tonO", whereby to prevent the data of the slave apparatus preempting the area Pl from being transmitted incorrectly.
The slave apparatus which could not transmit data through the area Pl again transmits data on the basis of the start bit SB which occurs at the beginning of the area P2 (step 104). A determination whether or not the area P2 is vacant is made in the same way as earlier noted at steps lO5 and 106. If the area P2 is vacant, it is selected as the transmission area of that slave apparatus. If on the other hand it is occupied, a determination whether or not the area Pl is vacant described above is made again in the next cycle. The operation described above is repeatedly carried out until a vacant area is detected.
Fig. 5 schematically illustrates these operations.
In Fig. 5, a slave apparatus I (for example, a tuner) and another slave apparatus II (for example, an editing . . .
-apparatus) compete with each other with respect to the transmission demand in the area P1 and the editlng apparatus as the slave apparatus II transmi9sion switches into the area P2. The master apparatus (VTR) receives in areas P
and P2 and transmits in the areas P3 and P4. Both slave apparatus receive in areas P3 and P4. Both atte~pt to transmit in the area Pl ~left half of Fig. 5). The tuner preempts the area P1 and the editor then switches to the area P2 (right half of Fig. 5).
The checking of the area at every bit can be performed easily by the shift register 211, which is formed as a 9-bit shift register. In practice, since the shift register that the 4-bit microcomputer incorporates therein is of a 9-bit type, such shift register can be used without modification.
During the pause or stop interval next following the communication interval formed of the four areas P1 to P4, the data processing based on the content of the received data is carried out by the VTR 10, the video camera 20 and other slave apparatus, and other processing is carried out in a time division manner.
As described below, the communication interval including the transmission from the VTR 10 and the transmission from the slave apparatus such as the video camera 20 and the like into one block is repeated cyclically, the pause interval being interposed therein. In this embodiment, since the start bit SB is generated only by the master apparatus and the time control is carried out by the master apparatus, the areas Pl to P~ can be discriminated surely and the communication interval and the .. . .
pause interval can be reliablv distinguished from each -other .
These operations are execute~ i3n0~c4c~ance with the followlng pro~ram routines of the microcomputer of the VT~ 10 and the video camera 20.
Fig. 6 is a flow chart of the program steps for the VTR 10, in which steps 201 to 209 are executed sequentially and repeatedly. In steps 205 to 207, either the from the video camera 20 or the function key operation of the VTR 10 is ~iven priority, whereby the mode of the VTR
10 is determined. These steps 205 to 207 are used to prevent erroneous operation.
In step 209, data co~rrespondina to the key operation at the VTR 10 and data indicative of the mode of the VTR 10 designated by the remote control signal from the video camera 20 are generated; and data indicative of "no operation to be performed" is generated when there are no command and no mode to be transmitted to the video camera 20.
More particularly, step 201, the start SB is transmitted by the VTR 10 (master apparatus). At step 202, data is received. At step 203, the start bit SB is transmitted. At step 204, data is transmitted. At step 205, the received data is analyzed. At step 206, the operated function key of the VTR 10 is read. At step 207, the mode of the VTR 10 is determined. At step 208, the mode of the VTR 10 is displayed. At step 209, the data to be transmitted is generated. The program then recycles to step 201.
Fig. 7 is a flow chart of the program routine for the video camera 20, in which steps 301 to 308 are executed sequentially and repeatedly. In step 308, the tran ~ ~Q ~o~9 2 data is generated and stored in the register and the video camera 20 is set in the standby mode until the start bit i9 received. The transmission data is transmitted at step 304.
More particularly, step 301, the start SB is received by the video camera 20 (slave apparatus). At step 302, data is transmitted. At step 303, the start bit SB i9 received. At step 304, data is received. At step 305, the received data is analyzed. At step 306, the mode of the camera 20 is displayed. At step 307, the operated function key of the camera 20 is read. At step 308, the data to be transmitted is generated. The program then recycles to step 301.
The generation of the start bit and of the clock pulse in the communication controller 112 and the detection of the start bit and the generation of the clock pulse in the communication controller 212 may be carried out under the control of the microcomputers 110 and 210, respectively, or by other hardware, as those skilled in the art will understand.
The communication is carried out in synchronism with the vertical sync signal VD as described above. When an artificial sync signal is mixed into the vertical sync signal VD or the television channel is changed by the television tuner, the period of vertical sync signal is disordered temporarily. If the communication responds to the disorder of the vertical sync signal, the communication may be interrupted, or malfunctions may occur in processes or operations other than the communication.
_~4_ Therefore, the following operations arQ performed so as to cope with the disorder of the vertical synchronizin~ signal.
The follo~ing data processing is executed by the software program of the microcomputer 110 of the VTR 10 that is used as the master apparatus for communica~ion.
The VTR 10 is set ~n the standby mode, in which lt is momentarily inoperative, after a period S that begins at the leading edge of the vertical sync signal VD (Fig. 8A) and that is selected so that TF > S. The period S may be, for example, 15 msec (see Fig. 8B). More specifically, the communication interval begins at the leading edge of the vertical sync signal VD, and the pause or stop interval, in which operations other than communication are performed, begins at the end of the period S. These other operations are interrupted until the time S is passed from the leading edge of the vertical sync signal VD. The normal complete cycle is 16.7 msec.
The vertical sync signal VD is not disordered, the following vertical sync signal VD arrives at the end of the time TF, whereby the VTR 10 is released from its waiting mode and the communication begins (see Fig. 8B). This operation is repeated indefinitely.
Generally, if the maximum waiting interval is taken as 2 ~S, the waiting mode is released at the midpoint thereof. That is, TF = S + Q S is approximately established. Theoretically, TF is a constant (16.66... msec = 1/60 sec), but actually it contains a periodic error ~T, as discussed below.
If the period of the vertical sync signal VD is disordered by channel selection and the like as shown in _q~_ `
1309492 .i~
Fig. 8A, whe~ the constant waitinq period 2~ S passes (Fig.
8B), the waiting mode i9 released and hence the communication begins. If the vertical sync signal VD
arrives before 3 msec passes ~ollow~ng the end of period S), the waiting mode is released upon its arrival; i.e., the waiting mode is released without waiting for the full 3 msec. Thus the VTR 10 is designed to follow the disorder of the period of the vertical sync signal VD if the time displacement of the vertical sync signal VD does not exceed + ~S. However, when the disorder of the period of the vertical sync signal VD is such that the time displacement thereof exceeds + ~S, the VTR 10 is not synchronized with the vertical sync signal VD for a certain time duration and the free-running cycle of duration S + 2 ~S that is determined by the microcomputer 110 continues. Thereafter, when the vertical sync siqnal VD again enters into the waiting period of 2 ~S, communication is started in synchronism with the vertical sync signal VD.
That is, when the vertical sync signal VD is disordered, a window having a width of + ~S is provided for the vertical period TF. Accordingly, disorder of the synchronization is known to exist when the vertical sync signal VD is outside this window. Then, until the vertical sync signal enters into the window, the communication is carried out at the free-running cycle of S ~ 2 a s. The time required by the VTR 1 n to return to synchronization with the vertical sync signal VD is determined by the width 2 ~S of the window. In Fig. 8 two successive vertical sync signals VD are shown to occur with a period Xl that deviates considerably from the norm. If the periodic error of the vertical sync signal VD is taken as + ~T where ~S ~ ~T and the displacement between the vertical sync signal VD and the ~`~ communication cycle after the channeL is changed is taken as X2, the following equation ~e9ults:
1309~92 X2 = (Xl + TF + QT) - (S + 2 ~ S) = Xl - {S + 2 ~S - (TF + ~T)}
= Xl - { (S + l~ S) - TF + ( ~ S + ~ T)}
= X~ S + ~T) (thus S + ~S = TF) The displacement is thus reduced by (~S + ~T) at e~ery period and hence in the worst case the vertical sync signal VD again enters into the window after a period of = 1 , and the VTR 10 is locked to the vertical ~S - QT
sync signal VD. These operations are carried out in accordance with the flow chart of Fig. 9. At step 401, the timer is cleared. At step 402, communication and other processes are carried out. At at step 4Q3, a determination is made whether or not the value registered by the timer has reached the starting point of the window. The determination is made repeatedly until the answer is yes. At step 404 a determination is made whether or not the sync signal has arrived. If so the program loops back to step 401. If not a determination is made at step 405 whether or not the value registered by the timer has reached the end point of the window. As long as the end point of the window has not been reached, the program loops back to step 404; when the end point of the window is reached, the program loops back to step 401.
As described above, when a P~L circuit is constructed by the software of the microcomputer, the communication can be carried out in synchronism with the vertical sync siqnal VD. 1 3 0 9 ~ 9 2 Accordingl~ if the vertical sync signal VD i9 disordered rapidly or the sync signal is weakened to destroy the synchronization, free-running synchronization is established by the PLL circuit provided by the software of the microcomputer so that interruption of communication is prevented and the communication therefore follows the vertical sync signal VD.
Since the processing time for transmission and reception is provided by making the length of the end bit longer than the norm, the serial data can be read out and written easily by the software. In addition, with respect to the hardware, there is the advantage than an extra la~ch circuit is not required.
Further, this system is an excellent match for the RS-232C that is the communication interface standard widely used in apparatus of this kind. In the communication system of this embodiment, using the RS-232C system communication channel, the data can be read out only by voltage conversion.
Since the communication is carried out cyclically and can be free-running, the correct content of the communication is restored immediately in case of a dropout or inadvertent error in the communication.
Furthermore, only the transmission line is needed, an expensive interface is not used, the communication and related functions can all be carried out by a one-chip microcomputer, and bidirectional digital data communication can be realized by inexpensive home LSIs.
In addition, since synchronization of the 13 b 9 4 ~ 2 communicatlon is established by the master apparatus, even whan a plurallty of operations A, 3, C and D ~Figs. lOA and lOB) in addition to the communication must be performed in a time division manner, it is poss~ble to prevent a given operation from being interrupted while ln progress.
~ hat i5, synchronizat~on o~ the communication i9 not established and an expensive interface is not employed, the communication may be carried out in the midst of one operation as shown in Fig. lOA so that other operations cannot be carried out. In this embodiment, since the synchronization of the communication is established by the master apparatus and other operations are carried out in the pause or stop interval of constant length, the control of the time division multiplexing processing became easy as shown in Fig. lOB. As a result, there is the advantage that the signal processing can be carried out by an inexpensive microcomputer.
In the embodiment described above, the communication is started in synchronism with the vertical sync signal VD itself; alternatively, communication may be started in synchronism with a signal synchronized with the vertical sync signal: for example, a signal indicative of the rotary phase of a rotary head and a switching signal for two rotary heads.
While the embodiment described above is the special case where communication can be realized by a single communication line, the present invention can be applied also to a case where two lines for transmission and reception, respectively, extend from the master apparatus to a plurality of slave apparatus.
l~hile in the embodiment described abovle a check is made at intervals or one bit to determine whether or not the transmission area is vacant, a check may be ma~e at intervals of, for example, one word ~8 bits).
If in the embodiment of Fig. 2 the earlier areas Pl and P2 are assigned as transmission periods of the slave apparatus and the later areas P3 and P4 are assi~ned as transmission periods of the master apparatus, only the start bit of the first half can always be transmitted cyclically, while the start bit of the second half can be transmitted only when data is transmitted from the master apparatus.
Further, if the reception of incoming data is carried out before the transmission of outgoing data, it is possible to reduce considerably the buffer memories that store the data in the communication controller 212 and the microcomputer 210 of the slave apparatus.
In accordance with the present invention, since the transmission from the slave apparatus is carried out by using a selected unoccupied area of the plurality of time division areas, the number of time division areas can be smaller than the number of slave apparatus; in addition, the unused areas are reduced and the efficiencv of use is increased. Furthermore, when the communication is carried out at a constant period, for example the vertical period, it is possible to prevent the length of the communication interval from becoming too long. Accordingly, it is possible to preserve the time necessary for carrying out operations other than communication during the stop mode interval.
Further, according to the present invention, since the communication is carried out periodically, if the communication is carried out once erroneously, the ~ 9 2 data is transmitted on the next occasion, whereby the erron~ous communication is restored t~ the correct one. In addition, according to the present invention, since the communication is carried out ln synchronism with a signal synchronized with the vertical sync signal, it is possible to transmit as communication da~a signals corresponding to the frame number and field of the video signal.
Furthermore, since the communication timing can be predicted, the design of the hardware of the peripheral apparatus and the main body is simplified.
In addition, since the communication is carried out in synchronism with the vertical period, the mixing of noise into the picture due to the communication or the like can be detected easily and the debugging period is reduced.
Thus there is provided in accordance with the invention a novel and highly effective method and apparatus for communication between vîdeo information apparatus, such as a VTR or video disc player, and peripheral apparatus, such as a tuner, a timer, a video camera, editing apparatus, a computer and so on. Many modifications of the preferred embodiment of the invention described above will readily occur to those skilled in the art without departing from the spirit or scope of the invention. Accordingly, the invention is defined by the appended claims only.
.
Claims (9)
1. A system for communicating between master video apparatus and peripheral apparatus wherein video signals having vertical sync signals are processed and said master video apparatus and said peripheral apparatus are connected with only one transmission line, said system comprising:
means for generating timing signals synchronously with said vertical sync signals;
means for establishing first communication intervals having a substantially constant phase relation with respect to said timing signals; and communication means for periodically and repeatedly effecting communication between said master apparatus and said peripheral apparatus through said one transmission line during said first communication intervals.
means for generating timing signals synchronously with said vertical sync signals;
means for establishing first communication intervals having a substantially constant phase relation with respect to said timing signals; and communication means for periodically and repeatedly effecting communication between said master apparatus and said peripheral apparatus through said one transmission line during said first communication intervals.
2. A system according to claim 1; further comprising:
means for establishing a window within which said timing signals normally appear;
detecting means for detecting the presence of said timing signals within said window;
free-running timing means for establishing second communication intervals; and means responsive to failure of said detecting means to detect said timing signals within said window for temporarily substituting said second communication intervals for said first communication intervals, whereby said communication temporarily takes place during the second communication intervals.
means for establishing a window within which said timing signals normally appear;
detecting means for detecting the presence of said timing signals within said window;
free-running timing means for establishing second communication intervals; and means responsive to failure of said detecting means to detect said timing signals within said window for temporarily substituting said second communication intervals for said first communication intervals, whereby said communication temporarily takes place during the second communication intervals.
3. A system according to claim 2; wherein said first and second intervals respectively have periods such that, in case of communication in said second intervals, said timing signals ultimately reappear within said window and said communication then takes place in said first intervals,
4. A system according to claim 1; wherein said first communication intervals are divided into separate transmission areas, a plurality of said transmission areas being reserved for transmission of communications by said peripheral apparatus, the number of said reserved areas being less than the number of said peripheral apparatus, and means whereby one of said peripheral apparatus can preempt one of said reserved areas for transmission therein.
5. A system according to claim 4; further comprising a transmission line connecting said master apparatus with each of said peripheral apparatus and wherein said means for preempting comprises means in each of said peripheral apparatus for monitoring the state of said transmission line, for comparing the state thereof with the data transmitted thereto, and for terminating transmission in said area in case of a discrepancy between the state of said transmission line and the state of data transmitted thereto.
6. A system according to claim 5; wherein said transmitted data consists of bits representing "0's" and "1's" and said transmission line assumes two states respectively in accordance with said "0's" and "1's", and in case of competing transmissions by two of said peripheral apparatus in the same transmission area, where one of said peripheral apparatus transmits a "0" and another of said peripheral apparatus transmits a "1", the state of said line follows a selected bit representing one of said "0" and "1"
in preference to the other, the one of said peripheral apparatus having transmitted the selected bit preempting said transmission area and the other of said peripheral apparatus yielding said transmission area.
in preference to the other, the one of said peripheral apparatus having transmitted the selected bit preempting said transmission area and the other of said peripheral apparatus yielding said transmission area.
7. A system according to claim 6; wherein transmission of a "1" by one of said peripheral apparatus grounds said transmission line, whereby simultaneous transmission of a "0" by any other of said peripheral apparatus results in an inconsistency between said data transmitted by such other of said peripheral apparatus and the state of said transmission line, causing said one of said peripheral apparatus to preempt said transmission area and said other of said peripheral apparatus to yield said transmission area.
8. A data communication method for communicating serial data between a master apparatus and a plurality of slave apparatus in a bidirectionalmanner comprising the steps of:
repeating cyclically a communication interval which is in synchronism with the vertical synchronizing signal of a video signal and which is formed of a plurality of separate communication areas, the number of said areas being less than the number of said slave apparatus;
reserving first selected ones of said areas for transmission by said master apparatus and second selected ones of said areas for transmission by saidslave apparatus; and respectively allocating said second areas to individual ones of said slave apparatus on a first-come, first-served basis.
repeating cyclically a communication interval which is in synchronism with the vertical synchronizing signal of a video signal and which is formed of a plurality of separate communication areas, the number of said areas being less than the number of said slave apparatus;
reserving first selected ones of said areas for transmission by said master apparatus and second selected ones of said areas for transmission by saidslave apparatus; and respectively allocating said second areas to individual ones of said slave apparatus on a first-come, first-served basis.
9. A method according to claim 8; wherein, within each of said intervals, said second selected areas precede said first selected areas.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59270042A JP2593842B2 (en) | 1984-12-21 | 1984-12-21 | Communication method and apparatus for video information equipment |
| JP280042/84 | 1984-12-21 | ||
| JP280077/84 | 1984-12-28 | ||
| JP28007784A JPS61158237A (en) | 1984-12-28 | 1984-12-28 | Data communication method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1309492C true CA1309492C (en) | 1992-10-27 |
Family
ID=26549038
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000498264A Expired - Lifetime CA1309492C (en) | 1984-12-21 | 1985-12-20 | Communication system for video information apparatus |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US4821032A (en) |
| EP (1) | EP0186468B1 (en) |
| AU (1) | AU590236B2 (en) |
| CA (1) | CA1309492C (en) |
| DE (1) | DE3580014D1 (en) |
| HK (1) | HK72894A (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4965825A (en) | 1981-11-03 | 1990-10-23 | The Personalized Mass Media Corporation | Signal processing apparatus and methods |
| USRE47642E1 (en) | 1981-11-03 | 2019-10-08 | Personalized Media Communications LLC | Signal processing apparatus and methods |
| US7831204B1 (en) | 1981-11-03 | 2010-11-09 | Personalized Media Communications, Llc | Signal processing apparatus and methods |
| JP2513182B2 (en) * | 1986-04-09 | 1996-07-03 | ソニー株式会社 | Digital video signal recording method |
| JPH02260997A (en) * | 1989-03-31 | 1990-10-23 | Toshiba Corp | Input/output switching circuit |
| US5099319A (en) * | 1989-10-23 | 1992-03-24 | Esch Arthur G | Video information delivery method and apparatus |
| DE4008967A1 (en) * | 1990-03-20 | 1991-09-26 | Thomson Brandt Gmbh | Communication system for colour television signals - switching and control functions can be operated or adjusted by several remote controls |
| JPH03295495A (en) * | 1990-04-13 | 1991-12-26 | Toshiba Corp | Timer device |
| FR2693066A1 (en) * | 1992-06-24 | 1993-12-31 | Philips Electronics Nv | Connection device between a television set and a peripheral device. |
| JPH06284216A (en) * | 1993-03-25 | 1994-10-07 | Sony Corp | Check and adjustment system for electronic device using telephone line |
| CA2258935A1 (en) * | 1997-04-30 | 1998-11-05 | Sony Corporation | Device and method for transmitting digital data |
| US6879347B1 (en) | 1999-12-30 | 2005-04-12 | Gateway, Inc. | Method and apparatus for communicating state information using vertical blanking interval |
| JP3937332B2 (en) * | 2003-03-11 | 2007-06-27 | ソニー株式会社 | Shooting system |
| JP5970748B2 (en) * | 2011-06-03 | 2016-08-17 | ソニー株式会社 | Moving image photographing system and synchronization control method |
| CN111123760A (en) * | 2019-11-22 | 2020-05-08 | 北京讯风光通信技术开发有限责任公司 | Communication bus method for realizing master-slave automatic control by utilizing determined time sequence |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4268722A (en) * | 1978-02-13 | 1981-05-19 | Motorola, Inc. | Radiotelephone communications system |
| JPS551622A (en) * | 1978-06-19 | 1980-01-08 | Sony Corp | Code signal reader |
| JPS551724A (en) * | 1978-06-19 | 1980-01-08 | Sony Corp | Video signal reproducing unit |
| GB2087194B (en) * | 1980-11-07 | 1985-09-11 | Victor Company Of Japan | Video signal recording/reproducing apparatus controllable via camera |
| JPS586635A (en) * | 1981-07-03 | 1983-01-14 | Matsushita Electric Ind Co Ltd | Signal transmission system |
| DE3210893C2 (en) * | 1982-03-25 | 1984-01-05 | Standard Elektrik Lorenz Ag, 7000 Stuttgart | Device arrangement with a television receiver and a Videdo recording and / or reproducing device |
| US4509073A (en) * | 1982-04-29 | 1985-04-02 | Packet Technologies, Inc. | Two-way cable-television system |
| JPS58205395A (en) * | 1982-05-25 | 1983-11-30 | Sony Corp | Remote control device |
| US4593282A (en) * | 1983-04-14 | 1986-06-03 | At&T Information Systems Inc. | Network protocol for integrating synchronous and asynchronous traffic on a common serial data bus |
| FR2552609B1 (en) * | 1983-09-27 | 1985-10-25 | Cit Alcatel | METHOD AND DEVICE FOR SELECTING A STATION FROM A SET OF STATIONS DIALOGUING WITH A MAIN STATION |
| US4628311A (en) * | 1983-10-19 | 1986-12-09 | International Business Machines Corporation | Carrier sense multiple access with collision avoidance utilizing rotating time staggered access windows |
| US4626847A (en) * | 1983-12-27 | 1986-12-02 | Zenith Electronics Corporation | Remote control transmitter system |
| US4570257A (en) * | 1984-02-14 | 1986-02-11 | Rosemount Inc. | Communication system with slot time error detection |
-
1985
- 1985-12-18 AU AU51403/85A patent/AU590236B2/en not_active Expired
- 1985-12-20 CA CA000498264A patent/CA1309492C/en not_active Expired - Lifetime
- 1985-12-20 EP EP85309334A patent/EP0186468B1/en not_active Expired
- 1985-12-20 DE DE8585309334T patent/DE3580014D1/en not_active Expired - Lifetime
- 1985-12-23 US US06/812,529 patent/US4821032A/en not_active Ceased
-
1991
- 1991-04-05 US US07/692,449 patent/USRE34650E/en not_active Expired - Lifetime
-
1994
- 1994-07-28 HK HK72894A patent/HK72894A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| EP0186468A3 (en) | 1987-06-16 |
| US4821032A (en) | 1989-04-11 |
| AU590236B2 (en) | 1989-11-02 |
| DE3580014D1 (en) | 1990-11-08 |
| EP0186468A2 (en) | 1986-07-02 |
| USRE34650E (en) | 1994-06-28 |
| HK72894A (en) | 1994-08-05 |
| AU5140385A (en) | 1986-06-26 |
| EP0186468B1 (en) | 1990-10-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1309492C (en) | Communication system for video information apparatus | |
| US3900887A (en) | Method of simultaneous multiplex recording of picture and data and of regenerating such record and apparatus therefor | |
| US4000510A (en) | System for storage and retrieval of video information on a cyclical storage device | |
| US4993003A (en) | Apparatus for updating time-of-day information in a signal | |
| CA1320271C (en) | Computer memory back-up with automatic tape positioning | |
| KR0180542B1 (en) | System and device for digital information transmission/reception and recording/reproducing | |
| US5150212A (en) | Control system for recording and reproducing a plurality of video signals | |
| US4991121A (en) | Image display system | |
| US4713702A (en) | Data communication apparatus | |
| EP0286857B1 (en) | Image signal processor | |
| JPH03243076A (en) | Audio/video system | |
| US5812209A (en) | Television device | |
| US4991013A (en) | Picture-in-picture television apparatus with sync controlled memory addressing | |
| EP0368313B1 (en) | Video tape recorder capable of receiving teletext broadcasting | |
| JPH01213853A (en) | Video tape recorder | |
| JP3080001B2 (en) | TV broadcasting system | |
| KR940008100B1 (en) | Communication system for video information apparatus | |
| GB2238925A (en) | Prior warning of programme change | |
| AU5534394A (en) | Method and apparatus for preprogramming a video cassette recorder | |
| WO1991015083A1 (en) | Apparatus and method for controlling a recording machine | |
| JPS6249791A (en) | Control data processing method for recording and reproducing device | |
| EP0448279B1 (en) | Control system for reproduction devices | |
| JP2575100B2 (en) | Data communication device and data communication method | |
| JPS61257025A (en) | Receiver | |
| KR900005066B1 (en) | Program reproducing circuit due to the signal source of broadcasting information |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |