CA1295745C - Method and apparatus for error correction - Google Patents
Method and apparatus for error correctionInfo
- Publication number
- CA1295745C CA1295745C CA000558190A CA558190A CA1295745C CA 1295745 C CA1295745 C CA 1295745C CA 000558190 A CA000558190 A CA 000558190A CA 558190 A CA558190 A CA 558190A CA 1295745 C CA1295745 C CA 1295745C
- Authority
- CA
- Canada
- Prior art keywords
- error
- correcting
- checking
- syndrome
- parity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/1515—Reed-Solomon codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
- H03M13/2909—Product codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
- H03M13/2927—Decoding strategies
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2948—Iterative decoding
Abstract
ABSTRACT OF THE DISCLOSURE
An error-correcting method and apparatus for a block of data provided with an error-correcting parity for error correction and an error-checking parity that can be used to generate a syndrome for error-checking, in which error correction is carried out by the use of the error-correcting parity and then an error check is carried out by the use of the error-checking parity thereby to increase the reliability of the error-corrected data, wherein error information produced by the error-correction process using the error-correcting parity is utilized to correct the syndrome used in the error-checking process, so as to execute the respective operations in parallel and reduce the required data processing time or through-put.
An error-correcting method and apparatus for a block of data provided with an error-correcting parity for error correction and an error-checking parity that can be used to generate a syndrome for error-checking, in which error correction is carried out by the use of the error-correcting parity and then an error check is carried out by the use of the error-checking parity thereby to increase the reliability of the error-corrected data, wherein error information produced by the error-correction process using the error-correcting parity is utilized to correct the syndrome used in the error-checking process, so as to execute the respective operations in parallel and reduce the required data processing time or through-put.
Description
BACRGROUND OF THE INVENTION
Field of the Invention This invention relates generally to a method and apparatus for error correction and, more particularly, ko a method and apparatus suitable for faithfullv and accurately reproducing data from each sector of a track on a disk-shaped recording medium, suc:h as a magneto-optic disk.
Descri~tion of the Prior Art There is already known a technique by which digital data is recorded on, and reproduced ~rom, a disk-shaped record medium, such as an optical disk, a hard magnetic disk, or the like. In general, digital data is recorded and reproduced along with some sort of error-correcting parity that serves to detect and correct data errors that might possibly occur during recording or reproduction. In such cases, a block-completion type data format is usually employed in which an error-correcting parity is produced for a predetermined number of the data samples in the block.
In addition, magneto-optic disks are now being used as a record medium. These are so-called erasable discs in which a laser is used to alter the magnetization o~ a magnetic layer exhibiting perpendicular anisotropy, for example, as described in U.S. Patent 4,610,009.
In the case where the data is intended for use in a computer, such data cannot be used at all unless it is correct and the user has faith in its accuracy. Thus, a parity code for checXing errors is also added to the data on ~,.
~p~ S03339 a block unit basis to check whether errors occur in the data and thereby to improve the fidelity of the data.
Fi~. 1 represents an example of such a data block, in which digital data is arranged in a memory in matrix form having m bytes in the row direction and n bytes in the column direction. A (k, m) code is produced for each element of m-byte data arranged in the row direction and k-m error detecting and correcting parities Cl are added to each of the data blocks in the row direction. Similarly, an (1, n) code is produced for each element of n-byte data arranged in the column direction and 1-n error detecting and correcting parities C2 are added to each of the data blocks in the column direction. The two error detecting and correcting parities, C1 and C2, form a product code.
In the product code represented in Fi~. 1, there is introduced into the last row of the data block, an error-checking parity or error-detecting code ~EDC) for a final check as to whether or not the data blocks contain errors. ~he error-checking parity EDC is produced by sequentially rsading the data from the uppermost row to the lowermost row and along the row direction.
Assuming in the above product code that the data read/write direction is in the row direction, error correction is effected first for the data block on each row by the use of the parity Cl and next for the data block on each column by the use of the parity C2. Errors can be gradually reduced by subsequently repeating the error-correcting process, however, i the error correction is performed to the limit of the error-correcting abilitv, there is the fear that the fidelity of the data mav be ~ S03339 degraded and, also, the required processing time becomes increasinglv longer. For this reason, it is usuall~ the case that continued repetitions of the error-correcting operation are stopped after a suitable number, and error-checking of the block of data, ~or which the error correction has been carried out, is effected by use of the error-checking parity EDC.
In the error-correcting process, as well in the error-checking process after error correction, as mantioned above, the reproduced data is temporarily written into a buffer memory in the form of the matri~ represented in Fig.
1. The written data is then sequentially read out from the buffer memory along the row direction, and the error correction is effected by the use of the parity Cl. After this error correction is finished, the data is sequentially read out in the column direction, while effecting the error correction using the parity C2. It has been found that it is possible to correct almost all errors by repeating the error correction process using the two parities C1 and C2.
When the error-correcting process is finished, the data is again sequentially read out from the buffer memory along the row direction to effect the error-checking process by using the error-checking paritv EDC. Thus, it is necessary once again to read the data from the buffer memory for the error check after the error correction, so that the processing time is further prolonged. This is a disadvantage in this error-correction process, which needs to read data from a memory a large number of times.
57~5 S03339 OBJECTS AND SUMMARY OF TE~E INVENTION
Accordingly, it is an object of the present invention to provide a method and apparatus for improving the through-put of the error-correction signal processing.
It is another object of the present invention to provide a method and apparatus that substantially i~prove the signal processing speed by reducing the numbex of times that data is read out from a memory.
According to a first as,pect of the invention, there is provided an error correcting method for checking whether or not an error occurs in a block of data that have been provided with an error-correcting parity for correcting an error and with an error-checking parity for checking the presence of an error by first effecting an error-correcting process using the error-correcting parity and next effecting an error-checking process using the error-checking parity.
This error-correc~ing method comprises the steps of:
a) producing an error-correcting syndrome during the error-correcting process;
b) producing an error-checking syndrome at the time the error-correcting syndrome is produced; and c~ amending the error-checking syndrome on the basis of error information produced during the error-correcting process, whereby a final error-checking syndrome will have been produced by the time the. error-checking process is completed and will be available to control the data output.
According to a second aspect of the invention, there is provided an errQr-correcting apparatus for checkihg whether an errox occurs in a block of data to which has been added an error-correcting parity for correcting an error and ~9~7 ~S S03339 an error-checking parity for checking an error by first effecting an error-correcting process using the error-correcting paritv and next effecting an error-checking process using the error-checking parity. This apparatus comprising:
a) an error-correcting syndrome generator ~or producing an error-correcting s~ndrome for an error-correcting operation;
b) an error-checking syndrome generator for producing an error-checking syndrome for an error-checking operation;
c) a detector for determining error information including an error location and an error value on the basis of the error-correcting syndrome produced by the error-correcting syndrome generator and for correcting an error based on the error information; and d) a syndrome modification circuit for amending an error-checking syndrome produced bv the error-checking syndrome generator on the basis of the error location and the error value, whereby a final error-checking syndrome for the error-checking operation will have been produced at the time the error-correcting process is finished.
These anZ other objects, features, and advantages of the present invention will become apparent from the following detailed description of the preferred embodiment taken in conJunc~ion with the accompanving drawings, throughout which like reference numerals designate like elements and parts.
- BRIEF DES~RIPTION OF THE DRAWINGS
Fig. 1 is a representation of an arranyement of data and a product code in the form of a data block;
, 3L2~
Figs. 2~ and B are repxesentations of a data format used with a disk-shaped recording medium;
Fig. 3 is a representation showing data arranged in a data block;
Fig. 4 is a schematic in block diagram form of an embodiment of the present invention; and Fig. 5 is a flow chart useful in explaining error-correcting and error-checking operations according to the present invention.
DETAI~ED DESCRIPTION OF A PREFERRED EM~ODIMEN~ .
In Figs. 2A and 2B the data format of a magneto-optic disk is shown, in which data is recorded on a track 12 that is concentrically or spirally formed on a magneto-optic disk 11 with one track per rotation, and is available to be subsequently reproduced from track 12.
Track 12 is formed of a plurality of segments or sectors of equal size in the circumferential direction and can comprise, for example, 32 sectors. On each sector there is recorded a predetermined amount of data with error-correcting and error-checking parities generated therefor. Each sector comprises a header area, a data area, and gap areas ~GAP) provided behind each respective header and data area ! as shown in Fig. 23.
The header area is-formed with a preamble signal or information at the beginning and following the preamble an address signal ADD, which consists of a track address data TA and a sector address data SA, an address synchronizing signal ASYNC, and an error-correcting parity ECC for the address signal are recorded twice.
~2~ s S03339 The data area is formed with a preamble signal at its beginning and a data sync word DSYNC, followed by the data with an error-correcting parity ECC and an error-checking parity EDC and the like generated specifically for that data.
In the present embodime!nt, if disk 11 is to be used for computer storage then a unit amount of data to be recorded in the data area of one sector is assumed to be 512 bytes.
The arrangement of the data area is shown in more detail in Fig. 3, in which there are 512 bytes of data, Do to D511, recorded in the data area. In addition to the actual data, an additional information area of 16 bytes is added to data Do to D511 to therebv form a matrix having 44 byte~ in the row direction and 12 bytes in the column direction, that is, a total of 528 (44 x 12~ bytes of data.
More specifically, a reserve of 12 bytes is provided immediately after the 512 bytes of data, Do - D511, for recording a track number, a sector number, data identification.information, and the like. Following those 524 bytes of data, which include the reserve region,. a 4-byte error-checking parity EDC in the row direction is provided and is allocated to the last 4-byte portion of this 16-byte additional information area~ The 4-byte error-checking parity EDC can be a Reed-Solomon code, for exampIe.
The 4-byte error-checking parity EDC is generated, taking as the source of GF (2 ) (Galois Field), so as to satisfy the following equations:
~ ~9~ S03339 n4iDi ~ 0 C~5iDi o ~ 6 iDi = O
o~7iDi = O
i=O
... (1) where N is 527 in this example.
Then, 4 bvtes of a first error-correcting code, for example, a (48, 44) Reed-Solomon code, which is the parity code C1, is added to each row of the 12 rows of the 528-byte data matrix, which includes the 4 bytes of the error-checking parity EDC. In the same manner, 2 bytes of a second error-correcting code, for example, a (14, 12) Reed-Solomon code, which is the parity code C2, are added to each of the 44 columns of the matrix.
Thus, a data block comprising 528 bytes is formed of 512 bytes of data, with 16 bytes o~ additional information relative to that data, and is arranged in a matrix of 12 rows and 44 columns. The parities Cl and C2 are generated and respectively added to each of the rows and columns to form a product code, which is recorded as one sector of the disk.
Am emhodiment of apparatus according to this invention by which the error-correcting and error-checking processes are effected on the above-mentioned data block is shown in Fig. 4 in bloc~ diagram form. A RAM 1 is used for storing or buffering data and the read and write timing of RAM 1 is controlled by a timin~ controller 3, which _9_ lZ9~ S03339 functionally is a microcomputer~ An address controller 2 i8 provided in conjunction with P~M 1 to provide writelreaa commands and address information at respective inputs on RAM
1. Switches 4 and 5 are respectively provided at the input and output sides of the RAM 1 and controlled by a change-over signal from timing controller 3. When the data reproduced from magneto~optic disk 11 is to be written into RAM 1, switch 4 is changed over t:o input contact A. Then, the data that was reproduced from the magneto-optic disk 11 and converted to a digital signal is supplied through an input terminal 6 and switch 4 to a data input terminal IN of RAM 1. In this case, the data from disk 11 is reproduced on a sector unit basis, as shown in Yig. 2A, for example, and this data is formed in a block, as shown in Fig. 3. RAM 1 is placed in a write-enable condition by a write/read control signal generated from address controller 2, so that the reproduced data can be sequentially written into RAM 1 based on a write-addresses specified by address controller 2. Thus, a block of data in the form of the matrix shown in Fig. 3 is formed in the memory (RAM).
When this aata writins process has been completed, error correction is first carried out and then error check is next effected. In this case, the error correction can be effected such that an error correction using the parity Cl and an error correction using the parity C2 are sequentially repeated, with the final error correction using the parity C~. According to this invention, when the error correction using the parity Cl is repeated at a predetermined time, for example, during the final error correction sequence, an error-checking syndrome is also produced at such time..
~295~5 S03~39 In performing the error corrections using the parities Cl and C2, switches 4 and 5 are respectively connected to contacts B and B' for the error correction using the parity Cl. Data stored in RAM 1 is read out along the row dixection, as shown in Fig. 3, and supplied through switch 5 to a first syndrome generator 7 that generates a syndrome for each row of the data matrix shown in Fig. 3.
If the data contains an error, a detectinq circuit 8 detects the relevant information concerning that error, that is, its location and value. ~he information on the error location and the error value is supplied to an error corrector 9 to correct the corresponding error. The data indicative of the error location from error information generator 8 is also supplied to address controller 2, so that the error data in each of the rows of the data matrix in RAM 1 can be pointed out by the address signal generated by address controller 2 and replaced with correct data supplied from error corrector 9.
After the error correction using the parity Cl has been completed, the error correction using the parity C2 is then effected. Switches ~ and 5 are connected to contacts C
and C', respectively, and data stored in matrix form in RAM
1 is read out along the column direction and supplied through switch 5 to a second syndrome generator 10, wherein a syndrome is proauced for each column of the data matrix shown in Fig. 3. If that data contains an error, an error information generator 11 generates the relevant information about the error, that is, its location and value. In the preceding operation, an error flag may be added to a row in which an error could not be corrected by the use of parity ~Z~7~5 S03339 Cl and such e.rror referred for error correction using the arity C2.
The information on the error location and the error value is supplied to an error corrector 12 to correct the erroneous data. The data inclicative of the error location is also supplied to address controller 2, 50 that the errors in the columns of the data matrix can be pointed out by address signals generated from address controller 2 and replaced with correct data supplied from error corrector 12.
The error corrections using the parities C1 and C2 are repeated a predetermined number of times, and the error-checking syndrome is produced during the last cycle of error corrections usin~ the parities C1 and C2.
This error-checking syndrome is produced as follows. When performing error correction using the parity Cl, switches 4 and 5 are connected to the contacts B and B', .respectively, to read out the data from RAM 1 along the row direction of the data matrix that is configured as represented in Fig. 3. The data thus read out is supplied to first syndrome generator 7 and also to a checking syndrome generator 13. Thus r at the time the error correction is effected on each row the error-checking svndrome can be simultaneously produced. When all the data has been read out from RAM 1, the error-checking syndrome generation will also be finished, however, this error-checking syndrome may include some errors, because it is based upon data that is obtained before error correction using the parity Cl has been effected. If the correct error-checking svndrome S is expressed by:
. , .
lZ 9'~ 7 ~ ~ S03339 /S,3~ ' S = S
.. S6 1 S7~ 2) the actually produced syndrome S' is:
s4' ~4iej 1~4ke; ,S4 S5 l C~ 5iej ¦ ~ 5ke j S5 S' = S6, = ~6ie; ~ ¦ ~6kej ~ ~6 s7l ~7iej l~7kej S7 ...(3) where j, k ... represent error locations ej, ek ...
represent error values, and S4, S5, S6 and 57 represent the syndromes.
Thus, if9~aiej and ~akek (a = 4, 5, 6, 7) included in S' are calculated and added bv modulo 2 addition with S', ~a~ej + ~aiej = 0, whereby S = S' is established and accordinglv the original error-checking syndrome that was generated is corrected to become a correct error-checking syndrome.
Thus, the correct error-checking syndr~me can be obtained by executing the following operations:
Upon performing an error correction using the parity code C1, the information on the error location and the error value detected by error information detecting circuit 8 is also supplied to a syndrome correcting h 12~3~7~ S03339 information detector 14, wherein information for correcting the produced syndrome is generated on the basis of the error location and error value supplied thereto from error information generator 8. The information on the error location in the respective rows is converted to positional information relative to the data numbered Do to D511 in the matrix. The above-mentioned error information ~aiej and o~akek ... ta = ~, 5, 6, 7) is calculated from the positional information and the error value. Then, the error information is supplied to a syn~1rome modifier 15 that also receives the error-checking syndxome produced by the error-checking syndrome generator 13. The syndrome modifier 15, which may comprise an exclusive OR, effects an addition of modulo 2, whereby the influence of the errors included in the syndrome as described above is removed. In other words, the error-checking syndrome is produced from data that has had its errors corrected by the use of the parity Cl.
When the error correction using the parity C2 is next effected, the information on the error location and the error value detec~ed by the error information detector 11 is also supplied to the syndrome correcting information generator 1~, wherein error information is produced on the basis of the information relating to the error location and the error value. The error information thus produced is supplied to the syndrome corrector 15, wherein the influence of the errors included in the data is removed, also as described above. In other words, the error-checking syndrome is effectively produced Crom data which has had its errors corrected bv the use of the parity C2.
~ S03339 The error-checking syndrome, which has been corrected by syndrome modifier 15, is supplied to a syndrome error-checking circuit 16 to make certain that the errors have been removed therefrom. The output signal from the syndrome error-checking circuit 16 indicates the checking results and is supplied to an enable terminal of a buffer amplifier 17, which may comprise a so-called three state buffer. The signal enables amplifier 17 when the checking result of syndrome error-checking circuit 16 shows that all errors have been removed, and the signal also disables amplifier 17 when the checking result shows that some error still remains.
After the error-correcting and error-checking processes have been completed, switch 5 is connected to contact A' to read out the error-corrected data, however, if any errors still remain after the error-checking process, the data cannot pass through the buffer amplifier 17 and accordingly cannot arrive at the output terminal 18.
Therefore, only data that is free from errors can be delivered to output terminal 18.
Alternatively, the data may be prevented from being read out from RAM 1 if the output from error-checking circuit 16 indicates the existence of a remaining error.
Fig. S is a flow chart of an e~ample of the above-descrlbed error-correcting and error-checking operations where the error corrections using the parities C
and C2 are each effected once. It will be noted after the first syndrome is generated based on parities Cl, that syndrome is modified and, subse~uently, after the second syndrome is generated based on parities C2 that syndrome is ~ z 9 ~ S03339 also modified based on the generated error value and location. In addition, although only one error correction cvcle is shown in Fig. 5 it will be appreciated that any number of iterations of this process can be performed, with the error-checking syndrome being generated and modified if necessary on the last cycle of er.ror-correcting.
In addition to the above-described embodiment a modification is possible in which the error-checking syndrome is produced the first time the error correction using the parity Cl is effacted and is amended on the basis of error values and locations generated during that first error correction, so that when error correction using the parity Cl is performed the second time, the error-checking syndrome is not produced but the previously produced error-checking syndrome is modified based on error values and locations generated during the second error correction.
Of course, the error-checking syndrome is also amended based on the error information derived from error loca~ions and error values generated during the error correction using the parity C2.
As described above, the error-checking svndrome is simultaneously produced when the error corrections using the paritY C1, which was added to the data arranged in the respective rows, and parity C2, which was added to the data arranged in the respective columns, are effected for the last time. Nevertheless, in an alternative.embodiment the error-checking syndrome may be produced at the same time error correction using the parity Cl is effected for the first time or at some other arbitrary time. In another ~9~ S03339 alternate embodiment, the error checking syndrome can be produced and modified based solely on the error information relating to the error locations and error values generated duxing the error correction using the parity C1, as well as on the basis of error locations and error values generated during the error corrections using both parities Cl and C2.
The error-checking parities are not limited to the above-mentioned Reed-Solomon codes, and other error detecting codes and error-correct:ing codes, such as a CRC
(cyclic redundancy check) code, may be employed.
According to the present invention, in the event that a block of data, which incll1des an error-correcting parity for correcting an error and an error-checking parity for checking an error, is subjected to error correction using the error-correcting code and then to error check using the error-checking parity so as to elevate the fidelity of the data whose error is corrected, an error-checking syndrome is produced simultaneously with the error correction using the error-correcting parity and is then modified on ~he basis of the error information (errox locations and error values) generated during the error correction usina the error-correcting parity. In this way, a final error-checking syndrome has already been produced at the time the error-correcting process is finished, so that it is not necessarv to provide a further process for producing the error-checking syndrome after the error-correcting process is finished, whereby the error correction through-put or signal processing rate can be improved.
~ 7 ~5 ~03339 The above description is given on a single preferred embodiment of the present in~ention but it will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spirit or scope of the novel concepts of the invention so that the scope of the invention should be determined by the appended claims only.
Field of the Invention This invention relates generally to a method and apparatus for error correction and, more particularly, ko a method and apparatus suitable for faithfullv and accurately reproducing data from each sector of a track on a disk-shaped recording medium, suc:h as a magneto-optic disk.
Descri~tion of the Prior Art There is already known a technique by which digital data is recorded on, and reproduced ~rom, a disk-shaped record medium, such as an optical disk, a hard magnetic disk, or the like. In general, digital data is recorded and reproduced along with some sort of error-correcting parity that serves to detect and correct data errors that might possibly occur during recording or reproduction. In such cases, a block-completion type data format is usually employed in which an error-correcting parity is produced for a predetermined number of the data samples in the block.
In addition, magneto-optic disks are now being used as a record medium. These are so-called erasable discs in which a laser is used to alter the magnetization o~ a magnetic layer exhibiting perpendicular anisotropy, for example, as described in U.S. Patent 4,610,009.
In the case where the data is intended for use in a computer, such data cannot be used at all unless it is correct and the user has faith in its accuracy. Thus, a parity code for checXing errors is also added to the data on ~,.
~p~ S03339 a block unit basis to check whether errors occur in the data and thereby to improve the fidelity of the data.
Fi~. 1 represents an example of such a data block, in which digital data is arranged in a memory in matrix form having m bytes in the row direction and n bytes in the column direction. A (k, m) code is produced for each element of m-byte data arranged in the row direction and k-m error detecting and correcting parities Cl are added to each of the data blocks in the row direction. Similarly, an (1, n) code is produced for each element of n-byte data arranged in the column direction and 1-n error detecting and correcting parities C2 are added to each of the data blocks in the column direction. The two error detecting and correcting parities, C1 and C2, form a product code.
In the product code represented in Fi~. 1, there is introduced into the last row of the data block, an error-checking parity or error-detecting code ~EDC) for a final check as to whether or not the data blocks contain errors. ~he error-checking parity EDC is produced by sequentially rsading the data from the uppermost row to the lowermost row and along the row direction.
Assuming in the above product code that the data read/write direction is in the row direction, error correction is effected first for the data block on each row by the use of the parity Cl and next for the data block on each column by the use of the parity C2. Errors can be gradually reduced by subsequently repeating the error-correcting process, however, i the error correction is performed to the limit of the error-correcting abilitv, there is the fear that the fidelity of the data mav be ~ S03339 degraded and, also, the required processing time becomes increasinglv longer. For this reason, it is usuall~ the case that continued repetitions of the error-correcting operation are stopped after a suitable number, and error-checking of the block of data, ~or which the error correction has been carried out, is effected by use of the error-checking parity EDC.
In the error-correcting process, as well in the error-checking process after error correction, as mantioned above, the reproduced data is temporarily written into a buffer memory in the form of the matri~ represented in Fig.
1. The written data is then sequentially read out from the buffer memory along the row direction, and the error correction is effected by the use of the parity Cl. After this error correction is finished, the data is sequentially read out in the column direction, while effecting the error correction using the parity C2. It has been found that it is possible to correct almost all errors by repeating the error correction process using the two parities C1 and C2.
When the error-correcting process is finished, the data is again sequentially read out from the buffer memory along the row direction to effect the error-checking process by using the error-checking paritv EDC. Thus, it is necessary once again to read the data from the buffer memory for the error check after the error correction, so that the processing time is further prolonged. This is a disadvantage in this error-correction process, which needs to read data from a memory a large number of times.
57~5 S03339 OBJECTS AND SUMMARY OF TE~E INVENTION
Accordingly, it is an object of the present invention to provide a method and apparatus for improving the through-put of the error-correction signal processing.
It is another object of the present invention to provide a method and apparatus that substantially i~prove the signal processing speed by reducing the numbex of times that data is read out from a memory.
According to a first as,pect of the invention, there is provided an error correcting method for checking whether or not an error occurs in a block of data that have been provided with an error-correcting parity for correcting an error and with an error-checking parity for checking the presence of an error by first effecting an error-correcting process using the error-correcting parity and next effecting an error-checking process using the error-checking parity.
This error-correc~ing method comprises the steps of:
a) producing an error-correcting syndrome during the error-correcting process;
b) producing an error-checking syndrome at the time the error-correcting syndrome is produced; and c~ amending the error-checking syndrome on the basis of error information produced during the error-correcting process, whereby a final error-checking syndrome will have been produced by the time the. error-checking process is completed and will be available to control the data output.
According to a second aspect of the invention, there is provided an errQr-correcting apparatus for checkihg whether an errox occurs in a block of data to which has been added an error-correcting parity for correcting an error and ~9~7 ~S S03339 an error-checking parity for checking an error by first effecting an error-correcting process using the error-correcting paritv and next effecting an error-checking process using the error-checking parity. This apparatus comprising:
a) an error-correcting syndrome generator ~or producing an error-correcting s~ndrome for an error-correcting operation;
b) an error-checking syndrome generator for producing an error-checking syndrome for an error-checking operation;
c) a detector for determining error information including an error location and an error value on the basis of the error-correcting syndrome produced by the error-correcting syndrome generator and for correcting an error based on the error information; and d) a syndrome modification circuit for amending an error-checking syndrome produced bv the error-checking syndrome generator on the basis of the error location and the error value, whereby a final error-checking syndrome for the error-checking operation will have been produced at the time the error-correcting process is finished.
These anZ other objects, features, and advantages of the present invention will become apparent from the following detailed description of the preferred embodiment taken in conJunc~ion with the accompanving drawings, throughout which like reference numerals designate like elements and parts.
- BRIEF DES~RIPTION OF THE DRAWINGS
Fig. 1 is a representation of an arranyement of data and a product code in the form of a data block;
, 3L2~
Figs. 2~ and B are repxesentations of a data format used with a disk-shaped recording medium;
Fig. 3 is a representation showing data arranged in a data block;
Fig. 4 is a schematic in block diagram form of an embodiment of the present invention; and Fig. 5 is a flow chart useful in explaining error-correcting and error-checking operations according to the present invention.
DETAI~ED DESCRIPTION OF A PREFERRED EM~ODIMEN~ .
In Figs. 2A and 2B the data format of a magneto-optic disk is shown, in which data is recorded on a track 12 that is concentrically or spirally formed on a magneto-optic disk 11 with one track per rotation, and is available to be subsequently reproduced from track 12.
Track 12 is formed of a plurality of segments or sectors of equal size in the circumferential direction and can comprise, for example, 32 sectors. On each sector there is recorded a predetermined amount of data with error-correcting and error-checking parities generated therefor. Each sector comprises a header area, a data area, and gap areas ~GAP) provided behind each respective header and data area ! as shown in Fig. 23.
The header area is-formed with a preamble signal or information at the beginning and following the preamble an address signal ADD, which consists of a track address data TA and a sector address data SA, an address synchronizing signal ASYNC, and an error-correcting parity ECC for the address signal are recorded twice.
~2~ s S03339 The data area is formed with a preamble signal at its beginning and a data sync word DSYNC, followed by the data with an error-correcting parity ECC and an error-checking parity EDC and the like generated specifically for that data.
In the present embodime!nt, if disk 11 is to be used for computer storage then a unit amount of data to be recorded in the data area of one sector is assumed to be 512 bytes.
The arrangement of the data area is shown in more detail in Fig. 3, in which there are 512 bytes of data, Do to D511, recorded in the data area. In addition to the actual data, an additional information area of 16 bytes is added to data Do to D511 to therebv form a matrix having 44 byte~ in the row direction and 12 bytes in the column direction, that is, a total of 528 (44 x 12~ bytes of data.
More specifically, a reserve of 12 bytes is provided immediately after the 512 bytes of data, Do - D511, for recording a track number, a sector number, data identification.information, and the like. Following those 524 bytes of data, which include the reserve region,. a 4-byte error-checking parity EDC in the row direction is provided and is allocated to the last 4-byte portion of this 16-byte additional information area~ The 4-byte error-checking parity EDC can be a Reed-Solomon code, for exampIe.
The 4-byte error-checking parity EDC is generated, taking as the source of GF (2 ) (Galois Field), so as to satisfy the following equations:
~ ~9~ S03339 n4iDi ~ 0 C~5iDi o ~ 6 iDi = O
o~7iDi = O
i=O
... (1) where N is 527 in this example.
Then, 4 bvtes of a first error-correcting code, for example, a (48, 44) Reed-Solomon code, which is the parity code C1, is added to each row of the 12 rows of the 528-byte data matrix, which includes the 4 bytes of the error-checking parity EDC. In the same manner, 2 bytes of a second error-correcting code, for example, a (14, 12) Reed-Solomon code, which is the parity code C2, are added to each of the 44 columns of the matrix.
Thus, a data block comprising 528 bytes is formed of 512 bytes of data, with 16 bytes o~ additional information relative to that data, and is arranged in a matrix of 12 rows and 44 columns. The parities Cl and C2 are generated and respectively added to each of the rows and columns to form a product code, which is recorded as one sector of the disk.
Am emhodiment of apparatus according to this invention by which the error-correcting and error-checking processes are effected on the above-mentioned data block is shown in Fig. 4 in bloc~ diagram form. A RAM 1 is used for storing or buffering data and the read and write timing of RAM 1 is controlled by a timin~ controller 3, which _9_ lZ9~ S03339 functionally is a microcomputer~ An address controller 2 i8 provided in conjunction with P~M 1 to provide writelreaa commands and address information at respective inputs on RAM
1. Switches 4 and 5 are respectively provided at the input and output sides of the RAM 1 and controlled by a change-over signal from timing controller 3. When the data reproduced from magneto~optic disk 11 is to be written into RAM 1, switch 4 is changed over t:o input contact A. Then, the data that was reproduced from the magneto-optic disk 11 and converted to a digital signal is supplied through an input terminal 6 and switch 4 to a data input terminal IN of RAM 1. In this case, the data from disk 11 is reproduced on a sector unit basis, as shown in Yig. 2A, for example, and this data is formed in a block, as shown in Fig. 3. RAM 1 is placed in a write-enable condition by a write/read control signal generated from address controller 2, so that the reproduced data can be sequentially written into RAM 1 based on a write-addresses specified by address controller 2. Thus, a block of data in the form of the matrix shown in Fig. 3 is formed in the memory (RAM).
When this aata writins process has been completed, error correction is first carried out and then error check is next effected. In this case, the error correction can be effected such that an error correction using the parity Cl and an error correction using the parity C2 are sequentially repeated, with the final error correction using the parity C~. According to this invention, when the error correction using the parity Cl is repeated at a predetermined time, for example, during the final error correction sequence, an error-checking syndrome is also produced at such time..
~295~5 S03~39 In performing the error corrections using the parities Cl and C2, switches 4 and 5 are respectively connected to contacts B and B' for the error correction using the parity Cl. Data stored in RAM 1 is read out along the row dixection, as shown in Fig. 3, and supplied through switch 5 to a first syndrome generator 7 that generates a syndrome for each row of the data matrix shown in Fig. 3.
If the data contains an error, a detectinq circuit 8 detects the relevant information concerning that error, that is, its location and value. ~he information on the error location and the error value is supplied to an error corrector 9 to correct the corresponding error. The data indicative of the error location from error information generator 8 is also supplied to address controller 2, so that the error data in each of the rows of the data matrix in RAM 1 can be pointed out by the address signal generated by address controller 2 and replaced with correct data supplied from error corrector 9.
After the error correction using the parity Cl has been completed, the error correction using the parity C2 is then effected. Switches ~ and 5 are connected to contacts C
and C', respectively, and data stored in matrix form in RAM
1 is read out along the column direction and supplied through switch 5 to a second syndrome generator 10, wherein a syndrome is proauced for each column of the data matrix shown in Fig. 3. If that data contains an error, an error information generator 11 generates the relevant information about the error, that is, its location and value. In the preceding operation, an error flag may be added to a row in which an error could not be corrected by the use of parity ~Z~7~5 S03339 Cl and such e.rror referred for error correction using the arity C2.
The information on the error location and the error value is supplied to an error corrector 12 to correct the erroneous data. The data inclicative of the error location is also supplied to address controller 2, 50 that the errors in the columns of the data matrix can be pointed out by address signals generated from address controller 2 and replaced with correct data supplied from error corrector 12.
The error corrections using the parities C1 and C2 are repeated a predetermined number of times, and the error-checking syndrome is produced during the last cycle of error corrections usin~ the parities C1 and C2.
This error-checking syndrome is produced as follows. When performing error correction using the parity Cl, switches 4 and 5 are connected to the contacts B and B', .respectively, to read out the data from RAM 1 along the row direction of the data matrix that is configured as represented in Fig. 3. The data thus read out is supplied to first syndrome generator 7 and also to a checking syndrome generator 13. Thus r at the time the error correction is effected on each row the error-checking svndrome can be simultaneously produced. When all the data has been read out from RAM 1, the error-checking syndrome generation will also be finished, however, this error-checking syndrome may include some errors, because it is based upon data that is obtained before error correction using the parity Cl has been effected. If the correct error-checking svndrome S is expressed by:
. , .
lZ 9'~ 7 ~ ~ S03339 /S,3~ ' S = S
.. S6 1 S7~ 2) the actually produced syndrome S' is:
s4' ~4iej 1~4ke; ,S4 S5 l C~ 5iej ¦ ~ 5ke j S5 S' = S6, = ~6ie; ~ ¦ ~6kej ~ ~6 s7l ~7iej l~7kej S7 ...(3) where j, k ... represent error locations ej, ek ...
represent error values, and S4, S5, S6 and 57 represent the syndromes.
Thus, if9~aiej and ~akek (a = 4, 5, 6, 7) included in S' are calculated and added bv modulo 2 addition with S', ~a~ej + ~aiej = 0, whereby S = S' is established and accordinglv the original error-checking syndrome that was generated is corrected to become a correct error-checking syndrome.
Thus, the correct error-checking syndr~me can be obtained by executing the following operations:
Upon performing an error correction using the parity code C1, the information on the error location and the error value detected by error information detecting circuit 8 is also supplied to a syndrome correcting h 12~3~7~ S03339 information detector 14, wherein information for correcting the produced syndrome is generated on the basis of the error location and error value supplied thereto from error information generator 8. The information on the error location in the respective rows is converted to positional information relative to the data numbered Do to D511 in the matrix. The above-mentioned error information ~aiej and o~akek ... ta = ~, 5, 6, 7) is calculated from the positional information and the error value. Then, the error information is supplied to a syn~1rome modifier 15 that also receives the error-checking syndxome produced by the error-checking syndrome generator 13. The syndrome modifier 15, which may comprise an exclusive OR, effects an addition of modulo 2, whereby the influence of the errors included in the syndrome as described above is removed. In other words, the error-checking syndrome is produced from data that has had its errors corrected by the use of the parity Cl.
When the error correction using the parity C2 is next effected, the information on the error location and the error value detec~ed by the error information detector 11 is also supplied to the syndrome correcting information generator 1~, wherein error information is produced on the basis of the information relating to the error location and the error value. The error information thus produced is supplied to the syndrome corrector 15, wherein the influence of the errors included in the data is removed, also as described above. In other words, the error-checking syndrome is effectively produced Crom data which has had its errors corrected bv the use of the parity C2.
~ S03339 The error-checking syndrome, which has been corrected by syndrome modifier 15, is supplied to a syndrome error-checking circuit 16 to make certain that the errors have been removed therefrom. The output signal from the syndrome error-checking circuit 16 indicates the checking results and is supplied to an enable terminal of a buffer amplifier 17, which may comprise a so-called three state buffer. The signal enables amplifier 17 when the checking result of syndrome error-checking circuit 16 shows that all errors have been removed, and the signal also disables amplifier 17 when the checking result shows that some error still remains.
After the error-correcting and error-checking processes have been completed, switch 5 is connected to contact A' to read out the error-corrected data, however, if any errors still remain after the error-checking process, the data cannot pass through the buffer amplifier 17 and accordingly cannot arrive at the output terminal 18.
Therefore, only data that is free from errors can be delivered to output terminal 18.
Alternatively, the data may be prevented from being read out from RAM 1 if the output from error-checking circuit 16 indicates the existence of a remaining error.
Fig. S is a flow chart of an e~ample of the above-descrlbed error-correcting and error-checking operations where the error corrections using the parities C
and C2 are each effected once. It will be noted after the first syndrome is generated based on parities Cl, that syndrome is modified and, subse~uently, after the second syndrome is generated based on parities C2 that syndrome is ~ z 9 ~ S03339 also modified based on the generated error value and location. In addition, although only one error correction cvcle is shown in Fig. 5 it will be appreciated that any number of iterations of this process can be performed, with the error-checking syndrome being generated and modified if necessary on the last cycle of er.ror-correcting.
In addition to the above-described embodiment a modification is possible in which the error-checking syndrome is produced the first time the error correction using the parity Cl is effacted and is amended on the basis of error values and locations generated during that first error correction, so that when error correction using the parity Cl is performed the second time, the error-checking syndrome is not produced but the previously produced error-checking syndrome is modified based on error values and locations generated during the second error correction.
Of course, the error-checking syndrome is also amended based on the error information derived from error loca~ions and error values generated during the error correction using the parity C2.
As described above, the error-checking svndrome is simultaneously produced when the error corrections using the paritY C1, which was added to the data arranged in the respective rows, and parity C2, which was added to the data arranged in the respective columns, are effected for the last time. Nevertheless, in an alternative.embodiment the error-checking syndrome may be produced at the same time error correction using the parity Cl is effected for the first time or at some other arbitrary time. In another ~9~ S03339 alternate embodiment, the error checking syndrome can be produced and modified based solely on the error information relating to the error locations and error values generated duxing the error correction using the parity C1, as well as on the basis of error locations and error values generated during the error corrections using both parities Cl and C2.
The error-checking parities are not limited to the above-mentioned Reed-Solomon codes, and other error detecting codes and error-correct:ing codes, such as a CRC
(cyclic redundancy check) code, may be employed.
According to the present invention, in the event that a block of data, which incll1des an error-correcting parity for correcting an error and an error-checking parity for checking an error, is subjected to error correction using the error-correcting code and then to error check using the error-checking parity so as to elevate the fidelity of the data whose error is corrected, an error-checking syndrome is produced simultaneously with the error correction using the error-correcting parity and is then modified on ~he basis of the error information (errox locations and error values) generated during the error correction usina the error-correcting parity. In this way, a final error-checking syndrome has already been produced at the time the error-correcting process is finished, so that it is not necessarv to provide a further process for producing the error-checking syndrome after the error-correcting process is finished, whereby the error correction through-put or signal processing rate can be improved.
~ 7 ~5 ~03339 The above description is given on a single preferred embodiment of the present in~ention but it will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spirit or scope of the novel concepts of the invention so that the scope of the invention should be determined by the appended claims only.
Claims (13)
1. An error-correcting method for checking whether an error occurs in a predetermined data arrangement that includes an error-correcting parity for correcting an error by effecting an error-correcting process by the use of said error-correcting parity and an error-checking parity for checking an error by effecting an error-checking process by the use of said error-checking parity, said error-correcting method comprising the steps of:
a) producing an error-correcting syndrome using said error-correcting parity during said error-correcting process;
b) producing an error-checking syndrome substantially simultaneously with said producing of said error-correcting syndrome; and c) amending said error-checking syndrome on the basis of error information produced during said error-correcting process, whereby an amended error-checking syndrome is finally produced by the time the error-correcting process is completed.
a) producing an error-correcting syndrome using said error-correcting parity during said error-correcting process;
b) producing an error-checking syndrome substantially simultaneously with said producing of said error-correcting syndrome; and c) amending said error-checking syndrome on the basis of error information produced during said error-correcting process, whereby an amended error-checking syndrome is finally produced by the time the error-correcting process is completed.
2. An error-checking method according to claim 1, wherein said error-checking parity is produced on the basis of a cyclic redundancy check (CRC) code.
3. An error-checking method according to claim 1, wherein said error-correcting parity is produced on the basis of a Reed-Solomon code.
4. An error-checking method according to claim 1, wherein said error information includes error location and error value.
5. An error-correcting method for checking whether an error occurs in a block of data formed of a predetermined number of data and error-checking parities for checking the presence of an error in said predetermined number of data, said block of data including error-correcting parities for respective data arranged in a predetermined direction by effecting an error-correcting process using said error-correcting parities, said method comprising the steps of:
a) producing an error-correcting syndrome for respective data arranged along said predetermined direction of said block of data;
b) producing an error-checking syndrome during the step of producing said error-correcting syndrome; and c) amending said error-checking syndrome using error information based upon said error-correcting syndrome produced during said error-correcting process, whereby an amended error-checking syndrome for use in a subsequent error-checking process is produced by the time the error-correcting process is completed.
a) producing an error-correcting syndrome for respective data arranged along said predetermined direction of said block of data;
b) producing an error-checking syndrome during the step of producing said error-correcting syndrome; and c) amending said error-checking syndrome using error information based upon said error-correcting syndrome produced during said error-correcting process, whereby an amended error-checking syndrome for use in a subsequent error-checking process is produced by the time the error-correcting process is completed.
6. An error-checking method according to claim 5, wherein said error-checking parity is produced on the basis of a cyclic redundancy check (CRC) code.
7. An error-checking method according to claim 5, wherein said error-correcting parity is produced on the basis of a Reed-Solomon code.
8. An error-checking method according to claim 5, wherein said error information includes error location and error value.
9. An error-checking method according to claim 1, wherein a second error-correcting parity is added to respective data arranged in a second direction different than said predetermined direction, and said error-checking syndrome is amended using error information based upon an error-correcting syndrome produced using said second error-correcting parity.
10. An error-checking method according to claim 9, wherein said predetermined direction is the row direction and said second direction is the column direction in said block of data.
11. An error-correcting apparatus for checking whether an error occurs in a predetermined array of data including an error-correcting parity for correcting an error by effecting an error correction process using said error-correcting parity and an error-checking parity for checking the presence of an error by first effecting an error-checking process using said error-checking parity, said apparatus comprising:
a) error-correcting syndrome producing means for producing from said error-correcting parity an error-correcting syndrome for correcting data errors;
b) error-checking syndrome producing means for producing from said error-checking parity an error-checking syndrome for checking the presence of data errors;
c) error-correcting means for calculating an error location and an error value on the basis of said error-correcting syndrome produced by said error-correcting syndrome producing means and for correcting an error; and d) syndrome amending means for amending an error-checking syndrome produced by said error-checking syndrome producing means on the basis of said error location and said error value, whereby an amended error-checking syndrome for the error-checking operation is produced by the time the error-correcting process is finished.
a) error-correcting syndrome producing means for producing from said error-correcting parity an error-correcting syndrome for correcting data errors;
b) error-checking syndrome producing means for producing from said error-checking parity an error-checking syndrome for checking the presence of data errors;
c) error-correcting means for calculating an error location and an error value on the basis of said error-correcting syndrome produced by said error-correcting syndrome producing means and for correcting an error; and d) syndrome amending means for amending an error-checking syndrome produced by said error-checking syndrome producing means on the basis of said error location and said error value, whereby an amended error-checking syndrome for the error-checking operation is produced by the time the error-correcting process is finished.
12. An error-correcting apparatus for checking whether an error occurs in a two-dimensional data array formed of a predetermined number of data and an error-checking parity for checking the presence of an error in said predetermined number of data, said data array including error-correcting parities added to respective data arranged in a predetermined direction, by effecting an error-correcting process using said error-correcting parities and effecting an error-checking process using said error-checking parity, said apparatus comprising:
a) error-correcting syndrome producing means for producing an error-correcting syndrome for respective data arranged in said predetermined direction of said two-dimensional array data;
(b) error-checking syndrome producing means for producing an error-checking syndrome based on data supplied to said error-correcting syndrome producing means for producing said error-correcting syndrome;
(c) error-correcting means for determining an error location and an error value on the basis of the error-correcting syndrome produced by said error-correcting syndrome producing means and for correcting an error; and (d) syndrome amending means for amending the error-checking syndrome produced by said error-checking syndrome producing means whereby a final error-checking syndrome for the error-checking process has been produced at the time the error-correcting process is completed.
a) error-correcting syndrome producing means for producing an error-correcting syndrome for respective data arranged in said predetermined direction of said two-dimensional array data;
(b) error-checking syndrome producing means for producing an error-checking syndrome based on data supplied to said error-correcting syndrome producing means for producing said error-correcting syndrome;
(c) error-correcting means for determining an error location and an error value on the basis of the error-correcting syndrome produced by said error-correcting syndrome producing means and for correcting an error; and (d) syndrome amending means for amending the error-checking syndrome produced by said error-checking syndrome producing means whereby a final error-checking syndrome for the error-checking process has been produced at the time the error-correcting process is completed.
13. An error-correcting apparatus according to claim 12, further comprising:
a) second error-correcting syndrome producing means for producing a second error-correcting syndrome for respective data arranged in a second direction different than said predetermined direction, said second error-correcting syndrome being based on a second error-correcting parity for respective data in said second direction and for correcting an error thereof; and b) second error-correcting means for calculating an error location and an error value on the basis of the second error-correcting syndrome produced by said second error-correcting syndrome producing means and correcting errors, whereby syndrome amending means also receives said error, location and error value from said second error-correcting means and said error-checking syndrome is amended also on the basis of error location and the error value derived by said second error-correcting means.
a) second error-correcting syndrome producing means for producing a second error-correcting syndrome for respective data arranged in a second direction different than said predetermined direction, said second error-correcting syndrome being based on a second error-correcting parity for respective data in said second direction and for correcting an error thereof; and b) second error-correcting means for calculating an error location and an error value on the basis of the second error-correcting syndrome produced by said second error-correcting syndrome producing means and correcting errors, whereby syndrome amending means also receives said error, location and error value from said second error-correcting means and said error-checking syndrome is amended also on the basis of error location and the error value derived by said second error-correcting means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP029351/87 | 1987-02-10 | ||
| JP62029351A JP2605271B2 (en) | 1987-02-10 | 1987-02-10 | Error correction and checking device |
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| Publication Number | Publication Date |
|---|---|
| CA1295745C true CA1295745C (en) | 1992-02-11 |
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ID=12273795
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000558190A Expired - Lifetime CA1295745C (en) | 1987-02-10 | 1988-02-04 | Method and apparatus for error correction |
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|---|---|
| US (1) | US4881232A (en) |
| EP (1) | EP0278700A3 (en) |
| JP (1) | JP2605271B2 (en) |
| KR (1) | KR880010403A (en) |
| AU (1) | AU604836B2 (en) |
| CA (1) | CA1295745C (en) |
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-
1987
- 1987-02-10 JP JP62029351A patent/JP2605271B2/en not_active Expired - Lifetime
-
1988
- 1988-02-04 CA CA000558190A patent/CA1295745C/en not_active Expired - Lifetime
- 1988-02-05 US US07/152,472 patent/US4881232A/en not_active Expired - Fee Related
- 1988-02-05 EP EP19880300997 patent/EP0278700A3/en not_active Ceased
- 1988-02-09 AU AU11468/88A patent/AU604836B2/en not_active Ceased
- 1988-02-09 KR KR1019880001183A patent/KR880010403A/en not_active Application Discontinuation
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| Publication number | Publication date |
|---|---|
| AU604836B2 (en) | 1991-01-03 |
| KR880010403A (en) | 1988-10-08 |
| JP2605271B2 (en) | 1997-04-30 |
| EP0278700A3 (en) | 1991-08-14 |
| EP0278700A2 (en) | 1988-08-17 |
| US4881232A (en) | 1989-11-14 |
| JPS63197123A (en) | 1988-08-16 |
| AU1146888A (en) | 1988-08-11 |
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