CA1289201C - Optical inverter and logic devices using same with the buffer limited electrical interface - Google Patents
Optical inverter and logic devices using same with the buffer limited electrical interfaceInfo
- Publication number
- CA1289201C CA1289201C CA000509778A CA509778A CA1289201C CA 1289201 C CA1289201 C CA 1289201C CA 000509778 A CA000509778 A CA 000509778A CA 509778 A CA509778 A CA 509778A CA 1289201 C CA1289201 C CA 1289201C
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- CA
- Canada
- Prior art keywords
- optical
- pair
- devices
- optical signal
- output
- Prior art date
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- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F3/00—Optical logic elements; Optical bistable devices
Abstract
ABSTRACT OF THE DISCLOSURE
OPTICAL LOGIC DEVICE AND ASSEMBLY
An optical logic device comprises a source of sub-stantially constant, incoherent, optical power. Optical signal output means such as a waveguide switch receives the optical power from the source and has two output ports. The waveguide switch is responsive to electrical control signals selectively to generate optical signals on its output ports.
A photodetector detects the logical condltion of an optical input signal and generates a corresponding electrical control signal for controlling the waveguide switch. The arrangement is such that the optical condition of the output port is the logical complement of the logical condition respresented by the optical input signal.
OPTICAL LOGIC DEVICE AND ASSEMBLY
An optical logic device comprises a source of sub-stantially constant, incoherent, optical power. Optical signal output means such as a waveguide switch receives the optical power from the source and has two output ports. The waveguide switch is responsive to electrical control signals selectively to generate optical signals on its output ports.
A photodetector detects the logical condltion of an optical input signal and generates a corresponding electrical control signal for controlling the waveguide switch. The arrangement is such that the optical condition of the output port is the logical complement of the logical condition respresented by the optical input signal.
Description
;o~
The invention relates to optical logic devices and assemblies for carrying out a logic function on an incident optical signal.
Optical logic i5 most often proposed u~ing active optical components such as bistable devices using laser diode6 and photodiodes, laser amplifiers operating with feedback to achieve bistability, ~elf electro-optic effect devices (SEED), holograms and liquid crystal light valves. Some optical logic devices have included wavegides which have a non-linear refractive index so that an incoming light signal switches between output paths in accordance with the intensity of the signal.
The main problems with these devices are their complexity and in some cases the need for feedback. Also, it is not easy to monitor the optical signals.
In accordance with the present invention, an optlcal logic device comprises an optical logic device comprises: a source of substantially constant optical power, optical signal output means to which the optical power is fed, the optical signal output means having at least one output port and being responsive to electrical control signals selectlvely to génerate optical signals on its at least one output port, optical signal input means to which an incoming optical signal is fed, and detection means for detecting an optical signal fed to the optical signal input means and for generating a corresponding electrical control signal limited in magnitude to a ,predetermined maximum value by a buffer limiting device and coupled to control the optical signal output means so ithat the optical condition of the output port 1~ changed in the opposite sense to the incoming optical signal.
According to a ~urther aspect of the invention in an optical signal inverter having an optical-electrical-opticai lnterface wherein an optical output signal i~ switched under control of an electrical control signal generated by detection of an incoming optical 8 i gnal, the improvement comprises: electrical signal buffering means for limiting the magnitude of the electrical control signal to no more than a predetermined maximum value which is below the value otherwise produced by incoming optical signal(s) in excess of a predetermined optical intensity.
This logic device i5 based on the principle of providing an electronic interface between the incoming optical signals and the outgoing optical signals. This means that no optical feedback i5 required and enables very fast component parts to be used. Potentially, very high speed~ may be obtained, po~sibly of the order o a few tens of pico seconds. The power consumption o~ the device may be only a few tens of mW at several GBit/s operating speeds. This should be compared with co~nercial ~CL which has typical power disslpation per gate of about 50mW but at only a few hundred MBits/s.
A fur~her advantage of the invention i8 that the optical power generation i~ xemote ~rom the other components of the device and thus the to~al dissipation is simply that of the detection means since in practice the dissipation of the optical signal output means will be negligible. Also, the operation of the device is not dependant upon the optical source wavelength to any marked degree. Elowever, it is preferable if the source generates an incohexent optical beam so that destructive interference does not occur at the optical signal output means.
The logical value of the input optical signal and the output optical signal will be determined by external factors. In the simplest case, the presence of an optical signal may represent one logical condition wh~le the absence of an opt~cal siqnal may represent the complementary logical condition. Alternatively, a non-zero threshold may be set so that optical signals having an intensity greater thaTI the threshold will represent one logical con~ition while optical signals having an intensity equal ~o or less than the threshold will represent the complementary condition. Furthermore, different definitions can be used for the input signals and the output signals.
Monitoring of the high speed optical signals may be achieved by fabricating low coupling ratio directional couplers in the optical paths where required. Such monitoring will not substantially compromise the logic 2~
circuit performance in contrast to what may occur wi~h electronic logic at very high speed, Preferably, the optical signal output means ha~ two output ports, the optical conditions of the output p~rts 5 ~eing changed in opposite sen~es ~n response to the same electrical control signals.
This is particularly advantageous since the device will then produce logically complemen~ary outputs automatically.
Preferably~, the optical signa1 output means comprises a wavequide ~witch.
The detection means may comprise a photodetector which is convenien~ly electrically connected to a buffer limiting device~ The advantage o~ providing a buffer limiting device w'ill be explained in more detail below.
The invèntion in its simplest form defined above comprises an optical inverter. Any logic function can be obtained by using a combination of inversion and combinillg functions and in one particularly convenient arrangement, the device further comprises optical signal coupling means for coupllng two input optical signals and for feedin~ the ~esultant coupled signal to the optical signal input means. This arrangement allows OR and NOR
functions to be obtainea. In this case, it 1~
advan~a~eous to provide a buffer llmiting device since when the input optical siynals both have a significant power value this could result in the detection means generating an undesira~ly high electrical control signal.
The buffer limiting device prevents this from happening.
The bas~c building block of the inven-tion can be used in a variety of ways to form more complex loqic assem~lie~. In one example of such a lo~ic assembly a conunoll 60urce of substantially constant optlcal power is provided, This is a partisularly advantageous feature 8~
which enables long signal delays to be avoided and simplifie6 the overall construction of the assen~ly.
In this specification the term optical is intended to refer to that part of the electro-magnetic spectrum which is generally known as the visible region together with those parts of the infra-red and ultra-violet regions at each of the visible region which are capable of being transmitted by dielectric optical waveguides such as optical fibre~.
The main advantages of the invention may be summarised as follows:-i there i~ no optical feedback for the basic gate functions .
ii it does not rely on bistability of optical device6 iii more complex logic functions are configurable rom the basic gate using simple fibre or waveguide interconnections.
iv it is conceivable tllat tlle optical logic block could be monolithically integrated.
In order that the invention may be better understood, two examples of loglc devices and an assembly including the devices accordingto the islvention will now be described with reference to the accompanying drawings, 25j in which:-Figure 1 is a schematic, perspective view of anoptical inverterS
Figure 2 illustrates an optical OR/NOR gate; and, Fiqure 3 illustrates a logic assembly providing 30 OR,NOR, ~ND and NAND functions.
The optical inverter shown in Figure 1 comprises a ~ase 1 on which is mounted a photodetector 2. An optical fibre or planar wavequide 3 carries an input optical signal "A" which is applied to the photodetector 2. The photodetector 2 i~ connected via electrical wires 4 with a current to voltage buffer clrcuit 5 which is conveniently provided with a voltage limiting capability.
The voltage buf~er circuit 5 is connected via electrical wires Ç to an optical waveguide switch 7 of conventional ~orm. A la~er assembly 8 generates an incoherer~t ~eam of optical radiation which i5 fed along an optical waveguide such as an op~ical f~bre 9 to one input port 10 of the wavegu~de sw~tch 7. The switch 7 has two output ports 11, 12 to which optical power received on the input port 10 i5 selectively coupled depending upon the potential di~ference on the wires 6.
' Electrical dc power is applied to the voltage buffer - circuit 5 via a voltage input 13.
The optical signals output fxom the ports 11, lZ are arranged to have logical conditions which are re~pectively complemental and the same as the logical condition of the input optical slgnal ~A". It is ~he optical signal output from the port 11 which is the more important since this iB the inverse or logical complement 20 O~ the input signal.
The transfer function and propagation delay of the inverter shown in Fiyure 1 are dependant upon the logic levels required. The power P from the laser assembly 8 is required to be as high as possible to minimise the buf~er circuit 5 complexity ~o that the propagation delay, .a critical parameter in lo~ic de~ign, is minimised.
If the switching voltage for the waveguide ~witch is V~, the photodetector responsivi~y is X and the buffer transresistance is T~ then the opt~ca~ logic power level Pl i~ given by., V W
P - g --XT
If Vs ~ 5. X - lA/W and T = 50n then Pl 3 l00mW
T~1is rather high level of optical power may be recluced if a hlgher buffer transresistance is prov~ded.
For instance for a transresistance of 50011 the optical power level reduces to l0mW. The u~e of a detector with scme internal gain, such as a photoconductor or avalanche p}1otodiode, may allow reduction o~ the required optical power or transresi~tance.
The progagation delay is the addition of the delay through the fibre or planar waveyuide inputs and outputs and the delay in the photodetector, buffer and switch.
To minimise this delay an optimisation i~ required to set values for the optical power level and transresistance.
The optical power (cw) could be generated in a high power cw laser or other light source and distributed to the inverters using fibres and/or planar waveguides.
A logic device ba~ed on the device shown in ~igure l i8 illustrated in Figure 2. The inverter o~ Figure l is indica-ted at 14 and it will be seen that the optical fibre 3 is coupled with an optical coupler 15 having two inputs connected to optical fibres 16, 17 respectively.
The assembly shown in Figure 2 operates on the two incoming optical signals "A" and "B1' so that the optical ~ignal output from the port ll represents A OR B. The output from th~ port l~ represents A NOR B.
It should be understood that in a simple case one logical condition will be repxesented by the absence of an optical signal while the other logical condition is represented by the presence of an optical signal.
The truth table for the assembly ~hown in Figure 2 i~ given below.
The invention relates to optical logic devices and assemblies for carrying out a logic function on an incident optical signal.
Optical logic i5 most often proposed u~ing active optical components such as bistable devices using laser diode6 and photodiodes, laser amplifiers operating with feedback to achieve bistability, ~elf electro-optic effect devices (SEED), holograms and liquid crystal light valves. Some optical logic devices have included wavegides which have a non-linear refractive index so that an incoming light signal switches between output paths in accordance with the intensity of the signal.
The main problems with these devices are their complexity and in some cases the need for feedback. Also, it is not easy to monitor the optical signals.
In accordance with the present invention, an optlcal logic device comprises an optical logic device comprises: a source of substantially constant optical power, optical signal output means to which the optical power is fed, the optical signal output means having at least one output port and being responsive to electrical control signals selectlvely to génerate optical signals on its at least one output port, optical signal input means to which an incoming optical signal is fed, and detection means for detecting an optical signal fed to the optical signal input means and for generating a corresponding electrical control signal limited in magnitude to a ,predetermined maximum value by a buffer limiting device and coupled to control the optical signal output means so ithat the optical condition of the output port 1~ changed in the opposite sense to the incoming optical signal.
According to a ~urther aspect of the invention in an optical signal inverter having an optical-electrical-opticai lnterface wherein an optical output signal i~ switched under control of an electrical control signal generated by detection of an incoming optical 8 i gnal, the improvement comprises: electrical signal buffering means for limiting the magnitude of the electrical control signal to no more than a predetermined maximum value which is below the value otherwise produced by incoming optical signal(s) in excess of a predetermined optical intensity.
This logic device i5 based on the principle of providing an electronic interface between the incoming optical signals and the outgoing optical signals. This means that no optical feedback i5 required and enables very fast component parts to be used. Potentially, very high speed~ may be obtained, po~sibly of the order o a few tens of pico seconds. The power consumption o~ the device may be only a few tens of mW at several GBit/s operating speeds. This should be compared with co~nercial ~CL which has typical power disslpation per gate of about 50mW but at only a few hundred MBits/s.
A fur~her advantage of the invention i8 that the optical power generation i~ xemote ~rom the other components of the device and thus the to~al dissipation is simply that of the detection means since in practice the dissipation of the optical signal output means will be negligible. Also, the operation of the device is not dependant upon the optical source wavelength to any marked degree. Elowever, it is preferable if the source generates an incohexent optical beam so that destructive interference does not occur at the optical signal output means.
The logical value of the input optical signal and the output optical signal will be determined by external factors. In the simplest case, the presence of an optical signal may represent one logical condition wh~le the absence of an opt~cal siqnal may represent the complementary logical condition. Alternatively, a non-zero threshold may be set so that optical signals having an intensity greater thaTI the threshold will represent one logical con~ition while optical signals having an intensity equal ~o or less than the threshold will represent the complementary condition. Furthermore, different definitions can be used for the input signals and the output signals.
Monitoring of the high speed optical signals may be achieved by fabricating low coupling ratio directional couplers in the optical paths where required. Such monitoring will not substantially compromise the logic 2~
circuit performance in contrast to what may occur wi~h electronic logic at very high speed, Preferably, the optical signal output means ha~ two output ports, the optical conditions of the output p~rts 5 ~eing changed in opposite sen~es ~n response to the same electrical control signals.
This is particularly advantageous since the device will then produce logically complemen~ary outputs automatically.
Preferably~, the optical signa1 output means comprises a wavequide ~witch.
The detection means may comprise a photodetector which is convenien~ly electrically connected to a buffer limiting device~ The advantage o~ providing a buffer limiting device w'ill be explained in more detail below.
The invèntion in its simplest form defined above comprises an optical inverter. Any logic function can be obtained by using a combination of inversion and combinillg functions and in one particularly convenient arrangement, the device further comprises optical signal coupling means for coupllng two input optical signals and for feedin~ the ~esultant coupled signal to the optical signal input means. This arrangement allows OR and NOR
functions to be obtainea. In this case, it 1~
advan~a~eous to provide a buffer llmiting device since when the input optical siynals both have a significant power value this could result in the detection means generating an undesira~ly high electrical control signal.
The buffer limiting device prevents this from happening.
The bas~c building block of the inven-tion can be used in a variety of ways to form more complex loqic assem~lie~. In one example of such a lo~ic assembly a conunoll 60urce of substantially constant optlcal power is provided, This is a partisularly advantageous feature 8~
which enables long signal delays to be avoided and simplifie6 the overall construction of the assen~ly.
In this specification the term optical is intended to refer to that part of the electro-magnetic spectrum which is generally known as the visible region together with those parts of the infra-red and ultra-violet regions at each of the visible region which are capable of being transmitted by dielectric optical waveguides such as optical fibre~.
The main advantages of the invention may be summarised as follows:-i there i~ no optical feedback for the basic gate functions .
ii it does not rely on bistability of optical device6 iii more complex logic functions are configurable rom the basic gate using simple fibre or waveguide interconnections.
iv it is conceivable tllat tlle optical logic block could be monolithically integrated.
In order that the invention may be better understood, two examples of loglc devices and an assembly including the devices accordingto the islvention will now be described with reference to the accompanying drawings, 25j in which:-Figure 1 is a schematic, perspective view of anoptical inverterS
Figure 2 illustrates an optical OR/NOR gate; and, Fiqure 3 illustrates a logic assembly providing 30 OR,NOR, ~ND and NAND functions.
The optical inverter shown in Figure 1 comprises a ~ase 1 on which is mounted a photodetector 2. An optical fibre or planar wavequide 3 carries an input optical signal "A" which is applied to the photodetector 2. The photodetector 2 i~ connected via electrical wires 4 with a current to voltage buffer clrcuit 5 which is conveniently provided with a voltage limiting capability.
The voltage buf~er circuit 5 is connected via electrical wires Ç to an optical waveguide switch 7 of conventional ~orm. A la~er assembly 8 generates an incoherer~t ~eam of optical radiation which i5 fed along an optical waveguide such as an op~ical f~bre 9 to one input port 10 of the wavegu~de sw~tch 7. The switch 7 has two output ports 11, 12 to which optical power received on the input port 10 i5 selectively coupled depending upon the potential di~ference on the wires 6.
' Electrical dc power is applied to the voltage buffer - circuit 5 via a voltage input 13.
The optical signals output fxom the ports 11, lZ are arranged to have logical conditions which are re~pectively complemental and the same as the logical condition of the input optical slgnal ~A". It is ~he optical signal output from the port 11 which is the more important since this iB the inverse or logical complement 20 O~ the input signal.
The transfer function and propagation delay of the inverter shown in Fiyure 1 are dependant upon the logic levels required. The power P from the laser assembly 8 is required to be as high as possible to minimise the buf~er circuit 5 complexity ~o that the propagation delay, .a critical parameter in lo~ic de~ign, is minimised.
If the switching voltage for the waveguide ~witch is V~, the photodetector responsivi~y is X and the buffer transresistance is T~ then the opt~ca~ logic power level Pl i~ given by., V W
P - g --XT
If Vs ~ 5. X - lA/W and T = 50n then Pl 3 l00mW
T~1is rather high level of optical power may be recluced if a hlgher buffer transresistance is prov~ded.
For instance for a transresistance of 50011 the optical power level reduces to l0mW. The u~e of a detector with scme internal gain, such as a photoconductor or avalanche p}1otodiode, may allow reduction o~ the required optical power or transresi~tance.
The progagation delay is the addition of the delay through the fibre or planar waveyuide inputs and outputs and the delay in the photodetector, buffer and switch.
To minimise this delay an optimisation i~ required to set values for the optical power level and transresistance.
The optical power (cw) could be generated in a high power cw laser or other light source and distributed to the inverters using fibres and/or planar waveguides.
A logic device ba~ed on the device shown in ~igure l i8 illustrated in Figure 2. The inverter o~ Figure l is indica-ted at 14 and it will be seen that the optical fibre 3 is coupled with an optical coupler 15 having two inputs connected to optical fibres 16, 17 respectively.
The assembly shown in Figure 2 operates on the two incoming optical signals "A" and "B1' so that the optical ~ignal output from the port ll represents A OR B. The output from th~ port l~ represents A NOR B.
It should be understood that in a simple case one logical condition will be repxesented by the absence of an optical signal while the other logical condition is represented by the presence of an optical signal.
The truth table for the assembly ~hown in Figure 2 i~ given below.
3~
~28~
TABLE
A B C
O O O
A logic assembly i~ illustrated in ~igure 3. This assembly comprises four optical lnverters similar to that shown in Figure 1 labelled 18-~1. The optical inverters 18, 19 receive input optical ~ignals ~ and generate corresponding logically complemental output siqnals A, A;
and B, B respectively. The A and B output signals are fed to an optical coupler 22 connected to th~ input port of the optical inverter 20. ~he outputs ~ and B are fed to an optical coupler 23 connected to an input port ~f the optical inverter 21. The optical inverters 20, -~1 have a total of four output ports whose logica~
conditions represent A OR B, A NOR B, A NAND B, and A AND
~ respectively.
In a modification ~not s}lown) the 6ignals A, B could be split prior to reaching the invertors 18, 19 and be ~ed additionally directly to the coupler 22.
The optical inverter forming the basic building block of the in~ention is simple and it m~y be possible to fabricate arrays of the {nverter~ which could be "hard ibred" ~or specific functions. Thi~ leads to the pos~ibility that an assembly ~uch as that shown in Figure 3 could be reprodu~ed as a monolithic array allowing a range of MSI or LSI functions to be achieved.
~28~
TABLE
A B C
O O O
A logic assembly i~ illustrated in ~igure 3. This assembly comprises four optical lnverters similar to that shown in Figure 1 labelled 18-~1. The optical inverters 18, 19 receive input optical ~ignals ~ and generate corresponding logically complemental output siqnals A, A;
and B, B respectively. The A and B output signals are fed to an optical coupler 22 connected to th~ input port of the optical inverter 20. ~he outputs ~ and B are fed to an optical coupler 23 connected to an input port ~f the optical inverter 21. The optical inverters 20, -~1 have a total of four output ports whose logica~
conditions represent A OR B, A NOR B, A NAND B, and A AND
~ respectively.
In a modification ~not s}lown) the 6ignals A, B could be split prior to reaching the invertors 18, 19 and be ~ed additionally directly to the coupler 22.
The optical inverter forming the basic building block of the in~ention is simple and it m~y be possible to fabricate arrays of the {nverter~ which could be "hard ibred" ~or specific functions. Thi~ leads to the pos~ibility that an assembly ~uch as that shown in Figure 3 could be reprodu~ed as a monolithic array allowing a range of MSI or LSI functions to be achieved.
Claims (12)
1. An optical logic device comprising:
a source of substantially constant optical power;
optical signal output means to which the optical power is fed, the optical signal output means having at least one output port and being responsive to electrical control signals selectively to generate optical signals on its at least one output port;
optical signal input means to which an incoming optical signal is fed; and detection means for detecting an optical signal fed to the optical signal input means and for generating a corresponding electrical control signal limited in magnitude to a predetermined maximum value by a buffer limiting device and coupled to control the optical signal output means so that the optical condition of the output port is changed in the opposite sense to the incoming optical signal.
a source of substantially constant optical power;
optical signal output means to which the optical power is fed, the optical signal output means having at least one output port and being responsive to electrical control signals selectively to generate optical signals on its at least one output port;
optical signal input means to which an incoming optical signal is fed; and detection means for detecting an optical signal fed to the optical signal input means and for generating a corresponding electrical control signal limited in magnitude to a predetermined maximum value by a buffer limiting device and coupled to control the optical signal output means so that the optical condition of the output port is changed in the opposite sense to the incoming optical signal.
2. A device according to claim 1, wherein the optical signal output means has two output ports, the optical conditions of the output ports being changed in opposite senses in response to the same electrical control signals.
3. A device according to claim 2, wherein the optical signal output means comprises optical coupling means having an input port to which optical power from the source is fed and which is adapted to couple different proportions of the optical power to the two output ports in response to the electrical control signals.
4. A device according to claim 3, wherein the optical coupling means couples substantially all the optical power from the source to respective ones of its output ports.
5. A device according to claim 4, wherein the optical coupling means comprises a waveguide switch.
6. A device according to claim 1, 2 or 3, wherein the detection means comprises a photodetector.
7. A device according to claim 1, 2 or 3, wherein the source generates an incoherent optical beam.
8. A device according to claim 1, further comprising optical signal coupling means for coupling two input optical signals and for feeding the resultant coupled signal to the optical signal input means.
9. An optical logic assembly comprising a first pair of devices according to claim 2 or 3, and a second pair of devices according to claim 8, the output ports of the first pair of devices being coupled with the optical signal coupling means of the second pair of devices such that the logic functions defined by signals generated on the output ports of the second pair of devices represent OR, NOR, NAND and AND respectively relative to the optical signals input to the first pair of devices.
10. An optical logic assembly comprising a first pair of devices according to claim 4 or 5, and a second pair of devices according to claim 8, the output ports of the first pair of devices being coupled with the optical signal coupling means of the second pair of devices such that the logic functions defined by signals generated on the output ports of the second pair of devices represent OR, NOR, NAND, AND respectively relative to the optical signals input to the first pair of devices.
11. An optical logic assembly comprising a plurality of devices according to claim 1, 2 or 3, wherein a common source of substantially constant optical power is provided.
12. An optical logic assembly comprising a plurality of devices according to claim 4, 5 or 8, wherein a common source of substantially constant optical power is provided.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB858513192A GB8513192D0 (en) | 1985-05-24 | 1985-05-24 | Optical logic devices |
| GB8513192 | 1985-05-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1289201C true CA1289201C (en) | 1991-09-17 |
Family
ID=10579643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000509778A Expired - Fee Related CA1289201C (en) | 1985-05-24 | 1986-05-22 | Optical inverter and logic devices using same with the buffer limited electrical interface |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4810050A (en) |
| EP (1) | EP0224542B1 (en) |
| JP (1) | JPS62502919A (en) |
| CA (1) | CA1289201C (en) |
| DE (1) | DE3676653D1 (en) |
| GB (1) | GB8513192D0 (en) |
| WO (1) | WO1986007166A1 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5130528A (en) * | 1991-03-01 | 1992-07-14 | International Business Machines Corporation | Opto-photo-electric switch |
| US5414789A (en) * | 1992-07-30 | 1995-05-09 | United States Of America | Optical logic gates with high extinction ratio using inverse scattering technique and method using same |
| US5493437A (en) * | 1993-09-13 | 1996-02-20 | Motorola | External communication link for a credit card pager |
| WO1996039221A1 (en) | 1995-06-06 | 1996-12-12 | Vincent Chow | Multi-phasic microphotodiode retinal implant and adaptive imaging retinal stimulation system |
| US6389317B1 (en) * | 2000-03-31 | 2002-05-14 | Optobionics Corporation | Multi-phasic microphotodetector retinal implant with variable voltage and current capability |
| US6427087B1 (en) * | 2000-05-04 | 2002-07-30 | Optobionics Corporation | Artificial retina device with stimulating and ground return electrodes disposed on opposite sides of the neuroretina and method of attachment |
| US7037943B2 (en) | 2001-04-10 | 2006-05-02 | Optobionics Corporation | Retinal treatment method |
| US20050033202A1 (en) * | 2001-06-29 | 2005-02-10 | Chow Alan Y. | Mechanically activated objects for treatment of degenerative retinal disease |
| US20050004625A1 (en) * | 2001-06-29 | 2005-01-06 | Chow Alan Y. | Treatment of degenerative retinal disease via electrical stimulation of surface structures |
| US7031776B2 (en) * | 2001-06-29 | 2006-04-18 | Optobionics | Methods for improving damaged retinal cell function |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL212435A (en) * | 1955-12-07 | |||
| GB1373956A (en) * | 1971-04-17 | 1974-11-13 | Plessey Co Ltd | Waveguide arrangements |
| JPS56137332A (en) * | 1980-03-31 | 1981-10-27 | Mitsubishi Electric Corp | Optical not circuit |
| JPS5936230A (en) * | 1982-08-24 | 1984-02-28 | Omron Tateisi Electronics Co | Optical logical circuit |
| JPS59222820A (en) * | 1983-06-01 | 1984-12-14 | Matsushita Electric Ind Co Ltd | Optical integrated circuit |
| JPS60263926A (en) * | 1984-06-12 | 1985-12-27 | Omron Tateisi Electronics Co | Optical exor circuit |
| JPS60263126A (en) * | 1984-06-12 | 1985-12-26 | Omron Tateisi Electronics Co | Optical logical circuit |
| JPS6142619A (en) * | 1984-08-03 | 1986-03-01 | Omron Tateisi Electronics Co | Optical coinciding circuit |
| JPS6142620A (en) * | 1984-08-03 | 1986-03-01 | Omron Tateisi Electronics Co | Optical exor circuit |
| JPS6186738A (en) * | 1984-10-03 | 1986-05-02 | Omron Tateisi Electronics Co | Optical 'or' circuit |
| JPS6188232A (en) * | 1984-10-08 | 1986-05-06 | Omron Tateisi Electronics Co | Optical and circuit |
| JPS6188233A (en) * | 1984-10-08 | 1986-05-06 | Omron Tateisi Electronics Co | Optical or circuit |
| JPS61121030A (en) * | 1984-11-16 | 1986-06-09 | Omron Tateisi Electronics Co | Voltage sensor of optical waveguide type |
-
1985
- 1985-05-24 GB GB858513192A patent/GB8513192D0/en active Pending
-
1986
- 1986-05-21 JP JP61502958A patent/JPS62502919A/en active Pending
- 1986-05-21 EP EP86903476A patent/EP0224542B1/en not_active Expired - Lifetime
- 1986-05-21 WO PCT/GB1986/000288 patent/WO1986007166A1/en active IP Right Grant
- 1986-05-21 US US07/006,668 patent/US4810050A/en not_active Expired - Lifetime
- 1986-05-21 DE DE8686903476T patent/DE3676653D1/en not_active Expired - Fee Related
- 1986-05-22 CA CA000509778A patent/CA1289201C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| EP0224542B1 (en) | 1990-12-27 |
| DE3676653D1 (en) | 1991-02-07 |
| JPS62502919A (en) | 1987-11-19 |
| GB8513192D0 (en) | 1985-06-26 |
| EP0224542A1 (en) | 1987-06-10 |
| WO1986007166A1 (en) | 1986-12-04 |
| US4810050A (en) | 1989-03-07 |
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| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |