CA1285077C - High speed interconnect unit for digital data processing system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A digital data processing system transfers information with an external device through an interconnect unit over a bus which includes separates sets of lines for transferring control information and transferring user information. The user information lines include a bidirectional information transfer lines and unidirectional antiparallel lines for transferring direction control signals and synchronization signals between the interconnect unit and the external device, the direction control signals identifying the direc-tion of transfer over the information transfer lines, and the synchronization signals identifying when the transmit-ting unit has transmitted the signals and when the receiving unit has latched the signals. The control information lines include unidirectional antiparallel lines for transferring control information and a synchronization signal. The syn-chronization signal is transmitted when control information signals are being transmitted on the control information lines.

Description

3'77 BAC~G~O~ND OF T~ INV~TION

1. Field of the In~entioD

The invention relates generally to the field of digital data proce~sing systems, and more specifically to high speed point-to-point interconnection apparatus for transferring data into or out of the ~ystem from or to an external device.

2. Description of the Prior Art A typical digital data processing system include3 three basic elements, namely H proce~sor element, a ~emory ele-ment, and an input/output element. The memory element stored information in addressable ~torage locstions. This information includes both data and instructions for proc-essing the data. The processor element includes one or more digital data processing unit~, each of which causes informa-tion to be transferred, or fetched, to it from the memory element, interpret3 the incoming information as either in-structions or data, and processes the data in accordance with the instructions. The result~ are then stored in ad-dressed locations in the memory element.

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The input/output ele~ent slso co~unicates with the ~e~ory element in order to transfer infor~ation into the system and to obtain the proce3sed data from it. Units com-prising the input/output ele~ent nor~ally operate in accord-ance with control informatioD supplied to it by the proc-es~or element. The control information defines the opera-tion to be performed by the input/output unit. ht least one class of operation~ perfor~ed by an input/output unit i8 the tran~fer of user infor~ation, that i~, information used by u~er program, between the input/output unit and the me~ory element. Typical units compri~ing the inputJoutput element include, for ex~ple, printers, teletypewriters, and video diRplay terminal3, and ~ay also include secondary informa-tion storage devices ~uch a8 di~k or tape storage units.
The input/output units msy also include point-to-point in-for~ation transfer units, that i~, interconnect units, for connection to, typically, one external device. An intercon-nect unit transfers infor~ation at a very high rate between the sy~tem and the external device. Illustrative external device~ include, for example, an array processor, a ~pecial scientific laboratory instrument or even another digital data processing syste~.

~ .S. Patent No. 4,319,323, entitled Communications Device For Data Proce~sing System, i~sued to Thoma~ R.
Er~olovich, et al., on March 9, 1982, and a~ig~ed to the asRignee of the present inVentioD, de'scribss ~n interconnect unit (ter~ed therein a "communication~ unit") for transfer-ring information between a digital data processing syRtem and an external device. The interconnect unit described in the patent connects to the external device over a bu~ which transfers information between two and only two device3, na~ely, the interconnect unit and the external device. The interconnect unit include~ a ~ection which tran~fers control information and a section which transfer~ user information.
As with control information provided by the processor to control an input/output unit9 the control information trans-ferred over the bus between the interconnect unit and the external device provides infor~ation about, and defines, the transfer of u~er infor~ation therebetween over the user in-formation tran~fer section.

One problem which has arisen with the interconnect unit de~cribed in the afore-mentioned patent is that the protocol for transferring information over the bus is a complex one, ;

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which ~ake~ it relatively difficult and expensive to con-~truct an external device that can connect t~ it.

For example, the u~er infor~ation tran~fer ~ection trRnsfer~ information ~ynchronou~ly, that i3, :;t includes a line which transfer~ a timing ~ignal which times the data as it i~ transferred between the two devices. In addition, the tran~fer section includes a plurality of wire~ for tran~fer-ring ~ignal~ between the interconnect unit and the external device relating to the current status of the unit~ in con-nection with the infor~ation tran~fer. In particular, the ~ignals indicate whether the units (a) are currently engaged in ~ data transfer and (b~ are currently able to transmit or receive data, while engaged in the transfer. ThHt i5, the ~ignal3 indicate whether or not the units are "st~lled". In a synchronous transfer, a information signals must be placed on the data lines by the tran3mitting unit and latched by the receiving unit with every tick of the tran~fer ~yn-chronizing signal~ However, in many circumstances, the transmitting unit may, because of delays it may have iD ob-taining information to tran3fer, have short periods of time during which it has no information to tran~mit. Similarly, the receiving unit ~ay be temporarily unable to take data which the transmitting device ha~ ready for it. If either of these were to occur, for exa~ple, in a transfer between memory and a dis~ or tape storage unit, ~n error would be noted by the disk or tape storage unit 9 and the transfer ~ould be aborted. The proces~or wo~ld then be interrupted, which may cause the transfer to be repeated. However, if the external device were one of certain types of scientific insruments, repeating the transfer ~ay not be po~sible or practical.

&UMMARY OF_T~ INY~N~ION

The invention provides a new and improved interconnect unit including a bus for transferrin~ infor~ation, including both control and user infor~ation, between the unit and R
~ingle external device, the bu~ having a simplified protocol fsr accommodating stalls in transferring information between the two unit~.

;
In brief, thç new interconnect unit connects to, ~nd tran~fers information with, an external device over a bus which has a control informatioD tran~fer section and a u~er information transfer aection. The user information tran~fer section include~ u~er infor~ation transfer line3 over which user in~ormation i~ tran3ferred. Prior to tran~ferring user information, the transmitting device asserts a direction ~ignal which indicate~ that it ~ill be transmitting u~er in-formation. Aftcr placing user information signals on cor-responding line~ of the bus, the trans~itting unit as~ert~ a synchroniæing signal to synchronize the information trans-fer. The ~ynchronizing signal enables the receiving unit to receive and latch the user information signals~ On receiv-ing the user information signals, the receiving unit a~3erts an acknowledgement ~ignal which indic~tes that it has received the user infor~ation word, which, in turn, allow~
the transmitting device to transmit further u~er information ~ignal B .

The interconnect unit transfers information over selected ones of the ~er informHtion tran~fer lines, to fa-cilit~te accommodation to external devices which do not tran~fer information ~ignals Dver all of the user informa-tion transfer lines at onç time. The interconnect unit pack~ the received information for transmisqion to the syste~ memory, or it unpacks the information which it receives from the system memory and tran~its it over the selected user information transfer line~.

- ~ ) 7~7 The control infor~ation transfer section includes two sets of lines each for tran3ferring control inf3r~stion un-idirectionally between one of the unit~ and the other. The sets of lines are antiparallel, that i3, one set transfers control information fro~ one unit to the second unit, and the other set transfers control information from the second unit to the fir~t. ~ach set of lines ha~ an associated syn-chronization ~ignal which, when a~serted, indicate~ to the receiving device that the state of the signals on the as~o-ciated control infor~ation transfer lines has changed. A
unit recei~ing the control information ~ignals and the ~yn-chronization signal ~ay u~e the strobing aignal to initiate latching of the control infor~ation ~ignals, or it ~ay alternatively ignore the ~ynchronization signal and con-tinuously ~onitor the control information line~ ~nd use the ~ignals tr~n~ferred thereover a~ indications of the ~tatu~
of the trans~itting unit.

The synchronizing signal/Qeknowledgement signal protocol of the user information tran~fer section allows the transmitting and receiving unit~ to stall, or temporarily stop, transferring user information while 8 transfer opera-tion is in progress, without a transfer error being processed.
The protocol of the control information transfer sec-tion permits the flexible use of the control information transfer lines.
The invention may be summarized, according -to one broad aspect as an interconnect unit for connection to a system kus in a digital data processing system including a memory for storing information and a processor means for controlling the system, said interconnect unit transferring information between the memory over said system bus and an external device over an external bus, said external bus including bidirectional information transfer lines for transferring information signals, antiparallel unidirectional direction control lines having selected conditions for transferr-ing direction control signals identifying a direction of transfer of information and antiparallel unidirectional synchronization lines for transferring synchronization signals, in response to ; commands from the processor means, said interconnect unit includ-ing: A. system transfer means for connection to said sys-tem bus for transferring information to or from said memory, B. external device transfer means including means for connection to said external bus for transmitting and receiving information over said external bus, and further including information transfer means connected to said system transfer means and for connection to said information transfer lines for transferring information between said system transfer means and said information transfer lines, said direc-tion control lines asserting a signal on one of said direction control lines and receiving a signal on a second of said direction control lines identifying a condition of -the direction - 8a - 72896-43 of transfer of information over said information transfer lines, said synchronization lines asserting a signal on one of said syn-chronization lines and receiving a signal on a second of said synchronization lines to synchronize the transfer of information over said information -transfer lines, and C. control means for operational control of the interconnect unit in transferring in-formation over said inEormation transfer lines, said control means including a first register enabling the transmission and reception of the direction control signals over the respective direction control lines to iden-tify the direction of transfer, said control means enabling -the selection of transmission or reception of in-formation signals over said information transfer lines responsive to the condition of said direction control signals, and said con-trol means for enabling a synchronization signal to identify: I.
when information signals are being transferred over said informa-tion transfer lines when said direction control signals indicate that information is being transferred to said external device to enable said external device to receive said information signals, or II. when information signals have been received from said information transfer lines when said direction con-trol signals indicate that information is being transferred from said external device.
According to another broad aspect, the invention pro-vides an external unit for connection to a digi-tal data processing system for transferring information with said data processing system over an external bus, said external bus including bidirec-tional information transfer lines for transferring information )77 - 8b - 72896-43 signals, antiparallel unidirectional direction control lines hav-ing selected conditions for transferring direction control signals and antiparallel unidirectional synchronization lines for tran-sferring synchronization signals, said external unit including:
A. external device transfer means including means for connection : to said external bus for transmitting and receiving information over said external bus, and further including information transfer means connected to said system transfer means and for connection to said information transfer lines for transferring information between said system transfer means and said information trans-fer lines, said direction control lines asserting a signal on one of said lines and receiving a signal on a second of said lines iden-tifying a condition of the direction oE transfer of informationover said information transfer lines, said synchronization lines asserting a signal on one of said synchronization lines and receiving a signal on a second of said synchronization lines to synchronize the transfer of information over said information transfer lines, and B. control means for operational control of the interconnect uni.t in transferring information over said infor-mation -transfer lines, said control means including a first re-gister enabling the transmission and reception of the direc-tion control signals over the respective direction con-trol lines to identify the direction o transfer, said control means enabling the selection of transmission or recep-tion of information signal over said information transfer lines responsive to the condition of said direction control signals, and said control means enabling a synchronization signal to identify when information signals re - 8c - 72896-43 being trans-ferred over said information transfer lines when said direction control signals indicate -that information is being transferred to said external device to enable said external device to receive said information signals, or when information signals have been received from said informa-tion transfer lines when said direction control signals indicate that informa-tion is being transferred from said external device.
BRIEF DESCRIPTIO~ OF THE DRAWI~GS
This invention is pointed out with particularity in the appended claims. The above and further advantages of this inven-tion may be better understood by referring to the following des-cription taken in conjunc-tion with the accompanying drawings, in which:
Fig. 1 is a block diagram o~ a digital data processing system including a new interconnect uni-t constructed in accordance with the invention;
Fig~ 2 is a block diagram of the interconnect unit depicted in Fig. 1;
Fig. 3 is a detailed diagram of the point-to-point interconnect for transferring information between the interconnect unit depicted in Fig. 2 and an external device;
Fig. 4, comprising Figs. 4A and 4B, depicts timing dia-grams useful in unders-tanding the transfer protocol for the inter-connect depicted in Fig. 3.;

~2~ 7~ 1 ~3-393 _g_ Fig. 5 depict3 certain data structures in the informa-tion trsns~er unit shown in Fig. 2.

D~T~IL~D DBSC~IPTIO~ OF ~ IL~UST~ATI~ BODIM~T

Referring to Fig. 1, a data processing ~yste~ iDcluding the invention includes, as ba~ic elements, a proce~sor 10, a ~e~ory 11 and one or more input~output u~it~ 12. A bu~ 13 interconnect~ the proces~or 10, me~ory 11 and input/output units 12 in parallel. The proces~or 10 executes instruc-tion3 that are atored in addres3able atorage locations in the memory unit 11. The instructions identify operationq that are to be per~ormed on Gperand~, which are al~o ~tored in addressHble locations in the memory unit. The instruc-tions and operands are fetched by the proce~sor 10 a~ they are needed, and processed data are returned for ~tor~ge in the ~e~ory 11. The proce~sor 10 al~o tran3mits control in-formation to the input/output units 12, enabling the~ to perform selected operation3, such a~ transmitting data to or retrieving data from the memory 11. Such data ~ay include instruction3 or operands which may be transmitted to the ~emory 11 or proces~ed data which is retrieved from the memory 11 for ~torage or display.

'7'7 An operators console 14 serve~ as the operator'~ inter-face. It allows the operator to exa~ine and deposit data, halt the operation of the processor 10 or step the processor 10 through a ~equence of iDstruction~ and determine the responses of the processor 10 in response thereto. It also enables an operator to initialize the sy~tem through a boot ~trap procedure, and perform various diagno~tic te~ts on the entire data processing ~yAtem.

The me~ory 11 include~ a ~emory controller 15, which i~
connected directly to the bus 13 and to a plurality of ar-rays 17. The arrays 17 contain a plurality of addressable ~torage location in which infor~ation i~ ~tored. The ~eDory controller 1~ receive~ tran~fer requests frDm the proce~sor 10 or from an input/output unit 12 over the bu~ 13. The ~emory controller 16 may receive several typeY of transfer reque.qts over bus 13, which fall into two general categories. In one category, information i~ written into, or stored in, a 3torage location, and in the other category, information i8 retrieved, or read, from a storage location.

The data processing system may include several types of input/output unit~ 12, including disk and tape secondary "7 ~torage unit83 teletypewriters, video di~play terminals, line printer~, telephone and c~mp~ter network unit~, snd the like. All of these units communicate with the bus 13 over e device bus through one or more bus adapter~. AB shown in Fig. 1, the disk drives 20 are connected to a ~econdary storage bus adapter 21 over a device bus 22. The ~econdary ~torage bus adapter 21 is, in turn is connected to bus 13.
Other~ of inputfoutput units 12 are connected to an inputtoutput bus adapter 23 over a device bu~ 24.

In accordance with this invention, one of the input/output units 12 also includes an interconnect unit 30 that connects to sn external device 31. The external device msy compri~e any of a number of` different types of electron-ic equipment depending on the applicstion to be perfor~ed.
In one application, the external device 27 will compri3e ~n array proces~or or ~pecial laboratory te~t equipment. In aDother application, the external device 27 will comprise another data processing system a~ shown in Fig. 1, with the connection to the interconnect unit 30 being through another interconnect unit 30 of simil~r construction.

Fig. 2 depicts, in functional form, the interconnect unit 30 of this invention and itB interconnection with the 7~7 the bus 13 and external device 31. The interconnect unit 30 includes ~ bus interface circuit 50 that connects to bus 13 and receives Qnd latches all of the ~ignals therefrom ~t predeter~ined times in a well-known manner. Under ~ome cir-cumstances, certain of the signal~ received by the intercon-nect unit 30 from bus 13 comprise addre~ ~ignal~, which identify addressable locations in the interconnect unit 30, follo~ed by (or conte~poraneous with) infor~ation signals which are to be latched in the location identified by the address. The interconnect unit 30 include~ liDes 51 ~or transmitting the received address signal~ and line3 52 for tran ferring the information signsls to the variou3 other circuit~ within the interconnect unit 30, including a local memory 53, a map register control and physical addres~ gen-erator circuit 54, snd a microprocessor 55. A conventional microsequencer (not ~hown) connects to the elements depicted in Fig. 2 to control the operation of the interconnect unit 30 in transferring information between the memory 11 and the external device 31 aq described below in connection with Fig. 5. The microsequencer operates in connection with ôp-erational command information provided directly by the proc-essor 10 or indirectly from the processor 10 through micro-processor 55.

~3-393 The address signals may also identify nddressable 1OCQ-tions in the external device 31, in particular control reg-isters for controlling the transfer of user information be-tween the interconnect unit 30 and the e~ternal device 31.
The addres3es and accompanying control information are transmitted by the interconnect unit 30 through the external bus interface ~6 over a control information bus 57.

The control information bu~ 57 ~ay also carry coDtrol information frDm the external device 31 to the interconnect unit 30. These signal~ are received iD the external bus in-terface 56 and transmitted to other circuits in the inter-connect unit 30 for processing. In so~e circumstances, the control information may require processing by the system's processor 10 (Fig. l); if such processing is necessary, the interconnect unit 3G will interrupt the proces30r 10 over sy~tem bus 13 and request interrupt service iD a conven-tionsl manner.

The control information received by the interconnect unit 30 from the procesqor 10 includes certain types of co~-mands which ensble the interconnect unit 30 to transfer in-, - ~285~ 7 ~ 3-393 formation between the ~e~vry 11 (Fig. 1) and the external device 31. Preliminarily~ the interconnect Qnit 30 trans-fers information with ~mory 11 in a "DMA" (direct me~ory acce~R) tran~fer ~ode. In a DMA operation, the procesBor 10 provides three general ite~ of information to the intercon-nect unit 30, including (1) the direction of transfer9 that is, whether the information is to be transferred to or from the ~emory 11, (2) the starting address in memory 11 of the information to be transferred or into which the information i~ to be ~tored, and (3) the a~ount of information to be transferred. After that information is supplied, the inter-connect unit 30 transfers information in blocks from or to consecutive locations in the memory 119 with the len$th of the block being identified by (3).

In one specific embodiment of the invention, the ad-dress (2) that i8 provided by the processor i~ not the ac-tual phy~ical addrsss in memory 11, but is instead a virtual address which is translated into a physical address by the circuit 54 ~Fig. 2~ in a conventional ~anner. The physical addres~ 80 tran~lated identifies the physical location in ~emory 11 into or from which the information is to be coupled. In a transfer, the information is trsnsferred ~5~)~7~7 ~ 3-393 u~ing con~ecutive virtual addre~es, which ~ay not be con-~e~utive physical locations in the ~emory 11.

After determining the physical addres~, the circuit 54 transmits it over the address line~ 51 to the bu~ interface circuit ~0. I* information is to be transmitted to the me~ory 11, that inforDation i8 received from the externnl device 31 over user information line~ 60 through external bu~ interface 56 and is placed on the infor~ation line~ 52 for tran~fer to the bus interface 50. The information may be tran~ferred directly to the bus interface 50, or it may be buffered in memory 53. The bus interface 50 receives the addre~s and information from line~ 51 and 52 and transmits them over bus 13 in the tran~fer protocol required by that bus. If information i8 to be obtained from the memory, only the addres~ is trnnsmitted over over Address line~ 51 through the bus interface 50 and over the bus 13, and the memory 11 returns the information from the addressed loca-tion over the bus 13 in a conventional manner. The infor~a-tion is received in the bu~ interface circuit 50 and trans-ferred over the information lines 52, through external bus interface circuit 56 and over the user information lines 60.

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For transfer~ of information in either direction5 the information may be buffered in the memory 53. That i8, if information is being received from the external device 31 faster that it can be tran3mitted over bus 13, some portion of the informatiDn ~ay be temporarily stored in local memory 53. Similarly, if interconnect unit 30 obtain~ information from memory 11, in a transfer to the external device 31, if it can obtain information from the ~emory 11 faster th~n it can transfer it to the external device 31 over u~er informs-tion lines 60, the infur~ation may be temporsrily buffered in local memory 53.

The 1OCA1 memory 53 also serves another purpose. In one specific embodiment, the bus 13 tran~fer~ information thirty-two bits (that is, four bytes) at a time. In that embodiment, depending on the nature of the external device 31, the interconnect unit 30 may traDsfer information over the user information lines 60 eight, sixteen, or thirty-two bits at a time. The local me~ory 53 is used for temporary storage of the information received in four byte group3 from bus 13 through bus interface 50, which information i9 then transferred one, two or four bytes at a time through ex-ternal bus interface 60 over user information lines 60.

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When information to be transferred to me~ory 11, it i9 received from the external device 31 over user information lines 60 through external bus interface 56 oDe, two or four bytes at ~ time and stored in local memory 53. Thereafter, the information i~ transferred out of local memory 53 four bytes at a time over information line~ 52, through bus ir-terface 50 and over bus 13 for storage in memory 11 (Fig. 1).

The various lines comprising contrDl information bus ~7 and user u~er information bus 60 ere depicted in Fig. 3.
With reference to Fig. 3, the lnformation bu~ 60 includes 8 set of information transfer lines 61 which transfers in-formation bidirectionally between the interconnect unit 30 and the external devic~ 31. Specifically, the information transferred over lines 61 comprise~ the information which ha~ been obtained from, or iB being tran~ferred to, the memory 11 (Fig. 1). In one specific embodiment, the in-formation transfer line~ 61 compri~e thirty-two lines which transfer information thirty-two, si~teen or eight bits fit a time, with one bit being transferred over each line.

The information bus 60 al30 includes two lines for car-rying synchronization signals. A line 62 carries a ~.2~35077 SYNC(L:~) local to external ~ynchronization signal~ ~nd a line 63 carries a SYNC(E:L) e~ternal to local synchroniza-tion signal. The SYNC(L:E) local to external synchroniza-tion signal i~ tran~nitted fro~ the interconnect unit 30 to the external device 31, and the SYNC(E:L) e~ternal to local Rynchronization signal i~ trans~itted ~rom the external device 31 to the interconnect unit 30. They are used to synchronize the tranafer of infor~ation over the infor~ation transfer line3 61, in a manner which will be de~cribed below in connection with Fig. 4.

Finally, the infor~ation bus 60 include~ two lines for carrying direction control signals. A line 64 carries a DIR(L:E) local to external direction signal, and a line 65 carries a DIR(E:L) external to local direction signal. The DIR(L:E) local to external direction signal iB transmitted from the interconnect unit 30 to the ex$ernal device 31, and the DIR(E:L) extern~l to local direction signal i3 trans-mitted from the external device 31 to the interconnect unit 30. They are used to identify the direction of transfer of information over the in~ormation transfer lines 61, in a manner which will be de~cribed below in connection with Fig. 4.

35~77 The control information bus 57 includes two anti-parallel control information tran~fer bu~es 66 and 67 for tran~ferriDg information unidirectionally between the inter-connect unit 30 and the external device 31. Control in-formHtion bus 66 transfers CTRL INFO (1:B) control informa-tion signal~ from the interconnect unit 30 to the external device 31, and control infor~ation bus 67 tran~fers CTRL
INFO (~:L) control information signals ~rom the extern~l device 31 to the interconnect unit 30.

The control information bus 57 also includes two lines 70 and 71, each of which carries a strobe signsl for the as-sociated control information tran~fer busses 66 and 67, respectively. Specifically, line 70 carries a CTRL SYNC
(L:E) control synchronization signal from the interconnect unit 30 to the external device 31, and ~ line 71 carries a CTRL SYNC (E:L) control synchronization signal from the ex-ternal device 31 to the interconnect unit 30. Each of the control ~ynchronization signals is asserted to indicate when the condition of the signals on the associated control in-formation transfer bu~es 66 and 67 has changed ~tate, that i~, when at least oDe of the signals on the buses ha~

~8~077 switched fro~ an a3serted to Q negated condition or vice VerBa. A ~ore detailed description o~ the ~ignal protocol over the control infor~ation bu~ ~7 will be presented below in connection with Fig. 4.

In addition to the user information bus 60 and the con-trol information bu~ 57, a device status bus 72 tran6fers ~ignal~ between the interconnect unit 30 and the external device 31 each indicating that the unit tran~mitting the respective ~ignal i~ operative. ~u~ 72 includes a line 73 which carrie3 an IU ACTIVE interconnect unit active signal from the interconnect unit 30 to the external device 31, which i~ a~serted when the interconnect unit 30 i~ opera-tive. The device statu~ bus 72 also includes a line 74 which carries an ED ACTIVF external device active signal from the external device 31 to the interconnect unit 30, which i~ a3serted whèn the external device 31 is operative.

Figs. 4A and 4B depict the protocol for tran3ferring u~er information over information bus 60 and control in-formation over control information bus 67, respectively.
The transfer protocol~ over both buses 67 and 60 are sym-metric, that is, the assertions and negations of the syn-~ 3-393 chroniziDx and direction control signals are the ~a~e in tran~fer~ fro~ the interconnect unit 30 to the external device 31 and from the exterDal device 31 to the intercon-nect unit 30. In Fig~. 4A snd 4B, the "A" and ~B" de~igna-tions represent the "L" and "~" designations in Fig. 3.

For example, depending on the direction of transfer over infor~ation bus 60, the DIR(A:B) direction signal ~y correspond to the DI~L:~) local to external direction ~ig-nal in Fig. 3. If so, the DIR(B:A) direction ~ignal cor-re3pond~ to the DIR(~:~) external to local direction ~ignal.
In addition, the SYNC(~:B) synchronizing signal in Fig. 4A
corresponds to the SYNC(L:E) local to external synchronl~a-tion signal in Fig. 3, ~nd the SYNC(B:~) synchronizing sig-n~l in Fig. 4A correspond~ to the SYNC(~:L) externsl to local synchronizstion signal in Fig. 3. A similsr cor-re~pondence i8 used between the ~ign~18 represented in Fig. 4B and the signals depicted in Fig. 3.

With reference to Fig. 4A, when one unit, either the interconnect unit 30 or the external device 31, iB to make tran~fer to the other unit, it as~erts it DIR(A:B) direction signal (ti~e A). If the DIR(B:A) direction signal îs not , 3L~ (3'77 already negated, tne unit wait3 until the signal is negated (ti~e B), after which it places information ~ignal~ on the information bus 60 (time C). A short ti~e later, to allow the sign~l~ on the information bus 60 ti~e to settle and de-~kew, the unit asserts its SYNC(A:B) synchronizing 3ignal (ti~e D). The other unit uses the SYNC(A:B) signal a8 a strobing signal, enabling it to latch the information ~ig-nals on the information bus 60. Contemporaneously, the other unit a~serts its SYNC(B:A) synchronizing ~ignal (time E).

In respon~e to the assertion of the SYNC~B:A) ~yn-chronizing ~ignal at time ~, the unit tran~mitting over the information bus 60 negates its SYNC(A:B) synchronizing 5ig-nal and re~oves the information signals then on the infor~a-tion bu~ 60. Sometime later, in re~ponse to the negation of the SYNC(A:B) synchronizin ~ignal, the other unit will negate its SYNC(B:A) synchronizing signal (time F).

If the unit has additional transfers to make over the infor~ation bus 60, it will place the next ~et of informa-tion signal~, representing the next word of information to be transferred, onto the information bus 60 (time G), and ~35()7~ ' ~ 3-393 ~fter the deskewing time ha~ p~s3ed, the unit ~sert~ the SYNC(A:B) signal again (ti~e R), ~nd the sequence proceed3 as in the fir~t transfer (times E through F). ~fter the unit has ~ade all of the transfers required over information bus 60 to transfer all of the information to be tr~nsferred, the unit negates it~ DIR(A:~) direction control signal (time I). At that point the other unit ~ay begin a transfer over the information b~s 60.

With reference to Fig. 4L, when a unit i9 to ~ake a transfer of control infor~Qtion over the control information bus 57, it pleces a word of control information signals CTRL INFO(A:B) corresponding to the control infor~ation to be traDsferred OD the it~ control information lines 66 or 67 (time 3). A Relected ti~e later, the unit a~ert~ its CTRL
SYNC~A:B) control synchronizntion signal (time K). The delay between time~ J and K is determined .bY the ti~e re-quired for the control information ~ignals to deskew at the receiving unit. The receiving unit may u~e the CTRL
SYNC(A:B) control synchronizQtion signal to ~trobe the ~ig-nals on the control information lines. A short time later, the transmitting unit negates the CTRL SYNC(A:B) control synchronization signals ~time L) and remove~ the control in-7~

formation ~ignals CTRL INFO~A:B) (time M). The seguence may be repeated ~or sub~cquent word~ of control in~or~atio~ sig-nals.

It will be appreciated that the protocol for transfer-ring in~ormation over the information bus 60 (Fig. 4A) and the control informstion bus 57 (Fig. 4B~ is much simpler than i8 the protocol for the communications de~ice described in the aforementioned U.S. P~tent 4,319,323, and that it i~
much ea#ier to con~truct an e~ternal device for connection to the interconnect unit 30 described herein than tv the communication~ device described in that patent. Indeed, ~ince the timing of $he transfer of each word of in~ormation over the information line~ 61 (Fig. 3) i3 governed by the SYNC~:L) external to local synchroni~ation signal and the SYNC(L:R) local to external synchronization signal, rather than by a periodic synchronizing signal as in the communica--tions device described in the patent, the stall condition can be readily accommodated. The transmitting unit does not a~sert its SYNC(A:B) synchronizing signal until it has placed a word of iDformation signals onto the information lines 61. Accordingly, if it temporarily has no data to transmit, it does not assert its SYNC(A:B) signal until it V :~l28~7 7 does have infor~ation to transmit. Similarly, if the receiving unit iQ teMporarily unable to receiYe a word of informntion being transmitting, it does not assert it~
SYNC(B:A~ signal until it i9 able to acco~modate the iD-formation word.

The protocol for transferring control information over the control information bus 57 is al~o simpler than in the aforementioned U.S. Patent 4,319,323, aR the receiving unit does not need to generate an acknowledgement signal. Fur-thermore, depending on the nature of the external device 31, the CTRL INFO (L:E) control information signals may comprise in~ormation words, which are transferred in synchronism with the respective CTRL SYNC (E:L) control synchronization sig-nal and CTRL SYNC (L:~ control synchronization ~ignal.
Alternatively, they may comprise continually-monitored con-trol or status signals, with the coDtrol synchronization signals being ignored.

Fig. 5 depicts a plurality of information structures in the interconnect unit 30 used by the processor 10 ~Fig. 1) and microproces~or 55 ~Fig. 2) for controlling the operation of the interconnect unit 30. Initially, it should be note~

that one embodiment of the interconnect unit 30 is used in a data processing system, and is connected to a system bus, wh~ch is described in U.S. Patent Application Serial No. 534,82g filed September 22, 1983 and issued on November 22, 1988 as U.S. Patent 4,787,033 in the name of Frank C. Bomha, et al., and entitled Arbitrati~n Mechanism For Assigning Control Of A Communications Path In A Di~ital Computer System, and assigned to the assignee of this application. One embodimerlt of the system bus is a BI bus ~hat is incorporated into a VAX8~00 digital data processing system sold hy the assignee of ~his invention.
With reference to Fig. 5, the information structures in the interconnect unit 30 are divided into three general categories, including a set of bus interface registers 100, a set of control and status registers 101, and a set of address translation registers 102. The bus interface registers, which are included in the bus interface 50 (Fig. 2) generally control the operation of the interconnect unit 30 over system bus 13 (Fig. 1).
They contain such information as the type of device, whether bus errors have occurred and the nature of any bus errors, whether the device may transmit an interrupt request, ~he address space of the address signals on the system bus 13 to which the device will respond, and so forth.

The rddress translation regi~ters 10~ contain the in-formation required by the map registers control ~nd phy~ical ~ddres~ generator circuit 54 ~Fig. 2~ to generate the physi-cal addresses from the virtual address ~upplied to the in-terconnect unit 30 by proces~or 10. The registers 102 ~re loaded by the proce~sor 10 (Fig. 1) prior to any trsn-~fers between the intercon~ect unit 30 and the external device 31 and identify sequenti~lly the page~ in the ~y~tem ~e~ory 11 into which the information from information bus 60 is to be stored, or from which infor~ation to be trans~itted over in-formation bus 60 i9 to be obtained. ~egisters 102 include two ~ets of register~, one set which is used during a cur-rent transfer (which are identified as "CURR~NT" register~
in Fig. 5) and a second set which ~ay be loaded during e current transfer for a subsequent tranæfer (which are iden-tified as 'lNEXT" registers in Fig. 5). The ~et of regi~ters 102 which are used ag "CURRENT" registeræ are identified by a pointer in the control and statu~ register~, whioh are de-scribed below.

The remaining registers depicted in Fig. 5 comprise the control and status registers 101. They include R control - . .. . . . .. ..

-~ i :~2~

regi~ter 103, an external bus ~et-up reister 104, and a bus width regiater 105, which control the tr~n~fers of infor~a-tion over information bus 60, all of which are used by the ~icrosequencer in controlling the interconnect unit 30 in transferring information over the information bus 60. Ini-tially, the processor 10 loads register 105 with a code which identifies the Du~ber of bits of information to be tran~mitted sver infor~ation bus 60 at a time. ~hen the in-terconnect unit 30 i8 to engage in a transfer, the processor 10 ~Fig. 1) initially tests a flag 120 in setup register lV4 to determine whether the external device i~ active. The state of this flag reflects the current state of line 74 (Fig. 3), and in particular whether the ED ACTIVE signal is ssserted. If it i8, the external device 31 can engage in a trHnsfer .

If a trancfer over the information bus 60 is to be to the external device 31, the processor 10 sets a DIR OUT flag 121, which causes the as~ertion of the DIR~L:~) local to ex-ternal direction signal on line 64. When ~ DIR IN flag 122 indicates that the DTR(~:L) external to local direction sig-nal hss been negated, the processor 10 loads a value in a GO
flag 123 of control register 103 ~hich enables the transfer ~ . , , . , ~ .. .. .. ..

~s5077 to proceed. The transfer continues until completed normal-ly, as described below, or until the processor 10 sets an A~ORT flag 124 in register 103.

On the other hand, the proces~or l0 also periodically monitors the DIR IN fleg 122 to determine whether the condi-tion of the DIR~E:L) external to local direction ~ignal in-dicates that the external device 31 i3 to transmit informa-tion over infor~ation bus 60 to the interconnect unit 30.
When the DIR I~ flag i~ set, the external device 31 i8 t~
tran~mit infor~ation, and the processor 10 clear~ the DI~
OUT flag 121 to ensure that the DIR(L:~) local to external direction signal is negated and sets the GO flsg 123. The interconnect unit 30 then receives information ovsr informa-tion bus 6U until the transfer is completed normally, as de-scribed below, or until the processor 10 sets the ABORT flag in register 103. ~ ~

On transferq of information to the external device 31 from the interconnect unit 30, a regiqter 110 contsins the information to be trsnsferred over information lines 61 o-f information bus 60. On transfers to the interconnect unit 30 from the external device 31, tbe same register 110 is ~S~)7'7 83-~g3 receive~ the informstion fro~ the externsl device 31. Dur-ing a tran3fer over information bus 60 in either directioD, pointers 106 identify the current state of the tr~ns~er. In particul~r, a BLFT bytes left register 114, which i8 ini-tially loaded by the proces30r with the number of bytes to be transferred, is decremented when each byte of information is transmitted or received over the information bus 60.
When the contents of the BLFT bytes left regi~ter 114 reach zero, the transfer i~ ended.

ID addition, three regi~ters in pointers 106 are used in connection with the virtual address translation, includ-ing ~ tr~n31ation register pointer 111, a TOMR top of map regi~ter~ pointer 112, and Qn of~et register 113. The translation register pointer 111 identifies the register in address tran~lation regi~ters 102 which i3 being used in connection with the virtual to physical addres3 translation.
The content3 of the register identi~ied by the pointer 111 identify the page in ~emory 11 with respect to which the tran3fer i8 to occur. For tran3fers to or from the fir~t page, the contents of the offset regi~ter 113 identify the beginning location in the page in system memory 11 into which the information i~ to be stored, or from which the in-)77 formation i5 to be retrieved. The contents of off3et regi~-ter 13 4re only u~ed during the initial tran~fer to or from the first page in memQry 11 BO that transfers clo not have to begin at the beginning of the page; tran~fer~ to subsequent pages begin at the beginning of the page.

For the first transfer to or from the memory 11, the contents of the off~et register 113 are concatenated to the content~ of the register 102 pointed to by the tran~lation register pointer 111 a~ the lea~t signific~nt bit~ thereof.
~he result, which i8 a phy~ical addres~ then stored in a phy~ical addres~ regi~ter 107. The contents of physical ad-dre~3 regi~ter 107 are used by bus interfsce circuit 50 in tran3ferring i~formation to or fro~ ~emory 11 (Fig. 1). If information i.q being transferred to memory 11, that informa-tion i~ in register 110 and is transmitted by bus interface circuit 50 to memory 11. Alternatively, if the information i8 being received from the memory 11, the information is stored in the register 110 `oefore being tr~n~ferred over the information bus 60 to external device 31.

Whenever the interconnect unit 30 trans~ers a word of infor~ation to or from memory 11, the contents of the physi-~Z~507~7 83-3g3 cal addre~ register 107 are incremented. When the content~
ha~e reHched the ~aximum nu~ber o~ byte~ in a pae, they are reset and the content~ of the pointer 111 are incremented to identify the next page to receive information. The conteDt~
of pointer 111 are then co~pared to the contents of pointer 112, and if they are equal, the tran~fer terminate~ regard-le~s of the contents of register 114. If the content~ of pointer~ 111 and 112 are no~ equal, the transfer continue~.
The contents of the addres~ translation regi~ter that i8 then pointed to by the translation register pointer 111 are tran~ferred to the mo~t ~ignificant portion of the phy~ical addres~ regi~ter, and the tran~fer contiDue3.

As ha~ been ~entioned, the interconnect unit 30 in-clude~ two ~ets o~ addrecs translation regi~ters so that the processor 10 can ~et up an infor~ation transfer while a tran~fer i~ currently taking place. The interconnect unit 30 includes two ~ets of pointers 106~ one for the current transfer and the other for the next traDsfer. A pointer (not shown) identifie~ the current and next tran~fer pointers, and a PDG SEG pending aegment transfer flag 12~ in control regi~ter 103 i~ set by the proces~or 10 when another tran~fer ha~ been ~et up.

Control information i8 tran~ferred through another reg-i~ter, nsmely regi~ter 115. A CTRL OUT ~egment 126 of reg-ister 115 is used for tran~ers of control infor~ation over lines 66 of control information bu~ 67. To determine con-trol information being tranQmitted over line~ 67, the proc-e~sor may read a CTRL IN ~egment 12~ of regi~ter 115. The proces~or 10 ~ay read the CTRL IN segment when the external device 31 a3sert~ the CTRL SYNC (8:L) control synchroniza-tion signal. The assertion of the CTRL SYNC (~:L) control ~ynchroni2ation signal which may result in an interrup$ to the processor 10 enabling it, in turn to read the register.
Alternatively, the interconnect unit 30 may ignore the CTRL
SYNC (E:L) control ~ynchronization signal, and the proce~sor may read the regi~ter periodicslly.

A~ has been noted, the microprocessor 5~ ~Fig. 2) ~ay al~o provide command information ~or controlling the inter-connect unit 30. ~ather than requiring the proce3~0r 10 to directly load tran~fer command and control information into the register~ (Fig. 5) that control the interconnect unit 30, information may be loaded into que~e~ and the micro-proce~sor 55 ~ay be programmed to iterati~ely retrieve the 7~
83-3g3 information, load it into the proper regi~ters, monitor the content~ of various regi3ters~ and otherwise ~uper~i~9e the transfers. After each transfer, the ~icroproces~or may transfer an indication that the tran3fer wa~ completed to another queue.

In one specific e~bodiment, the microprocessor 55 com-municate~ with the other element~ of the intercon~ect unit 30 through the map register control ~nd phy~ical addres~
generating circuit~ 54. With reference to Fig. 2, the ~i-crvprocessor 55 both tran~mit~ address ~ignsl~ end transfer~
information signal~ over infor~ation line~ 52 to circuit~
54. If the address Qignals from the microproce~sor identify a location in circuits 54, the information i8 re~eived and used by tho~e circuitF9, if the transfer i~ from the micro-proce~or. Alternatively, if iDformation is to be tranq-ferred to the ~icroprocessor9 the circuits 54 transmit the information signals over iDformation lines 52t which ~ignals are received by the microproces~or.

If, on the other hand, the addre~s ~ignal~ identify locations in other parts of the interconnect unit 30, parti cularly the mecory 53 o~ bus interface 50, the circuits 54 ~5~?~7 - 35 - 72896-~3 transmit the address signals, which they receive from the micro-processor 55 over khe information lines, over the address lines 51. If the information is to be transferred to the addressed circuit, -the circuit receives the information signals over the information lines 52, and if the information is to be transferred to the microprocessor 55, the circuit transmits the information over the information lines 52.
The foregoing description has been limited to a specific embodiment of this invention. It will be apparent, however, that variations and modifications may be made to the invention, with the attainment oE some or all of the advantages oE the invention.
Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the true spirit and scope of the invention.

Claims (6)

1. An interconnect unit for connection to a system bus in a digital data processing system including a memory for storing information and a processor means for controlling the system, said interconnect unit transferring information between the memory over said system bus and an external device over an external bus, said external bus including bidirectional information transfer lines for transferring information signals, antiparallel unidirectional direction control lines having selected conditions for transferring direction control signals identifying a direction of transfer of information and antiparallel unidirectional synchronization lines for transferring synchronization signals, in response to commands from the processor means, said interconnect unit including:
A. system transfer means for connection to said system bus for transferring information to or from said memory, B. external device transfer means including means for connection to said external bus for transmitting and receiving information over said external bus, and further including information transfer means connected to said system transfer means and for connection to said information transfer lines for transferring information between said system transfer means and said information transfer lines, said direction control lines asserting a signal on one of said direction control lines and receiving a signal on a second of said direction control lines identifying a condition of the direction of transfer of information over said information transfer lines, said synchronization lines asserting a signal on one of said synchronization lines and receiving a signal on a second of said synchronization lines to synchronize the transfer of information over said information transfer lines, and C. control means for operational control of the interconnect unit in transferring information over said information transfer lines, said control means including a first register enabling the transmission and reception of the direction control signals over the respective direction control lines to identify the direction of transfer, said control means enabling the selection of transmission or reception of information signals over said information transfer lines responsive to the condition of said direction control signals, and said control means for enabling a synchronization signal to identify:
I. when information signals are being transferred over said information transfer lines when said direction control signals indicate that information is being transferred to said external device to enable said external device to receive said information signals, or II. when information signals have been received from said information transfer lines when said direction control signals indicate that information is being transferred from said external device.

2. An interconnect unit as defined in claim 1 in which said external bus further includes unidirectional antiparallel control information lines for transferring control information signals and synchronization control lines for transferring synchronization control signals, said interconnect unit further including a second register for transmitting and receiving control information signals over respective ones of said control information transfer lines, said synchronization control signal transfer lines transmitting and receiving synchronization control signals over respective ones of said synchronization control signal transfer lines, and C. said control means for operational control of the interconnect unit enabling said second register to transmit control information over one of said respective control information transfer lines and said control means transmitting a contemporaneous synchronization control signal over one of said synchronization control signal transfer lines to enable said external unit to receive said control information signals, and said control means enabling said second register to receive control information signals over a second of said respective control information transfer lines in response to the receipt of a synchronization signal over a corresponding synchronization control signal transfer line.

3. An external unit for connection to a digital data processing system for transferring information with said data processing system over an external bus, said external bus including bidirectional information transfer lines for transferring information signals, antiparallel unidirectional direction control lines having selected conditions for transferring direction control signals and antiparallel unidirectional synchronization lines for transferring synchronization signals, said external unit including:
A. external device transfer means including means for connection to said external bus for transmitting and receiving information over said external bus, and further including information transfer means connected to said system transfer means and for connection to said information transfer lines for transferring information between said system transfer means and said information transfer lines, said direction control lines asserting a signal on one of said lines and receiving a signal on a second of said lines identifying a condition of the direction of transfer of information over said information transfer lines, said synchronization lines asserting a signal on one of said synchronization lines and receiving a signal on a second of said synchronization lines to synchronize the transfer of information over said information transfer lines, and B. control means for operational control of the interconnect unit in transferring information over said information transfer lines, said control means including a first register enabling the transmission and reception of the direction control signals over the respective direction control lines to identify the direction of transfer, said control means enabling the selection of transmission or reception of information signal over said information transfer lines responsive to the condition of said direction control signals, and said control means enabling a synchronization signal to identify when information signals re being transferred over said information transfer lines when said direction control signals indicate that information is being transferred to said external device to enable said external device to receive said information signals, or when information signals have been received from said information transfer lines when said direction control signals indicate that information is being transferred from said external device.

4. An external unit is defined in claim 3 in which said external bus further includes unidirectional antiparallel control information lines for transferring control information signals and synchronization control lines for transferring synchronization control signals, said interconnect unit further including a second register for transmitting and receiving control information signals over respective ones of said control information transfer lines, said synchronization control signal transfer lines transmitting and receiving synchronization control signals over respective ones of said synchronization control signal transfer lines, C. said control means for operational control of the interconnect unit enabling said second register to transmit control information over one of said respective control information transfer lines and said control means transmitting a contemporaneous synchronization control signal over one of said synchronization control signal transfer lines to enable said external unit to receive said control information signals, and said control means enabling said second register to receive control information signals over a second of said respective control information transfer lines in response to the receipt of a synchronization signal over a corresponding synchronization control signal transfer line.

5. An interconnect unit as defined in claim 1, as external bus further including antiparallel unidirectional status indicating lines, said external device transfer means further including a status indicating control means for connection to said antiparallel unidirectional status indicating lines and responsive to said control means for operational control of the status indicating control means, for transmitting a signal over one of said status indicating lines and receiving a signal from a second of said status indicating lines to indicate the status of transmitting unit.

6. An external unit as defined in claim 3, said external bus further including antiparallel unidirectional status indicating lines, said external device transfer means further including a status indicating control means for connection to said antiparallel unidirectional status indicating lines and responsive to said control means for operational control of the status indicating control means, for transmitting a signal over one of said status indicating lines and receiving a signal from a second of said status indicating lines to indicate the status of the transmitting unit.