CA1281822C - Subsidiary station capable of automatically adjusting an internal delay in response to a number signal received in a downward signal by the subsidiary station - Google Patents
Subsidiary station capable of automatically adjusting an internal delay in response to a number signal received in a downward signal by the subsidiary stationInfo
- Publication number
- CA1281822C CA1281822C CA000547177A CA547177A CA1281822C CA 1281822 C CA1281822 C CA 1281822C CA 000547177 A CA000547177 A CA 000547177A CA 547177 A CA547177 A CA 547177A CA 1281822 C CA1281822 C CA 1281822C
- Authority
- CA
- Canada
- Prior art keywords
- signal
- station
- downward
- delay
- upward
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/24—Radio transmission systems, i.e. using radiation field for communication between two or more posts
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
Abstract
Abstract of the Disclosure:
In a repeater station (20) for receiving a first downward signal from a next preceding station (21) with a propagation delay and for transmitting a second downward signal to a next succeeding station, a first delay circuit (15) gives a fixed delay to the first downward signal to produce a delayed signal for use as the second downward signal. The first downward signal has a frame period and includes a reference signal and a number signal representative of an integer for the repeater station. The fixed delay is rendered equal to an integral submultiple of the frame period minus the propagation delay. A first detector (17) detects the reference signal to produce a first detection signal. A
second detector (23) detects the number signal to produce a second detection signal representative of the integer. Responsive to the second detection signal, an internal delay circuit (24) gives an internal delay to the first detection signal to produce a delayed detection signal. The internal delay is decided in consideration of the integer. Responsive to the delayed detection signal, a multiplexer (25) processes a first upward signal received from the succeeding station into a processed signal. A second delay circuit (26) gives the fixed delay to the processed signal to produce a second upward signal which should be received by the preceding station with the propagation delay. The repeater station may be used as a terminal station.
In a repeater station (20) for receiving a first downward signal from a next preceding station (21) with a propagation delay and for transmitting a second downward signal to a next succeeding station, a first delay circuit (15) gives a fixed delay to the first downward signal to produce a delayed signal for use as the second downward signal. The first downward signal has a frame period and includes a reference signal and a number signal representative of an integer for the repeater station. The fixed delay is rendered equal to an integral submultiple of the frame period minus the propagation delay. A first detector (17) detects the reference signal to produce a first detection signal. A
second detector (23) detects the number signal to produce a second detection signal representative of the integer. Responsive to the second detection signal, an internal delay circuit (24) gives an internal delay to the first detection signal to produce a delayed detection signal. The internal delay is decided in consideration of the integer. Responsive to the delayed detection signal, a multiplexer (25) processes a first upward signal received from the succeeding station into a processed signal. A second delay circuit (26) gives the fixed delay to the processed signal to produce a second upward signal which should be received by the preceding station with the propagation delay. The repeater station may be used as a terminal station.
Description
~28~32X
SUBSIDIARY STATION CAPABLE OF AUTOMATICALLY
ADJUSTING AN INTERNA~ DELAY IN RESPONSE TO
A NUMBER SIGNAL RECEIVED IN A DOWNWARD SIGNAL
BY THE SUBSIDIARY STATION
Background of the Invention:
This invention relates to a subsidiary station for use in a time division multiple access network.
Such a time division multiple access network comprises a central or base station, a terminal station remote from the central station, and at least one repeater station placed between the central sta-tion and the terminal station. For convenience of description, each o the terminal and the repeater s-tations is called a subsidiary station.
When initially sét or newly installed in the network, a conventional subsidiary station must be given an internal delay so that a total delay given by adding the internal delay to twice a propagation delay from a next preceding station of the network to the subsidiary station should be equal to a frame period oE a downwar~
ax2 signal received from the central station as will later be described. When the subsidiary station receives the downward signal from the central station, the subsidiary station transmits an upward signal towards the central 5 station. When at least one preceding repeater station is placed between the central station and the subsidiary station, the upward signal reaches the central station a lapse of a time duration, given by multiplying the frame period by the number of the preceding repeater station, 10 a~ter transmission of the downward signal from the central station. Thus, a long time is wasted until reception of the upward signal at the central station after transmission of the downward signal from the central station.
A repeater station is disclosed in United States Patent No. 4,490,813 issued to Shigeru Otsuka and assigned to NEC Corporation. The repeater station is also disclosed in Canadian Patent No. 1,191,205 and in ~ustralian Patent No. 553,157. The repeater station may 20 have a prede-termined initial delay shor-ter than the frame period. It is therefore possible to shorten the time duration between transmission of the downward signal Erom the central station and reception oE the upward signal at the central station. ~lowever, the 25 repeater station is incapable of automatically deciding the internal delay.
~2~3~8~
Summary of the Invention:
It is an object of this invention to provide a subsidiary station capable of automatically deciding an internal delay in response to a particular signal 5 included in a downward signal.
Other objects of this invention will become clear as the description proceeds.
A repeater station to which this invention is applicable is for receiving a first downward signal from 10 a next preceding station with a propagation delay, for transmitting a second downward signal to a next succeeding station, for receiving a first upward signal from the succeeding station, and for transmitting to the preceding station a second upward signal which should be 15 received by the preceding station with the propagation delay. Each of the first and the second downward signals has a frame period and includes a reference signal. Each of the first and the second upward signals has said frame period. The repeater station includes a 20 first delay circuit for giving a fixed delay to the first downward signal, and a first detector for d~tecting the reference signal of the first downward signal to produce a first detection signal. According to an aspect of this invention, the fi~ed delay is 25 rendered equal -to cln inteyral submultiple of said frame period minus said propagation delay. The first downward signal includes a number signal representative o~ an integer corresponding in number to at least one other station through which the firs-t downward signal is received from an originating s-tation. The at least one other station comprises the preceding sta-tion. The repeater station comprises: a second detector for 5 detecting the number signal to produce a second detection signal representative of the integer; an internal delay circuit responsive to the second detection signal for giving an internal delay to the first detection signal to produce a delayed detection 10 signal, the internal delay being decided in consideration of the integer; processing means responsive to the delayed detection signal for processing the first upward signal into a processed signal; and a second delay circuit for giving the fixed 15 delay to the processed signal to produce the second upward signal.
~ terminal station to which this invention is applicable is ~or receiving a downward signal from a next preceding station with a propagation delay and for 20 transmitting to the preceding station an upward signal which should be received by -the preceding station with the propagation delay. The downward signal has a frame period and includes a reference siynal. The upward signal has the frame period. The texminal station 25 includes a fir~t delay circuit for giving a Eixed delay to the downward signal to produce a delayed signal, and a first detector for detecting the reference signal to produce a first de-tection signal. ~ccording to another ~LX~318~Z
aspect of this invention, the fixed delay is rendered equal to an integral submultiple of the frame period minus said propagation delay. The downward signal includes a number signal representative of an integer 5 corresponding in number to at least one repeater station through which the downward signal is received from an originating station. The terminal station comprises: a second detec-tor for detecting the number signal to produce a second detection signal representative of the 10 integer; an internal delay circuit responsive to the second detection signal for giving an internal delay to the first detection signal to produce a delayed detection signal, the internal delay being decided in considexation of the integer; processing means 15 responsive to the delayed detection signal for processing an input signal into a processed signal: and a second delay circuit for giving the fixed delay to the processed signal to produce the upward signal.
Brief Description of the Drawing:
Fig. 1 shows a block diagram of a conventional repeater station together with a next preceding station;
Fig. 2 is a -time chart for use in describing operation O:e the conventional repeater statlon illustrated in Fig. 1:
Fiy. 3 shows a block diagram of a repeater station according to a preferred embodiment of this in~ention together with a next preceding and a next succeeding station;
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Fig. 4 shows formats for downward and upward signals received by the repeater station illustrated in Fig. 3;
Fig. 5 is a time chart for use in describing 5 operation of the repeater station illus-trated in Fig. 3;
and Fig. 6 is another time chart for use in describing modified operation of the repeater station illustrated in Fig. 3.
Description of the Preferr_d Embodiment:
Referring to Fig. 1, a conventional repeater station 10 will be described at first for a better understanding of this invention. The repeater station 10 is for receiving a first downward signal from a next 15 preceding station 11 with a downward propagation delay defined by a downward propagation path 13 and for transmitting a second downward signal to a next succeeding station (later illustrated). The repeater station 10 i.s also for receiving a first upward signal 20 from the succeeding s-tation and for transmitting to the prececling station 11 a second upward signal which should be received by the prec~ding station 11 with an upward propagation delay defined by an upward propagation path 14. The upward propagation delay is substantially equal 25 to the downward propagation delay.
The preceding station 11 may be either a central station or another repeater station. The succeeding uqL~
station may be either a terminal station or another repeater station.
Each of the first and the second downward and upward signals has a frame period. Each of the first 5 and the second downward signals includes a frame alignment signal as a reEerence signal. It will be assumed throughout the following that each frame consists of N bits, where N represents a prescribed natural number.
The repeater station 10 includes a delay circuit 15 for giving a fixed delay to the first downward signal through a first receiving circuit 15' to produce a delayed signal. The fixed delay is rendered equal to a difference between one frame period and a sum of the 15 upward and the downward propagation delays. A first transmitting circuit 16 transmits the delayed signal to the succeeding station as the second downward signal.
Responsive to the delayed signal, a frame allgnment circuit 17 reproduces the frame alignment 20 signal, namely, the reference signal. That is, the frame alignment circuit 17 is operable as a first detector for detecting the reference signal of the first downward signal to produce a first detection signal.
A second receiving circuit 1~ receives the first 25 upward signal. ~ multiplexer 19 processes the first upward signal into a proce.ssed signal in accordance with the first detection signal. The processed signal is transmitted to the preceding station 11 through a second .~
~L28~8Z2 transmitting circuit 19' and the upward propagation path 1~ as the second upward signal.
A terminal station need not comprise the first transmitting and the second receiving circuits 16 and 5 18.
Referring to Fig. 2 together with Fig. 1, description will be made as regards operation of the repeater station 10. It will be assumèd that first, second, and third repeater stations are placed between a 10 central station and a terminal station. Each of the first, the second and the -third stations is similar in structure to the repeater station 10. In Fig. 2, the abscissa represents time while the ordinate represents a distance from the central station.
The central station transmits a first downward signal to the first repeater station. The first repeater station receives the first downward signal with the downward propagation delay. Merely for convenience of description, the downward propagation delay will be 20 assumed to be equal to 1/4 of the frame period.
In the first repeater station, the delay circuit 15 has a fixed delay which is rendered equal to 2/4 of the frame period. Thereore, the delay circuit 15 produces the delayed signal 3/4 frame period after 25 transmission of the first downward signal from the central station.
The frame alignment circuit 17 of the first repeater station extracts the frame alignment signal ~8~ Z
~rom the delayed signal. In accordance with the frame alignment signal, the multiplexer 19 of the first repeater station processes a first upward signal into a processed signal for use as a second upward signal in 5 the manner described above. The second upward signal i~
transmitted -to the central station through the upward propagation path 14 which has the upward propagation delay. Inasmuch as the downward delay is assumed to be 1/4 frame period, khe upward propagation delay is also 10 equal to 1/4 of the frame period. Thus, the central station receives the second upward signal a lapse of one frame period after the first downward signal is sent by the central station.
The first transmitting circuit 16 of the first 15 repeater station transmits the delayed signal as a sQcond downward signal to the second repeater station through another downward propagation path which is between the first and the second repeater stations. The downward propagation path will be assumed to be equal to 20 1/4 of the frame period like the downward propagation path between -the central and the first repea-ter stations. Thus, the second downward signal is received by the second repeater station a lapse of one Erame period after the first downward signal is sent by the 25 central station.
After reception of the second downward signal, the second repeater station transmits another upward signal to the first repeater station in the manner 32~
similar to the ~irst repeater station. This upward signal is immediately repeated by the first repeater station to the central station. As a result, the central station receives the upward signal from the S second repeater station a lapse o~ two frame periods after the irst downward signal is sent by the central stakion.
In this manner, the central station receives an upward signal from the third repeater station a lapse of 10 three frame periods after the central station sends the first downward signal. As for an upward signal of the terminal station, a long time duration of four frame periods is necessary, until reception of the upward signal after transmission of the downward signal of ~he 15 central station. It is now understood that the internal delay of the repeater station results in an objectional delay in reception of an upward signal of a remote station at the central station.
Referring to Fig. 3, a repeater s-tation 20 20 according to a preferred embodiment of this invention comprises similar parts designated by like reference numerals. The rep~ater station 20 is for receiving a first downward signal from a next preceding station 21 with a down propagation delay defined by the downward 25 propagation path 13 and for transmitting a second downward signal to a next succeeding s-tation. The repeater station 20 is also for receiving a first upward signal from the succeeding station and for transmitting l l to the preceding station 21 a second upward signal which should be received by the preceding station 21 with an upward propagation delay defined by the upward propagation path 14.
The preceding station 21 may be either a central station or another repeater station. The succeeding station may be either a terminal station or another repeater station.
Turning to Fig. 4, the first downward signal has 10 a frame period depicted along a top line. As depicted along a second line from the top, the first downward signal includes a frame alignment signal labeled "F" and a number signal labeled "NS" representative of an integer corresponding in number to at least one other 15 station through which the first downward signal is received from an originating station which is usually the central station. The at least one other station comprises the preceding station. The frame alignment signal and the number signal are included in an initial 20 acquision channel labeled "ACQ CH". The frame alignment signal is used as the reference signal. The number ~ignal is called a particular signal hereinabove and is for use in declding an internal delay of each subsidiary station in the manner which will later be described. In 25 the manner known in the ar-t, the first downward signal further includes an order wire channel labeled "OW CH", a predetermined number of voice channels each of which is labeled "V CH", a control channel labeled "C CH", a ~Z818~
supervisory channel labeled "SV CH", and a teleprinter exchange channel labeled "TELEX CH".
As depicted along a bottom line, the upward signal comprises an ini.tial acquision pattern labeled 5 "ACQ P~TTERN" in the initial acquision channel "ACQ CH".
In the manner known in the art, the acquision pattern is interposed between two guard time portions each labeled "G".
Turning back to Fig. 3, the repeater station 20 10 comprises a first delay circuit 15 for giving a fixed delay to the first downward signal through the first receiving circuit 13' to produce a delayed signal as described in conjunction with Fig. 1. It is, however, to be noted that the fixed delay is rendered equal to an 15 integral submultiple l/M of the frame period minus the propagation delay of the downward propagation path 13, where M represents a preselected natural number.
The frame alignment circuit 17 serves as a first detector for detecting the frame alignment or reference 20 signal of the firs-t downward signal to produce a first detection signal as described in conjunction with Fig.
1. In the example being illustrated, the frame alignment ci.rcuit 17 recei.ves the delayed signal from the first delay circuit 15.
~ number signal detector 23 is operable as a second detector for detecting the number signal in the delayed signal with reEerence to the first detection signal to produce a second detection signal ~.
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representative of the integer. In this manner, the number signal detector 23 detects the number signal in the first downward signal to produce the second detection signal.
Responsive to the second detection signal, an internal delay circuit 2~ gives an internal delay to the first detection signal to produce a delayed detection signal. The internal delay is automatically decided in consideration of the integer by a read-only memory.
When the repeater station 20 is operable also as a terminal station, a multiplexer 25 is used for connection ko a signal transmission line ~not shown~ for local signals. The multiplexer 25 is for multiplexing the local signals and the ~irst upwara signal received 15 through the second receiving circuit 18 into a multiplexed signal. The first upward signal includes a control signal for supervision in the manner known in the art. The multiplexer 25 is operable as a processing circuit responsive to the delayed detection signal for 20 processing the multiplexed signal into a processed signal. When attention is directed to the ~irst upward signal, it is possible to understand that the mul-tiplexer 25 processes the ~irst upward signal into the processed signal.
A second delay circuit 26 is for giving the fixed delay to the processed signal to produce the second upward signal whieh is transmitted to the preceding station 21 through the second transmitting 8X~
circuit 19' and the upward propagation path 14. The fixed delay is rendered equal to an integral submultiple l/M of the frame period minus the propagation delay of the upward propagation path 1~.
A number signal modifying circuit 27 is operable as a first modifying circuit for modifying the number signal into a modified signal representative of another integer or the succeeding station. Typically, the modified signal is representative of one plus the 10 integer.
A first transmitting circuit 28 serves as a second modifying circuit responsive to the modified signal for modifying the delayed signal into a second downward signal with the modified signal substituted for 15 the number signal included in the delayed signal. When the repeater station 20 is used also as the terminal station in the manner described above, the first transmitting circuit 28 serves at least parthy as a demultiplexer.
In a terminal station, the first transmittiny and the second receiving cirauits 28 and 1~ and the numher signal modifying circuit 27 are unnecessary. The multiplexer 25 is used in multiplexing only local signals which may collec-tively called an input signal.
25 The multiplexer 25 serves as a processing circuit responsive to the delayed signal for processing the input signal into a processed signal.
Referring to Fig. 5 together with Fig, 3, description will proceed to operation of the repeater station 20 and the terminal station. It will be assumed that first, second and third repeater stations are 5 placed between a central station and the terminal station. Each of the first the second and the third stations is similar to the repeater station 20.
The central station transmits to the first repeater station a first downward signal including a 10 frame alignment or reference signal and a number signal.
The number signal may represent unity. The first downward signal reaches the first repeater station with a downward propagation delay of a downward propagation path between the central and the first repeater 15 stations. The first delay circuit 15 produces the delayed signal by giving a fixed delay to the first downward signal. The fixed delay is preliminarily decided so that the delayed signal be produced with a total difference of 1/~ of the frame period relative to 20 transmission of the first downward signal from the central station. For this purpose, the fixed de,lay is rendered equal to an integral submultiple 1/4 of the Erame period minus the downward propagation delay.
Responsive to the number sign~l representative 25 of unity, the internal delay circuit 2~ automatically adjusts the internal delay to 1/2 of the frame period.
The internal delay circuit 2~ gives the internal delay to the first detection signal received from the Erame ~;t7' \~
~IL2~3~8X2 alignment circui~ 17 and produces the delayed detection signal 3/4 frame period after transmission of the first downward signal at the central station.
Responsive to the delayed detection signal, the 5 multiplexer 25 processes the first upward signal into the processed signal. The delayed de-tection signal is used in making the multiplexer 25 begin to produae the processed signal concurrently with the delayed detection signal.
A fixed delay of the second delay circuit 26 is rendered equal to an integral submultiple 1/4 of the frame period minus an upward propagation delay of the upward propagation path 14. Inasmuch as the upward propagation delay is substantially equal to the downward ! 15 propagation delay, the fixed delay of the second delay circuit 26 is substantially equal to the fixed delay of the first delay circuit 15. The second delay circuit 26 gives the fixed delay to the processed signal. As a result, the central station receives the second upward 20 signal a lapse of one frame period after the first downward signal is sent by the central station.
Meanwhile the first detection signal is subjected to the internal delay in the internal delay circuit 2~, the number signal modifying circuit 27 25 modifles the number signal received from the number signal detector 23 into a modified signal representative of another integer for the second station. This integer may be equal to two. In the second downward signal, the ~LX8~3X~
modified signal is substituted for the number signal included in the delayed signal. The first transmitting circuit 28 sends the second downward signal including the modiied signal to a downward propagation path 5 between the first and the second repeater stations.
This downward signal reaches the second repeater station with a downward propagation delay of the downward propagation path. The downward signal therefore reaches the second repeater station, after 10 transmission of the downward signal at the central station, with a delay which is equal -to a sum of the downward propagation delays of the propagation paths between the central and the first repeater stations and between the first and the second repeater stations.
In the second repeater station, the first delay circuit 15 gives a fixed delay to the downward signal.
The fixed delay is preliminarily decided so as to be equal to 1/4 of the frame period minus the propagation delay between the first and the second repeater 20 ~tations. ~s a result, the second repeater station receives the downward signal a lapse of 1/2 of the frame period ater the downward ~ignal is sent by the central station.
Responsive to the modified signal representative 25 of two, the internal delay circuit 24 of the second repeater station gives an internal delay to the first detection signal received from the frame alignment circuit 17. The internal delay is now equal to zero.
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Therefore, the second repeater sta-tion produces the processed signal with a delay of 1/2 frame period relative to transmission of the downward signal at the central station.
The second repeater station sends the upward signal to the first repeater station with a total delay of 3/4 frame period after the downward signal is sent by the central station. Thus, the central station receives the upward signal from the second repeater sta-tion a 10 lapse of one frame period after the downward signal is sent by the central station.
Likewise, the third repeater and the terminal stations receive the number signals representative of three and four, respectively. Responsive to the number 15 signal representative of three, the internal delay circuit 24 of the third repeater station gives an internal delay of 1/2 frame period to the first detection signal received from the frame alignment circuit 17. Responsive to the number signal 20 representative of four, the internal delay circuit 24 of the terminal station gives an internal delay of zero to a first detection signal.
As a result, the central station receive3 the upward signals from the third repeater and the terminal 25 stations a lapse of two frame periods after the central station sends the downward signal.
Thus, the central station receives the upward signal from the terminal stations with only a short 11 Z~
delay after transmission oE the downward signal at -the central station. Each of the firs~ through the thir~
repeater stations and the terminal station automatically decides the internal delay in response to the number 5 signal included in the downward signal.
Referring to Fig. 6, description will now be made as regards modified operation of the repeater station 20 (Fig. 3) and the terminal s-tation. In this case, flrst through eighth repea-ter stations are placed lO between central and terminal stations. For each of the repeater and the -terminal stations, a total delay of a downward path 13 (Fig. 3) and a first delay circuit 15 (Fig. 3) is rendered equal to l/24 of a frame period.
~nother to-tal delay of an upward path 14 (Fig. 3) and a ! 15 second delay circuit 26 (Fig. 3) is also rendered equal to 1/24 of the frame period for each of the repeater and the terminal stations. In each of the repeater and the -terminal stations, an internal delay circuit 24 (Fig. 3) gives a first detection signal an internal delay equal 20 to (12 - n)/12 of the frame period, where n represents an integex represented by a number signal received by the internal delay circuit. In the example being illustrated, the central station can receive all of upward signals transmitted from all of the repeater and 25 the terminal stations a lapse of one frame period after the central station sencls a downward signal towards the Eirst repea-ter station.
SUBSIDIARY STATION CAPABLE OF AUTOMATICALLY
ADJUSTING AN INTERNA~ DELAY IN RESPONSE TO
A NUMBER SIGNAL RECEIVED IN A DOWNWARD SIGNAL
BY THE SUBSIDIARY STATION
Background of the Invention:
This invention relates to a subsidiary station for use in a time division multiple access network.
Such a time division multiple access network comprises a central or base station, a terminal station remote from the central station, and at least one repeater station placed between the central sta-tion and the terminal station. For convenience of description, each o the terminal and the repeater s-tations is called a subsidiary station.
When initially sét or newly installed in the network, a conventional subsidiary station must be given an internal delay so that a total delay given by adding the internal delay to twice a propagation delay from a next preceding station of the network to the subsidiary station should be equal to a frame period oE a downwar~
ax2 signal received from the central station as will later be described. When the subsidiary station receives the downward signal from the central station, the subsidiary station transmits an upward signal towards the central 5 station. When at least one preceding repeater station is placed between the central station and the subsidiary station, the upward signal reaches the central station a lapse of a time duration, given by multiplying the frame period by the number of the preceding repeater station, 10 a~ter transmission of the downward signal from the central station. Thus, a long time is wasted until reception of the upward signal at the central station after transmission of the downward signal from the central station.
A repeater station is disclosed in United States Patent No. 4,490,813 issued to Shigeru Otsuka and assigned to NEC Corporation. The repeater station is also disclosed in Canadian Patent No. 1,191,205 and in ~ustralian Patent No. 553,157. The repeater station may 20 have a prede-termined initial delay shor-ter than the frame period. It is therefore possible to shorten the time duration between transmission of the downward signal Erom the central station and reception oE the upward signal at the central station. ~lowever, the 25 repeater station is incapable of automatically deciding the internal delay.
~2~3~8~
Summary of the Invention:
It is an object of this invention to provide a subsidiary station capable of automatically deciding an internal delay in response to a particular signal 5 included in a downward signal.
Other objects of this invention will become clear as the description proceeds.
A repeater station to which this invention is applicable is for receiving a first downward signal from 10 a next preceding station with a propagation delay, for transmitting a second downward signal to a next succeeding station, for receiving a first upward signal from the succeeding station, and for transmitting to the preceding station a second upward signal which should be 15 received by the preceding station with the propagation delay. Each of the first and the second downward signals has a frame period and includes a reference signal. Each of the first and the second upward signals has said frame period. The repeater station includes a 20 first delay circuit for giving a fixed delay to the first downward signal, and a first detector for d~tecting the reference signal of the first downward signal to produce a first detection signal. According to an aspect of this invention, the fi~ed delay is 25 rendered equal -to cln inteyral submultiple of said frame period minus said propagation delay. The first downward signal includes a number signal representative o~ an integer corresponding in number to at least one other station through which the firs-t downward signal is received from an originating s-tation. The at least one other station comprises the preceding sta-tion. The repeater station comprises: a second detector for 5 detecting the number signal to produce a second detection signal representative of the integer; an internal delay circuit responsive to the second detection signal for giving an internal delay to the first detection signal to produce a delayed detection 10 signal, the internal delay being decided in consideration of the integer; processing means responsive to the delayed detection signal for processing the first upward signal into a processed signal; and a second delay circuit for giving the fixed 15 delay to the processed signal to produce the second upward signal.
~ terminal station to which this invention is applicable is ~or receiving a downward signal from a next preceding station with a propagation delay and for 20 transmitting to the preceding station an upward signal which should be received by -the preceding station with the propagation delay. The downward signal has a frame period and includes a reference siynal. The upward signal has the frame period. The texminal station 25 includes a fir~t delay circuit for giving a Eixed delay to the downward signal to produce a delayed signal, and a first detector for detecting the reference signal to produce a first de-tection signal. ~ccording to another ~LX~318~Z
aspect of this invention, the fixed delay is rendered equal to an integral submultiple of the frame period minus said propagation delay. The downward signal includes a number signal representative of an integer 5 corresponding in number to at least one repeater station through which the downward signal is received from an originating station. The terminal station comprises: a second detec-tor for detecting the number signal to produce a second detection signal representative of the 10 integer; an internal delay circuit responsive to the second detection signal for giving an internal delay to the first detection signal to produce a delayed detection signal, the internal delay being decided in considexation of the integer; processing means 15 responsive to the delayed detection signal for processing an input signal into a processed signal: and a second delay circuit for giving the fixed delay to the processed signal to produce the upward signal.
Brief Description of the Drawing:
Fig. 1 shows a block diagram of a conventional repeater station together with a next preceding station;
Fig. 2 is a -time chart for use in describing operation O:e the conventional repeater statlon illustrated in Fig. 1:
Fiy. 3 shows a block diagram of a repeater station according to a preferred embodiment of this in~ention together with a next preceding and a next succeeding station;
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Fig. 4 shows formats for downward and upward signals received by the repeater station illustrated in Fig. 3;
Fig. 5 is a time chart for use in describing 5 operation of the repeater station illus-trated in Fig. 3;
and Fig. 6 is another time chart for use in describing modified operation of the repeater station illustrated in Fig. 3.
Description of the Preferr_d Embodiment:
Referring to Fig. 1, a conventional repeater station 10 will be described at first for a better understanding of this invention. The repeater station 10 is for receiving a first downward signal from a next 15 preceding station 11 with a downward propagation delay defined by a downward propagation path 13 and for transmitting a second downward signal to a next succeeding station (later illustrated). The repeater station 10 i.s also for receiving a first upward signal 20 from the succeeding s-tation and for transmitting to the prececling station 11 a second upward signal which should be received by the prec~ding station 11 with an upward propagation delay defined by an upward propagation path 14. The upward propagation delay is substantially equal 25 to the downward propagation delay.
The preceding station 11 may be either a central station or another repeater station. The succeeding uqL~
station may be either a terminal station or another repeater station.
Each of the first and the second downward and upward signals has a frame period. Each of the first 5 and the second downward signals includes a frame alignment signal as a reEerence signal. It will be assumed throughout the following that each frame consists of N bits, where N represents a prescribed natural number.
The repeater station 10 includes a delay circuit 15 for giving a fixed delay to the first downward signal through a first receiving circuit 15' to produce a delayed signal. The fixed delay is rendered equal to a difference between one frame period and a sum of the 15 upward and the downward propagation delays. A first transmitting circuit 16 transmits the delayed signal to the succeeding station as the second downward signal.
Responsive to the delayed signal, a frame allgnment circuit 17 reproduces the frame alignment 20 signal, namely, the reference signal. That is, the frame alignment circuit 17 is operable as a first detector for detecting the reference signal of the first downward signal to produce a first detection signal.
A second receiving circuit 1~ receives the first 25 upward signal. ~ multiplexer 19 processes the first upward signal into a proce.ssed signal in accordance with the first detection signal. The processed signal is transmitted to the preceding station 11 through a second .~
~L28~8Z2 transmitting circuit 19' and the upward propagation path 1~ as the second upward signal.
A terminal station need not comprise the first transmitting and the second receiving circuits 16 and 5 18.
Referring to Fig. 2 together with Fig. 1, description will be made as regards operation of the repeater station 10. It will be assumèd that first, second, and third repeater stations are placed between a 10 central station and a terminal station. Each of the first, the second and the -third stations is similar in structure to the repeater station 10. In Fig. 2, the abscissa represents time while the ordinate represents a distance from the central station.
The central station transmits a first downward signal to the first repeater station. The first repeater station receives the first downward signal with the downward propagation delay. Merely for convenience of description, the downward propagation delay will be 20 assumed to be equal to 1/4 of the frame period.
In the first repeater station, the delay circuit 15 has a fixed delay which is rendered equal to 2/4 of the frame period. Thereore, the delay circuit 15 produces the delayed signal 3/4 frame period after 25 transmission of the first downward signal from the central station.
The frame alignment circuit 17 of the first repeater station extracts the frame alignment signal ~8~ Z
~rom the delayed signal. In accordance with the frame alignment signal, the multiplexer 19 of the first repeater station processes a first upward signal into a processed signal for use as a second upward signal in 5 the manner described above. The second upward signal i~
transmitted -to the central station through the upward propagation path 14 which has the upward propagation delay. Inasmuch as the downward delay is assumed to be 1/4 frame period, khe upward propagation delay is also 10 equal to 1/4 of the frame period. Thus, the central station receives the second upward signal a lapse of one frame period after the first downward signal is sent by the central station.
The first transmitting circuit 16 of the first 15 repeater station transmits the delayed signal as a sQcond downward signal to the second repeater station through another downward propagation path which is between the first and the second repeater stations. The downward propagation path will be assumed to be equal to 20 1/4 of the frame period like the downward propagation path between -the central and the first repea-ter stations. Thus, the second downward signal is received by the second repeater station a lapse of one Erame period after the first downward signal is sent by the 25 central station.
After reception of the second downward signal, the second repeater station transmits another upward signal to the first repeater station in the manner 32~
similar to the ~irst repeater station. This upward signal is immediately repeated by the first repeater station to the central station. As a result, the central station receives the upward signal from the S second repeater station a lapse o~ two frame periods after the irst downward signal is sent by the central stakion.
In this manner, the central station receives an upward signal from the third repeater station a lapse of 10 three frame periods after the central station sends the first downward signal. As for an upward signal of the terminal station, a long time duration of four frame periods is necessary, until reception of the upward signal after transmission of the downward signal of ~he 15 central station. It is now understood that the internal delay of the repeater station results in an objectional delay in reception of an upward signal of a remote station at the central station.
Referring to Fig. 3, a repeater s-tation 20 20 according to a preferred embodiment of this invention comprises similar parts designated by like reference numerals. The rep~ater station 20 is for receiving a first downward signal from a next preceding station 21 with a down propagation delay defined by the downward 25 propagation path 13 and for transmitting a second downward signal to a next succeeding s-tation. The repeater station 20 is also for receiving a first upward signal from the succeeding station and for transmitting l l to the preceding station 21 a second upward signal which should be received by the preceding station 21 with an upward propagation delay defined by the upward propagation path 14.
The preceding station 21 may be either a central station or another repeater station. The succeeding station may be either a terminal station or another repeater station.
Turning to Fig. 4, the first downward signal has 10 a frame period depicted along a top line. As depicted along a second line from the top, the first downward signal includes a frame alignment signal labeled "F" and a number signal labeled "NS" representative of an integer corresponding in number to at least one other 15 station through which the first downward signal is received from an originating station which is usually the central station. The at least one other station comprises the preceding station. The frame alignment signal and the number signal are included in an initial 20 acquision channel labeled "ACQ CH". The frame alignment signal is used as the reference signal. The number ~ignal is called a particular signal hereinabove and is for use in declding an internal delay of each subsidiary station in the manner which will later be described. In 25 the manner known in the ar-t, the first downward signal further includes an order wire channel labeled "OW CH", a predetermined number of voice channels each of which is labeled "V CH", a control channel labeled "C CH", a ~Z818~
supervisory channel labeled "SV CH", and a teleprinter exchange channel labeled "TELEX CH".
As depicted along a bottom line, the upward signal comprises an ini.tial acquision pattern labeled 5 "ACQ P~TTERN" in the initial acquision channel "ACQ CH".
In the manner known in the art, the acquision pattern is interposed between two guard time portions each labeled "G".
Turning back to Fig. 3, the repeater station 20 10 comprises a first delay circuit 15 for giving a fixed delay to the first downward signal through the first receiving circuit 13' to produce a delayed signal as described in conjunction with Fig. 1. It is, however, to be noted that the fixed delay is rendered equal to an 15 integral submultiple l/M of the frame period minus the propagation delay of the downward propagation path 13, where M represents a preselected natural number.
The frame alignment circuit 17 serves as a first detector for detecting the frame alignment or reference 20 signal of the firs-t downward signal to produce a first detection signal as described in conjunction with Fig.
1. In the example being illustrated, the frame alignment ci.rcuit 17 recei.ves the delayed signal from the first delay circuit 15.
~ number signal detector 23 is operable as a second detector for detecting the number signal in the delayed signal with reEerence to the first detection signal to produce a second detection signal ~.
~8~82~
representative of the integer. In this manner, the number signal detector 23 detects the number signal in the first downward signal to produce the second detection signal.
Responsive to the second detection signal, an internal delay circuit 2~ gives an internal delay to the first detection signal to produce a delayed detection signal. The internal delay is automatically decided in consideration of the integer by a read-only memory.
When the repeater station 20 is operable also as a terminal station, a multiplexer 25 is used for connection ko a signal transmission line ~not shown~ for local signals. The multiplexer 25 is for multiplexing the local signals and the ~irst upwara signal received 15 through the second receiving circuit 18 into a multiplexed signal. The first upward signal includes a control signal for supervision in the manner known in the art. The multiplexer 25 is operable as a processing circuit responsive to the delayed detection signal for 20 processing the multiplexed signal into a processed signal. When attention is directed to the ~irst upward signal, it is possible to understand that the mul-tiplexer 25 processes the ~irst upward signal into the processed signal.
A second delay circuit 26 is for giving the fixed delay to the processed signal to produce the second upward signal whieh is transmitted to the preceding station 21 through the second transmitting 8X~
circuit 19' and the upward propagation path 14. The fixed delay is rendered equal to an integral submultiple l/M of the frame period minus the propagation delay of the upward propagation path 1~.
A number signal modifying circuit 27 is operable as a first modifying circuit for modifying the number signal into a modified signal representative of another integer or the succeeding station. Typically, the modified signal is representative of one plus the 10 integer.
A first transmitting circuit 28 serves as a second modifying circuit responsive to the modified signal for modifying the delayed signal into a second downward signal with the modified signal substituted for 15 the number signal included in the delayed signal. When the repeater station 20 is used also as the terminal station in the manner described above, the first transmitting circuit 28 serves at least parthy as a demultiplexer.
In a terminal station, the first transmittiny and the second receiving cirauits 28 and 1~ and the numher signal modifying circuit 27 are unnecessary. The multiplexer 25 is used in multiplexing only local signals which may collec-tively called an input signal.
25 The multiplexer 25 serves as a processing circuit responsive to the delayed signal for processing the input signal into a processed signal.
Referring to Fig. 5 together with Fig, 3, description will proceed to operation of the repeater station 20 and the terminal station. It will be assumed that first, second and third repeater stations are 5 placed between a central station and the terminal station. Each of the first the second and the third stations is similar to the repeater station 20.
The central station transmits to the first repeater station a first downward signal including a 10 frame alignment or reference signal and a number signal.
The number signal may represent unity. The first downward signal reaches the first repeater station with a downward propagation delay of a downward propagation path between the central and the first repeater 15 stations. The first delay circuit 15 produces the delayed signal by giving a fixed delay to the first downward signal. The fixed delay is preliminarily decided so that the delayed signal be produced with a total difference of 1/~ of the frame period relative to 20 transmission of the first downward signal from the central station. For this purpose, the fixed de,lay is rendered equal to an integral submultiple 1/4 of the Erame period minus the downward propagation delay.
Responsive to the number sign~l representative 25 of unity, the internal delay circuit 2~ automatically adjusts the internal delay to 1/2 of the frame period.
The internal delay circuit 2~ gives the internal delay to the first detection signal received from the Erame ~;t7' \~
~IL2~3~8X2 alignment circui~ 17 and produces the delayed detection signal 3/4 frame period after transmission of the first downward signal at the central station.
Responsive to the delayed detection signal, the 5 multiplexer 25 processes the first upward signal into the processed signal. The delayed de-tection signal is used in making the multiplexer 25 begin to produae the processed signal concurrently with the delayed detection signal.
A fixed delay of the second delay circuit 26 is rendered equal to an integral submultiple 1/4 of the frame period minus an upward propagation delay of the upward propagation path 14. Inasmuch as the upward propagation delay is substantially equal to the downward ! 15 propagation delay, the fixed delay of the second delay circuit 26 is substantially equal to the fixed delay of the first delay circuit 15. The second delay circuit 26 gives the fixed delay to the processed signal. As a result, the central station receives the second upward 20 signal a lapse of one frame period after the first downward signal is sent by the central station.
Meanwhile the first detection signal is subjected to the internal delay in the internal delay circuit 2~, the number signal modifying circuit 27 25 modifles the number signal received from the number signal detector 23 into a modified signal representative of another integer for the second station. This integer may be equal to two. In the second downward signal, the ~LX8~3X~
modified signal is substituted for the number signal included in the delayed signal. The first transmitting circuit 28 sends the second downward signal including the modiied signal to a downward propagation path 5 between the first and the second repeater stations.
This downward signal reaches the second repeater station with a downward propagation delay of the downward propagation path. The downward signal therefore reaches the second repeater station, after 10 transmission of the downward signal at the central station, with a delay which is equal -to a sum of the downward propagation delays of the propagation paths between the central and the first repeater stations and between the first and the second repeater stations.
In the second repeater station, the first delay circuit 15 gives a fixed delay to the downward signal.
The fixed delay is preliminarily decided so as to be equal to 1/4 of the frame period minus the propagation delay between the first and the second repeater 20 ~tations. ~s a result, the second repeater station receives the downward signal a lapse of 1/2 of the frame period ater the downward ~ignal is sent by the central station.
Responsive to the modified signal representative 25 of two, the internal delay circuit 24 of the second repeater station gives an internal delay to the first detection signal received from the frame alignment circuit 17. The internal delay is now equal to zero.
'~-82~
Therefore, the second repeater sta-tion produces the processed signal with a delay of 1/2 frame period relative to transmission of the downward signal at the central station.
The second repeater station sends the upward signal to the first repeater station with a total delay of 3/4 frame period after the downward signal is sent by the central station. Thus, the central station receives the upward signal from the second repeater sta-tion a 10 lapse of one frame period after the downward signal is sent by the central station.
Likewise, the third repeater and the terminal stations receive the number signals representative of three and four, respectively. Responsive to the number 15 signal representative of three, the internal delay circuit 24 of the third repeater station gives an internal delay of 1/2 frame period to the first detection signal received from the frame alignment circuit 17. Responsive to the number signal 20 representative of four, the internal delay circuit 24 of the terminal station gives an internal delay of zero to a first detection signal.
As a result, the central station receive3 the upward signals from the third repeater and the terminal 25 stations a lapse of two frame periods after the central station sends the downward signal.
Thus, the central station receives the upward signal from the terminal stations with only a short 11 Z~
delay after transmission oE the downward signal at -the central station. Each of the firs~ through the thir~
repeater stations and the terminal station automatically decides the internal delay in response to the number 5 signal included in the downward signal.
Referring to Fig. 6, description will now be made as regards modified operation of the repeater station 20 (Fig. 3) and the terminal s-tation. In this case, flrst through eighth repea-ter stations are placed lO between central and terminal stations. For each of the repeater and the -terminal stations, a total delay of a downward path 13 (Fig. 3) and a first delay circuit 15 (Fig. 3) is rendered equal to l/24 of a frame period.
~nother to-tal delay of an upward path 14 (Fig. 3) and a ! 15 second delay circuit 26 (Fig. 3) is also rendered equal to 1/24 of the frame period for each of the repeater and the terminal stations. In each of the repeater and the -terminal stations, an internal delay circuit 24 (Fig. 3) gives a first detection signal an internal delay equal 20 to (12 - n)/12 of the frame period, where n represents an integex represented by a number signal received by the internal delay circuit. In the example being illustrated, the central station can receive all of upward signals transmitted from all of the repeater and 25 the terminal stations a lapse of one frame period after the central station sencls a downward signal towards the Eirst repea-ter station.
Claims (3)
1. In a repeater station for receiving a first downward signal from a next preceding station with a propagation delay, for transmitting a second downward signal to a next succeeding station, for receiving a first upward signal from said succeeding station, and for transmitting to said preceding station a second upward signal which should be received by said preceding station with said propagation delay, each of said first and said second downward signals having a frame period and including a reference signal, each of said first and said second upward signals having said frame period, said repeater station including a first delay circuit for giving a fixed delay to said first downward signal to produce a delayed signal for use as said second downward signal, and a first detector for detecting the reference signal of said first downward signal to produce a first detection signal, the improvement wherein:
said fixed delay is rendered equal to an integral submultiple of said frame period minus said propagation delay;
said first downward signal including a number signal representative of an integer corresponding in number to at least one other station through which said first downward signal is received from an originating (Claim 1 continued) station, said at least one other station comprising said preceding station;
said repeater station comprising:
a second detector for detecting said number signal to produce a second detection signal representative of said integer;
an internal delay circuit responsive to said second detection signal for giving an internal delay to said first detection signal to produce a delayed detection signal, said internal delay being decided in consideration of said integer;
processing means responsive to said delayed detection signal for processing said first upward signal into a processed signal; and a second delay circuit for giving said fixed delay to said processed signal to produce said second upward signal.
said fixed delay is rendered equal to an integral submultiple of said frame period minus said propagation delay;
said first downward signal including a number signal representative of an integer corresponding in number to at least one other station through which said first downward signal is received from an originating (Claim 1 continued) station, said at least one other station comprising said preceding station;
said repeater station comprising:
a second detector for detecting said number signal to produce a second detection signal representative of said integer;
an internal delay circuit responsive to said second detection signal for giving an internal delay to said first detection signal to produce a delayed detection signal, said internal delay being decided in consideration of said integer;
processing means responsive to said delayed detection signal for processing said first upward signal into a processed signal; and a second delay circuit for giving said fixed delay to said processed signal to produce said second upward signal.
2. A repeater station as claimed in Claim 1, further comprising:
first modifying means for modifying said number signal into a modified signal representative of another integer for said succeeding station; and second modifying means responsive to said modified signal for modifying said delayed signal into said second downward signal with said modified signal substituted for the number signal included in said delayed signal.
first modifying means for modifying said number signal into a modified signal representative of another integer for said succeeding station; and second modifying means responsive to said modified signal for modifying said delayed signal into said second downward signal with said modified signal substituted for the number signal included in said delayed signal.
3. In a terminal station for receiving a downward signal from a next preceding station with a propagation delay and for transmitting to said preceding station an upward signal which should be received by said preceding station with said propagation delay, said downward signal having a frame period and including a reference signal, said upward signal having said frame period, said terminal station including a first delay circuit for giving a fixed delay to said downward signal to produce a delayed signal, and a first detector for detecting said reference signal to produce a first detection signal, the improvement wherein:
said fixed delay is rendered equal to an integral submultiple of said frame period minus said propagation delay;
said downward signal including a number signal representative of an integer corresponding in number to at least one repeater station through which said downward signal is received from an originating station;
said terminal station comprising:
a second detector for detecting said number signal to produce a second detection signal representative of said integer;
an internal delay circuit responsive to said second detection signal for giving an internal delay to said first detection signal to produce a delayed detection signal, said internal delay being decided in consideration of said integer;
(Claim 3 continued) a second delay circuit for giving said fixed delay to a processed signal to produce said upward signal; and processing means responsive to said delayed detection signal for processing an input signal into said processed signal.
said fixed delay is rendered equal to an integral submultiple of said frame period minus said propagation delay;
said downward signal including a number signal representative of an integer corresponding in number to at least one repeater station through which said downward signal is received from an originating station;
said terminal station comprising:
a second detector for detecting said number signal to produce a second detection signal representative of said integer;
an internal delay circuit responsive to said second detection signal for giving an internal delay to said first detection signal to produce a delayed detection signal, said internal delay being decided in consideration of said integer;
(Claim 3 continued) a second delay circuit for giving said fixed delay to a processed signal to produce said upward signal; and processing means responsive to said delayed detection signal for processing an input signal into said processed signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61218874A JPS6374234A (en) | 1986-09-17 | 1986-09-17 | Multi-direction multiplex communication system |
| JP218874/1986 | 1986-09-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1281822C true CA1281822C (en) | 1991-03-19 |
Family
ID=16726656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000547177A Expired - Fee Related CA1281822C (en) | 1986-09-17 | 1987-09-17 | Subsidiary station capable of automatically adjusting an internal delay in response to a number signal received in a downward signal by the subsidiary station |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4937812A (en) |
| EP (1) | EP0260696B1 (en) |
| JP (1) | JPS6374234A (en) |
| AU (1) | AU594194B2 (en) |
| CA (1) | CA1281822C (en) |
| DE (1) | DE3782896T2 (en) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4805196A (en) * | 1987-04-29 | 1989-02-14 | Gte Laboratories Incorporated | Line delay compensation for digital transmission systems utilizing low power line drivers |
| EP0515029B1 (en) * | 1991-04-19 | 1996-06-26 | Nec Corporation | Time-division multiplex communication system |
| FR2708814B1 (en) * | 1993-07-30 | 1995-09-01 | Alcatel Mobile Comm France | Method for covering the shadow areas of a radiocommunication network, and radio repeater for implementing this method. |
| US5706485A (en) * | 1993-09-21 | 1998-01-06 | Intel Corporation | Method and apparatus for synchronizing clock signals in a multiple die circuit including a stop clock feature |
| US5541979A (en) * | 1994-03-08 | 1996-07-30 | Allen Telecom Group, Inc. | Cell extender with timing alignment for use in time division multiple-access and similar cellular telephone systems |
| US5530451A (en) * | 1994-04-12 | 1996-06-25 | Northrop Grumman Corporation | Repeater with low spurious time outputs |
| US5659575A (en) * | 1995-04-28 | 1997-08-19 | Grinnell Corporation | Method and apparatus for improving data regeneration in asynchronous network communication |
| US5764633A (en) * | 1995-07-31 | 1998-06-09 | Bell; David T. | Method and system for transferring digital telephone circuits |
| JP3417741B2 (en) * | 1995-10-06 | 2003-06-16 | 富士通株式会社 | Transaction control system |
| JPH09214458A (en) * | 1996-01-30 | 1997-08-15 | Fujitsu Ltd | Radio repeater |
| US5838226A (en) * | 1996-02-07 | 1998-11-17 | Lutron Electronics Co.Inc. | Communication protocol for transmission system for controlling and determining the status of electrical devices from remote locations |
| DE19649855B4 (en) * | 1996-12-02 | 2004-08-05 | T-Mobile Deutschland Gmbh | Repeater for radio signals |
| JP3180735B2 (en) * | 1997-10-22 | 2001-06-25 | 松下電器産業株式会社 | Wireless terminal with transmission timing correction function and method of manufacturing the same |
| WO2000003500A1 (en) * | 1998-07-13 | 2000-01-20 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and apparatus for determining optimal time differences between communication channels |
| US6999718B2 (en) | 2001-10-17 | 2006-02-14 | Hitachi Kokusai Electric Inc. | Relay apparatus in a digital radio communication system and a relay method thereof |
| GB0500460D0 (en) * | 2005-01-11 | 2005-02-16 | Koninkl Philips Electronics Nv | Time of flight |
| JP5049652B2 (en) * | 2006-09-07 | 2012-10-17 | キヤノン株式会社 | Communication system, data reproduction control method, controller, controller control method, adapter, adapter control method, and program |
| JP4760978B2 (en) | 2007-03-28 | 2011-08-31 | 株式会社安川電機 | Communication device, synchronous communication system, and synchronous communication method |
| FR2960666B1 (en) * | 2010-05-27 | 2012-08-17 | Airbus Operations Sas | METHOD AND DEVICE FOR SYNCHRONIZATION AND DATATION FOR EQUIPMENT OF AN AFDX COMMUNICATION NETWORK |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2454728A1 (en) * | 1979-04-19 | 1980-11-14 | Telecommunications Sa | METHOD AND DEVICE FOR MONITORING DIGITAL OR ANALOG TELECOMMUNICATIONS LINKS |
| JPS58182928A (en) * | 1982-04-20 | 1983-10-26 | Nec Corp | Radio repeating system |
| JPS59158637A (en) * | 1983-02-28 | 1984-09-08 | Nec Corp | Radio relaying system of time division multiplex multi-access communication system |
| NL8303944A (en) * | 1983-11-17 | 1985-06-17 | Philips Nv | METHOD FOR CONTROLLING A MONITORING DEVICE IN A DIGITAL TRANSMISSION SYSTEM. |
| JPS60241351A (en) * | 1984-05-16 | 1985-11-30 | Kokusai Denshin Denwa Co Ltd <Kdd> | Optical repeater monitor system |
| JPS6225523A (en) * | 1985-07-25 | 1987-02-03 | Nec Corp | Radio communication system |
-
1986
- 1986-09-17 JP JP61218874A patent/JPS6374234A/en active Pending
-
1987
- 1987-09-17 AU AU78615/87A patent/AU594194B2/en not_active Ceased
- 1987-09-17 US US07/097,858 patent/US4937812A/en not_active Expired - Lifetime
- 1987-09-17 EP EP87113623A patent/EP0260696B1/en not_active Expired - Lifetime
- 1987-09-17 DE DE8787113623T patent/DE3782896T2/en not_active Expired - Fee Related
- 1987-09-17 CA CA000547177A patent/CA1281822C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE3782896D1 (en) | 1993-01-14 |
| AU7861587A (en) | 1988-03-24 |
| JPS6374234A (en) | 1988-04-04 |
| EP0260696A2 (en) | 1988-03-23 |
| EP0260696B1 (en) | 1992-12-02 |
| AU594194B2 (en) | 1990-03-01 |
| DE3782896T2 (en) | 1993-04-08 |
| US4937812A (en) | 1990-06-26 |
| EP0260696A3 (en) | 1989-05-24 |
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| Date | Code | Title | Description |
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| MKLA | Lapsed |