CA1278889C - Liquid crystal display driver - Google Patents
Liquid crystal display driverInfo
- Publication number
- CA1278889C CA1278889C CA000527817A CA527817A CA1278889C CA 1278889 C CA1278889 C CA 1278889C CA 000527817 A CA000527817 A CA 000527817A CA 527817 A CA527817 A CA 527817A CA 1278889 C CA1278889 C CA 1278889C
- Authority
- CA
- Canada
- Prior art keywords
- duty
- liquid crystal
- segment
- crystal display
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/04—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
- G09G3/16—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions by control of light from an independent source
- G09G3/18—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions by control of light from an independent source using liquid crystals
Abstract
ABSTRACT OF THE DISCLOSURE
There is disclosed a liquid crystal display driver based on a 1/4-duty binary-voltage driving system.
The driver comprises a driver for generating at least four kinds of common signals and a ROM for generating at least eleven kinds of segment signals, wherein the Von/Voff ratio of the effective value is set to be greater than about 1.7.
There is disclosed a liquid crystal display driver based on a 1/4-duty binary-voltage driving system.
The driver comprises a driver for generating at least four kinds of common signals and a ROM for generating at least eleven kinds of segment signals, wherein the Von/Voff ratio of the effective value is set to be greater than about 1.7.
Description
-` ~2~1389 The present invention relates to a liquid crystal display driver for use in a display unit oE a desktop electronic calculator (hereinafter referred to as a calculator) or the like.
5In the accompanying drawings:-Figures l to 6 show an exemplary embodiment o~
the present invention, in which:
Figure 1 is a circuit diagram of a liquid crystal display driver;
10Figure 2 is a timing chart of output signals from a divider and a ring counter shown in Figure l;
Figure 3 is a timing chart of signals from a clock generator, a ROM and a segment shift register-latch;
Figures 4 (a), (b) and (c) are timing charts of common waveforms, segment waveforms and exemplary applied-voltage waveforms;
Figure 5 is a connection diagram of a l/4 duty segment pattern; and Figure 6 illustrates how the liquid crystal display driver is constituted on a tape; and Figures 7 to 12 show a conventional liquid crystal driver, in which Figures 7 (a), (b) and (c) are timing charts of common waveforms, segment waveforms and exemplary applied-voltage waveforms in a l/3 dutyOl/3 bias driving system;
Figure 8 is a timing chart of drive signals in a l/2 duty pulse driving system;
Figure 9 is a timi.ng chart of drive signals in a 1/3 duty pulse driving system;
30Figure 10 is a circui.t diagram of a 1/~ duty.l/3 bias common waveform generator;
Figure 11 is a connection diagram of a 1/4 duty segment pattern; and Figure 12 illustrates how the liquid crystal display driver is constituted on a tape.
For duty-driving a liquid crystal display (hereinafter abbreviated to LCD), it is necessary to apply ~r a bias voltage so as to obtain a proper on-off effective . , , ., . .,~
.
~2'~
value. In this operation, at least three voltages have been required heretofore, inclusive of more than one intermediate level voltage in addition to a supply voltage. For example, in a dry battery type calculator, a driving operation is performed with 1/3 duty~l/3 bias or 1/4 duty.l/3 bias having two values of intermediate level voltage. The above 1/3 duty.l/3 bias is effected by signals of the waveforms shown in Figure 7. Supposing now E=1.5 V, the VON/VoFF ratio a becomes ~ -. 1.73. In a solar battery type calculator (hereinafter referred to as SB calculator), it is customary to perform a driving operation with 1/3 duty.l/2 bias having three values of a solar battery voltage, a doubled voltage thereof obtained through a booster and an intermediate level voltage. In the former dry battery type calculator where intermediate level voltages are obtained by division through a bleeder resistor, the current is merely slight. However, in the latter SB calculator where the set current is as small as 1/2 to 1/3 of the bleeder current in the dry battery type, it is impossible to adopt a means of producing an intermediate level voltage by a bleeder resistor.
Therefore its power source is formed by the use of a booster equipped with two capacitors outside of an LSI.
However, in the above-described structure, the number of required component parts is increased due to the necessity of providing a booster, and the circuit configuration is rendered complicated.
Meanwhile, with regard to another system for duty-driving the LCD at two voltages o-f a single power source without using such booster which causes-the aforementioned disadvantages, there is known a pulse control syste~l that executes driving by pulses of the waveforms shown in Figure 8 or 9. In the 1/2 duty pulses of Figure 8: (a) shows a waveform Hl where hl represents a selection period and h2 a half selection period; and (b) shows another waveform H2 where h2 represents a selection period and hl a hal-E selection period. The waveform so shaped so shaped as to apply a voltage during each 1-~7~8g ' selection period has an eEfective on-value in its common, while the waveform so shaped as not to apply any voltage has an effective off-value.
When E=1.5 V, VON = ~ E = 1.3 V and VOFF =
~ E = 0 75 V. Therefore the VON/VoFF
becomes ~ 1.73. Meanwhile, in the 1/3 duty pulse shown in Figure 9, VON = 1.22 V and VOFF
= 1.41. Although it is possible to produce a 1/4 duty waveform in a similar way, the ratio ~ becomes as small as 1.29. Since the contrast of the LCD becomes higher with increase o~ the ratio ~ , it is customary in the calculator to adopt a system that ensures a greater value of ~ exceeding 1.73.
The number of signals required for driving the 15 LCD elements can be reduced as the denominator in the LCD-driving duty factor becomes greater, in such a manner that 1/3 is superior to 1/2, 1/4 to 1/3 and so forth.
Therefore, duty drive with such a greater value is desirable on condition that the same display quality can be achieved.
However, in the conventional structure mentioned above, 1/2 duty is the limit due to the value of ~ for pulse-driving the liquid crystal display in the calculator, and 1/3 duty is not employable with respect to the display quality or contrast. Meanwhile for LCD drive in the SB calculator, a 1/3 duty.l/2 bias system is adopted in most cases. In driving an 8-digit LCD, for example, required signals are 27 in total. As compared therewith, at least 36 signals are required in the case oE
using 1/2 duty pulses to consequently bring about an increase of the chip size in an LSI and also a larger number of package plns, thereby causing a higher cost of production.
The present invention has been accomplished in view of the above problems observed in the prior art. An object of the present invention is to provide an improved liquid crystal display driver which is based on a l/4-duty binary-voltage driving system and is capable of reducing f^;~
~.~2~7~
the number of required signals for driving the LCD, thereby realizing dimensional reduction of the LSI with resultant curtailment of the production cost.
Accordingly, the present invention provides a liquid crystal display driver based on a 1/4-duty binary-voltage driving system, comprising, a means for generating at least four kinds of common signals and a means for generating at least eleven kinds of segment signals, wherein the Von/Voff ratio of the effective value is set to be greater than about 1.7.
The present invention will become more fully understood from the detailed description of an embodiment thereof given hereinbelow by way of example with reference to the accompanying drawings, which are given by way of illustration only, and thus are not limitative of the present invention.
A liquid crystal display driver embodying the present invention is based on a l/4-duty binary-voltage driving system as shown in Figure 1. It comprises a clock generator 1; a divider 2 for producing a display signal by dividing an original oscillation frequency into a frequency ~f; a ring counter 3 for producing timing signals hl - h5; a common driver 4 which is a common signal generating means to produce at least 4 kinds of common waveforms Hl - H4; a ROM 5 consisting of a data address decoder 5a and a main ROM 5b to serve as a means for generating at least 11 kinds of segment signals, a segment shi~t register~latch 6 consisting oE a segment shift register ,6a and a segment l,atch 6b; and a segment driver 7 for driving segment signals. The ring counter 3 is connected to the common driver 4 via a T flip-flop 8 and is further connected to the segment shift register,latch 6 via the T flip-flop 8 and an exclusive OR
9. The ROM 5 is connected to the segment shift register~latch 6 via the exclusive OR 9.
Now the operation o~ the liquid crystal display driver having the above constitution will be described ' ~ below with reference to the timing charts of Figures 2 and 1~7~
3. The clock generator 1 produces output signals ~ 2 shown in Figure 3 (a), (b). The output ~f of the divider 2 shown in Figure 2 (a) is synchronous with ~2 as the former is obtained from the latter by frequency division.
Accordingly, hl - h5 of Figure 2 (b) - (f) and Hl - H4 of Figure 2 (h) - (k) are also synchronous with ~2 respectively. The ring counter 3 produces waveEorms of hl - h5 by using ~f as clock pulses. ~ signal FR of Figure 2 (g) is used for inversion per frame and is inverted at the fall of hl. Hl - H4 are EX-OR signals of h2 - h5 and FR.
The ROM 5 generates segment signals and performs the operation shown in Table 1 of truth values where 5 bits of DP and X4 - Xl are used as data and 6 bits of ai/bi and hl - h5 as addresses (10 combinations in total since hl - h5 become 1 simultaneously in only one bit thereof).
1~7~88g' TABLE
, _ ~ming ~, b ~
\ ~ _ _ _ _ llz 11~ 11~ 115 Il, lI'z 11~ 11~ lls 1~ _ _ _ _ _ I_ U O O 1 O 1 () 'O 1 O 1 O I _ _ I
_ 1 1 1 1 l () O O 1 O l O O. O 1 1 O O 'O O O O
1 _ l _ ___ 1 O O O 1 1 O O () O U
l __ _ O () 1 1 O O O 1 () O 1 Z _ I _ _ - I_ 1 O 1 O O I O 1 O () 1 _ _ _ __ O O O 1' O 1 O 1 O 1 O
5In the accompanying drawings:-Figures l to 6 show an exemplary embodiment o~
the present invention, in which:
Figure 1 is a circuit diagram of a liquid crystal display driver;
10Figure 2 is a timing chart of output signals from a divider and a ring counter shown in Figure l;
Figure 3 is a timing chart of signals from a clock generator, a ROM and a segment shift register-latch;
Figures 4 (a), (b) and (c) are timing charts of common waveforms, segment waveforms and exemplary applied-voltage waveforms;
Figure 5 is a connection diagram of a l/4 duty segment pattern; and Figure 6 illustrates how the liquid crystal display driver is constituted on a tape; and Figures 7 to 12 show a conventional liquid crystal driver, in which Figures 7 (a), (b) and (c) are timing charts of common waveforms, segment waveforms and exemplary applied-voltage waveforms in a l/3 dutyOl/3 bias driving system;
Figure 8 is a timing chart of drive signals in a l/2 duty pulse driving system;
Figure 9 is a timi.ng chart of drive signals in a 1/3 duty pulse driving system;
30Figure 10 is a circui.t diagram of a 1/~ duty.l/3 bias common waveform generator;
Figure 11 is a connection diagram of a 1/4 duty segment pattern; and Figure 12 illustrates how the liquid crystal display driver is constituted on a tape.
For duty-driving a liquid crystal display (hereinafter abbreviated to LCD), it is necessary to apply ~r a bias voltage so as to obtain a proper on-off effective . , , ., . .,~
.
~2'~
value. In this operation, at least three voltages have been required heretofore, inclusive of more than one intermediate level voltage in addition to a supply voltage. For example, in a dry battery type calculator, a driving operation is performed with 1/3 duty~l/3 bias or 1/4 duty.l/3 bias having two values of intermediate level voltage. The above 1/3 duty.l/3 bias is effected by signals of the waveforms shown in Figure 7. Supposing now E=1.5 V, the VON/VoFF ratio a becomes ~ -. 1.73. In a solar battery type calculator (hereinafter referred to as SB calculator), it is customary to perform a driving operation with 1/3 duty.l/2 bias having three values of a solar battery voltage, a doubled voltage thereof obtained through a booster and an intermediate level voltage. In the former dry battery type calculator where intermediate level voltages are obtained by division through a bleeder resistor, the current is merely slight. However, in the latter SB calculator where the set current is as small as 1/2 to 1/3 of the bleeder current in the dry battery type, it is impossible to adopt a means of producing an intermediate level voltage by a bleeder resistor.
Therefore its power source is formed by the use of a booster equipped with two capacitors outside of an LSI.
However, in the above-described structure, the number of required component parts is increased due to the necessity of providing a booster, and the circuit configuration is rendered complicated.
Meanwhile, with regard to another system for duty-driving the LCD at two voltages o-f a single power source without using such booster which causes-the aforementioned disadvantages, there is known a pulse control syste~l that executes driving by pulses of the waveforms shown in Figure 8 or 9. In the 1/2 duty pulses of Figure 8: (a) shows a waveform Hl where hl represents a selection period and h2 a half selection period; and (b) shows another waveform H2 where h2 represents a selection period and hl a hal-E selection period. The waveform so shaped so shaped as to apply a voltage during each 1-~7~8g ' selection period has an eEfective on-value in its common, while the waveform so shaped as not to apply any voltage has an effective off-value.
When E=1.5 V, VON = ~ E = 1.3 V and VOFF =
~ E = 0 75 V. Therefore the VON/VoFF
becomes ~ 1.73. Meanwhile, in the 1/3 duty pulse shown in Figure 9, VON = 1.22 V and VOFF
= 1.41. Although it is possible to produce a 1/4 duty waveform in a similar way, the ratio ~ becomes as small as 1.29. Since the contrast of the LCD becomes higher with increase o~ the ratio ~ , it is customary in the calculator to adopt a system that ensures a greater value of ~ exceeding 1.73.
The number of signals required for driving the 15 LCD elements can be reduced as the denominator in the LCD-driving duty factor becomes greater, in such a manner that 1/3 is superior to 1/2, 1/4 to 1/3 and so forth.
Therefore, duty drive with such a greater value is desirable on condition that the same display quality can be achieved.
However, in the conventional structure mentioned above, 1/2 duty is the limit due to the value of ~ for pulse-driving the liquid crystal display in the calculator, and 1/3 duty is not employable with respect to the display quality or contrast. Meanwhile for LCD drive in the SB calculator, a 1/3 duty.l/2 bias system is adopted in most cases. In driving an 8-digit LCD, for example, required signals are 27 in total. As compared therewith, at least 36 signals are required in the case oE
using 1/2 duty pulses to consequently bring about an increase of the chip size in an LSI and also a larger number of package plns, thereby causing a higher cost of production.
The present invention has been accomplished in view of the above problems observed in the prior art. An object of the present invention is to provide an improved liquid crystal display driver which is based on a l/4-duty binary-voltage driving system and is capable of reducing f^;~
~.~2~7~
the number of required signals for driving the LCD, thereby realizing dimensional reduction of the LSI with resultant curtailment of the production cost.
Accordingly, the present invention provides a liquid crystal display driver based on a 1/4-duty binary-voltage driving system, comprising, a means for generating at least four kinds of common signals and a means for generating at least eleven kinds of segment signals, wherein the Von/Voff ratio of the effective value is set to be greater than about 1.7.
The present invention will become more fully understood from the detailed description of an embodiment thereof given hereinbelow by way of example with reference to the accompanying drawings, which are given by way of illustration only, and thus are not limitative of the present invention.
A liquid crystal display driver embodying the present invention is based on a l/4-duty binary-voltage driving system as shown in Figure 1. It comprises a clock generator 1; a divider 2 for producing a display signal by dividing an original oscillation frequency into a frequency ~f; a ring counter 3 for producing timing signals hl - h5; a common driver 4 which is a common signal generating means to produce at least 4 kinds of common waveforms Hl - H4; a ROM 5 consisting of a data address decoder 5a and a main ROM 5b to serve as a means for generating at least 11 kinds of segment signals, a segment shi~t register~latch 6 consisting oE a segment shift register ,6a and a segment l,atch 6b; and a segment driver 7 for driving segment signals. The ring counter 3 is connected to the common driver 4 via a T flip-flop 8 and is further connected to the segment shift register,latch 6 via the T flip-flop 8 and an exclusive OR
9. The ROM 5 is connected to the segment shift register~latch 6 via the exclusive OR 9.
Now the operation o~ the liquid crystal display driver having the above constitution will be described ' ~ below with reference to the timing charts of Figures 2 and 1~7~
3. The clock generator 1 produces output signals ~ 2 shown in Figure 3 (a), (b). The output ~f of the divider 2 shown in Figure 2 (a) is synchronous with ~2 as the former is obtained from the latter by frequency division.
Accordingly, hl - h5 of Figure 2 (b) - (f) and Hl - H4 of Figure 2 (h) - (k) are also synchronous with ~2 respectively. The ring counter 3 produces waveEorms of hl - h5 by using ~f as clock pulses. ~ signal FR of Figure 2 (g) is used for inversion per frame and is inverted at the fall of hl. Hl - H4 are EX-OR signals of h2 - h5 and FR.
The ROM 5 generates segment signals and performs the operation shown in Table 1 of truth values where 5 bits of DP and X4 - Xl are used as data and 6 bits of ai/bi and hl - h5 as addresses (10 combinations in total since hl - h5 become 1 simultaneously in only one bit thereof).
1~7~88g' TABLE
, _ ~ming ~, b ~
\ ~ _ _ _ _ llz 11~ 11~ 115 Il, lI'z 11~ 11~ lls 1~ _ _ _ _ _ I_ U O O 1 O 1 () 'O 1 O 1 O I _ _ I
_ 1 1 1 1 l () O O 1 O l O O. O 1 1 O O 'O O O O
1 _ l _ ___ 1 O O O 1 1 O O () O U
l __ _ O () 1 1 O O O 1 () O 1 Z _ I _ _ - I_ 1 O 1 O O I O 1 O () 1 _ _ _ __ O O O 1' O 1 O 1 O 1 O
3 I _ _ _ _ I I_ _ __ _ _ I
O O O, 1 1 O 1 O O 1 O
O O O, 1 1 O 1 O O 1 O
4 I _ _ I_ I
5 _ _ _ l 1 O O O 1 O O O 1 G _ _ l I _ _ __ _ 7 _ _ I _ _ _ __ .
_ _ _ _ _ _ 1. 1 1 1 1 O 1 1 1 1 O
--1------- I I _ _ 9 _ __ I _ __ _ _ _ _ . ' 1 1 1 1 1 O O O O 1 1 _ ~ I ~--_ __ .__ 1~ n O O O O O O O () () O O
k _ I_ _ _ __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ (Bnk: Blank) : . .
..
`` ~2~8~
X4 - Xl and DP denote signals from a data register ~not shown), and the output Q of the ROM 5 is obtained in accordance with such contents and the timing of ai/bi and hl - hS. For example, at the timing of hl as shown in Figure 3, first a signal al is decoded according to ~w of Figure 3 (d) with ai/bi = 1 (timing of ai) in Figure 3 (e) and then is inputted to the segment shift register 6a~ In this stage, if the display content of the first digit (al, bl) is 8, it follows that Q = 0 as the ROM 5 produces an output 0 due to Xin = 8, DP = 0 and al-hl from Table 1. In case FR = 0, a bit 0 is inputted tothe fore (left) end oE the segment shift register 6a. At the next timing, Q = 1 as ai/bi = 0 (bi), Xin = 8, DP = 0 and hl from Table 1, so that a bit 1 is inputted to the fore end of the segment shift register 6a according to ~w, and simultaneously the content of the segment shift register 6a is shifted rightward by one bit. When the display content of the second digit is 2, it follows similarly that Q = 0 as ai/bi = 1, Xin = 2, DP = 1 and hl;
and Q = 0 as ai/bi = 0, Xi = 2, DP = 1 and hl. Thereafter the operation is continued until signals for the eighth digit and the symbol digit S are decoded, whereby the entire 17 bits of the segment shift register 6a are filled with data.
~T in Figure 2 (Q) denotes a signal produced at the fall of hl and serving to decide the timing to transfer the content of the segment shift register 6a to the segment latch 6b in parallel. The 17-bit data decoded at the timing of hl is transferred to the segment latch 6b according to the pulse '~T produced synchronously with the fall of hl and is outputted Erom terminals al-bl - S via a buffer of the segment driver 7. The timing aEter such transfer according to the pulse '~T corresponds to h2, but the content oE the display signal outputted from the terminals corresponds to hl~ Any timing error caused by the segment shift register 6a and the segment latch 6b is corrected by changing h2 to Hl, h3 to H2, h4 to H3 and h5 to H4 respectively in the common driver 4. At the timing .. : ~ .~,, . .. . ., ; . :
::
~7~38~
of h2, decoding is executed in accordance with Xin, ~P, ai.bi and h2, and after being inputted to the segment shift register 6a, the data is transferred to the segment latch 6b according to the pulse ~T produced at the fall of h2 and then is displayed. Thereafter the data is decoded similarly to the above until the timing of h5 and subse~uently the procedure is returned to the timing of hl. This operation is performed exactly in the same manner until the output Q oE the ROM 5 is obtained, and thereafter the signal FR becomes 1, so that an inverted signal of Q is fed to the segment shift register 6a.
Denoted by Xin-DP in Figure 3 (i) is a timing to switch over the data synchronously with ~2. A shiEt pulse ~w for the segment shift register 6a is sampled at the timing of ~1. Shown in Figure 3 (j) is the output waveform of Q
~timing of hl) obtained when the content of the display data register representing the values of Xin and DP is 64512.8. The terminal S is provided for turning on a symbol or the like other than ~-shaped character segments, and it is usable within a range of combinations of the segment waveforms shown in Figure 3.
The liquid crystal display driver described hereinabove has the following features in compa~ison with the aforementioned conventional one.
(1) With regard to the driving signal waveform shown in Figure 4, the portions corresponding to hl ana h2 in the driving pulses of Figure 8 are existent merely as timing, and the respective eEfective values are obtainable throughout the entirety oE one frame. The timing is composed oE 5 bits despite 1/4 duty and fulEills an important role as a correction period for ensuring a proper effective value relative to the portion denoted by T in Figure 4 (a).
(2) When E = 1.5, the effective value of the driving signal waveform is, Erom Figure 4, VON = ~7-5-E =
1.16 V and VOFF = ~l7~.E = 0.67 V. Although this value is about 10~ smaller than that obtained in the pulse drive of Figure 8, it may be taken into consideration at the time ~Z71!3~3~39 o~ selecting Vth of the LC~. The VON/VoFF ratio ~ becomes ~- - 1.73, which is equal to the value in the aForesaid pulse drive.
(3) Due to the 1/4 duty, the number of required drive signals in an 8-digit desktop electronic calculator is 21 which is less by 15 signals as compared with l/2 duty pulses and corresponds to less than 60% thereof, whereby the number of pads in the LSI chip can be diminished to eventually realize dimensional reduction of both the LSI and the apparatus to which the present invention is applied. Furthermore, since the number of package pins can also be diminished, it becomes possible to lower the production cost of the LSI. In addition, the common driver 4 shown in Figure l is widely simplified in comparison with the conventional l/4 duty-l/3 bias common signal generator of Figure lO.
(4) The l/4-duty binary-voltage driving; system adopted in the present invention is contrived in the following manner correspondingly to a ~ -shaped character ~0 pattern. As is apparent from the waveEorms of Figure 4, 16 patterns formable by on-o-Ef combinations of Hl - H4 are not entirely existent in this system, and there are merely 12 patterns with the exception of 4 patterns where one of Hl - ~4 is on while the remaining three are off.
Meanwhile, in the case of representing 0 - 9 (inclusive of a sign ) with ~ -shaped character segments, there are only 11 patterns of on-off combinations as shown in Tables 4 and 5 according to the conventional method of connecting l/4 duty segments shown in Figure ll. ~owever, Table 5 includes a pattern (lO00) which is not existent in Figure 4, so that it is not usable directly without any change.
Accordingly, with respect to the ~ -shaped character segment pattern, the combinations have been modified to those shown in Figure 5. Patterns of such modiEied combinations are shown in Tables 2 and 3. The patterns oE
Table 3 are entirely included in those of Figure 4 and can therefore be displayed. Denoted by x in ai - H4 of Table f 1 4 and ai - H3 of Table 5 represents either 1 or 0, ~Z7~ 39 signifying that there are two cases with and without a decimal point.
~LX~8~39 a I b . 11,1-1 z 11 ~ 11, ~I z 11 __ l 1 1 x () (1 () O () __ 1 ~
_1_, 1 () X 1 1 1 0 1 1 _1 1 1 x 1 1 0 1 0 _--~ _ 1_1 1 1 x ~ O ~ 1 0 _... _ 1- 1 X 1I 1 1 () _-- I ~_ ~ 1 x 1 _ 1 1 1 1 _ 1l 1 l x o 1 1 () U
1-1 1 , x 1 _--..
1-1 1 1 x 1 1 1 1 () __.1 1 1,1 l ~ x ~ 1 1 0 1 Entire patterns of ai and ki (11 p~tterns) l _ 0 0''0 0 IO 0 1 ~ 1 ~ O 10 1 1 0 1 1 1 11 () O
12~8889 T~,BLE 4 ~ 2 ~ 1 ~ z --. _.._ 1. o 1 1 x () ~) () o ~ _ _ _ rl. 1 1 o x U ~ _ -I I I Ix () I () I
_,__,. _ .
. . ~ 1... () I 1 x ~
5. lolx 1 l()l _., .,. . __ .!-1..... 1 (" x , 1 1 1- , -Fl ,, x l () o u _ '-I 1 1 lx I I, (, . 1 1 1 X 1 () 1 Entire pa-tterns oE ai and bl (11 patt~r~) O U' U U I O O O
~) 1 1 U 1 () I 1 U 1 1 1 I I O () 1 1 () I
1 1 1 () I 1 l 1 ~_q,~ 8~
(5) In this display driver where the number of both LCD driving signals and pac~age pins are diminished, terminals can be disposed in an improved array particularly when manufacturing an LSI package with a film carrier by the art of TAB (tape automated bonding), thereby attaining remarkable ef~ects in reducing the number of film pitches and curtailing the material cost.
Fiqure 12 illustrates an exemplary arrangement of a conventional film carrier LSI, wherein terminals 20 ...
for the LCD and keys are arrayed in parallel with one another in the longitudinal direction of a tape 21, and the width of the LSI is determined by that of the tape 21 (actually the effective width W with the exception of sprockets 22 ...). The number of pitches or sprockets 22 ... is adjusted in accordance with the number of terminals 20 ... to determine the tape length for each LSI 23. The number of terminals 20 ... disposable within one pitch is determined substantially by the mounting precision.
Supposing that the terminal pitch is 0.9 mm as illustrated 20 in Figure 12, a tape length of 27.9 mm is required for arraying 31 terminals 20, thereby necessitating 6 pitches.
Meanwhile 26 terminals are provided as shown in Figure 6, so that the tape length required is 23.4 mm which corresponds to 5 pitches. However, since the transverse 25 effective length of the tape 21 is 25.4 mm, it becomes possible to achieve a transverse array of terminals 20 .... In contrast with the tape 21 of Figure 12 where power terminals and component mounting pads are arrayed transversely with margin space, there exists the possibility in the example of Figure 6 that the density can be increased to 2 - 3 pitches corresponding to 9.5-14.25 mm. Consequently, as compared with 5 pitches in the conventional structure, the number of film pitches can be diminished to a half to eventually accomplish wide reduction of the required material and, thus, of the production C08 t.
As described hereinabove, the liquid crystal display driver of the present invention is based on a 1/4-:
8~389 duty binary-voltage driving system and is equipped with a means for generating at least 4 kinds of common signals and a means for generating at least 11 kinds of segment signals, wherein the Von/Voff ratio is set to be greater than about 1.7, so that the following advantageous effects are attainable.
(1) Due to its operation performed with a single power source, no booster is required to consequently simplify the circuit configuration.
Therefore a capacitor for the booster can be eliminated to reduce the number of component parts, whereby a dimensional reduction is achievable relative to the LSI
chip with resultant curtailment of the production cost.
(2) The number of LCD driving terminals can be diminished as compared with the known device to eventually reduce the dimensions of the LSI package, hence curtailing the production cost of the LSI and rendering the display driver more compact.
(3) Because a booster is not necessary, the driving voltage can be lowered to eventually decrease the power consumed in the LSI and LCD. Accordingly, it becomes possible to realize a smaller power source with reduced production cost.
While only certain embodiments of the present invention have been described, it will be apparent to those skilled in the art that various changes and modifications maybe made therein without departing Erom the spirit and scope of the present invention as claimed.
r,f9,
_ _ _ _ _ _ 1. 1 1 1 1 O 1 1 1 1 O
--1------- I I _ _ 9 _ __ I _ __ _ _ _ _ . ' 1 1 1 1 1 O O O O 1 1 _ ~ I ~--_ __ .__ 1~ n O O O O O O O () () O O
k _ I_ _ _ __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ (Bnk: Blank) : . .
..
`` ~2~8~
X4 - Xl and DP denote signals from a data register ~not shown), and the output Q of the ROM 5 is obtained in accordance with such contents and the timing of ai/bi and hl - hS. For example, at the timing of hl as shown in Figure 3, first a signal al is decoded according to ~w of Figure 3 (d) with ai/bi = 1 (timing of ai) in Figure 3 (e) and then is inputted to the segment shift register 6a~ In this stage, if the display content of the first digit (al, bl) is 8, it follows that Q = 0 as the ROM 5 produces an output 0 due to Xin = 8, DP = 0 and al-hl from Table 1. In case FR = 0, a bit 0 is inputted tothe fore (left) end oE the segment shift register 6a. At the next timing, Q = 1 as ai/bi = 0 (bi), Xin = 8, DP = 0 and hl from Table 1, so that a bit 1 is inputted to the fore end of the segment shift register 6a according to ~w, and simultaneously the content of the segment shift register 6a is shifted rightward by one bit. When the display content of the second digit is 2, it follows similarly that Q = 0 as ai/bi = 1, Xin = 2, DP = 1 and hl;
and Q = 0 as ai/bi = 0, Xi = 2, DP = 1 and hl. Thereafter the operation is continued until signals for the eighth digit and the symbol digit S are decoded, whereby the entire 17 bits of the segment shift register 6a are filled with data.
~T in Figure 2 (Q) denotes a signal produced at the fall of hl and serving to decide the timing to transfer the content of the segment shift register 6a to the segment latch 6b in parallel. The 17-bit data decoded at the timing of hl is transferred to the segment latch 6b according to the pulse '~T produced synchronously with the fall of hl and is outputted Erom terminals al-bl - S via a buffer of the segment driver 7. The timing aEter such transfer according to the pulse '~T corresponds to h2, but the content oE the display signal outputted from the terminals corresponds to hl~ Any timing error caused by the segment shift register 6a and the segment latch 6b is corrected by changing h2 to Hl, h3 to H2, h4 to H3 and h5 to H4 respectively in the common driver 4. At the timing .. : ~ .~,, . .. . ., ; . :
::
~7~38~
of h2, decoding is executed in accordance with Xin, ~P, ai.bi and h2, and after being inputted to the segment shift register 6a, the data is transferred to the segment latch 6b according to the pulse ~T produced at the fall of h2 and then is displayed. Thereafter the data is decoded similarly to the above until the timing of h5 and subse~uently the procedure is returned to the timing of hl. This operation is performed exactly in the same manner until the output Q oE the ROM 5 is obtained, and thereafter the signal FR becomes 1, so that an inverted signal of Q is fed to the segment shift register 6a.
Denoted by Xin-DP in Figure 3 (i) is a timing to switch over the data synchronously with ~2. A shiEt pulse ~w for the segment shift register 6a is sampled at the timing of ~1. Shown in Figure 3 (j) is the output waveform of Q
~timing of hl) obtained when the content of the display data register representing the values of Xin and DP is 64512.8. The terminal S is provided for turning on a symbol or the like other than ~-shaped character segments, and it is usable within a range of combinations of the segment waveforms shown in Figure 3.
The liquid crystal display driver described hereinabove has the following features in compa~ison with the aforementioned conventional one.
(1) With regard to the driving signal waveform shown in Figure 4, the portions corresponding to hl ana h2 in the driving pulses of Figure 8 are existent merely as timing, and the respective eEfective values are obtainable throughout the entirety oE one frame. The timing is composed oE 5 bits despite 1/4 duty and fulEills an important role as a correction period for ensuring a proper effective value relative to the portion denoted by T in Figure 4 (a).
(2) When E = 1.5, the effective value of the driving signal waveform is, Erom Figure 4, VON = ~7-5-E =
1.16 V and VOFF = ~l7~.E = 0.67 V. Although this value is about 10~ smaller than that obtained in the pulse drive of Figure 8, it may be taken into consideration at the time ~Z71!3~3~39 o~ selecting Vth of the LC~. The VON/VoFF ratio ~ becomes ~- - 1.73, which is equal to the value in the aForesaid pulse drive.
(3) Due to the 1/4 duty, the number of required drive signals in an 8-digit desktop electronic calculator is 21 which is less by 15 signals as compared with l/2 duty pulses and corresponds to less than 60% thereof, whereby the number of pads in the LSI chip can be diminished to eventually realize dimensional reduction of both the LSI and the apparatus to which the present invention is applied. Furthermore, since the number of package pins can also be diminished, it becomes possible to lower the production cost of the LSI. In addition, the common driver 4 shown in Figure l is widely simplified in comparison with the conventional l/4 duty-l/3 bias common signal generator of Figure lO.
(4) The l/4-duty binary-voltage driving; system adopted in the present invention is contrived in the following manner correspondingly to a ~ -shaped character ~0 pattern. As is apparent from the waveEorms of Figure 4, 16 patterns formable by on-o-Ef combinations of Hl - H4 are not entirely existent in this system, and there are merely 12 patterns with the exception of 4 patterns where one of Hl - ~4 is on while the remaining three are off.
Meanwhile, in the case of representing 0 - 9 (inclusive of a sign ) with ~ -shaped character segments, there are only 11 patterns of on-off combinations as shown in Tables 4 and 5 according to the conventional method of connecting l/4 duty segments shown in Figure ll. ~owever, Table 5 includes a pattern (lO00) which is not existent in Figure 4, so that it is not usable directly without any change.
Accordingly, with respect to the ~ -shaped character segment pattern, the combinations have been modified to those shown in Figure 5. Patterns of such modiEied combinations are shown in Tables 2 and 3. The patterns oE
Table 3 are entirely included in those of Figure 4 and can therefore be displayed. Denoted by x in ai - H4 of Table f 1 4 and ai - H3 of Table 5 represents either 1 or 0, ~Z7~ 39 signifying that there are two cases with and without a decimal point.
~LX~8~39 a I b . 11,1-1 z 11 ~ 11, ~I z 11 __ l 1 1 x () (1 () O () __ 1 ~
_1_, 1 () X 1 1 1 0 1 1 _1 1 1 x 1 1 0 1 0 _--~ _ 1_1 1 1 x ~ O ~ 1 0 _... _ 1- 1 X 1I 1 1 () _-- I ~_ ~ 1 x 1 _ 1 1 1 1 _ 1l 1 l x o 1 1 () U
1-1 1 , x 1 _--..
1-1 1 1 x 1 1 1 1 () __.1 1 1,1 l ~ x ~ 1 1 0 1 Entire patterns of ai and ki (11 p~tterns) l _ 0 0''0 0 IO 0 1 ~ 1 ~ O 10 1 1 0 1 1 1 11 () O
12~8889 T~,BLE 4 ~ 2 ~ 1 ~ z --. _.._ 1. o 1 1 x () ~) () o ~ _ _ _ rl. 1 1 o x U ~ _ -I I I Ix () I () I
_,__,. _ .
. . ~ 1... () I 1 x ~
5. lolx 1 l()l _., .,. . __ .!-1..... 1 (" x , 1 1 1- , -Fl ,, x l () o u _ '-I 1 1 lx I I, (, . 1 1 1 X 1 () 1 Entire pa-tterns oE ai and bl (11 patt~r~) O U' U U I O O O
~) 1 1 U 1 () I 1 U 1 1 1 I I O () 1 1 () I
1 1 1 () I 1 l 1 ~_q,~ 8~
(5) In this display driver where the number of both LCD driving signals and pac~age pins are diminished, terminals can be disposed in an improved array particularly when manufacturing an LSI package with a film carrier by the art of TAB (tape automated bonding), thereby attaining remarkable ef~ects in reducing the number of film pitches and curtailing the material cost.
Fiqure 12 illustrates an exemplary arrangement of a conventional film carrier LSI, wherein terminals 20 ...
for the LCD and keys are arrayed in parallel with one another in the longitudinal direction of a tape 21, and the width of the LSI is determined by that of the tape 21 (actually the effective width W with the exception of sprockets 22 ...). The number of pitches or sprockets 22 ... is adjusted in accordance with the number of terminals 20 ... to determine the tape length for each LSI 23. The number of terminals 20 ... disposable within one pitch is determined substantially by the mounting precision.
Supposing that the terminal pitch is 0.9 mm as illustrated 20 in Figure 12, a tape length of 27.9 mm is required for arraying 31 terminals 20, thereby necessitating 6 pitches.
Meanwhile 26 terminals are provided as shown in Figure 6, so that the tape length required is 23.4 mm which corresponds to 5 pitches. However, since the transverse 25 effective length of the tape 21 is 25.4 mm, it becomes possible to achieve a transverse array of terminals 20 .... In contrast with the tape 21 of Figure 12 where power terminals and component mounting pads are arrayed transversely with margin space, there exists the possibility in the example of Figure 6 that the density can be increased to 2 - 3 pitches corresponding to 9.5-14.25 mm. Consequently, as compared with 5 pitches in the conventional structure, the number of film pitches can be diminished to a half to eventually accomplish wide reduction of the required material and, thus, of the production C08 t.
As described hereinabove, the liquid crystal display driver of the present invention is based on a 1/4-:
8~389 duty binary-voltage driving system and is equipped with a means for generating at least 4 kinds of common signals and a means for generating at least 11 kinds of segment signals, wherein the Von/Voff ratio is set to be greater than about 1.7, so that the following advantageous effects are attainable.
(1) Due to its operation performed with a single power source, no booster is required to consequently simplify the circuit configuration.
Therefore a capacitor for the booster can be eliminated to reduce the number of component parts, whereby a dimensional reduction is achievable relative to the LSI
chip with resultant curtailment of the production cost.
(2) The number of LCD driving terminals can be diminished as compared with the known device to eventually reduce the dimensions of the LSI package, hence curtailing the production cost of the LSI and rendering the display driver more compact.
(3) Because a booster is not necessary, the driving voltage can be lowered to eventually decrease the power consumed in the LSI and LCD. Accordingly, it becomes possible to realize a smaller power source with reduced production cost.
While only certain embodiments of the present invention have been described, it will be apparent to those skilled in the art that various changes and modifications maybe made therein without departing Erom the spirit and scope of the present invention as claimed.
r,f9,
Claims (2)
1. A liquid crystal display driver based on a 1/4-duty binary-voltage driving system, comprising a means for generating at least four kinds of common signals and a means for generating at least eleven kinds of segment signals, wherein the Von/Voff ratio of the effective value is set to be greater than about 1.7.
2. The liquid crystal display driver as defined in Claim 1, wherein patterns of ?-shaped characters are displayed.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61014372A JPS62172324A (en) | 1986-01-24 | 1986-01-24 | Liquid crystal display |
| JP61-14372 | 1986-01-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1278889C true CA1278889C (en) | 1991-01-08 |
Family
ID=11859218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000527817A Expired - Lifetime CA1278889C (en) | 1986-01-24 | 1987-01-21 | Liquid crystal display driver |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4981339A (en) |
| EP (1) | EP0234734B1 (en) |
| JP (1) | JPS62172324A (en) |
| CA (1) | CA1278889C (en) |
| DE (1) | DE3789978T2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950012082B1 (en) * | 1991-04-25 | 1995-10-13 | 니뽄 덴끼 가부시끼가이샤 | Display controller |
| JP3139892B2 (en) * | 1993-09-13 | 2001-03-05 | 株式会社東芝 | Data selection circuit |
| JP3572473B2 (en) * | 1997-01-30 | 2004-10-06 | 株式会社ルネサステクノロジ | Liquid crystal display control device |
| JPH1152332A (en) | 1997-08-08 | 1999-02-26 | Matsushita Electric Ind Co Ltd | Simple matrix liquid crystal driving method |
| US6670938B1 (en) * | 1999-02-16 | 2003-12-30 | Canon Kabushiki Kaisha | Electronic circuit and liquid crystal display apparatus including same |
| US20040070555A1 (en) * | 2002-10-03 | 2004-04-15 | Kinpo Electronics, Inc. | Driving device of double-display calculating machine |
| CN109064991B (en) * | 2018-10-23 | 2020-12-29 | 京东方科技集团股份有限公司 | Gate drive circuit, control method thereof and display device |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3820108A (en) * | 1972-03-10 | 1974-06-25 | Optel Corp | Decoder and driver circuits particularly adapted for use with liquid crystal displays |
| JPS5234918B2 (en) * | 1974-05-31 | 1977-09-06 | ||
| JPS5189348A (en) * | 1975-02-04 | 1976-08-05 | ||
| JPS5271152A (en) * | 1975-12-10 | 1977-06-14 | Seiko Epson Corp | Computer |
| JPS5335432A (en) * | 1976-09-14 | 1978-04-01 | Canon Inc | Display unit |
| GB1595861A (en) * | 1977-02-14 | 1981-08-19 | Citizen Watch Co Ltd | Matrix drive system for liquid crystal display |
| JPS53139494A (en) * | 1977-05-11 | 1978-12-05 | Seiko Epson Corp | Electrode structure of display unit |
| JPS5491144A (en) * | 1977-12-28 | 1979-07-19 | Canon Inc | Electronic apparatus |
| JPS56150785A (en) * | 1980-04-23 | 1981-11-21 | Hitachi Ltd | Liquid crystal display unit |
| JPS5983013A (en) * | 1982-11-02 | 1984-05-14 | Shiojiri Kogyo Kk | Liquid crystal display type digital multimeter |
-
1986
- 1986-01-24 JP JP61014372A patent/JPS62172324A/en active Granted
-
1987
- 1987-01-21 CA CA000527817A patent/CA1278889C/en not_active Expired - Lifetime
- 1987-01-26 DE DE3789978T patent/DE3789978T2/en not_active Expired - Lifetime
- 1987-01-26 EP EP87300645A patent/EP0234734B1/en not_active Expired - Lifetime
-
1989
- 1989-09-05 US US07/403,982 patent/US4981339A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0439649B2 (en) | 1992-06-30 |
| EP0234734B1 (en) | 1994-06-08 |
| DE3789978D1 (en) | 1994-07-14 |
| US4981339A (en) | 1991-01-01 |
| EP0234734A3 (en) | 1989-06-07 |
| EP0234734A2 (en) | 1987-09-02 |
| DE3789978T2 (en) | 1994-11-03 |
| JPS62172324A (en) | 1987-07-29 |
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