CA1270339A - System for determining a truth of software in an information processing apparatus - Google Patents

Abstract

ABSTRACT
A system for determining a truth comprises a main unit which is employed together with an external memory, for example, ROM cartridge, floppy disk or the like. The main unit is operated following a program contained in the exter-nal memory. In the external memory and the main unit, the same semiconductor devices, for example, microprocessors are incorporated respectively, and the former device acts as a key device and the latter device acts as a lock device. The key device and the lock device are synchronized with each other, executing the same arithmetic operation following the same program. The results of this operation are exchanged with each other, and the two devices compare the result of operation by their own with the result of operation by the other, respectively. If they both coincide, software is determined to be true and the main unit is allowed to operate, but if they do not coincide, the software is determined to be false and the main unit is left reset intact. Thereby, pro-cessing in the information processing apparatus is disabled when the software contained in the external memory is not true.

Description

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TITLE OF TEIE INVENTION
A system for determining a truth of software in an in~ormation processing apparatus The present invention relates to a system for deter-mining a truth of software in an information processing apparatus. More specifically, the present invention relates to a system for determining a truth of software contained in 10 an external memory, for example, ROM cartridge, floppy disk or the like which is employed together ~ith a main unit.

Conventionallyj such informatian processing apparatuses are known wherein an external memory is loaded in a main unit 15 and the main unit executes a predetermined operation follow-ing software contained in this external memory. The assignee of the present invention also manufactures and sells the home video game apparatus "Nintendo Entertainment System (trade mark~" as one sxample of such information processing appara-20 tuses, wherein a ROM cartridge is loaded on the main unit,the main unit i5 connected to a television receiver, and thereby various games can be enjoyed on the screen of the television receiver. A large number o~ softwares (ROM

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ca~tridge) which can be utilized for such information pro-cessing apparatuses are commercially available. However, such softwares simply suffer from imitation or forgery by other persons, and accordingly, those who developed an ex-5 cellent software incurs a great damage. However, such asystem capable o~ determining a truth of software has not been proposed till now.

Therefore, the present inventinn provldes a system capable of determining a truth of software contained in an external memory which is employed together with a main unit in an information processing apparatus.
Another object of the present invention is to provide a 15 system for determining a truth of software in an information p~ocessing apparatus wherein any use other than true software contained in an external me~ory can be excluded.
An information processing apparatus whereto the present invention is appli~able comprises a main unit and an external 20 memory connected to this main unit, and the external memory comprises a program (software~ for operating the main unit.
The external memory further comprises an active device for determining a--truth of software, and this active device functions as a ~ey device. Another active device is ins alled , : :

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in the main unit, and this active device func-tions as a lock device. By cooperation of the key device and the lock device, an inform~tion processing me~ns is enabled or dis-abled which is installed in the main unlt and executes a 5 predetermined information processing based on software contained in ~he external memory.
In accordance with the present in~ention, the main unit lS not enabled unless a true external memory (software) is loaded, and theref~re the use of a false external memory can 10 be excluded effectively.
In a preferred embodiment in accordance with the present invention, the same digital processing devices are used as the key device and the lock device. The two digital devices execute a predetermined data processing in synchro-15 nism with each other and following the same program. Then,the lock digital processing device compares the result of processing by its own with the result of processing by the Xey digital processinq device. In accordance with this preferred embodiment, a truth of the sof-tware of the external 20 memory can be determined reliably by such a simple config-uration that the same digital processing devices are added to the main unit and the external memory, respectively.
These objects and other objects, features, aspects and advantages of the present invention will become more apparent 25 from the following detailed description of the embodiments of ~`,' ' :
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. ':''' ' the present invention when -taken in conjunction ~ith accom-panying drawings, in which Fig. 1 is a perspective view showing an example of a 5 video game machine as one embodiment in accordance with the present invention.

Fig. 2 is a block diagram showing a system configura~
tion of this embodiment.
Fig. 3 is a block diagram showing a oircuit configura-10 kion o~ a lock device.
Fig. 4 is a timing chart for explaining the operation of the device of;Fig. 3.
Fig. 5 is a flow chart for explaining an outline ofoperation of the embodiment shown in Fig. 2.
Fig. 6 is a flow chart for explaining the operation of Fig. 5 in further detail.

Fig. 7 is a flow chart for explaining a modified exam-ple of Fig. 6.
Fig. 8 is a perspective view showing another example of 20 a video game machine as one embodiment in accordance with the present inven~ion.
FigO 9 is an illustrative view showing one example oE a floppy disk used for Fig. 8 embodiment.
Fig. 10 is an illustrative view showing one example of .,. .. :

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a reading apparatus of Fig. 8 embodiment.

Fig. 1 is a perspective view showing one example of a game machine as one embodiment in accordance with the present 5 invention. Hereinafter, description is made on the case where the present invention is applied to the game machine.
However, it i5 pointed out in advance that the present invention is applicable to an arbitrary information processing apparatus such as a computer, word processor, banking system 10 or the like which employs an external memory, for example, a cartridge, floppy disk, card or the like.
A game machine 10 comprises a main unit 1~, and controllers14a and 14b are connected to this main unit 12. A
cartridge 16 is further loaded on the main unit 12 as an lS external memory. As described in detail later, the cartridge 16 includes a ROM whereto a program necessary for the game and the like are written in advance. The main unit 12 prepares a video signal required for the game in response to signals from the controllers 14a and 14b following a program 20 in the cartridge 16, and gives this video signal intact or a television signal converted from this video signal to a television receive~ 18. The operator watches the picture on the screen of the television receiver 18, operates the con-trollers 14a and 14b as required, and thereby can enjoy the 25 game programmed in the cartridge 16.

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In reference to Fig. 2, a connector 20 is installed in the game machine main unit 12, and this connector 20 is engaged with a connector 22 of the cartridge 16~ and thereby the main unit 12 is connected electrically to the cartridge 5 16.
. A g~ne microprocessor 24, for example, the inte-grated circuit "Z80A" manuEactured by Zilo~ is mounted on the printed board (not shown~ of the main unit 12, and the above-described controllers 14a and 14b and TV receiver 18 . 10 are connected to this microprocessor 24 through an interface 26.
A PPU ~picture processing unit) 28, a semi-conductor device 30 for determining a truth and a clock oscillator 32 are further included in the main unit 12. The PPU 28 is 15 composed, for example, of the integrated circuit "2C03"
manufactured by ~intendo, outputting a video informakion processed by the game microprocessor 24 as a television signal for the TV receiver 18.
The semiconductor device 30 can be constituted with 4-20 bit microprocessor, for exarnple, the integrated circuit"lONES" manufactured by Nintendo likewise a semiconductor device 34 for determining a truth mounted on the printed board (not shown) of the cartridge 160 A reset switch 36 is connected to the reset terminal of the semiconductor device 25 30. A reset capacitor 38 is further connected to the raset ., .
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terminal in parallel with the reset switch 36. The reset capacitor 38 is charged when a power switch 40 (Fig. 1) is turned onJ thereby performing a so-call initial resek (power-on-clear) which keeps the semiconductor device 30 in 5 the reset state for a predetermined time.
. A ROM 42 for storing the game program (software) and a ROM 44 for generating data of charac~ers necessary for the game are mounted on the printed board of the cartridge 16.
This printed board of the cartridge 16 is connected elec-10 trically to the printed board of the main unit 12 through thetwo connectors 20 and 22 as described above~
A clock CL from the clock oscillator 32 is given also to the semiconductor device 34 for determining a truth installed in the cartridge 16 through the connectors 20 and 15 22.
As shown in Fig. 2, a predetermined terminal of the semiconductor device 30 is grounded, while a predetermined terminal of the semiconductor device 34 i5 connected to a power source Vcc. Thereby, these two semiconductor devices 20 30 and 34 can determine whether they themselves play a role of a key or a lock.
In order that the two semiconductor devices 30 and 34 exchange data with each other, the respectively corresponding terminals I, O and R are connected to each other through the 25 connectors 20 and 22. Also, as described above, the common 3~ ~

clock CL is give~ to these two semiconductor devices 30 and 34 from the clock oscillator 32. A~cordingly, ~he two semiconductor device 30 and 34 are operated in the state where respective periods and phases of operation are 5 synchronized completely with each other.
Next, further detailed description is made on the semi-conductor device 30 for determining a truth in reference to Fig. 3~ Meanwhile~ the semiconductor device 34 in the cartridge lS also has the same constitution, and therefore 10 reference codes related thereto are put in brackets to omit duplicate description thereon As described above, the semiconductor devices 30 and 34 determine ~whether the cartridge 16 is true or false in cooperation with each other. The functions o~ these two 15 semiconductor devices 30 and 34 can be compared to a relationship between a lock and a key~ Accordingly, in the following aescription, the semiconductor device 30 is called a lock device and the semiconductor device 34 is called a key device.
In reference to Fig. 3, the lock device 30 is composed, for example, of a 4-bit microprocessor, comprising a CPU 30a as a data processing means and a ROM 30b and RAM 30c as semiconductor memories. The ROM 3Ob stores an operation program for the CPU 30a, and two arithmetic operation pro-25 grams are contained in this operation program~ Plural kinds . .

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of operation formulas and data of random numbers for the arithmetic operation following the operation formulas ar~
contained in one operation program. Also, a determining program for comparing the operation re~ult of the other 5 arithmetic operation program against that of the key device 34 and a determining program for comparing the operation result of one arithmetic operation program against that of the iock device 30 are contained in the operation program.
The CPU 30a functions as- a determining means when these 10 determining programs are executed.
Furthermore, a control progra~ for controlling reset or release of reset oE the main unit 12 based on the result of determination of the above-described determining program is contained in the operation program.
An accumulator 30d is connected to the CPU 30a. A
register 30e is connected to the ROM 30b. This register 30e is for temporarily storing the program data accessed from the ROM 30b. Furthermore, a frequency divider 30f for receiving the clock CL rom the clock oscillator 32 (Fig. 2) and divi-20 ding the frequency thereof is installed in the lock device 30, and the ratio of frequency division of the frequency divider 30f is set, for example, to 1/4. The CPU 30a exe-cutes sequential program steps in response to signals of respective phases ~ 2, ~3 and ~4 from the frequency 25 divider 30.

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The CPU 30a, the accumulator 30d and the register 30e are connected by a data bus 30g. This data bus 30g is con-nected to an I/O port 30hf data is outputted from the I/O
port 30h to the key device 34, and data from the key device 5 34 is.received through the I/O port 30h. :Furthermore, two reset signals RESETl . and ~ESET2 are outputted from the I/O port 30h. ~he reset signal RESETl is given to the key device 34 to reset it. The reset signal RESET2 i9 given to the game microprocessor 24, the PPU 28 and so on which are 10 contained in the main unit 1~ to reset them. In order to release the reset states of the key device 34 and the main unit 12, these reset signals RESETl and RESET2 ha~e only to be inversed.
Next, a brief description is made on operation of the 15 frequency divider 30f in reference to Fig. 4. As described above, the frequency divider 30f divides the requency of the clock CL from the clock oscillator 32 into 1/4. Accordingly, four signals ~1, 02, ~3 and 04 having different phases res-pectively are obtained from the frequency divider 30f. These 20 ~ignals ~ are given to the CPU 30a. The CPU 30a per-forms operations in sequence in synchronism with these four signals ~ 4. For example, data from the I/O port 30h is read in synchronism with the signal ~1, and predetermined arithmetic operations (data processing~ i5 per-25 formed in response to the signals ~2 and ~3. Then, data from the I/O port 30h is outp~tted by the final signal ~4.
Meanwhile, these signals ~ 4 are given also to the k~y device 34, and accordingly, the lock device 30 ana the key device 34 are operated in complete synchronism with each S other. Specifically, the lock device 30 and the key device 34 have the same number of steps of the operation program and the same architecture, also having the same hardware and the same clock, and therefore respective machine cycles coincide completely.
Next, a brief description is made on operation of the embodiment in reference to Fig. 5. Also, detailed descrip-tion on the operation is made later in reference to Fig. 6.
First, the cartridge 16 is loaded on the main unit 12, and the power switch 40 (Fig. 1~ of the main unit 12 is 15 turned on to start the operation (step Sl). In the following step S2, the lock device 30 outputs the reset signal RESET2 and resets the game microprocessor 24, the PPU 28 and so on comprised in the main unit 12, holding this state. Thus, no ga~e can be played in the state wherein the main unit 12 is 20 reset.
Next, in step S3, the lock device 30 is synchronized with the key device 34. A method of synchronization thereof is described in reference to Fig. 4. The machine cycle o the lock device 30 is set so that the reset signal RESETl 25 given to the key device 34 from the lock device 30 is out-27a33~

put~ed between signal ~4 of certain period of the clock CLand the signal ~1 of the next period. Consequently, the signal ~1 is first inputted without fail to the key device 34. Consequently, the key device 34 can start operation from 5 quite the same machine cycle ~1 as that of the lock device 30. Thus, in step S3 the lock device 30 is synchronized with the key device 34, and thereafter the respective devices 30 and 34 execute predetermined operations in completely syn-chronized state.
Next, in step S4, predetermined arithmetic operations are performed respectively by the lock device 30 and the key device 34. At this time, the arithmetic operation performed by the lock device 30 and the arithmetic operation performed by the key device 34 are the same. Accordingly, if the 15 cartridge 16 is true, the results of the two arithmetic operations performed in tnis step S4 will become the same one.
In step S5l the above-described results of the opera-tions are transferred mutually between the lock device 30 and 20 the key device 34. Then, in step S6, the lock device 30 and the key device 34 compare these two results of operations, respectively. In step S7, if it is determined that these two results of operations coincide, in step S8, the lock device 30 releases the reset signals RESETl and RESET2 , releas-25 ing the reset states of the key device 34 and the main unit . . . .

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In reverse, in step S7, if it is determined that the both do not coincide, in step S9, the lock device 30 con-tinues to output the reset signals RESETl and RBSET2 , and 5 accordingly, the reset states of the key device 34 and the main unit 12 are continued. The operator cannot play the game in this state.
Next, further detailed description on the operation is made based on Fig~ 6r In reference to Fig. 6, if the car-10 tridge 16 is loaded on the main unit 12 and the power switch40 (Fig. 1) of the main unit 12 is turned on or the reset sw.itch 36 is turned on, the resetting operation of the lock device 30 is performed, and this lock device 30 starts to operated in step S10.
In the following step Sll,- the lock device 30 deter-mines whether it functions as tha lock or a~ the key. As explained in~Fig. 2, this determination is performed by detecting whether the predeterminea terminal is grounded or connected to the power sowrce Vcc. In this case, the lock 20 device 30 should be determined to function as the lock, but in the casa where determination is made to function as the key, for example, due to wiring error, malfunction or the like, an unstable state takes place and no operations are performed at allO
In step S11, when "YES" is datermi~ed, in step S12, the - 1.3 -..
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lock device 30 outputs the reset signal RESET2 so that the main unit 12 cannot execute the game Program~ and the xeset state of -the main unit 12 is continued. The game micro-processor 24 and the PPU 28 (Fig. 2) are forcedly put in the 5 reset state and disabled until the reset is xeleased in the later-de~cribed step S21. And, in this step S12, the reset signal RESETl is also outputted to reset the key device 34.
In the next step S13, the lock device 30 releases the reset state of the key device 34, and synchronizes the two 10 devices 30 and 34 with each other likewise the case in the above-described step S3 (Fig. 5). Thereby, the two devices 30 and 34 are synchronized with each other, and thereafter the respective devices execute sequential program steps in the state of complete synchronism.
When the reset state of the key device 34 is released in step S13, the key device 34 determines whether if func-tions as the lock or as the key in the next step Sll'. The determination in this step Sll' can be made by detecting whether the predetermined terminal of ~he key device 34 is 20 grounded or connected to the power source Vcc likewise the determination in the above-descxibed step Sll. If "NO" is determined in this step Sll', an unstable state takes place and`no operations are performed at all.
Also, when "YES" is determined in step Sll', operations 25 in the following steps S14l and thereafter are executed.

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On the other hand, in the lock device 30, operations in steps S14 and thereafter are executed after the step S13 is executed. Accordingly, in the lock device 30 and the key device 34, the very same operations can be performed in 5 synchronism , that is~ in coincidence of the time axis.
First, the lock device 30 and the key device 34 output data of random numbers from the respective program ROMs 30b and 34b (Fig. 3) in step S14 and in step Sl4'. Output of these data of random numbers is performed using the very same 10 random function. Then, conditions given to the random func-tion is also tha same for the two devices 30 and 34~ Accor-dingly, ~hen the cartridge is true, the data of random numbers generated in the lock device 30 and the data of random numbexs generated in the key device 34 should be just 15 the same.
Next, in steps S15 and Sl5', the lock device 30 and the key device 34 exrhange data with each other, and read the data of random numbers generated by the counterpart, respec~
tively. Then, in steps Sl6 and Sl6'~ the both devices 30 and 20 34 perorm the predetermined data processings or ari-thmetic operations based on the data of random numbers inputted from the counterpart. The arithmetic operations formula used for the first arithmetic operation in these steps Sl6 and S16' is just the same in the two devices 30 and 34, and therefore the 25 results of these operations become the same when the inputted . .
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data of random numbers are the same. Then, in steps S17 and S17', the lock device 30 and the key device 34 output the results of arithmetic operations to the counterpart, respec~
tively. Responsively, in steps S18 and S18', the two devices 5 30 and 34 mutually receive the results of arithmetic opera-tion outputted from the counterpart. In this case, the lock device 30 and the key device 34 perform just the same opera-tion at the same timing, and therefore the results of opera-tion inputted from the counterpart are to be inputted also at 10 the same timing. Accordingly, in this embodiment, not only coincidence of the results of arithmetic operations but also coincidence of the time axes thereof are to be taken into account to determine a truth of the cartridge.
Next, in step S19, the lock device 30 compares the 15 result oL arithmetic operation by itsel against the result of operation given from the key device 34, determining whetller or not the both coincide. As a result of this com-parison, if "NO" is determined in step S20, the lock device 30 holds the reset state of each circuit in the main unit 12~
20 namely, the game microprocessor 24, the PPU 28 and so on in the next step S22~ TherebyJ the main unit 12 is inhibitea to execute the game program.
Meanwhile, an alarm may be generated in response to a determination of non-coincidence in place of such a hold of 25 the reset states, or processing may return to the initial : ~., ' , , .

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state, namely; the step Sll.
As a result of the comparison in step Sl9, if "YES" is determined in step S20, the lock device 30 releases the reset states of these circuits, namely, the game microprocessor 24, 5 the PPU 28 and so on in the next step S21.
Subsequently, in step S23, the lock device 30 generates two, a first and a second, data of random numbers based on a ~predetermined random function. Then, in step S24, th~ lock device 30 selects the kind of arithmetic operation formula 10 using the second data of random numbers, and sets the first and the second data of random numbers as the values sub-stituted into the arithmetic operation formula. More speci-fically, in this embodiment, n (positive integer) kinds of arithmetic operation formulas are set in advance in the 15 arithmetic operation program; in the ROM 30b (Fig. 3), and from among then, an arithmetic operation formula is selected in response to the second data of random numbers. Subse-quen ly, in step S25, the selected arithmetic operation wherein the first and the second data of random numbers are 20 substituted is executed based on the selected arithmetic operation formula.
Operations in these steps Sl9 - S25 are performed in the same manner at just the same timing also in the key device 34. Then, the same random function for generating the 25 first and the second data of random numbers as tha-t usea for . . .
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the lock device 30 is also used in this case. Also, condi-tions given to the random function for generating the first and the second data of random numbers is also the same for the lock device 30 and the key device 34 as described above.
5 Accordingly, i the cartridge 16 is true, just the same arithmetic operation foxmula is selected for the two devices 30 and 34, and the results o these arithmetic operations should be the same.
Next, in step S26, the lock device 30 gives the 10 results of arithmetic operation performed in step S25 to the key device 34, and also receives the results of arithme~ic operation done by the key device 34. A similar operation is performed also in the key device 34. Next, in step S27 and step S28, the lock device 30 compares and checks the 15 results of arithmetic operation by itself against the results of arithmetic operation received from the key device 34 and determines whether or not the both coincide with each other.
If the cartridge 16 loaded in the main unit 12 is not true, the results o arithmetic operations done by the both 20 do not coincida, and therefore, in this case, the lock device 30, in step 529, outputs the reset signal RESET 2, forcedly putting the game microprocessor 24, the PPU 28 and the like of the main unit 12 in the reset state to stop the operations thereafter~
On the other hand, when the lock device 30 determines 3~3~

that the result of arithmetic operation by itself and the result of arithmetic operation r~ceived from the key device 34 coincide with each other, processing returns again to step S24, and thereafter the operations in steps S24 - S28 are 5 repeated. In other words 9 in this embodiment, as long as the main unit 12 is operated, the second arithmetic operation program in steps S24 - S28 are executed repeatedly, and when a non-coincidence of the results of arithmetic operations takes place even once, step S29 is executed and the main unit 10 12 is stopped to operate.
~ In addition, the same operations as those in steps S26 - S29 are performed also in the key device 34. ~owever, the key device 34 has no effect on resetting and releasing each circuit of the main Ullit 120 Because/ no reset signal is lS outputted to the main unit 12 side from the k~y device 34.
Also, as for the operation of the key device 34 corresponding to step S29, since a chip-select terminal is normally installed in the ROMs 42 and 44 (Fig. 2), this chip-select terminal may be disabled. When the chip-select 20 terminal is disabled, the game microprocessor 24 and the PPU
28 of the main unit 12 cannot access these ROMs 42 and 44, and therefore continuation of playing the game becomes impossible.
Determinat.ion of a truth can be made enough only by 25 checking up the results of the first arithmetic operations in ~Z~3~

step S16 and step S16', but further in the above-described embodiment, the second arithmetic operations and check-up of the results thereof in steps S24 - S28 are performed repea-t-edly as long as the main unit 12 is operated, and therefore 5 the determination of a truth of the cartridge 1~ can be made nearly completely. Accordingly, in the case where a car-tridge containing ROMs copying the ROMs 42 and 44 in the cartridge 16 or a cartridge containing ROMs stoxing similar programs thereto is used, protection of such a software 10 cannot be broken unless just the same hardware as the key device 34 is obtained. Also, by using devices such ~s custom ICs or the like which are difficult to be obtained normally, such a protection can be macle more completely.
Thus, the protection of programs (software) contained 15 in the cartridge 16 can be made completely by installing the key device 34 for determining a truth of the cartridge 16 and making it cooperate with the lock device 30 of the main unit 12, and accordingly any copied or forged cartridge, that is, cartridge other than the true one is shut out.
Fig. 7 is a flow chart showing a modified example of Fig. 6. Nearly the same hardware as the embodiment in Fig. 6 is employed also in this embodiment, and for this Fig. 7 embodiment, though not illustrated, a counter is formed in the RAM 30c of the lock device 30 and the RAM 34c of the key 25 device 34 tFig. 3), respectively. Then, by utilizing this . :..,.~ ,., :

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counter, the second arithmetic operation is repeated by a predètermined number of times set by this counter.
To be further ~etailed, operations in steps SllO - S120 and Sllll - 119l of this Fig. 7 embodiment are the same as 5 those in steps S10 - S20 and Sll' - Sl9'(in Fig. 6), and therefore duplicate description is omitted here.
If a coincidence of the results of the first arithmetic operations is determined in step S120, in Fig. 7 embodiment, the counter formed in the RAM 30c of the lock device 30 is 10 reset in step S121. The second arithmetic operation is executed in the following steps S123 - S128 likewise in steps S23 - S28 in Fig. 6. Then, i~ a coi.ncidence of the results o the two arithmetic operations is determined in step S128, the lock device 30 increments the counter (not illustrated) 15 formed in the RAM 30c comprised therein i~ the next step S130. Then, in the next step S131~ determination is made on ~hether or not the value of the counter is the predetermined value. If the counted value of the counter does not reach the predetermined value, the lock device 30 repeats steps 20 S123 S130.
Then, if "YES" is determined in step S131, that is, if the second arithm~tic operation is repeated by the pre-determined number of times, the lock device 30 releases the reset states o the game microprocessosr 24, the PPU 28 and 25 so on of the main unit 12 in step S132 likewise in step S21 `~ ~;27~3~ ~

in Fig~ 6.
In addition/ i~ the embodiment in Fig. 7, the second arithmetic operation is performed repeatedly by the pre-determined number of times in steps Sl23 S131; but the S number of times may be oneO
Also, if the results o~ the first arithmetic operations in steps S114 - S116 coincide, the main unit 12 is enabled immediately, and thereafter the second arithmetic operation as shown in steps S123 - S131 is repeated, and when "NO" is 10 determined in step S128 during the repetition, the main unit 12 is disabled, and if a non-coincidence does not occur by repeating the second arithmetic operation, thereafter the main unit 12 may be kept emabled until the power switch 40 (Fig. 1) of the main unit 12 is turned off~
lS Furthermore, steps S22 and S29 in Fig. 6 and steps S122 and Sl29 in Fig. 7 may be modified as follows, respectively.
To be detailed, a black screen data for wholly blackening the screen of the television receiver 18 and a title data for displaying a game title are written in advance to the ROM 42 20 o the cartridge 16. Then, in the above-described step S22 or S29 and step S122 or Sl29, a pulse-reset si~nal is out-putted from the lock device 30, and thereby the black screen and the title screen are displayed repeatedly in an alterna-te fashion. Thereby the operator is informed that the cartridge 25 16 is not true.

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7~3~ ~_ In addition, the ROM cartridge 16 is used for an ex-ternal memory in the above-described embodimen-t~ However, for the external memory, a magnetic memory, for example, floppy disk~ maqnetic card or a~ optical memory, for example, 5 optical disk or the like may be used in place of such a cartridge 16.
Fig. 8 is a perspective view showing another embodiment in accordance with the present invention. This embodiment employs a floppy disk for an external memory. In the con-10 figuration of Fig. 1 embodiment, the floppy disk cannot beemployed intact, and therefore in the Fig. 8 embodiment, an adaptor 46 is used which has the salne shape as that of the cartridge 16 (Fig. 1) and is made attachable and detachable to the main unit 12. A reader 48 is connected to this 15 adaptor 46. ~hen, a floppy disk 50 is loaded in this reader 48. Accordingly, the program (software) written in advance to the floppy disk 50 is read by the reader 48, and it is given to the main unit 12 through the adaptor 46.
As shown in Fig. 9, the floppy disk 50 comprises a case 20 52 and a disc-shaped magnetic sheet 54 supported rotatably in the case 52. Then, the key device 34 and an electrode 56 for connecting the key device 34 are formed in the case 52.
As shown in Fig. 9, inside the reader 48 receiving such a floppy disk 50, a disk driver 58 is accommodated and also a 25 contact 60 connected to the electrode 56 is installed. Ac-. ,,, i.

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cordingly, the key device 34 installed in the floppy disk 50 is connected to the lock de~ice 30 of the main unit 12 through the electrode 56 ~nd the contact 60.
In the embodiment in Fi~. 8~ operation i5 executed 5 following the program as shown in Fig. 6 or 7 by cooperation of the lock device 30 (Fig. 23 comprised in the main unit 12 and the key dev.ice 34 formed in the floppy disk 50, and thereby determInation is made on whether or not the floppy disk 50 is true.
Meanwhile, the lock device 30 (Fig. 2) may be insta:Lled in the reader 48, not in the main unit 12. In this case, the reset signal will be given to the main unit 12 from the reader 48.
Furthermore, in the case where a memory means is com-15 prised in the apparatus itself which is connected to theadaptor 46, for example~ in the case where a sound source apparatus comprising a synthesizer ROM or the like is con-nected, the key device 34 is installed in the adaptor 46, and the operation in Fig. 6 or Fig. 7 may be executed by this key 20 device 34 and the lock device 30 built in the main unit 12.
In addition, in the above-described embodiment, micro-processors are employed for the lock device 30 and the key device 34. However, for these devices 30 and 34, simpler digital arithmetic operati.on devices may be employed, and 25 further analog processors may be employed which perform . .

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analog processing in place of digital processing. Also, a digital circuit may be employed in either of the lock device 30 and the key device 34 and an analog circuit in the other device.
In the case where the analog circuit is employed, various configurations can be u-tilized als~ other than the above-described analog processor. For example, detexmination of a truth of the exkernal memory (software) may be performed by a coincidence of frequencies of the clock CL converted by 10 both the lock device and the key de~ice following the same program. Furthermore, pulse signals are outputted from the lock device 30 and the key device 34, and the duty ratio of the pulse siganls is converted following a predetermined program, and thereby a truth can be determined also by a 15 coincidence of the duty ratios. Or, for example, de-termina-tion may be made by a coincidence of levels of integrations of the same saw-tooth waves, an~ further deferential may be used. In any cases, a truth of the external memory can be determined by determining a coincidence of the results of 20 analog processings of the two devices.
Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limikation, the spirit and scope of the 25 present`invention being limited only by the terms of the appended claims.

., ..

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A system for determining a truth of software in an information processing apparatus comprising:
a main unit, an external memory which is connected to said main unit, constitutes said information processing apparatus together with the main unit, and includes a program for information processing, a first active device which in installed in said external memory and performs a predetermined operation to determine a truth of said external memory, an information procesing means which is installed in said main unit and executes a predetermined information processing based on said program, a second active device which is installed in said main unit and performs a predetermined operation to determine a truth of said external memory, and a controlling means which enables or disables said information procesing means base on the states of said first and second active devices.
2. A system for determining a truth in accordance with claim 1, wherein said first and second active devices include the same active device.
3. A system for determing a truth in accordance with claim 2, wherein said active device includes an analog processing device, and said controlling means includes means for determining a coincidence of the results of processing by the first and second analog processing devices.
4. A system for determining a truth in accordance with claim 1, wherein said first and second active devices include a digital processing device respectively, and said controlling means comprises a determining means which determines whether or not the results of processing by a first and a second digital processing devices are in a predetermined relation.
5. A system for determining a truth in accordance with claim 4, which further comprises a program means including a processing program, wherein said first and second digital processing devices execute digital procesing for determining a truth by a program from said program means.
6. A system for determining a truth in accordance with claim 5, wherein said first and second digital processing devics include the same digital processing device, said program means gives the same processing program to said first and second digital processing devices, and said determining means includes means for determining whether or not the results of said processing coincide.
7. A system for determining a truth in accordance with claim 6, wherein said program means comprises a first semiconductor memory including a processing program for said first digital processing device and a second semiconductor memory including a processing program for said second digital processing device.
8. A system for determining a truth in accordance with claim 7, wherein said program means includes a clock means for giving the same clock to said first and second digital processing devices, and said determining means includes means for determing a coincidence of time series of process-ing by said first and second digital processing devices.
9. A system for determining a truth in accordance with claim 7, wherein said first and second semiconductor memories include different first and second processing programs res-pectively, said first and second digital processing devices execute a first and a second processing respectively in response to programs from said semiconductor memories, and said determining means include means for determining a coincidence of the results of proceesings by said first and second digital processing devices every time said first and second processing are performed.
10. A system for determining a truth in accordance with claim 9, wherein said first and second digital processing devices repeat said second processing, and said determining means determines whether or not the results of said processings coincide every time said second processing is repeated.
11. A system for determining a truth in accordance with claim 10, which further comprises means for counting the number of times of repetition of said second processing by said first and second digital processing means.
12. An external memory being connected to a main unit and constituting an information processing apparatus together with the main unit, comprising:
a semiconductor memory including a program for in-formation processing in said main unit, and an active device for performing a predetermined opera-tion to determine a truth.
13. An external memory in accordance with claim 12, wherein said active device includes a digital processing device, and said semiconductor memory comprises a processing program for said digital processing device.
14. A system for determining a truth of software in an information processing apparatus comprising:
a main unit, an external memory which is connected to said main unit, constitutes said information processing apparatus together with the main unit, and includes a program for information processing, a first means which is installed in said external memory and is for determining a truth of said external memory, and a second means which is installed in said main unit and cooperates with said first means to determine a truth of said external memory.

15. An external memory unit for connection to a main video game data processor unit having a video game processing means for executing videographics programs stored in said external memory unit, said video game processing means being capable of being reset and a dedicated authenticating processing means for executing a first predetermined authenticating program to for an information processing apparatus, said external memory unit comprising means for storing a videographics program that is to be executed by said video game processing means and external authenticating processing means for operating in accordance with a second predetermined authenticating program when said memory unit is connected to the video game data processor unit for verifying that said videographics program stored in said means for storing is authorized for execution by said video game processing means; means coupled to said external authenticating processing means and said means for storing, for connecting said external memory unit to said video game data processor unit and wherein said external authenticating processor means includes data transfer means coupled to said means for connecting for transferring data related to the results of the execution of said second authenticating program to said dedicated authenticating processing means, whereby the video game processor means in said main video game processor unit is reset unless the results of the execution of the second authenticating program exhibit a predetermined relationship with the results of the first predetermined authenticating program.

16. An external memory in accordance with claim 15 wherein said external authenticating processing means includes clock signal input means, coupled to said means for connecting, for receiving clock signals from said main video game data processor unit, wherein said external authenticating processing means further includes means responsive to said clock signal input means for executing a plurality of instructions in response to each received clock signal.

17. An external memory according to claim 16 wherein said means responsive to said clock signal input means includes frequency divider means for generating a plurality of timing signals each of which initiates the performance of a predetermined processing operation.

18. An external memory according to claim 15, wherein said external authenticating processing means includes means responsive to said plurality of timing signals for receiving data from said dedicated authenticating processing means in response to a first timing signal, for performing predetermined arithmetic operations in response to a second timing signal and for transferring data to said dedicated authenticating processing means in response to a third timing signal.

19. An external memory according to claim 15, wherein said data transfer means further includes input pin means, coupled to said means for connecting, for receiving data related to the results of the execution of said first predetermined authenticating program from said dedicated authenticating processing means and output pin means, coupled to said means for connecting, for transferring data related to the results of the execution of said second predetermined authenticating program to said dedicated authenticating processing means.

20. An external memory according to claim 19, wherein said data transfer means further includes reset pin means for receiving a reset related signal from said dedicated authenticating processing means, said external authenticating processing means including means responsive to said reset related signal for maintaining a reset state or releasing the reset state depending upon the state of the reset related signal.

21. An external memory according to claim 20 wherein said external authenticating processing means includes means responsive to said reset related signal from said dedicated authenticating processing means for releasing its reset state and for synchronizing its operation with the operation of the dedicated authenticating processing means.

22. An external memory according to claim 15, wherein said external authenticating processing means includes means responsive to a clock signal received from said main video game data processor unit for synchronizing its operations with predetermined operations performed by said dedicated authenticating processing means.

23. An external memory according to claim 15 wherein said external authenticating processing means includes a terminal having a predetermined voltage coupled thereto and further includes means responsive to detecting said predetermined voltage for determining the processing operations to be performed by said external authenticating processing means.

24. An external memory according to claim 15, wherein said external authenticating processing means includes means for generating at least one random number in accordance with a predetermined function.

25. An external memory according to claim 24, wherein said means for generating at least one random number includes memory means for storing data representing random numbers and means for reading out at least one random number in accordance with a predetermined function.

26. An external memory according to claim 24, wherein said external authenticating processing means further includes means for outputting said at least one random number and transferring said at least one random number to said dedicated authenticating processing means via said means for transferring, means for receiving data generated by said dedicated authenticating processing means via said means for transferring and means for performing predetermined processing operations on said data generated by said dedicated authenticating processing means.

27. An external memory according to claim 26, wherein said predetermined processing operations performed by said external authenticating processing means are performed in time coincidence with corresponding processing operations performed in said dedicated authenticating processing means.

28. An external memory according to claim 26, wherein said external authenticating processing means further includes means for outputting the results of said predetermined processing operations and for transferring the results to said dedicated authenticating processing means.

29. An external memory according to claim 28, wherein said external authenticating processing means further includes means for receiving results of corresponding processing operations performed by said dedicated authenticating processing means.

30. An external memory according to claim 29, wherein said external authenticating processing means further includes means for comparing the results generated by said dedicated authenticating processing means with the results generated by said external authenticating processing means.

31. An external memory according to claim 30, wherein said external authenticating processing means further includes means responsive to the detection of coincidence between the results generated by said external authenticating processing means and said dedicated authenticating processing means, for selecting at least a further arithmetic operation to be performed.

32. An external memory according to claim 31, further including means for storing indicia representing n arithmetic operations, where n is a positive integer, said means for selecting including, means for generating at least a first number and at least a second number, said at least a first number being used to select an arithmetic operation to be performed and said at least a second number being used to define variable values for said selected arithmetic operation.

33. An external memory according to claim 31, wherein said external authenticating processing means includes means for performing said further arithmetic operation and for outputting a result.

34. An external memory according to claim 33, wherein said further arithmetic operation performed by said external authenticating processing means is performed in time coincidence with a corresponding further arithmetic operation performed by said dedicated authenticating processing means.

35. An external memory according to claim 33, further including means for transferring the results of said further arithmetic operation to said dedicated authenticating processing means and for receiving the results of a corresponding further arithmetic operation from said dedicated authenticating processing means.

36. An external memory according to claim 35, wherein said external authenticating processing means further includes means for comparing the results of the further arithmetic operations performed by said external authenticating processing means and by said dedicated authenticating processor means.

37. An external memory according to claim 31, wherein said external authenticating processing means further includes means for repetitively performing further arithmetic operations.

38. An external memory according to claim 37, wherein said means for repetitively performing further arithmetic operations executes further arithmetic operations during the time period that said video game processing means executes said videographics program.

39. An external memory according to claim 36, wherein said external authenticating processing means includes means responsive to said means for comparing the results of the further arithmetic operations to prevent access to said means for storing a videographics program when the results do not coincide.

40. An external memory according to claim 37, further includes means for counting, and wherein said means for repetitively performing said further arithmetic operations continues performing further arithmetic operations until said means for counting reaches a predetermined value.

41. An external memory unit for removable connection to a main data processor unit having a video game processor for executing video game programs stored in said external memory unit, said video game processor being capable of being reset and a separate authenticating processor for executing a first predetermined authenticating program, said external memory unit comprising an external memory for storing a videographics program that is to be executed by said video game processor associated with said main data processor unit;
an external authenticating processor for executing a second predetermined authenticating program when said external memory unit is connected to the main data processor unit for verifying that said videographics program stored in said external memory is authorized for use in the main data processor unit; a connector, coupled to said external authenticating processor and said external memory, for interconnecting said authenticating processors and for interconnecting said external memory to said video game processor; and wherein said external authenticating processor includes a data transfer port for transferring data related to the results of the execution of said second predetermined authenticating program to said separate authenticating processor, whereby the video game processor in said main video game processor unit is reset unless the results of the execution of the second authenticating program exhibit a predetermined relationship with the results of the first predetermined authenticating program.

42. An external memory unit in accordance with claim 41, wherein said external authenticating processor includes a clock signal input, coupled to said connector, for receiving clock signals from said main data processor unit, wherein said external authenticating processor executes a plurality of instructions in response to each received clock signal.

43. An external memory unit according to claim 42, further including a frequency divider responsive to each received clock signal for generating a plurality of timing signals each of which initiates the performance of a predetermined processing operation.

44. An external memory unit according to claim 43, wherein said external authenticating processor responds to said plurality of timing signals by receiving data from said separate authenticating processor in response to a first timing signal, by performing predetermined arithmetic operations in response to a second timing signal and by transferring data to said separate authenticating processor in response to a third timing signal.

45. An external memory unit according to claim 41, wherein said data transfer port includes an input pin, coupled to said connector, for receiving data from said separate authenticating processor, an output pin, coupled to said connector, for transferring data to said separate authenticating processor and at least one reset pin for receiving a reset related signal from said separate authenticating processor, said external authenticating processor responding to said reset related signal by maintaining a reset state or releasing the reset state depending upon the state of the reset related signal.

46. An external memory according to claim 45, wherein said external authenticating processor responds to said related reset signal from said separate authenticating processor by releasing its reset state and by synchronizing its operation with the operation of said separate authenticating processor.

47. An external memory according to claim 41, wherein said external authenticating processor responds to a clock signal received from said main data processor unit for synchronizing its operation with the operation of said separate authenticating processor.

48. An external memory according to claim 41, wherein said external authenticating processor includes a terminal having a predetermined voltage coupled thereto, wherein said external authenticating processor is operable to detect said predetermined voltage and perform predetermined processing operations in response thereto.

49. An external memory according to claim 41, wherein said external authenticating processor is operable to generate at least one random number in accordance with a predetermined function.

50. An external memory according to claim 41, wherein said external authenticating processor is operable to perform predetermined processing operations in time coincidence with corresponding operations performed by said separate authenticating processor.

51. An external memory according to claim 50, wherein said external authenticating processor is operable to output the results of said predetermined processing operations and to transfer the results to said separate authenticating processor.

52. An external memory according to claim 51, wherein said external authenticating processor is operable to receive results of corresponding processing operations performed by said separate authenticating processor and to compare its own results with the results generated by said separate authenticating processor.

53. In a video game processing apparatus including a main video data processor unit having a video game data processor for executing videographics programs and a separate authenticating data processor for executing a first predetermined authenticating program and an external memory unit removably connected to said main video data processor unit and having a memory for storing at least one videographics software program to be executed by said video game data processor and an external authenticating processor for executing a second predetermined authenticating program;
a method of operating the external memory unit and the main video data processor unit to determine the authenticity of said external memory unit comprising the steps of connecting said external memory unit to said main video data processor unit, placing said video game data processor in a reset state, executing said first predetermined authenticating program by said separate authenticating processor to determine the authenticity of said external memory, executing said second predetermined authenticating program by said external authenticating processor to determine the authenticity of said external memory, transferring data relating to the results of the execution of said second predetermined authenticating program from said external authenticating processor to said separate authenticating processor, comparing the results of the execution of said first and second authenticating programs, releasing said video game data processor from said reset state and executing said at least one videographics software program by said video game processor if the results of the execution of the first authenticating program exhibit a predetermined relationship to the results of the execution of the second predetermined authenticating program and maintaining said video game data processor in said reset state if the results of the execution of said first authenticating program fail to exhibit a predetermined relationship to the results of the execution of the second predetermined relationship.

54. A method according to claim 53 further including the step of simultaneously transmitting clock signals to said separate authenticating processor and said external authenticating processor.

55. A method according to claim 53 further including the steps of inputting clock signal, to said separate authenticating processor and said external authenticating processor and executing a plurality of instructions in said separate authenticating process and said external authenticating processor in response to each received clock signal.

56. A method according to claim 55, wherein said step of executing a plurality of instructions includes the steps of receiving data from said separate authenticating processor in response to a first timing signal, performing predetermined arithmetic operations in response to a second timing signal and transferring data to said separate authenticating processor in response to a third timing signal.

57. A method according to claim 53, wherein said step of transferring data includes the step of transferring data from said separate authenticating processor to said external authenticating processor and from said external authenticating processor to said separate authenticating processor.

58. A method according to claim 53 further including the step of synchronizing the operation of the external authenticating processor with the operation of said separate authenticating processor.

59. A method according to claim 53 wherein said steps of executing said first and said second authenticating programs each includes the step of generating at least one random number in accordance with a predetermined function.

60. A method according to claim 59, wherein said step of generating at least one random number includes the step of storing random numbers in a memory device and reading out said random numbers in accordance with a predetermined function.

61. A method according to claim 60 wherein each of said external authenticating processor and said separate authenticating processor reads random data generated by the other processor and performs predetermined processing operations on such data.

62. A method according to claim 61 wherein said predetermined processing operations performed by said external authenticating processor are performed in time coincidence with corresponding operations performed by said separate authenticating processor.

63. A method according to claim 51 further including the steps of outputting the results of said predetermined processing operations and transferring the results to said other processor.

64. A method according to claim 63 further including the step of comparing the results generated by the separate authenticating data processor with the results generated by said external authenticating processor.

65. A method according to claim 64 further including the steps of selecting further arithmetic operations to be performed by said external authenticating processor and said separate authenticating processor in response to detecting coincidence between the results generated by said external authenticating processor and said separate authenticating processor.

65. A method according to claim 65 further including the step of storing indicia representing n arithmetic operations, where n is a positive integer, in a memory device associated with each of said external authenticating processor and said separate authenticating processor and wherein said step of selecting includes generating at least a first number and at least a second number and using said at least a first number to select an arithmetic operation to be performed and using said at least a second number to define variable values for said selected arithmetic operation.

67. A method according to claim 65, wherein each of said external authenticating processor and said separate authenticating processor performs said further arithmetic operations and outputs a result.

68. A method according to claim 67, wherein said further arithmetic operations performed by said external authenticating processor are performed in time coincidence with a corresponding further arithmetic operation performed by said separate authenticating processor.

69. A method according to claim 67, wherein said steps of executing said first and second authenticating programs each include the steps of transferring the results of said further arithmetic operations from said separate authenticating processor to said external authenticating processor and transferring the results of said further arithmetic operations from said external authenticating processor to said separate authenticating processor.

70. A method according to claim 69 further including the step of comparing the results of the further arithmetic operations performed by said external authenticating processor with the results of said further arithmetic operation performed by said separate authenticating processor.

71. A method according to claim 65 further including the step of repetitively performing said further arithmetic operations.

72. A method according to claim 71 further including the step of counting the number of times said further arithmetic operations are repetitively performed and wherein said step of repetitively performing said further arithmetic operations is continued until a predetermined count is reached.